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-rw-r--r--src/mesa/drivers/dri/i915/intel_ioctl.h44
-rw-r--r--src/mesa/drivers/dri/i965/brw_fallback.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c1
-rw-r--r--src/mesa/drivers/dri/intel/intel_batchbuffer.c1
-rw-r--r--src/mesa/drivers/dri/intel/intel_ioctl.h (renamed from src/mesa/drivers/dri/i965/intel_ioctl.h)0
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_subimage.c1
-rw-r--r--src/mesa/drivers/dri/r300/r300_emit.c12
-rw-r--r--src/mesa/drivers/dri/r300/r300_emit.h2
-rw-r--r--src/mesa/drivers/dri/r300/r300_ioctl.c2
-rw-r--r--src/mesa/drivers/dri/r300/r300_state.c76
-rw-r--r--src/mesa/drivers/dri/r300/r300_swtcl.c57
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c3
12 files changed, 83 insertions, 117 deletions
diff --git a/src/mesa/drivers/dri/i915/intel_ioctl.h b/src/mesa/drivers/dri/i915/intel_ioctl.h
deleted file mode 100644
index 60bc4a3fb9..0000000000
--- a/src/mesa/drivers/dri/i915/intel_ioctl.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-#ifndef INTEL_IOCTL_H
-#define INTEL_IOCTL_H
-
-#include "intel_context.h"
-
-void intelWaitIrq(struct intel_context *intel, int seq);
-int intelEmitIrqLocked(struct intel_context *intel);
-
-void intel_batch_ioctl(struct intel_context *intel,
- GLuint start_offset,
- GLuint used,
- GLboolean ignore_cliprects, GLboolean allow_unlock);
-void intel_exec_ioctl(struct intel_context *intel,
- GLuint used,
- GLboolean ignore_cliprects, GLboolean allow_unlock,
- void *start, GLuint count, dri_fence **fence);
-#endif
diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c
index 2cf29cc341..b5cf821a93 100644
--- a/src/mesa/drivers/dri/i965/brw_fallback.c
+++ b/src/mesa/drivers/dri/i965/brw_fallback.c
@@ -45,7 +45,6 @@ static GLboolean do_check_fallback(struct brw_context *brw)
{
GLcontext *ctx = &brw->intel.ctx;
GLuint i;
- struct gl_framebuffer *fb = ctx->DrawBuffer;
/* BRW_NEW_METAOPS
*/
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index f717b6f6c3..c38610b24e 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -33,6 +33,7 @@
#include "main/enums.h"
#include "shader/prog_parameter.h"
#include "shader/program.h"
+#include "shader/programopt.h"
#include "tnl/tnl.h"
#include "brw_context.h"
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index d4abbb0860..a594fb6cc4 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -269,7 +269,6 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
GLuint flags, GLuint delta)
{
int ret;
- int count = 0;
ret = dri_emit_reloc(batch->buf, flags, delta, batch->ptr - batch->map, buffer);
diff --git a/src/mesa/drivers/dri/i965/intel_ioctl.h b/src/mesa/drivers/dri/intel/intel_ioctl.h
index 8674aef723..8674aef723 100644
--- a/src/mesa/drivers/dri/i965/intel_ioctl.h
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.h
diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
index 688e3870df..78621814c3 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
@@ -29,6 +29,7 @@
#include "mtypes.h"
#include "texobj.h"
#include "texstore.h"
+#include "texcompress.h"
#include "enums.h"
#include "intel_context.h"
diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c
index 0eeb8bf98a..dc08b642c5 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.c
+++ b/src/mesa/drivers/dri/r300/r300_emit.c
@@ -207,7 +207,10 @@ static void r300EmitVec(GLcontext * ctx, struct r300_dma_region *rvb,
}
}
-static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
+#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \
+ (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT)
+
+GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
int *inputs, GLint * tab, GLuint nr)
{
GLuint i, dw;
@@ -216,16 +219,13 @@ static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
for (i = 0; i < nr; i += 2) {
/* make sure input is valid, would lockup the gpu */
assert(inputs[tab[i]] != -1);
- dw = (R300_SIGNED |
- (inputs[tab[i]] << R300_DST_VEC_LOC_SHIFT) |
- (attribptr[tab[i]]->size - 1)) << R300_DATA_TYPE_0_SHIFT;
+ dw = (R300_SIGNED | DW_SIZE(i));
if (i + 1 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
} else {
assert(inputs[tab[i + 1]] != -1);
dw |= (R300_SIGNED |
- (inputs[tab[i + 1]] << R300_DST_VEC_LOC_SHIFT) |
- (attribptr[tab[i + 1]]->size - 1)) << R300_DATA_TYPE_1_SHIFT;
+ DW_SIZE(i + 1)) << R300_DATA_TYPE_1_SHIFT;
if (i + 2 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
}
diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h
index 51302301f7..e6a6df8c4c 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.h
+++ b/src/mesa/drivers/dri/r300/r300_emit.h
@@ -257,6 +257,8 @@ extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
extern void r300EmitCacheFlush(r300ContextPtr rmesa);
+extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
+ int *inputs, GLint * tab, GLuint nr);
extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 04dbb957c2..d38ee9003d 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -306,7 +306,7 @@ static void r300EmitClearState(GLcontext * ctx)
R300_STATECHANGE(r300, rr);
reg_start(R300_RS_INST_0, 0);
- e32(R300_RS_INST_COL_CN_WRITE);
+ e32(R500_RS_INST_COL_CN_WRITE);
} else {
R300_STATECHANGE(r300, ri);
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index d596a0b9c4..21b5ac969b 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1491,21 +1491,17 @@ static void r300SetupRSUnit(GLcontext * ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
/* I'm still unsure if these are needed */
- GLuint interp_magic[8] = {
- 0x00,
- R300_RS_COL_PTR(1),
- R300_RS_COL_PTR(2),
- R300_RS_COL_PTR(3),
- 0x00,
- 0x00,
- 0x00,
- 0x00
- };
+ GLuint interp_col[8];
+ TNLcontext *tnl = TNL_CONTEXT(ctx);
+ struct vertex_buffer *VB = &tnl->vb;
union r300_outputs_written OutputsWritten;
GLuint InputsRead;
int fp_reg, high_rr;
- int in_texcoords, col_interp_nr;
- int i;
+ int col_interp_nr;
+ int rs_tex_count = 0, rs_col_count = 0;
+ int i, count;
+
+ memset(interp_col, 0, 8);
if (hw_tcl_on)
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
@@ -1523,7 +1519,7 @@ static void r300SetupRSUnit(GLcontext * ctx)
R300_STATECHANGE(r300, rc);
R300_STATECHANGE(r300, rr);
- fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
+ fp_reg = col_interp_nr = high_rr = 0;
r300->hw.rr.cmd[R300_RR_INST_1] = 0;
@@ -1541,12 +1537,50 @@ static void r300SetupRSUnit(GLcontext * ctx)
InputsRead &= ~FRAG_BIT_WPOS;
}
+ if (InputsRead & FRAG_BIT_COL0) {
+ count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
+ interp_col[0] |= R300_RS_COL_PTR(rs_col_count);
+ if (count == 3)
+ interp_col[0] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGB1);
+ rs_col_count += count;
+ }
+ else
+ interp_col[0] = R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
+
+ if (InputsRead & FRAG_BIT_COL1) {
+ count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
+ if (count == 3)
+ interp_col[1] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGB1);
+ interp_col[1] |= R300_RS_COL_PTR(1);
+ rs_col_count += count;
+ }
+
+
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
- | interp_magic[i];
+ int swiz;
+
+ /* with TCL we always seem to route 4 components */
+ if (hw_tcl_on)
+ count = 4;
+ else
+ count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size;
+ r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = interp_col[i] | rs_tex_count;
+ switch(count) {
+ case 4:swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break;
+ case 3: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
+ default:
+ case 1:
+ case 2: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
+ };
+
+ r300->hw.ri.cmd[R300_RI_INTERP_0 + i] |= swiz;
+
r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] = 0;
if (InputsRead & (FRAG_BIT_TEX0 << i)) {
+
+ rs_tex_count += count;
+
//assert(r300->state.texture.tc_count != 0);
r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] |= R300_RS_INST_TEX_CN_WRITE | i /* source INTERP */
| (fp_reg << R300_RS_INST_TEX_ADDR_SHIFT);
@@ -1560,10 +1594,6 @@ static void r300SetupRSUnit(GLcontext * ctx)
WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
}
}
- /* Need to count all coords enabled at vof */
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
- in_texcoords++;
- }
}
if (InputsRead & FRAG_BIT_COL0) {
@@ -1589,18 +1619,18 @@ static void r300SetupRSUnit(GLcontext * ctx)
}
/* Need at least one. This might still lock as the values are undefined... */
- if (in_texcoords == 0 && col_interp_nr == 0) {
+ if (rs_tex_count == 0 && col_interp_nr == 0) {
r300->hw.rr.cmd[R300_RR_INST_0] |= R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | (fp_reg++ << R300_RS_INST_COL_ADDR_SHIFT);
col_interp_nr++;
}
- r300->hw.rc.cmd[1] = 0 | ((in_texcoords << 2) << R300_IT_COUNT_SHIFT)
+ r300->hw.rc.cmd[1] = 0 | (rs_tex_count << R300_IT_COUNT_SHIFT)
| (col_interp_nr << R300_IC_COUNT_SHIFT)
| R300_HIRES_EN;
assert(high_rr >= 0);
r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
- r300->hw.rc.cmd[2] = 0xC0 | high_rr;
+ r300->hw.rc.cmd[2] = high_rr;
if (InputsRead)
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
@@ -2354,7 +2384,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa)
(char *)ctx->FragmentProgram._Current;
int i, k;
- if (!fp) /* should only happen once, just after context is created */
+ if (!fp) /* should only happenen once, just after context is created */
return;
r500TranslateFragmentShader(rmesa, fp);
diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c
index 699499d7cc..15e66317a9 100644
--- a/src/mesa/drivers/dri/r300/r300_swtcl.c
+++ b/src/mesa/drivers/dri/r300/r300_swtcl.c
@@ -78,36 +78,6 @@ do { \
rmesa->swtcl.vertex_attr_count++; \
} while (0)
-/* this differs from the VIR0 in emit.c - TODO merge them using another option */
-static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
- int *inputs, GLint * tab, GLuint nr)
-{
- GLuint i, dw;
-
- /* type, inputs, stop bit, size */
- for (i = 0; i < nr; i += 2) {
- /* make sure input is valid, would lockup the gpu */
- assert(inputs[tab[i]] != -1);
- dw = (R300_SIGNED |
- (inputs[tab[i]] << R300_DST_VEC_LOC_SHIFT) |
- (attribptr[tab[i]]->size - 1)) << R300_DATA_TYPE_0_SHIFT;
- if (i + 1 == nr) {
- dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
- } else {
- assert(inputs[tab[i + 1]] != -1);
- dw |= (R300_SIGNED |
- (inputs[tab[i + 1]] << R300_DST_VEC_LOC_SHIFT) |
- (attribptr[tab[i + 1]]->size - 1)) << R300_DATA_TYPE_1_SHIFT;
- if (i + 2 == nr) {
- dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
- }
- }
- dst[i >> 1] = dw;
- }
-
- return (nr + 1) >> 1;
-}
-
static void r300SetVertexFormat( GLcontext *ctx )
{
r300ContextPtr rmesa = R300_CONTEXT( ctx );
@@ -123,6 +93,7 @@ static void r300SetVertexFormat( GLcontext *ctx )
GLint tab[VERT_ATTRIB_MAX];
int swizzle[VERT_ATTRIB_MAX][4];
GLuint i, nr;
+ GLuint sz, vap_fmt_1 = 0;
DECLARE_RENDERINPUTS(render_inputs_bitset);
RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset);
@@ -145,14 +116,15 @@ static void r300SetVertexFormat( GLcontext *ctx )
* build up a hardware vertex.
*/
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POS)) {
- vap_vte_cntl |= R300_VTX_W0_FMT;
+ sz = VB->AttribPtr[VERT_ATTRIB_POS]->size;
InputsRead |= 1 << VERT_ATTRIB_POS;
OutputsWritten |= 1 << VERT_RESULT_HPOS;
- EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F );
- } else
+ EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_1F + sz - 1 );
+ offset = sz;
+ } else {
+ offset = 4;
EMIT_PAD(4 * sizeof(float));
-
- offset = 4;
+ }
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POINTSIZE )) {
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F );
@@ -161,18 +133,19 @@ static void r300SetVertexFormat( GLcontext *ctx )
}
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR0)) {
+ sz = VB->AttribPtr[VERT_ATTRIB_COLOR0]->size;
rmesa->swtcl.coloroffset = offset;
InputsRead |= 1 << VERT_ATTRIB_COLOR0;
OutputsWritten |= 1 << VERT_RESULT_COL0;
- EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4F );
+ EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_1F + sz - 1 );
+ offset += sz;
}
- offset += 4;
-
rmesa->swtcl.specoffset = 0;
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ sz = VB->AttribPtr[VERT_ATTRIB_COLOR1]->size;
rmesa->swtcl.specoffset = offset;
- EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4F );
+ EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_1F + sz - 1 );
InputsRead |= 1 << VERT_ATTRIB_COLOR1;
OutputsWritten |= 1 << VERT_RESULT_COL1;
}
@@ -182,9 +155,11 @@ static void r300SetVertexFormat( GLcontext *ctx )
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
+ sz = VB->TexCoordPtr[i]->size;
InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i);
OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i);
- EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_4F );
+ EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_1F + sz - 1 );
+ vap_fmt_1 |= sz << (3 * i);
}
}
}
@@ -243,7 +218,7 @@ static void r300SetVertexFormat( GLcontext *ctx )
R300_STATECHANGE(rmesa, vof);
rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten);
+ rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_fmt_1;
rmesa->swtcl.vertex_size =
_tnl_install_attrs( ctx,
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 0f716a0b70..d840e22742 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -827,6 +827,9 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
return NULL;
}
+ if (getenv("R300_NO_TCL"))
+ screen->chip_flags &= ~RADEON_CHIPSET_TCL;
+
if (screen->chip_family <= CHIP_FAMILY_RS200)
screen->chip_flags |= RADEON_CLASS_R100;
else if (screen->chip_family <= CHIP_FAMILY_RV280)
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-10 14:42:47 +0000