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path: root/src/gallium/drivers/nv20/nv20_state_emit.c
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Diffstat (limited to 'src/gallium/drivers/nv20/nv20_state_emit.c')
-rw-r--r--src/gallium/drivers/nv20/nv20_state_emit.c88
1 files changed, 45 insertions, 43 deletions
diff --git a/src/gallium/drivers/nv20/nv20_state_emit.c b/src/gallium/drivers/nv20/nv20_state_emit.c
index d0772c527b..5265bf3a31 100644
--- a/src/gallium/drivers/nv20/nv20_state_emit.c
+++ b/src/gallium/drivers/nv20/nv20_state_emit.c
@@ -6,15 +6,17 @@ static void nv20_state_emit_blend(struct nv20_context* nv20)
{
struct nv20_blend_state *b = nv20->blend;
- BEGIN_RING(kelvin, NV10TCL_DITHER_ENABLE, 1);
+ BEGIN_RING(kelvin, NV20TCL_DITHER_ENABLE, 1);
OUT_RING (b->d_enable);
- BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_ENABLE, 3);
+ BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
OUT_RING (b->b_enable);
+
+ BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_SRC, 2);
OUT_RING (b->b_srcfunc);
OUT_RING (b->b_dstfunc);
- BEGIN_RING(kelvin, NV10TCL_COLOR_MASK, 1);
+ BEGIN_RING(kelvin, NV20TCL_COLOR_MASK, 1);
OUT_RING (b->c_mask);
}
@@ -22,7 +24,7 @@ static void nv20_state_emit_blend_color(struct nv20_context* nv20)
{
struct pipe_blend_color *c = nv20->blend_color;
- BEGIN_RING(kelvin, NV10TCL_BLEND_COLOR, 1);
+ BEGIN_RING(kelvin, NV20TCL_BLEND_COLOR, 1);
OUT_RING ((float_to_ubyte(c->color[3]) << 24)|
(float_to_ubyte(c->color[0]) << 16)|
(float_to_ubyte(c->color[1]) << 8) |
@@ -33,28 +35,28 @@ static void nv20_state_emit_rast(struct nv20_context* nv20)
{
struct nv20_rasterizer_state *r = nv20->rast;
- BEGIN_RING(kelvin, NV10TCL_SHADE_MODEL, 2);
+ BEGIN_RING(kelvin, NV20TCL_SHADE_MODEL, 2);
OUT_RING (r->shade_model);
OUT_RING (r->line_width);
- BEGIN_RING(kelvin, NV10TCL_POINT_SIZE, 1);
+ BEGIN_RING(kelvin, NV20TCL_POINT_SIZE, 1);
OUT_RING (r->point_size);
- BEGIN_RING(kelvin, NV10TCL_POLYGON_MODE_FRONT, 2);
+ BEGIN_RING(kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
OUT_RING (r->poly_mode_front);
OUT_RING (r->poly_mode_back);
- BEGIN_RING(kelvin, NV10TCL_CULL_FACE, 2);
+ BEGIN_RING(kelvin, NV20TCL_CULL_FACE, 2);
OUT_RING (r->cull_face);
OUT_RING (r->front_face);
- BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 2);
+ BEGIN_RING(kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 2);
OUT_RING (r->line_smooth_en);
OUT_RING (r->poly_smooth_en);
- BEGIN_RING(kelvin, NV10TCL_CULL_FACE_ENABLE, 1);
+ BEGIN_RING(kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
OUT_RING (r->cull_face_en);
}
@@ -62,29 +64,29 @@ static void nv20_state_emit_dsa(struct nv20_context* nv20)
{
struct nv20_depth_stencil_alpha_state *d = nv20->dsa;
- BEGIN_RING(kelvin, NV10TCL_DEPTH_FUNC, 1);
+ BEGIN_RING(kelvin, NV20TCL_DEPTH_FUNC, 1);
OUT_RING (d->depth.func);
- BEGIN_RING(kelvin, NV10TCL_DEPTH_WRITE_ENABLE, 1);
+ BEGIN_RING(kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
OUT_RING (d->depth.write_enable);
- BEGIN_RING(kelvin, NV10TCL_DEPTH_TEST_ENABLE, 1);
+ BEGIN_RING(kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
OUT_RING (d->depth.test_enable);
#if 0
- BEGIN_RING(kelvin, NV10TCL_STENCIL_ENABLE, 1);
+ BEGIN_RING(kelvin, NV20TCL_STENCIL_ENABLE, 1);
OUT_RING (d->stencil.enable);
- BEGIN_RING(kelvin, NV10TCL_STENCIL_MASK, 7);
+ BEGIN_RING(kelvin, NV20TCL_STENCIL_MASK, 7);
OUT_RINGp ((uint32_t *)&(d->stencil.wmask), 7);
#endif
- BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_ENABLE, 1);
+ BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
OUT_RING (d->alpha.enabled);
- BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_FUNC, 1);
+ BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_FUNC, 1);
OUT_RING (d->alpha.func);
- BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_REF, 1);
+ BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_REF, 1);
OUT_RING (d->alpha.ref);
}
@@ -94,9 +96,9 @@ static void nv20_state_emit_viewport(struct nv20_context* nv20)
static void nv20_state_emit_scissor(struct nv20_context* nv20)
{
- // XXX this is so not working
+ /* NV20TCL_SCISSOR_* is probably a software method */
/* struct pipe_scissor_state *s = nv20->scissor;
- BEGIN_RING(kelvin, NV10TCL_SCISSOR_HORIZ, 2);
+ BEGIN_RING(kelvin, NV20TCL_SCISSOR_HORIZ, 2);
OUT_RING (((s->maxx - s->minx) << 16) | s->minx);
OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/
}
@@ -126,25 +128,25 @@ static void nv20_state_emit_framebuffer(struct nv20_context* nv20)
zeta = fb->zsbuf;
}
- rt_format = NV10TCL_RT_FORMAT_TYPE_LINEAR;
+ rt_format = NV20TCL_RT_FORMAT_TYPE_LINEAR | 0x20;
switch (colour_format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case 0:
- rt_format |= NV10TCL_RT_FORMAT_COLOR_A8R8G8B8;
+ rt_format |= NV20TCL_RT_FORMAT_COLOR_A8R8G8B8;
break;
case PIPE_FORMAT_R5G6B5_UNORM:
- rt_format |= NV10TCL_RT_FORMAT_COLOR_R5G6B5;
+ rt_format |= NV20TCL_RT_FORMAT_COLOR_R5G6B5;
break;
default:
assert(0);
}
if (zeta) {
- BEGIN_RING(kelvin, NV10TCL_RT_PITCH, 1);
+ BEGIN_RING(kelvin, NV20TCL_RT_PITCH, 1);
OUT_RING (rt->stride | (zeta->stride << 16));
} else {
- BEGIN_RING(kelvin, NV10TCL_RT_PITCH, 1);
+ BEGIN_RING(kelvin, NV20TCL_RT_PITCH, 1);
OUT_RING (rt->stride | (rt->stride << 16));
}
@@ -155,13 +157,13 @@ static void nv20_state_emit_framebuffer(struct nv20_context* nv20)
nv20->zeta = zeta->buffer;
}
- BEGIN_RING(kelvin, NV10TCL_RT_HORIZ, 3);
+ BEGIN_RING(kelvin, NV20TCL_RT_HORIZ, 3);
OUT_RING ((w << 16) | 0);
OUT_RING ((h << 16) | 0);
OUT_RING (rt_format);
- BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2);
- OUT_RING (((w - 1) << 16) | 0 | 0x08000800);
- OUT_RING (((h - 1) << 16) | 0 | 0x08000800);
+ BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 2);
+ OUT_RING (((w - 1) << 16) | 0);
+ OUT_RING (((h - 1) << 16) | 0);
}
static void nv20_vertex_layout(struct nv20_context *nv20)
@@ -317,17 +319,17 @@ nv20_emit_hw_state(struct nv20_context *nv20)
*/
/* Render target */
-// XXX figre out who's who for NV10TCL_DMA_* and fill accordingly
-// BEGIN_RING(kelvin, NV10TCL_DMA_COLOR0, 1);
-// OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
- BEGIN_RING(kelvin, NV10TCL_COLOR_OFFSET, 1);
+/* XXX figre out who's who for NV10TCL_DMA_* and fill accordingly
+ * BEGIN_RING(kelvin, NV20TCL_DMA_COLOR0, 1);
+ * OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); */
+ BEGIN_RING(kelvin, NV20TCL_COLOR_OFFSET, 1);
OUT_RELOCl(nv20->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
if (nv20->zeta) {
-// XXX
-// BEGIN_RING(kelvin, NV10TCL_DMA_ZETA, 1);
-// OUT_RELOCo(nv20->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
- BEGIN_RING(kelvin, NV10TCL_ZETA_OFFSET, 1);
+/* XXX
+ * BEGIN_RING(kelvin, NV20TCL_DMA_ZETA, 1);
+ * OUT_RELOCo(nv20->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); */
+ BEGIN_RING(kelvin, NV20TCL_ZETA_OFFSET, 1);
OUT_RELOCl(nv20->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
/* XXX for when we allocate LMA on nv17 */
/* BEGIN_RING(kelvin, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1);
@@ -335,23 +337,23 @@ nv20_emit_hw_state(struct nv20_context *nv20)
}
/* Vertex buffer */
- BEGIN_RING(kelvin, NV10TCL_DMA_VTXBUF0, 1);
+ BEGIN_RING(kelvin, NV20TCL_DMA_VTXBUF0, 1);
OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
- BEGIN_RING(kelvin, NV10TCL_COLOR_OFFSET, 1);
+ BEGIN_RING(kelvin, NV20TCL_COLOR_OFFSET, 1);
OUT_RELOCl(nv20->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
/* Texture images */
for (i = 0; i < 2; i++) {
if (!(nv20->fp_samplers & (1 << i)))
continue;
- BEGIN_RING(kelvin, NV10TCL_TX_OFFSET(i), 1);
+ BEGIN_RING(kelvin, NV20TCL_TX_OFFSET(i), 1);
OUT_RELOCl(nv20->tex[i].buffer, 0, NOUVEAU_BO_VRAM |
NOUVEAU_BO_GART | NOUVEAU_BO_RD);
- BEGIN_RING(kelvin, NV10TCL_TX_FORMAT(i), 1);
+ BEGIN_RING(kelvin, NV20TCL_TX_FORMAT(i), 1);
OUT_RELOCd(nv20->tex[i].buffer, nv20->tex[i].format,
NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
- NOUVEAU_BO_OR, NV10TCL_TX_FORMAT_DMA0,
- NV10TCL_TX_FORMAT_DMA1);
+ NOUVEAU_BO_OR, NV20TCL_TX_FORMAT_DMA0,
+ NV20TCL_TX_FORMAT_DMA1);
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-18 08:41:44 +0000