diff options
Diffstat (limited to 'src/gallium/drivers/nv50')
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_clear.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_context.h | 22 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_program.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_screen.c | 282 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_screen.h | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_state.c | 71 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_state_validate.c | 12 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_surface.c | 31 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_tex.c | 202 | ||||
| -rw-r--r-- | src/gallium/drivers/nv50/nv50_texture.h | 32 |
10 files changed, 395 insertions, 267 deletions
diff --git a/src/gallium/drivers/nv50/nv50_clear.c b/src/gallium/drivers/nv50/nv50_clear.c index 8afc95c9fc..5447904e9c 100644 --- a/src/gallium/drivers/nv50/nv50_clear.c +++ b/src/gallium/drivers/nv50/nv50_clear.c @@ -35,7 +35,10 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, struct nouveau_grobj *tesla = nv50->screen->tesla; struct pipe_framebuffer_state *fb = &nv50->framebuffer; unsigned mode = 0, i; + const unsigned dirty = nv50->dirty; + /* don't need NEW_BLEND, NV50TCL_COLOR_MASK doesn't affect CLEAR_BUFFERS */ + nv50->dirty &= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR; if (!nv50_state_validate(nv50, 64)) return; @@ -64,5 +67,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, BEGIN_RING(chan, tesla, NV50TCL_CLEAR_BUFFERS, 1); OUT_RING (chan, (i << 6) | 0x3c); } + nv50->dirty = dirty; } diff --git a/src/gallium/drivers/nv50/nv50_context.h b/src/gallium/drivers/nv50/nv50_context.h index 1743f6fb39..bc7831d9ac 100644 --- a/src/gallium/drivers/nv50/nv50_context.h +++ b/src/gallium/drivers/nv50/nv50_context.h @@ -72,12 +72,23 @@ struct nv50_sampler_stateobj { unsigned tsc[8]; }; +struct nv50_sampler_view { + struct pipe_sampler_view pipe; + uint32_t tic[8]; +}; + struct nv50_vtxelt_stateobj { struct pipe_vertex_element pipe[16]; unsigned num_elements; uint32_t hw[16]; }; +static INLINE struct nv50_sampler_view * +nv50_sampler_view(struct pipe_sampler_view *view) +{ + return (struct nv50_sampler_view *)view; +} + static INLINE unsigned get_tile_height(uint32_t tile_mode) { @@ -126,7 +137,7 @@ struct nv50_state { struct nouveau_stateobj *hw[64]; uint64_t hw_dirty; - unsigned miptree_nr[PIPE_SHADER_TYPES]; + unsigned sampler_view_nr[3]; struct nouveau_stateobj *vtxbuf; struct nouveau_stateobj *vtxattr; unsigned vtxelt_nr; @@ -158,10 +169,10 @@ struct nv50_context { struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS]; unsigned vtxbuf_nr; struct nv50_vtxelt_stateobj *vtxelt; - struct nv50_sampler_stateobj *sampler[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS]; - unsigned sampler_nr[PIPE_SHADER_TYPES]; - struct nv50_miptree *miptree[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS]; - unsigned miptree_nr[PIPE_SHADER_TYPES]; + struct nv50_sampler_stateobj *sampler[3][PIPE_MAX_SAMPLERS]; + unsigned sampler_nr[3]; + struct pipe_sampler_view *sampler_views[3][PIPE_MAX_SAMPLERS]; + unsigned sampler_view_nr[3]; unsigned vbo_fifo; }; @@ -243,6 +254,7 @@ extern void nv50_so_init_sifc(struct nv50_context *nv50, unsigned offset, unsigned size); /* nv50_tex.c */ +extern boolean nv50_tex_construct(struct nv50_sampler_view *view); extern void nv50_tex_relocs(struct nv50_context *); extern struct nouveau_stateobj *nv50_tex_validate(struct nv50_context *); diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c index c857816b31..d7e06c9327 100644 --- a/src/gallium/drivers/nv50/nv50_program.c +++ b/src/gallium/drivers/nv50/nv50_program.c @@ -3762,7 +3762,7 @@ nv50_program_tx_prep(struct nv50_pc *pc) p->cfg.in[n].hw = rid = aid; i = p->cfg.in[n].id; - if (p->info.input_semantic_name[n] == + if (p->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE) { load_frontfacing(pc, &pc->attr[i * 4]); continue; diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index adf0d3b374..1a4606d9e2 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -109,7 +109,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, int param) case PIPE_CAP_TWO_SIDED_STENCIL: return 1; case PIPE_CAP_GLSL: - return 0; + return 1; case PIPE_CAP_ANISOTROPIC_FILTER: return 1; case PIPE_CAP_POINT_SPRITE: @@ -190,8 +190,6 @@ nv50_screen_destroy(struct pipe_screen *pscreen) nouveau_bo_ref(NULL, &screen->tic); if (screen->tsc) nouveau_bo_ref(NULL, &screen->tsc); - if (screen->static_init) - so_ref(NULL, &screen->static_init); nouveau_notifier_free(&screen->sync); nouveau_grobj_free(&screen->tesla); @@ -204,16 +202,65 @@ nv50_screen_destroy(struct pipe_screen *pscreen) FREE(screen); } +#define BGN_RELOC(ch, bo, gr, m, n, fl) \ + OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0) + +void +nv50_screen_relocs(struct nv50_screen *screen) +{ + struct nouveau_channel *chan = screen->base.channel; + struct nouveau_grobj *tesla = screen->tesla; + unsigned i; + const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY; + + MARK_RING (chan, 28, 26); + + /* cause grobj autobind */ + BEGIN_RING(chan, tesla, 0x0100, 1); + OUT_RING (chan, 0); + + BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl); + OUT_RELOCh(chan, screen->tic, 0, rl); + OUT_RELOCl(chan, screen->tic, 0, rl); + + BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl); + OUT_RELOCh(chan, screen->tsc, 0, rl); + OUT_RELOCl(chan, screen->tsc, 0, rl); + + BGN_RELOC (chan, screen->constbuf_misc[0], + tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl); + OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl); + OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl); + OUT_RELOC (chan, screen->constbuf_misc[0], + (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0); + + BGN_RELOC (chan, screen->constbuf_misc[0], + tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl); + OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl); + OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl); + OUT_RELOC (chan, screen->constbuf_misc[0], + (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0); + + for (i = 0; i < 3; ++i) { + BGN_RELOC (chan, screen->constbuf_parm[i], + tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl); + OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl); + OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl); + OUT_RELOC (chan, screen->constbuf_parm[i], + ((NV50_CB_PVP + i) << 16) | 0x0800, rl, 0, 0); + } +} + struct pipe_screen * nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) { struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen); struct nouveau_channel *chan; struct pipe_screen *pscreen; - struct nouveau_stateobj *so; unsigned chipset = dev->chipset; unsigned tesla_class = 0; int ret, i; + const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; if (!screen) return NULL; @@ -296,64 +343,58 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) } /* Static M2MF init */ - so = so_new(1, 3, 0); - so_method(so, screen->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3); - so_data (so, screen->sync->handle); - so_data (so, chan->vram->handle); - so_data (so, chan->vram->handle); - so_emit(chan, so); - so_ref (NULL, &so); + BEGIN_RING(chan, screen->m2mf, + NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3); + OUT_RING (chan, screen->sync->handle); + OUT_RING (chan, chan->vram->handle); + OUT_RING (chan, chan->vram->handle); /* Static 2D init */ - so = so_new(4, 7, 0); - so_method(so, screen->eng2d, NV50_2D_DMA_NOTIFY, 4); - so_data (so, screen->sync->handle); - so_data (so, chan->vram->handle); - so_data (so, chan->vram->handle); - so_data (so, chan->vram->handle); - so_method(so, screen->eng2d, NV50_2D_OPERATION, 1); - so_data (so, NV50_2D_OPERATION_SRCCOPY); - so_method(so, screen->eng2d, NV50_2D_CLIP_ENABLE, 1); - so_data (so, 0); - so_method(so, screen->eng2d, 0x0888, 1); - so_data (so, 1); - so_emit(chan, so); - so_ref(NULL, &so); + BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4); + OUT_RING (chan, screen->sync->handle); + OUT_RING (chan, chan->vram->handle); + OUT_RING (chan, chan->vram->handle); + OUT_RING (chan, chan->vram->handle); + BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1); + OUT_RING (chan, NV50_2D_OPERATION_SRCCOPY); + BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1); + OUT_RING (chan, 0); + BEGIN_RING(chan, screen->eng2d, 0x0888, 1); + OUT_RING (chan, 1); /* Static tesla init */ - so = so_new(47, 95, 24); - - so_method(so, screen->tesla, NV50TCL_COND_MODE, 1); - so_data (so, NV50TCL_COND_MODE_ALWAYS); - so_method(so, screen->tesla, NV50TCL_DMA_NOTIFY, 1); - so_data (so, screen->sync->handle); - so_method(so, screen->tesla, NV50TCL_DMA_ZETA, 11); + BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1); + OUT_RING (chan, NV50TCL_COND_MODE_ALWAYS); + BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1); + OUT_RING (chan, screen->sync->handle); + BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11); for (i = 0; i < 11; i++) - so_data(so, chan->vram->handle); - so_method(so, screen->tesla, NV50TCL_DMA_COLOR(0), - NV50TCL_DMA_COLOR__SIZE); + OUT_RING (chan, chan->vram->handle); + BEGIN_RING(chan, screen->tesla, + NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE); for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++) - so_data(so, chan->vram->handle); - so_method(so, screen->tesla, NV50TCL_RT_CONTROL, 1); - so_data (so, 1); + OUT_RING (chan, chan->vram->handle); + + BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1); + OUT_RING (chan, 1); /* activate all 32 lanes (threads) in a warp */ - so_method(so, screen->tesla, NV50TCL_WARP_HALVES, 1); - so_data (so, 0x2); - so_method(so, screen->tesla, 0x1400, 1); - so_data (so, 0xf); + BEGIN_RING(chan, screen->tesla, NV50TCL_WARP_HALVES, 1); + OUT_RING (chan, 2); + BEGIN_RING(chan, screen->tesla, 0x1400, 1); + OUT_RING (chan, 0xf); /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */ for (i = 0; i < 3; ++i) { - so_method(so, screen->tesla, NV50TCL_TEX_LIMITS(i), 1); - so_data (so, 0x54); + BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1); + OUT_RING (chan, 0x54); } /* origin is top left (set to 1 for bottom left) */ - so_method(so, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1); - so_data (so, 0); - so_method(so, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1); - so_data (so, 8); + BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1); + OUT_RING (chan, 0); + BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1); + OUT_RING (chan, 8); /* constant buffers for immediates and VP/FP parameters */ ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4, @@ -362,6 +403,14 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) nv50_screen_destroy(pscreen); return NULL; } + BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); + OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl); + OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl); + OUT_RING (chan, (NV50_CB_PMISC << 16) | 0x0200); + BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); + OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl); + OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl); + OUT_RING (chan, (NV50_CB_AUX << 16) | 0x0200); for (i = 0; i < 3; i++) { ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (256 * 4) * 4, @@ -370,6 +419,10 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) nv50_screen_destroy(pscreen); return NULL; } + BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); + OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl); + OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl); + OUT_RING (chan, ((NV50_CB_PVP + i) << 16) | 0x0800); } if (nouveau_resource_init(&screen->immd_heap[0], 0, 128) || @@ -381,118 +434,67 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) return NULL; } - /* - // map constant buffers: - // B = buffer ID (maybe more than 1 byte) - // N = CB index used in shader instruction - // P = program type (0 = VP, 2 = GP, 3 = FP) - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x000BBNP1); - */ - - so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); - so_reloc (so, screen->constbuf_misc[0], 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->constbuf_misc[0], 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, (NV50_CB_PMISC << 16) | 0x00000200); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000001 | (NV50_CB_PMISC << 12)); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000021 | (NV50_CB_PMISC << 12)); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000031 | (NV50_CB_PMISC << 12)); - - /* bind auxiliary constbuf to immediate data bo */ - so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); - so_reloc (so, screen->constbuf_misc[0], (128 * 4) * 4, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->constbuf_misc[0], (128 * 4) * 4, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, (NV50_CB_AUX << 16) | 0x00000200); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000201 | (NV50_CB_AUX << 12)); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000221 | (NV50_CB_AUX << 12)); - - so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); - so_reloc (so, screen->constbuf_parm[PIPE_SHADER_VERTEX], 0, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->constbuf_parm[PIPE_SHADER_VERTEX], 0, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, (NV50_CB_PVP << 16) | 0x00000800); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000101 | (NV50_CB_PVP << 12)); - - so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); - so_reloc (so, screen->constbuf_parm[PIPE_SHADER_GEOMETRY], 0, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->constbuf_parm[PIPE_SHADER_GEOMETRY], 0, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, (NV50_CB_PGP << 16) | 0x00000800); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000121 | (NV50_CB_PGP << 12)); - - so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); - so_reloc (so, screen->constbuf_parm[PIPE_SHADER_FRAGMENT], 0, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->constbuf_parm[PIPE_SHADER_FRAGMENT], 0, - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, (NV50_CB_PFP << 16) | 0x00000800); - so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1); - so_data (so, 0x00000131 | (NV50_CB_PFP << 12)); - - ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, PIPE_SHADER_TYPES*32*32, + ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4), &screen->tic); if (ret) { nv50_screen_destroy(pscreen); return NULL; } + BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3); + OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RING (chan, 3 * 32 - 1); - so_method(so, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3); - so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, PIPE_SHADER_TYPES * 32 - 1); - - ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, PIPE_SHADER_TYPES*32*32, + ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4), &screen->tsc); if (ret) { nv50_screen_destroy(pscreen); return NULL; } - - so_method(so, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3); - so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0); - so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0); - so_data (so, 0x00000000); /* ignored if TSC_LINKED (0x1234) = 1 */ - + BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3); + OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RING (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */ + + /* map constant buffers: + * B = buffer ID (maybe more than 1 byte) + * N = CB index used in shader instruction + * P = program type (0 = VP, 2 = GP, 3 = FP) + * SET_PROGRAM_CB = 0x000BBNP1 + */ + BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8); + /* bind immediate buffer */ + OUT_RING (chan, 0x001 | (NV50_CB_PMISC << 12)); + OUT_RING (chan, 0x021 | (NV50_CB_PMISC << 12)); + OUT_RING (chan, 0x031 | (NV50_CB_PMISC << 12)); + /* bind auxiliary constbuf to immediate data bo */ + OUT_RING (chan, 0x201 | (NV50_CB_AUX << 12)); + OUT_RING (chan, 0x221 | (NV50_CB_AUX << 12)); + /* bind parameter buffers */ + OUT_RING (chan, 0x101 | (NV50_CB_PVP << 12)); + OUT_RING (chan, 0x121 | (NV50_CB_PGP << 12)); + OUT_RING (chan, 0x131 | (NV50_CB_PFP << 12)); /* Vertex array limits - max them out */ for (i = 0; i < 16; i++) { - so_method(so, screen->tesla, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2); - so_data (so, 0x000000ff); - so_data (so, 0xffffffff); + BEGIN_RING(chan, screen->tesla, + NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2); + OUT_RING (chan, 0x000000ff); + OUT_RING (chan, 0xffffffff); } - so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2); - so_data (so, fui(0.0)); - so_data (so, fui(1.0)); + BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2); + OUT_RINGf (chan, 0.0f); + OUT_RINGf (chan, 1.0f); /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */ - so_method(so, screen->tesla, NV50TCL_LINKED_TSC, 1); - so_data (so, 1); + BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1); + OUT_RING (chan, 1); - so_method(so, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1); - so_data (so, 1); /* default edgeflag to TRUE */ + BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1); + OUT_RING (chan, 1); /* default edgeflag to TRUE */ - so_emit(chan, so); - so_ref (so, &screen->static_init); - so_ref (NULL, &so); - nouveau_pushbuf_flush(chan, 0); + FIRE_RING (chan); screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE); return pscreen; diff --git a/src/gallium/drivers/nv50/nv50_screen.h b/src/gallium/drivers/nv50/nv50_screen.h index ec19ea655b..15bd4eed39 100644 --- a/src/gallium/drivers/nv50/nv50_screen.h +++ b/src/gallium/drivers/nv50/nv50_screen.h @@ -27,8 +27,6 @@ struct nv50_screen { struct nouveau_bo *tic; struct nouveau_bo *tsc; - struct nouveau_stateobj *static_init; - boolean force_push; }; @@ -38,4 +36,6 @@ nv50_screen(struct pipe_screen *screen) return (struct nv50_screen *)screen; } +extern void nv50_screen_relocs(struct nv50_screen *); + #endif diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c index b0e5552eff..c162808928 100644 --- a/src/gallium/drivers/nv50/nv50_state.c +++ b/src/gallium/drivers/nv50/nv50_state.c @@ -238,6 +238,9 @@ nv50_sampler_state_create(struct pipe_context *pipe, return (void *)sso; } +/* type == 0 for VPs, 1 for GPs, 2 for FPs, which is how the + * relevant tesla methods are indexed (NV50TCL_BIND_TSC etc.) + */ static INLINE void nv50_sampler_state_bind(struct pipe_context *pipe, unsigned type, unsigned nr, void **sampler) @@ -253,13 +256,13 @@ nv50_sampler_state_bind(struct pipe_context *pipe, unsigned type, static void nv50_vp_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **s) { - nv50_sampler_state_bind(pipe, PIPE_SHADER_VERTEX, nr, s); + nv50_sampler_state_bind(pipe, 0, nr, s); } static void nv50_fp_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **s) { - nv50_sampler_state_bind(pipe, PIPE_SHADER_FRAGMENT, nr, s); + nv50_sampler_state_bind(pipe, 2, nr, s); } static void @@ -269,35 +272,69 @@ nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso) } static INLINE void -nv50_set_sampler_texture(struct pipe_context *pipe, unsigned type, - unsigned nr, struct pipe_texture **pt) +nv50_set_sampler_views(struct pipe_context *pipe, unsigned p, + unsigned nr, + struct pipe_sampler_view **views) { struct nv50_context *nv50 = nv50_context(pipe); unsigned i; for (i = 0; i < nr; i++) - pipe_texture_reference((void *)&nv50->miptree[type][i], pt[i]); - for (i = nr; i < nv50->miptree_nr[type]; i++) - pipe_texture_reference((void *)&nv50->miptree[type][i], NULL); + pipe_sampler_view_reference(&nv50->sampler_views[p][i], + views[i]); + + for (i = nr; i < nv50->sampler_view_nr[p]; i++) + pipe_sampler_view_reference(&nv50->sampler_views[p][i], NULL); - nv50->miptree_nr[type] = nr; + nv50->sampler_view_nr[p] = nr; nv50->dirty |= NV50_NEW_TEXTURE; } static void -nv50_set_vp_sampler_textures(struct pipe_context *pipe, - unsigned nr, struct pipe_texture **pt) +nv50_set_vp_sampler_views(struct pipe_context *pipe, + unsigned nr, + struct pipe_sampler_view **views) { - nv50_set_sampler_texture(pipe, PIPE_SHADER_VERTEX, nr, pt); + nv50_set_sampler_views(pipe, 0, nr, views); } static void -nv50_set_fp_sampler_textures(struct pipe_context *pipe, - unsigned nr, struct pipe_texture **pt) +nv50_set_fp_sampler_views(struct pipe_context *pipe, + unsigned nr, + struct pipe_sampler_view **views) { - nv50_set_sampler_texture(pipe, PIPE_SHADER_FRAGMENT, nr, pt); + nv50_set_sampler_views(pipe, 2, nr, views); } +static void +nv50_sampler_view_destroy(struct pipe_context *pipe, + struct pipe_sampler_view *view) +{ + pipe_texture_reference(&view->texture, NULL); + FREE(nv50_sampler_view(view)); +} + +static struct pipe_sampler_view * +nv50_create_sampler_view(struct pipe_context *pipe, + struct pipe_texture *texture, + const struct pipe_sampler_view *templ) +{ + struct nv50_sampler_view *view = CALLOC_STRUCT(nv50_sampler_view); + + view->pipe = *templ; + view->pipe.reference.count = 1; + view->pipe.texture = NULL; + pipe_texture_reference(&view->pipe.texture, texture); + view->pipe.context = pipe; + + if (!nv50_tex_construct(view)) { + nv50_sampler_view_destroy(pipe, &view->pipe); + return NULL; + } + return &view->pipe; +} + + static void * nv50_rasterizer_state_create(struct pipe_context *pipe, const struct pipe_rasterizer_state *cso) @@ -765,8 +802,10 @@ nv50_init_state_functions(struct nv50_context *nv50) nv50->pipe.delete_sampler_state = nv50_sampler_state_delete; nv50->pipe.bind_fragment_sampler_states = nv50_fp_sampler_state_bind; nv50->pipe.bind_vertex_sampler_states = nv50_vp_sampler_state_bind; - nv50->pipe.set_fragment_sampler_textures = nv50_set_fp_sampler_textures; - nv50->pipe.set_vertex_sampler_textures = nv50_set_vp_sampler_textures; + nv50->pipe.set_fragment_sampler_views = nv50_set_fp_sampler_views; + nv50->pipe.set_vertex_sampler_views = nv50_set_vp_sampler_views; + nv50->pipe.create_sampler_view = nv50_create_sampler_view; + nv50->pipe.sampler_view_destroy = nv50_sampler_view_destroy; nv50->pipe.create_rasterizer_state = nv50_rasterizer_state_create; nv50->pipe.bind_rasterizer_state = nv50_rasterizer_state_bind; diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c index 2c8e7ca798..b7e355283c 100644 --- a/src/gallium/drivers/nv50/nv50_state_validate.c +++ b/src/gallium/drivers/nv50/nv50_state_validate.c @@ -310,15 +310,13 @@ validate_sampler(struct nv50_context *nv50) struct nouveau_stateobj *so; unsigned nr = 0, i; - for (i = 0; i < PIPE_SHADER_TYPES; ++i) + for (i = 0; i < 3; ++i) nr += nv50->sampler_nr[i]; - so = so_new(1 + 5 * PIPE_SHADER_TYPES, - 1 + 19 * PIPE_SHADER_TYPES + nr * 8, - PIPE_SHADER_TYPES * 2); + so = so_new(1 + 5 * 3, 1 + 19 * 3 + nr * 8, 3 * 2); - nv50_validate_samplers(nv50, so, PIPE_SHADER_VERTEX); - nv50_validate_samplers(nv50, so, PIPE_SHADER_FRAGMENT); + nv50_validate_samplers(nv50, so, 0); /* VP */ + nv50_validate_samplers(nv50, so, 2); /* FP */ so_method(so, tesla, 0x1334, 1); /* flush TSC */ so_data (so, 0); @@ -437,7 +435,7 @@ nv50_state_validate(struct nv50_context *nv50, unsigned wait_dwords) so_emit_reloc_markers(chan, nv50->state.hw[3]); /* vp */ so_emit_reloc_markers(chan, nv50->state.hw[4]); /* fp */ so_emit_reloc_markers(chan, nv50->state.hw[17]); /* vb */ - so_emit_reloc_markers(chan, nv50->screen->static_init); + nv50_screen_relocs(nv50->screen); /* No idea.. */ BEGIN_RING(chan, tesla, 0x142c, 1); diff --git a/src/gallium/drivers/nv50/nv50_surface.c b/src/gallium/drivers/nv50/nv50_surface.c index cabd148bc5..6467c48a32 100644 --- a/src/gallium/drivers/nv50/nv50_surface.c +++ b/src/gallium/drivers/nv50/nv50_surface.c @@ -28,6 +28,7 @@ #include "util/u_inlines.h" #include "util/u_tile.h" +#include "util/u_format.h" static INLINE int nv50_format(enum pipe_format format) @@ -37,10 +38,35 @@ nv50_format(enum pipe_format format) return NV50_2D_DST_FORMAT_A8R8G8B8_UNORM; case PIPE_FORMAT_B8G8R8X8_UNORM: return NV50_2D_DST_FORMAT_X8R8G8B8_UNORM; + case PIPE_FORMAT_B8G8R8A8_SRGB: + return NV50_2D_DST_FORMAT_A8R8G8B8_SRGB; + case PIPE_FORMAT_B8G8R8X8_SRGB: + return NV50_2D_DST_FORMAT_X8R8G8B8_SRGB; case PIPE_FORMAT_B5G6R5_UNORM: return NV50_2D_DST_FORMAT_R5G6B5_UNORM; + case PIPE_FORMAT_B5G5R5A1_UNORM: + return NV50_2D_DST_FORMAT_A1R5G5B5_UNORM; case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_L8_UNORM: return NV50_2D_DST_FORMAT_R8_UNORM; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + return NV50_2D_DST_FORMAT_R32G32B32A32_FLOAT; + case PIPE_FORMAT_R32G32B32_FLOAT: + return NV50_2D_DST_FORMAT_R32G32B32X32_FLOAT; + case PIPE_FORMAT_Z32_FLOAT: + return NV50_2D_DST_FORMAT_R32_FLOAT; + + /* only because we require src format == dst format: */ + case PIPE_FORMAT_R16G16_SNORM: + case PIPE_FORMAT_R16G16_UNORM: + case PIPE_FORMAT_S8Z24_UNORM: + case PIPE_FORMAT_Z24S8_UNORM: + return NV50_2D_DST_FORMAT_A8R8G8B8_UNORM; + case PIPE_FORMAT_L8A8_UNORM: + case PIPE_FORMAT_B4G4R4A4_UNORM: + return NV50_2D_DST_FORMAT_R16_UNORM; + default: return -1; } @@ -57,8 +83,11 @@ nv50_surface_set(struct nv50_screen *screen, struct pipe_surface *ps, int dst) int flags = NOUVEAU_BO_VRAM | (dst ? NOUVEAU_BO_WR : NOUVEAU_BO_RD); format = nv50_format(ps->format); - if (format < 0) + if (format < 0) { + NOUVEAU_ERR("invalid/unsupported surface format: %s\n", + util_format_name(ps->format)); return 1; + } if (!bo->tile_flags) { MARK_RING (chan, 9, 2); /* flush on lack of space or relocs */ diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c index 4c48b12cd8..85ab947c00 100644 --- a/src/gallium/drivers/nv50/nv50_tex.c +++ b/src/gallium/drivers/nv50/nv50_tex.c @@ -29,26 +29,16 @@ #include "util/u_format.h" #define _MIXED(pf, t0, t1, t2, t3, cr, cg, cb, ca, f) \ -{ \ - PIPE_FORMAT_##pf, \ +[PIPE_FORMAT_##pf] = ( \ NV50TIC_0_0_MAPR_##cr | NV50TIC_0_0_TYPER_##t0 | \ NV50TIC_0_0_MAPG_##cg | NV50TIC_0_0_TYPEG_##t1 | \ NV50TIC_0_0_MAPB_##cb | NV50TIC_0_0_TYPEB_##t2 | \ NV50TIC_0_0_MAPA_##ca | NV50TIC_0_0_TYPEA_##t3 | \ - NV50TIC_0_0_FMT_##f \ -} + NV50TIC_0_0_FMT_##f) #define _(pf, t, cr, cg, cb, ca, f) _MIXED(pf, t, t, t, t, cr, cg, cb, ca, f) -struct nv50_texture_format { - enum pipe_format pf; - uint32_t hw; -}; - -#define NV50_TEX_FORMAT_LIST_SIZE \ - (sizeof(nv50_tex_format_list) / sizeof(struct nv50_texture_format)) - -static const struct nv50_texture_format nv50_tex_format_list[] = +static const uint32_t nv50_texture_formats[PIPE_FORMAT_COUNT] = { _(B8G8R8A8_UNORM, UNORM, C2, C1, C0, C3, 8_8_8_8), _(B8G8R8A8_SRGB, UNORM, C2, C1, C0, C3, 8_8_8_8), @@ -60,10 +50,12 @@ static const struct nv50_texture_format nv50_tex_format_list[] = _(B5G6R5_UNORM, UNORM, C2, C1, C0, ONE, 5_6_5), _(L8_UNORM, UNORM, C0, C0, C0, ONE, 8), + _(L8_SRGB, UNORM, C0, C0, C0, ONE, 8), _(A8_UNORM, UNORM, ZERO, ZERO, ZERO, C0, 8), _(I8_UNORM, UNORM, C0, C0, C0, C0, 8), _(L8A8_UNORM, UNORM, C0, C0, C0, C1, 8_8), + _(L8A8_SRGB, UNORM, C0, C0, C0, C1, 8_8), _(DXT1_RGB, UNORM, C0, C1, C2, ONE, DXT1), _(DXT1_RGBA, UNORM, C0, C1, C2, C3, DXT1), @@ -81,117 +73,143 @@ static const struct nv50_texture_format nv50_tex_format_list[] = _(R16G16_UNORM, UNORM, C0, C1, ZERO, ONE, 16_16), _MIXED(Z32_FLOAT, FLOAT, UINT, UINT, UINT, C0, C0, C0, ONE, 32_DEPTH) - }; #undef _ #undef _MIXED -static int -nv50_tex_construct(struct nv50_context *nv50, struct nouveau_stateobj *so, - struct nv50_miptree *mt, int unit, unsigned p) +static INLINE uint32_t +nv50_tic_swizzle(uint32_t tc, unsigned swz) +{ + switch (swz) { + case PIPE_SWIZZLE_RED: + return (tc & NV50TIC_0_0_MAPR_MASK) >> NV50TIC_0_0_MAPR_SHIFT; + case PIPE_SWIZZLE_GREEN: + return (tc & NV50TIC_0_0_MAPG_MASK) >> NV50TIC_0_0_MAPG_SHIFT; + case PIPE_SWIZZLE_BLUE: + return (tc & NV50TIC_0_0_MAPB_MASK) >> NV50TIC_0_0_MAPB_SHIFT; + case PIPE_SWIZZLE_ALPHA: + return (tc & NV50TIC_0_0_MAPA_MASK) >> NV50TIC_0_0_MAPA_SHIFT; + case PIPE_SWIZZLE_ONE: + return 7; + case PIPE_SWIZZLE_ZERO: + default: + return 0; + } +} + +boolean +nv50_tex_construct(struct nv50_sampler_view *view) { - unsigned i; - uint32_t mode; const struct util_format_description *desc; + struct nv50_miptree *mt = nv50_miptree(view->pipe.texture); + uint32_t swz[4], *tic = view->tic; - for (i = 0; i < NV50_TEX_FORMAT_LIST_SIZE; i++) - if (nv50_tex_format_list[i].pf == mt->base.base.format) - break; - if (i == NV50_TEX_FORMAT_LIST_SIZE) - return 1; - - if (nv50->sampler[p][unit]->normalized) - mode = 0x50001000 | (1 << 31); - else { - mode = 0x50001000 | (7 << 14); - assert(mt->base.base.target == PIPE_TEXTURE_2D); - } + tic[0] = nv50_texture_formats[view->pipe.format]; - mode |= ((mt->base.bo->tile_mode & 0x0f) << 22) | - ((mt->base.bo->tile_mode & 0xf0) << 21); + swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r); + swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g); + swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b); + swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a); + view->tic[0] = (tic[0] & ~NV50TIC_0_0_SWIZZLE_MASK) | + (swz[0] << NV50TIC_0_0_MAPR_SHIFT) | + (swz[1] << NV50TIC_0_0_MAPG_SHIFT) | + (swz[2] << NV50TIC_0_0_MAPB_SHIFT) | + (swz[3] << NV50TIC_0_0_MAPA_SHIFT); - desc = util_format_description(mt->base.base.format); - assert(desc); + tic[2] = 0x50001000; + tic[2] |= ((mt->base.bo->tile_mode & 0x0f) << 22) | + ((mt->base.bo->tile_mode & 0xf0) << 21); + desc = util_format_description(mt->base.base.format); if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) - mode |= 0x0400; + tic[2] |= NV50TIC_0_2_COLORSPACE_SRGB; switch (mt->base.base.target) { case PIPE_TEXTURE_1D: + tic[2] |= NV50TIC_0_2_TARGET_1D; break; case PIPE_TEXTURE_2D: - mode |= (1 << 14); + tic[2] |= NV50TIC_0_2_TARGET_2D; break; case PIPE_TEXTURE_3D: - mode |= (2 << 14); + tic[2] |= NV50TIC_0_2_TARGET_3D; break; case PIPE_TEXTURE_CUBE: - mode |= (3 << 14); + tic[2] |= NV50TIC_0_2_TARGET_CUBE; break; default: - assert(!"unsupported texture target"); - break; + NOUVEAU_ERR("invalid texture target: %d\n", + mt->base.base.target); + return FALSE; } - so_data (so, nv50_tex_format_list[i].hw); - so_reloc(so, mt->base.bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW | - NOUVEAU_BO_RD, 0, 0); - so_data (so, mode); - so_data (so, 0x00300000); - so_data (so, mt->base.base.width0 | (1 << 31)); - so_data (so, (mt->base.base.last_level << 28) | - (mt->base.base.depth0 << 16) | mt->base.base.height0); - so_data (so, 0x03000000); - so_data (so, mt->base.base.last_level << 4); - - return 0; -} + tic[3] = 0x00300000; + + tic[4] = (1 << 31) | mt->base.base.width0; + tic[5] = (mt->base.base.last_level << 28) | + (mt->base.base.depth0 << 16) | mt->base.base.height0; + + tic[6] = 0x03000000; -#ifndef NV50TCL_BIND_TIC -#define NV50TCL_BIND_TIC(n) (0x1448 + 8 * n) -#endif + tic[7] = (view->pipe.last_level << 4) | view->pipe.first_level; + + return TRUE; +} -static boolean +static int nv50_validate_textures(struct nv50_context *nv50, struct nouveau_stateobj *so, unsigned p) { - static const unsigned p_remap[PIPE_SHADER_TYPES] = { 0, 2, 1 }; - struct nouveau_grobj *eng2d = nv50->screen->eng2d; struct nouveau_grobj *tesla = nv50->screen->tesla; - unsigned unit, j, p_hw = p_remap[p]; + unsigned unit, j; + + const unsigned rll = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW; + const unsigned rlh = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH + | NOUVEAU_BO_OR; nv50_so_init_sifc(nv50, so, nv50->screen->tic, NOUVEAU_BO_VRAM, - p * (32 * 8 * 4), nv50->miptree_nr[p] * 8 * 4); + p * (32 * 8 * 4), nv50->sampler_view_nr[p] * 8 * 4); - for (unit = 0; unit < nv50->miptree_nr[p]; ++unit) { - struct nv50_miptree *mt = nv50->miptree[p][unit]; + for (unit = 0; unit < nv50->sampler_view_nr[p]; ++unit) { + struct nv50_sampler_view *view = + nv50_sampler_view(nv50->sampler_views[p][unit]); so_method(so, eng2d, NV50_2D_SIFC_DATA | (2 << 29), 8); - if (mt) { - if (nv50_tex_construct(nv50, so, mt, unit, p)) - return FALSE; + if (view) { + uint32_t tic2 = view->tic[2]; + struct nv50_miptree *mt = + nv50_miptree(view->pipe.texture); + + if (nv50->sampler[p][unit]->normalized) + tic2 |= NV50TIC_0_2_NORMALIZED_COORDS; + + so_data (so, view->tic[0]); + so_reloc (so, mt->base.bo, 0, rll, 0, 0); + so_reloc (so, mt->base.bo, 0, rlh, tic2, tic2); + so_datap (so, &view->tic[3], 5); + /* Set TEX insn $t src binding $unit in program type p * to TIC, TSC entry (32 * p + unit), mark valid (1). */ - so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1); + so_method(so, tesla, NV50TCL_BIND_TIC(p), 1); so_data (so, ((32 * p + unit) << 9) | (unit << 1) | 1); } else { for (j = 0; j < 8; ++j) so_data(so, 0); - so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1); + so_method(so, tesla, NV50TCL_BIND_TIC(p), 1); so_data (so, (unit << 1) | 0); } } - for (; unit < nv50->state.miptree_nr[p]; unit++) { + for (; unit < nv50->state.sampler_view_nr[p]; unit++) { /* Make other bindings invalid. */ - so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1); + so_method(so, tesla, NV50TCL_BIND_TIC(p), 1); so_data (so, (unit << 1) | 0); } - nv50->state.miptree_nr[p] = nv50->miptree_nr[p]; + nv50->state.sampler_view_nr[p] = nv50->sampler_view_nr[p]; return TRUE; } @@ -202,23 +220,25 @@ nv50_tex_relocs(struct nv50_context *nv50) int p, unit; p = PIPE_SHADER_FRAGMENT; - for (unit = 0; unit < nv50->miptree_nr[p]; unit++) { - if (!nv50->miptree[p][unit]) + for (unit = 0; unit < nv50->sampler_view_nr[p]; unit++) { + struct pipe_sampler_view *view = nv50->sampler_views[p][unit]; + if (!view) continue; nouveau_reloc_emit(chan, nv50->screen->tic, ((p * 32) + unit) * 32, NULL, - nv50->miptree[p][unit]->base.bo, 0, 0, + nv50_miptree(view->texture)->base.bo, 0, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, 0); } p = PIPE_SHADER_VERTEX; - for (unit = 0; unit < nv50->miptree_nr[p]; unit++) { - if (!nv50->miptree[p][unit]) + for (unit = 0; unit < nv50->sampler_view_nr[p]; unit++) { + struct pipe_sampler_view *view = nv50->sampler_views[p][unit]; + if (!view) continue; nouveau_reloc_emit(chan, nv50->screen->tic, ((p * 32) + unit) * 32, NULL, - nv50->miptree[p][unit]->base.bo, 0, 0, + nv50_miptree(view->texture)->base.bo, 0, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, 0); } @@ -229,21 +249,23 @@ nv50_tex_validate(struct nv50_context *nv50) { struct nouveau_stateobj *so; struct nouveau_grobj *tesla = nv50->screen->tesla; - unsigned p, start, push, nrlc; - - for (nrlc = 0, start = 0, push = 0, p = 0; p < PIPE_SHADER_TYPES; ++p) { - start += MAX2(nv50->miptree_nr[p], nv50->state.miptree_nr[p]); - push += MAX2(nv50->miptree_nr[p], nv50->state.miptree_nr[p]); - nrlc += nv50->miptree_nr[p]; + unsigned p, m = 0, d = 0, r = 0; + + for (p = 0; p < 3; ++p) { + unsigned nr = MAX2(nv50->sampler_view_nr[p], + nv50->state.sampler_view_nr[p]); + m += nr; + d += nr; + r += nv50->sampler_view_nr[p]; } - start = start * 2 + 4 * PIPE_SHADER_TYPES + 2; - push = push * 9 + 19 * PIPE_SHADER_TYPES + 2; - nrlc = nrlc * 2 + 2 * PIPE_SHADER_TYPES; + m = m * 2 + 3 * 4 + 1; + d = d * 9 + 3 * 19 + 1; + r = r * 2 + 3 * 2; - so = so_new(start, push, nrlc); + so = so_new(m, d, r); - if (nv50_validate_textures(nv50, so, PIPE_SHADER_VERTEX) == FALSE || - nv50_validate_textures(nv50, so, PIPE_SHADER_FRAGMENT) == FALSE) { + if (nv50_validate_textures(nv50, so, 0) == FALSE || + nv50_validate_textures(nv50, so, 2) == FALSE) { so_ref(NULL, &so); NOUVEAU_ERR("failed tex validate\n"); diff --git a/src/gallium/drivers/nv50/nv50_texture.h b/src/gallium/drivers/nv50/nv50_texture.h index b870302019..3475d3e432 100644 --- a/src/gallium/drivers/nv50/nv50_texture.h +++ b/src/gallium/drivers/nv50/nv50_texture.h @@ -7,7 +7,9 @@ */ /* Texture image control block */ +#define NV50TIC_0_0_SWIZZLE_MASK 0x3ffc0000 #define NV50TIC_0_0_MAPA_MASK 0x38000000 +#define NV50TIC_0_0_MAPA_SHIFT 27 #define NV50TIC_0_0_MAPA_ZERO 0x00000000 #define NV50TIC_0_0_MAPA_C0 0x10000000 #define NV50TIC_0_0_MAPA_C1 0x18000000 @@ -15,6 +17,7 @@ #define NV50TIC_0_0_MAPA_C3 0x28000000 #define NV50TIC_0_0_MAPA_ONE 0x38000000 #define NV50TIC_0_0_MAPB_MASK 0x07000000 +#define NV50TIC_0_0_MAPB_SHIFT 24 #define NV50TIC_0_0_MAPB_ZERO 0x00000000 #define NV50TIC_0_0_MAPB_C0 0x02000000 #define NV50TIC_0_0_MAPB_C1 0x03000000 @@ -22,6 +25,7 @@ #define NV50TIC_0_0_MAPB_C3 0x05000000 #define NV50TIC_0_0_MAPB_ONE 0x07000000 #define NV50TIC_0_0_MAPG_MASK 0x00e00000 +#define NV50TIC_0_0_MAPG_SHIFT 21 #define NV50TIC_0_0_MAPG_ZERO 0x00000000 #define NV50TIC_0_0_MAPG_C0 0x00400000 #define NV50TIC_0_0_MAPG_C1 0x00600000 @@ -29,6 +33,7 @@ #define NV50TIC_0_0_MAPG_C3 0x00a00000 #define NV50TIC_0_0_MAPG_ONE 0x00e00000 #define NV50TIC_0_0_MAPR_MASK 0x001c0000 +#define NV50TIC_0_0_MAPR_SHIFT 18 #define NV50TIC_0_0_MAPR_ZERO 0x00000000 #define NV50TIC_0_0_MAPR_C0 0x00080000 #define NV50TIC_0_0_MAPR_C1 0x000c0000 @@ -89,22 +94,39 @@ #define NV50TIC_0_1_OFFSET_LOW_MASK 0xffffffff #define NV50TIC_0_1_OFFSET_LOW_SHIFT 0 -#define NV50TIC_0_2_UNKNOWN_MASK 0xffffffff +#define NV50TIC_0_2_COLORSPACE_SRGB 0x00000400 +#define NV50TIC_0_2_TARGET_1D 0x00000000 +#define NV50TIC_0_2_TARGET_2D 0x00004000 +#define NV50TIC_0_2_TARGET_3D 0x00008000 +#define NV50TIC_0_2_TARGET_CUBE 0x0000c000 +#define NV50TIC_0_2_TARGET_1D_ARRAY 0x00010000 +#define NV50TIC_0_2_TARGET_2D_ARRAY 0x00014000 +#define NV50TIC_0_2_TARGET_BUFFER 0x00018000 +#define NV50TIC_0_2_TARGET_RECT 0x0001c000 +/* #define NV50TIC_0_0_TILE_MODE_LINEAR 0x00040000 */ +#define NV50TIC_0_2_TILE_MODE_Y_MASK 0x01c00000 +#define NV50TIC_0_2_TILE_MODE_Y_SHIFT 22 +#define NV50TIC_0_2_TILE_MODE_Z_MASK 0x0e000000 +#define NV50TIC_0_2_TILE_MODE_Z_SHIFT 25 +#define NV50TIC_0_2_NORMALIZED_COORDS 0x80000000 #define NV50TIC_0_3_UNKNOWN_MASK 0xffffffff #define NV50TIC_0_4_WIDTH_MASK 0x0000ffff #define NV50TIC_0_4_WIDTH_SHIFT 0 -#define NV50TIC_0_5_DEPTH_MASK 0xffff0000 +#define NV50TIC_0_5_LAST_LEVEL_MASK 0xf0000000 +#define NV50TIC_0_5_LAST_LEVEL_SHIFT 28 +#define NV50TIC_0_5_DEPTH_MASK 0x0fff0000 #define NV50TIC_0_5_DEPTH_SHIFT 16 #define NV50TIC_0_5_HEIGHT_MASK 0x0000ffff #define NV50TIC_0_5_HEIGHT_SHIFT 0 - #define NV50TIC_0_6_UNKNOWN_MASK 0xffffffff -#define NV50TIC_0_7_OFFSET_HIGH_MASK 0xffffffff -#define NV50TIC_0_7_OFFSET_HIGH_SHIFT 0 +#define NV50TIC_0_7_BASE_LEVEL_MASK 0x0000000f +#define NV50TIC_0_7_BASE_LEVEL_SHIFT 0 +#define NV50TIC_0_7_MAX_LEVEL_MASK 0x000000f0 +#define NV50TIC_0_7_MAX_LEVEL_SHIFT 4 /* Texture sampler control block */ #define NV50TSC_1_0_WRAPS_MASK 0x00000007 |