diff options
Diffstat (limited to 'src/gallium/drivers/nvfx')
36 files changed, 4843 insertions, 1172 deletions
diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile index 6cbbad699e..46bb082388 100644 --- a/src/gallium/drivers/nvfx/Makefile +++ b/src/gallium/drivers/nvfx/Makefile @@ -19,14 +19,8 @@ C_SOURCES = \ nvfx_resource.c \ nvfx_screen.c \ nvfx_state.c \ - nvfx_state_blend.c \ - nvfx_state_emit.c \ + nvfx_state_emit.c \ nvfx_state_fb.c \ - nvfx_state_rasterizer.c \ - nvfx_state_scissor.c \ - nvfx_state_stipple.c \ - nvfx_state_viewport.c \ - nvfx_state_zsa.c \ nvfx_surface.c \ nvfx_transfer.c \ nvfx_vbo.c \ diff --git a/src/gallium/drivers/nvfx/SConscript b/src/gallium/drivers/nvfx/SConscript index 80e3ef2257..f1041e7763 100644 --- a/src/gallium/drivers/nvfx/SConscript +++ b/src/gallium/drivers/nvfx/SConscript @@ -24,14 +24,8 @@ nvfx = env.ConvenienceLibrary( 'nvfx_resource.c', 'nvfx_screen.c', 'nvfx_state.c', - 'nvfx_state_blend.c', 'nvfx_state_emit.c', 'nvfx_state_fb.c', - 'nvfx_state_rasterizer.c', - 'nvfx_state_scissor.c', - 'nvfx_state_stipple.c', - 'nvfx_state_viewport.c', - 'nvfx_state_zsa.c', 'nvfx_surface.c', 'nvfx_transfer.c', 'nvfx_vbo.c', diff --git a/src/gallium/drivers/nvfx/nv01_2d.xml.h b/src/gallium/drivers/nvfx/nv01_2d.xml.h new file mode 100644 index 0000000000..b963eb7edc --- /dev/null +++ b/src/gallium/drivers/nvfx/nv01_2d.xml.h @@ -0,0 +1,1343 @@ +#ifndef NV01_2D_XML +#define NV01_2D_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- nv01_2d.xml ( 33462 bytes, from 2010-08-05 19:38:53) +- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50) +- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53) +- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53) +- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53) + +Copyright (C) 2006-2010 by the following authors: +- Artur Huillet <arthur.huillet@free.fr> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <koala_br@users.sourceforge.net> (koala_br) +- Carlos Martin <carlosmn@users.sf.net> (carlosmn) +- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr) +- Dawid Gajownik <gajownik@users.sf.net> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag) +- EdB <edb_@users.sf.net> (edb_) +- Erik Waling <erikwailing@users.sf.net> (erikwaling) +- Francisco Jerez <currojerez@riseup.net> (curro, curro_, currojerez) +- imirkin <imirkin@users.sf.net> (imirkin) +- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome) +- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy) +- Laurent Carlier <lordheavym@gmail.com> (lordheavy) +- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1) +- Maarten Maathuis <madman2003@gmail.com> (stillunknown) +- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin) +- Mark Carey <mark.carey@gmail.com> (careym) +- Matthieu Castet <matthieu.castet@parrot.com> (mat-c) +- nvidiaman <nvidiaman@users.sf.net> (nvidiaman) +- Patrice Mandin <mandin.patrice@orange.fr> (pmandin, pmdata) +- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen) +- Peter Popov <ironpeter@users.sf.net> (ironpeter) +- Richard Hughes <hughsient@users.sf.net> (hughsient) +- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <leroutier@users.sf.net> (leroutier) +- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu) +- sturmflut <sturmflut@users.sf.net> (sturmflut) +- Sylvain Munaut <tnt@246tNt.com> +- Victor Stinner <victor.stinner@haypocalc.com> (haypo) +- Wladmir van der Laan <laanwj@gmail.com> (miathan6) +- Younes Manton <younes.m@gmail.com> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + + +#define NV01_CONTEXT_BETA1_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300 + + +#define NV04_BETA_SOLID_DMA_NOTIFY 0x00000180 + +#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300 + + +#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT 0x00000300 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304 + + +#define NV01_CONTEXT_PATTERN_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_PATTERN_COLOR_FORMAT 0x00000300 + +#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT 0x00000304 + +#define NV01_CONTEXT_PATTERN_SHAPE 0x00000308 + +#define NV01_CONTEXT_PATTERN_COLOR(i0) (0x00000310 + 0x4*(i0)) +#define NV01_CONTEXT_PATTERN_COLOR__ESIZE 0x00000004 +#define NV01_CONTEXT_PATTERN_COLOR__LEN 0x00000002 + +#define NV01_CONTEXT_PATTERN_PATTERN(i0) (0x00000318 + 0x4*(i0)) +#define NV01_CONTEXT_PATTERN_PATTERN__ESIZE 0x00000004 +#define NV01_CONTEXT_PATTERN_PATTERN__LEN 0x00000002 + + +#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT 0x00000300 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__MASK 0x0000ffff +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__SHIFT 0 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__MASK 0xffff0000 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__SHIFT 16 + +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE 0x00000304 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__MASK 0x0000ffff +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__SHIFT 0 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__MASK 0xffff0000 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__SHIFT 16 + + +#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180 + +#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE 0x00000184 + +#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN 0x00000188 + + +#define NV50_CONTEXT_SURFACES_2D_SRC_LINEAR 0x00000200 + +#define NV50_CONTEXT_SURFACES_2D_SRC_TILE_MODE 0x00000204 + +#define NV50_CONTEXT_SURFACES_2D_SRC_WIDTH 0x00000208 + +#define NV50_CONTEXT_SURFACES_2D_SRC_HEIGHT 0x0000020c + +#define NV50_CONTEXT_SURFACES_2D_UNK0210 0x00000210 + +#define NV50_CONTEXT_SURFACES_2D_UNK0214 0x00000214 + +#define NV50_CONTEXT_SURFACES_2D_DST_LINEAR 0x00000218 + +#define NV50_CONTEXT_SURFACES_2D_DST_TILE_MODE 0x0000021c + +#define NV50_CONTEXT_SURFACES_2D_DST_WIDTH 0x00000220 + +#define NV50_CONTEXT_SURFACES_2D_DST_HEIGHT 0x00000224 + +#define NV50_CONTEXT_SURFACES_2D_UNK0228 0x00000228 + +#define NV50_CONTEXT_SURFACES_2D_UNK022C 0x0000022c + +#define NV50_CONTEXT_SURFACES_2D_OFFSET_SOURCE_HIGH 0x00000230 + +#define NV50_CONTEXT_SURFACES_2D_OFFSET_DESTIN_HIGH 0x00000234 + +#define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8 0x00000001 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5 0x00000002 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5 0x00000003 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5 0x00000004 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16 0x00000005 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8 0x00000006 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8 0x00000007 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8 0x00000009 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8 0x0000000a +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32 0x0000000b + +#define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304 +#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__SHIFT 0 +#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__SHIFT 16 + +#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308 + +#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c + + +#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180 + +#define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184 + +#define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__MASK 0x000000ff +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__SHIFT 0 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8 0x00000001 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000002 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000003 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5 0x00000004 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16 0x00000005 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000006 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000007 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000009 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8 0x0000000a +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32 0x0000000b +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__MASK 0x00ff0000 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT 16 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__MASK 0xff000000 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT 24 + +#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304 + + +#define NV03_CONTEXT_ROP_DMA_NOTIFY 0x00000180 + +#define NV03_CONTEXT_ROP_ROP 0x00000300 + + +#define NV04_IMAGE_PATTERN_DMA_NOTIFY 0x00000180 + +#define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT 0x00000304 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6 0x00000001 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE 0x00000002 + +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8 0x00000000 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1 0x00000001 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64 0x00000002 + +#define NV04_IMAGE_PATTERN_PATTERN_SELECT 0x0000030c +#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO 0x00000001 +#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR 0x00000002 + +#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310 + +#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314 + +#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318 + +#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c + +#define NV04_IMAGE_PATTERN_PATTERN_Y8(i0) (0x00000400 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_Y8__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_Y8__LEN 0x00000010 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__MASK 0x000000ff +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__MASK 0x0000ff00 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__SHIFT 8 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__MASK 0x00ff0000 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__MASK 0xff000000 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__SHIFT 24 + +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(i0) (0x00000500 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__LEN 0x00000020 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__MASK 0x0000001f +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__MASK 0x000007e0 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__SHIFT 5 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__MASK 0x0000f800 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__SHIFT 11 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__MASK 0x001f0000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__MASK 0x07e00000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__SHIFT 21 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__MASK 0xf8000000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__SHIFT 27 + +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(i0) (0x00000600 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__LEN 0x00000020 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__MASK 0x0000001f +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__MASK 0x000003e0 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__SHIFT 5 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__MASK 0x00007c00 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__SHIFT 10 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__MASK 0x001f0000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__MASK 0x03e00000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__SHIFT 21 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__MASK 0x7c000000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__SHIFT 26 + +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(i0) (0x00000700 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__LEN 0x00000040 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__MASK 0x000000ff +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__MASK 0x0000ff00 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__SHIFT 8 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__MASK 0x00ff0000 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__SHIFT 16 + + +#define NV01_RENDER_SOLID_LINE_PATCH 0x0000010c + +#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY 0x00000180 + +#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE 0x00000184 + +#define NV01_RENDER_SOLID_LINE_PATTERN 0x00000188 + +#define NV04_RENDER_SOLID_LINE_PATTERN 0x00000188 + +#define NV01_RENDER_SOLID_LINE_ROP 0x0000018c + +#define NV01_RENDER_SOLID_LINE_BETA1 0x00000190 + +#define NV01_RENDER_SOLID_LINE_SURFACE_DST 0x00000194 + + +#define NV04_RENDER_SOLID_LINE_BETA4 0x00000194 + +#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198 + +#define NV01_RENDER_SOLID_LINE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_RENDER_SOLID_LINE_COLOR 0x00000304 + +#define NV01_RENDER_SOLID_LINE_LINE_POINT0(i0) (0x00000400 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE_POINT0__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0__LEN 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_LINE_LINE_POINT1(i0) (0x00000404 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE_POINT1__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1__LEN 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(i0) (0x00000480 + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(i0) (0x00000484 + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(i0) (0x00000488 + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(i0) (0x0000048c + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_POLYLINE(i0) (0x00000500 + 0x4*(i0)) +#define NV01_RENDER_SOLID_LINE_POLYLINE__ESIZE 0x00000004 +#define NV01_RENDER_SOLID_LINE_POLYLINE__LEN 0x00000020 +#define NV01_RENDER_SOLID_LINE_POLYLINE_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_POLYLINE_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(i0) (0x00000580 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(i0) (0x00000584 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(i0) (0x00000600 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(i0) (0x00000604 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__LEN 0x00000010 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__SHIFT 16 + + +#define NV01_RENDER_SOLID_TRIANGLE_PATCH 0x0000010c + +#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY 0x00000180 + +#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE 0x00000184 + +#define NV01_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188 + +#define NV04_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188 + +#define NV01_RENDER_SOLID_TRIANGLE_ROP 0x0000018c + +#define NV01_RENDER_SOLID_TRIANGLE_BETA1 0x00000190 + +#define NV01_RENDER_SOLID_TRIANGLE_SURFACE_DST 0x00000194 + + +#define NV04_RENDER_SOLID_TRIANGLE_BETA4 0x00000194 + +#define NV04_RENDER_SOLID_TRIANGLE_SURFACE 0x00000198 + +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_RENDER_SOLID_TRIANGLE_COLOR 0x00000304 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0 0x00000310 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1 0x00000314 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2 0x00000318 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X 0x00000320 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y 0x00000324 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X 0x00000328 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y 0x0000032c + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X 0x00000330 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y 0x00000334 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(i0) (0x00000400 + 0x4*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__ESIZE 0x00000004 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__LEN 0x00000020 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(i0) (0x00000480 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(i0) (0x00000484 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(i0) (0x00000500 + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__LEN 0x00000008 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(i0) (0x00000504 + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__LEN 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(i0) (0x00000508 + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__LEN 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(i0) (0x0000050c + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__LEN 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(i0) (0x00000580 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__LEN 0x00000010 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(i0) (0x00000584 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__LEN 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__SHIFT 16 + + +#define NV01_RENDER_SOLID_RECTANGLE_PATCH 0x0000010c + +#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY 0x00000180 + +#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE 0x00000184 + +#define NV01_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188 + +#define NV04_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188 + +#define NV01_RENDER_SOLID_RECTANGLE_ROP 0x0000018c + +#define NV01_RENDER_SOLID_RECTANGLE_BETA1 0x00000190 + +#define NV01_RENDER_SOLID_RECTANGLE_SURFACE_DST 0x00000194 + + +#define NV04_RENDER_SOLID_RECTANGLE_BETA4 0x00000194 + +#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198 + +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_RENDER_SOLID_RECTANGLE_COLOR 0x00000304 + +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(i0) (0x00000400 + 0x8*(i0)) +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__LEN 0x00000010 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__SHIFT 0 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(i0) (0x00000404 + 0x8*(i0)) +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__LEN 0x00000010 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__MASK 0x0000ffff +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__SHIFT 0 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__MASK 0xffff0000 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__SHIFT 16 + + +#define NV01_IMAGE_BLIT_PATCH 0x0000010c + + +#define NV11_IMAGE_BLIT_WAIT_FOR_IDLE 0x00000108 + +#define NV11_IMAGE_BLIT_UNK120 0x00000120 + +#define NV11_IMAGE_BLIT_UNK124 0x00000124 + +#define NV11_IMAGE_BLIT_UNK128 0x00000128 + +#define NV11_IMAGE_BLIT_UNK12C 0x0000012c + +#define NV11_IMAGE_BLIT_UNK130 0x00000130 + +#define NV11_IMAGE_BLIT_UNK134 0x00000134 + +#define NV01_IMAGE_BLIT_DMA_NOTIFY 0x00000180 + +#define NV01_IMAGE_BLIT_COLOR_KEY 0x00000184 + +#define NV04_IMAGE_BLIT_COLOR_KEY 0x00000184 + +#define NV01_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188 + +#define NV01_IMAGE_BLIT_PATTERN 0x0000018c + +#define NV04_IMAGE_BLIT_PATTERN 0x0000018c + +#define NV01_IMAGE_BLIT_ROP 0x00000190 + +#define NV01_IMAGE_BLIT_BETA1 0x00000194 + + +#define NV01_IMAGE_BLIT_SURFACE_SRC 0x00000198 + +#define NV01_IMAGE_BLIT_SURFACE_DST 0x0000019c + + +#define NV04_IMAGE_BLIT_BETA4 0x00000198 + +#define NV04_IMAGE_BLIT_SURFACES 0x0000019c + +#define NV01_IMAGE_BLIT_OPERATION 0x000002fc +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001 +#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002 +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003 +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_IMAGE_BLIT_POINT_IN 0x00000300 +#define NV01_IMAGE_BLIT_POINT_IN_X__MASK 0x0000ffff +#define NV01_IMAGE_BLIT_POINT_IN_X__SHIFT 0 +#define NV01_IMAGE_BLIT_POINT_IN_Y__MASK 0xffff0000 +#define NV01_IMAGE_BLIT_POINT_IN_Y__SHIFT 16 + +#define NV01_IMAGE_BLIT_POINT_OUT 0x00000304 +#define NV01_IMAGE_BLIT_POINT_OUT_X__MASK 0x0000ffff +#define NV01_IMAGE_BLIT_POINT_OUT_X__SHIFT 0 +#define NV01_IMAGE_BLIT_POINT_OUT_Y__MASK 0xffff0000 +#define NV01_IMAGE_BLIT_POINT_OUT_Y__SHIFT 16 + +#define NV01_IMAGE_BLIT_SIZE 0x00000308 +#define NV01_IMAGE_BLIT_SIZE_W__MASK 0x0000ffff +#define NV01_IMAGE_BLIT_SIZE_W__SHIFT 0 +#define NV01_IMAGE_BLIT_SIZE_H__MASK 0xffff0000 +#define NV01_IMAGE_BLIT_SIZE_H__SHIFT 16 + + +#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c + +#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184 + +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188 + +#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c + +#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190 + +#define NV04_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194 + +#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198 + +#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c + +#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0 + +#define NV05_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0 + +#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0 + +#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4 + +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8 + +#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec + +#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0 + +#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4 + +#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8 + +#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc + +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__LEN 0x00000700 + + +#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 + +#define NV01_IMAGE_FROM_CPU_PATCH 0x0000010c + +#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV01_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV04_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188 + +#define NV01_IMAGE_FROM_CPU_PATTERN 0x0000018c + +#define NV04_IMAGE_FROM_CPU_PATTERN 0x0000018c + +#define NV01_IMAGE_FROM_CPU_ROP 0x00000190 + +#define NV01_IMAGE_FROM_CPU_BETA1 0x00000194 + + +#define NV01_IMAGE_FROM_CPU_SURFACE_DST 0x00000198 + + +#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198 + +#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c + +#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 + +#define NV01_IMAGE_FROM_CPU_OPERATION 0x000002fc +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND 0x00000001 +#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND 0x00000002 +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY 0x00000003 +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_R5G6G5 0x00000001 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8 0x00000005 + +#define NV01_IMAGE_FROM_CPU_POINT 0x00000304 +#define NV01_IMAGE_FROM_CPU_POINT_X__MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_POINT_X__SHIFT 0 +#define NV01_IMAGE_FROM_CPU_POINT_Y__MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_POINT_Y__SHIFT 16 + +#define NV01_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__SHIFT 0 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__SHIFT 16 + +#define NV01_IMAGE_FROM_CPU_SIZE_IN 0x0000030c +#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT 0 +#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT 16 + +#define NV01_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV01_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV01_IMAGE_FROM_CPU_COLOR__LEN 0x00000020 + +#define NV04_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV04_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV04_IMAGE_FROM_CPU_COLOR__LEN 0x00000700 + + +#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH 0x0000010c + +#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP 0x0000018c + +#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1 0x00000190 + + +#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE_DST 0x00000194 + + +#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198 + +#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION 0x000002fc + +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN 0x00000304 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU 0x00000308 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV 0x0000030c + +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT 0x00000310 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE 0x00000314 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4 0x00000318 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__LEN 0x00000700 + + +#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 + +#define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c + +#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190 + + +#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE_DST 0x00000194 + + +#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194 + +#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 + +#define NV05_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c + +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__MASK 0x00ff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__MASK 0xff000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__SHIFT 24 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__SHIFT 16 + + +#define NV50_SCALED_IMAGE_FROM_MEMORY_OFFSET_HIGH 0x00000410 + +#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_LINEAR 0x00000414 + +#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_TILE_MODE 0x00000418 + + +#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 + +#define NV03_GDI_RECTANGLE_TEXT_PATTERN 0x00000184 + +#define NV03_GDI_RECTANGLE_TEXT_ROP 0x00000188 + +#define NV03_GDI_RECTANGLE_TEXT_BETA1 0x0000019c + +#define NV03_GDI_RECTANGLE_TEXT_SURFACE_DST 0x00000190 + +#define NV03_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc + +#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc + +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT 0x00000400 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE 0x00000404 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B 0x000007f4 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B 0x000007f8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B 0x000007fc + +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0 0x00000800 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1 0x00000804 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x00000bec +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x00000bf0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C 0x00000bf4 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C 0x00000bf8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_POINT_C 0x00000bfc +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0) (0x00000c00 + 0x4*(i0)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE 0x00000004 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN 0x00000020 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0 0x00000fe8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1 0x00000fec +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D 0x00000ff0 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D 0x00000ff4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D 0x00000ff8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_POINT_D 0x00000ffc +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(i0) (0x00001000 + 0x4*(i0)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__ESIZE 0x00000004 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__LEN 0x00000020 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x000013e4 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x000013e8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E 0x000013ec + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E 0x000013f0 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x000013f4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x000013f8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_POINT_E 0x000013fc +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0) (0x00001400 + 0x4*(i0)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE 0x00000004 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN 0x00000020 + + +#define NV04_GDI_RECTANGLE_TEXT_PATCH 0x0000010c + +#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 + +#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS 0x00000184 + +#define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188 + +#define NV04_GDI_RECTANGLE_TEXT_ROP 0x0000018c + +#define NV04_GDI_RECTANGLE_TEXT_BETA1 0x00000190 + +#define NV04_GDI_RECTANGLE_TEXT_BETA4 0x00000194 + +#define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198 + +#define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND 0x00000000 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY 0x00000003 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE 0x00000002 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc + +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(i0) (0x00000400 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(i0) (0x00000404 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0 0x000005f4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1 0x000005f8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B 0x000005fc + +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(i0) (0x00000600 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(i0) (0x00000604 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x000007ec +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x000007f0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C 0x000007f4 + +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C 0x000007f8 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_POINT_C 0x000007fc +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0) (0x00000800 + 0x4*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN 0x00000080 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x00000be4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x00000be8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E 0x00000bec + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E 0x00000bf0 + +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x00000bf4 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x00000bf8 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_POINT_E 0x00000bfc +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0) (0x00000c00 + 0x4*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN 0x00000080 + +#define NV04_GDI_RECTANGLE_TEXT_FONT_F 0x00000ff0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__MASK 0x0fffffff +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__MASK 0xf0000000 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__SHIFT 28 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0 0x00000ff4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1 0x00000ff8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F 0x00000ffc + +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(i0) (0x00001000 + 0x4*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__ESIZE 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__LEN 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__MASK 0x000000ff +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__MASK 0x000fff00 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__SHIFT 8 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__MASK 0xfff00000 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__SHIFT 20 + +#define NV04_GDI_RECTANGLE_TEXT_FONT_G 0x000017f0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__MASK 0x0fffffff +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__MASK 0xf0000000 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__SHIFT 28 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0 0x000017f4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1 0x000017f8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G 0x000017fc + +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(i0) (0x00001800 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__LEN 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(i0) (0x00001804 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__LEN 0x00000100 + + +#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 + +#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV10_TEXTURE_FROM_CPU_SURFACE 0x00000184 + +#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT 0x00000300 + +#define NV10_TEXTURE_FROM_CPU_POINT 0x00000304 +#define NV10_TEXTURE_FROM_CPU_POINT_X__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_POINT_X__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_POINT_Y__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_POINT_Y__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_SIZE 0x00000308 +#define NV10_TEXTURE_FROM_CPU_SIZE_W__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_SIZE_W__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_SIZE_H__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_SIZE_H__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL 0x0000030c +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL 0x00000310 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV10_TEXTURE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV10_TEXTURE_FROM_CPU_COLOR__LEN 0x00000700 + + +#endif /* NV01_2D_XML */ diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c index c05312219b..e0e65e7a87 100644 --- a/src/gallium/drivers/nvfx/nv04_2d.c +++ b/src/gallium/drivers/nvfx/nv04_2d.c @@ -33,7 +33,6 @@ #include <stdlib.h> #include <stdio.h> #include <stdint.h> -#include <nouveau/nouveau_class.h> #include <nouveau/nouveau_device.h> #include <nouveau/nouveau_pushbuf.h> #include <nouveau/nouveau_channel.h> @@ -42,6 +41,10 @@ #include <nouveau/nouveau_grobj.h> #include "nv04_2d.h" +#include "nouveau/nv_object.xml.h" +#include "nouveau/nv_m2mf.xml.h" +#include "nv01_2d.xml.h" + /* avoid depending on Mesa/Gallium */ #ifdef __GNUC__ #define likely(x) __builtin_expect(!!(x), 1) @@ -107,7 +110,7 @@ static inline unsigned log2i(unsigned i) //#define NV04_REGION_DEBUG // Yes, we really want to inline everything, since all the functions are used only once -#if defined(__GNUC__) && defined(DEBUG) +#if defined(__GNUC__) && !defined(DEBUG) #define inline __attribute__((always_inline)) inline #endif @@ -365,19 +368,21 @@ nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int { if(rgn->pitch > 0) { - int delta; - assert(!(rgn->offset & ((1 << rgn->bpps) - 1))); // fatal! - delta = rgn->offset & ((1 << shift) - 1); if(h <= 1) { - rgn->x += delta >> rgn->bpps; + int delta; + rgn->offset += rgn->y * rgn->pitch + (rgn->x << rgn->bpps); + delta = rgn->offset & ((1 << shift) - 1); + rgn->y = 0; + rgn->x = delta >> rgn->bpps; rgn->offset -= delta; rgn->pitch = align((rgn->x + w) << rgn->bpps, 1 << shift); } else { + int delta = rgn->offset & ((1 << shift) - 1); int newxo = (rgn->x << rgn->bpps) + delta; int dy = newxo / rgn->pitch; newxo -= dy * rgn->pitch; @@ -723,15 +728,58 @@ ms: nouveau_bo_unmap(dst->bo); } +static inline int +nv04_region_cs2d_format(struct nv04_region* rgn) +{ + switch(rgn->bpps) { + case 0: + return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8; + case 1: + if(rgn->one_bits >= 1) + return NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5; + else + return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5; + case 2: + if(rgn->one_bits >= 8) + return NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8; + else + return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8; + default: + return -1; + } +} + +static inline int +nv04_region_sifm_format(struct nv04_region* rgn) +{ + switch(rgn->bpps) { + case 0: + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8; + case 1: + if(rgn->one_bits >= 1) + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5; + else + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5; + case 2: + if(rgn->one_bits >= 8) + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8; + else + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8; + default: + return -1; + } +} static void nv04_region_copy_swizzle(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, - int w, int h, int cs2d_format, int sifm_format) + int w, int h) { struct nouveau_channel *chan = ctx->swzsurf->channel; struct nouveau_grobj *swzsurf = ctx->swzsurf; struct nouveau_grobj *sifm = ctx->sifm; + int cs2d_format = nv04_region_cs2d_format(dst); + int sifm_format = nv04_region_sifm_format(src); /* Max width & height may not be the same on all HW, but must be POT */ unsigned max_shift = 10; unsigned cw = 1 << max_shift; @@ -768,8 +816,8 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); OUT_RING (chan, cs2d_format | - log2i(cw) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | - log2i(ch) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); + log2i(cw) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT | + log2i(ch) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT); BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1); OUT_RELOCo(chan, src->bo, @@ -796,19 +844,19 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, OUT_RELOCl(chan, dst->bo, dst_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); - OUT_RING (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE); + BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); + OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE); OUT_RING (chan, sifm_format); OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY); - OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT)); - OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | rw); - OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT)); - OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | rw); + OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT)); + OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT | rw); + OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT)); + OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT | rw); OUT_RING (chan, 1 << 20); OUT_RING (chan, 1 << 20); BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4); - OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | align(rw, 8)); + OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT | align(rw, 8)); OUT_RING (chan, src->pitch | NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); @@ -828,7 +876,7 @@ nv04_copy_m2mf_begin(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, stru struct nouveau_channel *chan = ctx->m2mf->channel; struct nouveau_grobj *m2mf = ctx->m2mf; MARK_RING (chan, 3 + commands * 9, 2 + commands * 2); - BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2); + BEGIN_RING(chan, m2mf, NV04_M2MF_DMA_BUFFER_IN, 2); OUT_RELOCo(chan, srcbo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dstbo, @@ -845,7 +893,7 @@ nv04_copy_m2mf_body(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int* fprintf(stderr, "\t\t\tCOPY_M2MF_BODY [%i, %i] <%i[%u]> lin %u <- <%i[%u]> lin %u\n", size, lines, dstbo->handle, *pdstoff, dstpitch, srcbo->handle, *psrcoff, srcpitch); #endif - BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); + BEGIN_RING(chan, m2mf, NV04_M2MF_OFFSET_IN, 8); OUT_RELOCl(chan, srcbo, *psrcoff, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); OUT_RELOCl(chan, dstbo, *pdstoff, @@ -949,11 +997,12 @@ nv04_region_copy_m2mf(struct nv04_2d_context *ctx, struct nv04_region *dst, stru } static inline void -nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h, int format) +nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h) { struct nouveau_channel *chan = ctx->surf2d->channel; struct nouveau_grobj *surf2d = ctx->surf2d; struct nouveau_grobj *blit = ctx->blit; + int cs2d_format = nv04_region_cs2d_format(dst); #ifdef NV04_REGION_DEBUG fprintf(stderr, "\tRGN_COPY_BLIT [%i, %i: %i] ", w, h, dst->bpps); @@ -974,7 +1023,7 @@ nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, stru OUT_RELOCo(chan, src->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4); - OUT_RING (chan, format); + OUT_RING (chan, cs2d_format); OUT_RING (chan, (dst->pitch << 16) | src->pitch); OUT_RELOCl(chan, src->bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); @@ -1001,12 +1050,12 @@ nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, stru // dst and src may be modified, and the possibly modified version should be passed to nv04_region_cpu if necessary int nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, - int w, int h, int cs2d_format, int sifm_format, int dst_to_gpu, int src_on_gpu) + int w, int h, int dst_to_gpu, int src_on_gpu) { assert(src->bpps == dst->bpps); #ifdef NV04_REGION_DEBUG - fprintf(stderr, "RGN_COPY%s [%i, %i: %i] ", (cs2d_format >= 0) ? "_2D" : "_NO2D", w, h, dst->bpps); + fprintf(stderr, "RGN_COPY [%i, %i: %i] ", w, h, dst->bpps); for(int i = 0; i < 2; ++i) { int gpu = i ? src_on_gpu : dst_to_gpu; @@ -1059,7 +1108,7 @@ nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct { if (!dst->pitch) { - if(cs2d_format < 0 || sifm_format < 0 || !dst_to_gpu) + if(!dst_to_gpu) { #ifdef NV04_REGION_DEBUG fprintf(stderr, "\tCOPY_ENG3D\n"); @@ -1070,25 +1119,29 @@ nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct { assert(!nv04_region_align(dst, w, h, 6)); - nv04_region_copy_swizzle(ctx, dst, src, w, h, cs2d_format, sifm_format); + nv04_region_copy_swizzle(ctx, dst, src, w, h); return 0; } } else { /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback - * to NV_MEMORY_TO_MEMORY_FORMAT in this case. + * to NV_M2MF in this case. * TODO: is this also true for the source? possibly not + * TODO: should we just always use m2mf? + * TODO: if not, add support for multiple operations to copy_blit */ - if ((cs2d_format < 0) - || !dst_to_gpu + if (!dst_to_gpu + || w > 2047 + || h > 2047 + || (w & 1) || nv04_region_align(src, w, h, 6) || nv04_region_align(dst, w, h, 6) ) nv04_region_copy_m2mf(ctx, dst, src, w, h); else - nv04_region_copy_blit(ctx, dst, src, w, h, cs2d_format); + nv04_region_copy_blit(ctx, dst, src, w, h); return 0; } @@ -1110,26 +1163,25 @@ nv04_region_fill_gdirect(struct nv04_2d_context *ctx, struct nv04_region* dst, i assert(!(dst->pitch & 63) && dst->pitch); nv04_region_assert(dst, w, h); - if(dst->bpps == 0) + switch(dst->bpps) { + case 0: gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8; cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y8; - } - else if(dst->bpps == 1) - { + break; + case 1: gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5; cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y16; - } - else if(dst->bpps == 2) - { + break; + case 2: gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8; cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y32; - } - else - { + break; + default: assert(0); gdirect_format = 0; cs2d_format = 0; + break; } MARK_RING (chan, 15, 4); @@ -1225,7 +1277,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) return NULL; } - BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); + BEGIN_RING(chan, ctx->m2mf, NV04_M2MF_DMA_NOTIFY, 1); OUT_RING (chan, ctx->ntfy->handle); if (chan->device->chipset < 0x10) @@ -1247,7 +1299,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) if (chan->device->chipset < 0x10) class = NV04_IMAGE_BLIT; else - class = NV12_IMAGE_BLIT; + class = NV11_IMAGE_BLIT; ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit); if (ret) { @@ -1257,7 +1309,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1); OUT_RING (chan, ctx->ntfy->handle); - BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1); + BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACES, 1); OUT_RING (chan, ctx->surf2d->handle); BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1); OUT_RING (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY); @@ -1285,7 +1337,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) class = NV04_SWIZZLED_SURFACE; break; case 0x20: - class = NV20_SWIZZLED_SURFACE; + class = NV11_SWIZZLED_SURFACE; break; case 0x30: class = NV30_SWIZZLED_SURFACE; diff --git a/src/gallium/drivers/nvfx/nv04_2d.h b/src/gallium/drivers/nvfx/nv04_2d.h index e638b8c874..00ee5bc0b2 100644 --- a/src/gallium/drivers/nvfx/nv04_2d.h +++ b/src/gallium/drivers/nvfx/nv04_2d.h @@ -43,10 +43,31 @@ struct nv04_region { int offset; unsigned pitch; // 0 -> swizzled unsigned bpps; // bpp shift (0, 1, 2; 3, 4 for fp/compressed) + unsigned one_bits; // number of high bits read and written as ones (for "no-alpha" optimization) unsigned x, y, z; unsigned w, h, d; }; +static inline void +nv04_region_try_to_linearize(struct nv04_region* rgn) +{ + assert(!rgn->pitch); + + if(rgn->d <= 1) + { + if(rgn->h <= 1 || rgn->w <= 2) + rgn->pitch = rgn->w << rgn->bpps; + } + else + { + if(rgn->h <= 2 && rgn->w <= 2) + { + rgn->pitch = rgn->w << rgn->bpps; + rgn->offset += rgn->z * rgn->h * rgn->pitch; + } + } +} + void nv04_memcpy(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int dstoff, @@ -75,7 +96,6 @@ int nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h, - int cs2d_format, int sifm_format, int dst_to_gpu, int src_on_gpu); int diff --git a/src/gallium/drivers/nvfx/nv30-40_3d.xml.h b/src/gallium/drivers/nvfx/nv30-40_3d.xml.h new file mode 100644 index 0000000000..a705a6bd3f --- /dev/null +++ b/src/gallium/drivers/nvfx/nv30-40_3d.xml.h @@ -0,0 +1,2022 @@ +#ifndef NV30_40_3D_XML +#define NV30_40_3D_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- nv30-40_3d.xml ( 31709 bytes, from 2010-09-05 08:00:50) +- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50) +- nv_3ddefs.xml ( 15391 bytes, from 2010-09-05 08:00:46) +- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53) +- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53) +- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53) + +Copyright (C) 2006-2010 by the following authors: +- Artur Huillet <arthur.huillet@free.fr> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <koala_br@users.sourceforge.net> (koala_br) +- Carlos Martin <carlosmn@users.sf.net> (carlosmn) +- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr) +- Dawid Gajownik <gajownik@users.sf.net> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag) +- EdB <edb_@users.sf.net> (edb_) +- Erik Waling <erikwailing@users.sf.net> (erikwaling) +- Francisco Jerez <currojerez@riseup.net> (curro, curro_, currojerez) +- imirkin <imirkin@users.sf.net> (imirkin) +- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome) +- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy) +- Laurent Carlier <lordheavym@gmail.com> (lordheavy) +- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1) +- Maarten Maathuis <madman2003@gmail.com> (stillunknown) +- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin) +- Mark Carey <mark.carey@gmail.com> (careym) +- Matthieu Castet <matthieu.castet@parrot.com> (mat-c) +- nvidiaman <nvidiaman@users.sf.net> (nvidiaman) +- Patrice Mandin <mandin.patrice@orange.fr> (pmandin, pmdata) +- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen) +- Peter Popov <ironpeter@users.sf.net> (ironpeter) +- Richard Hughes <hughsient@users.sf.net> (hughsient) +- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <leroutier@users.sf.net> (leroutier) +- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu) +- sturmflut <sturmflut@users.sf.net> (sturmflut) +- Sylvain Munaut <tnt@246tNt.com> +- Victor Stinner <victor.stinner@haypocalc.com> (haypo) +- Wladmir van der Laan <laanwj@gmail.com> (miathan6) +- Younes Manton <younes.m@gmail.com> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + + +#define NV30_3D_DMA_NOTIFY 0x00000180 + +#define NV30_3D_DMA_TEXTURE0 0x00000184 + +#define NV30_3D_DMA_TEXTURE1 0x00000188 + +#define NV30_3D_DMA_COLOR1 0x0000018c + +#define NV30_3D_DMA_UNK190 0x00000190 + +#define NV30_3D_DMA_COLOR0 0x00000194 + +#define NV30_3D_DMA_ZETA 0x00000198 + +#define NV30_3D_DMA_VTXBUF0 0x0000019c + +#define NV30_3D_DMA_VTXBUF1 0x000001a0 + +#define NV30_3D_DMA_FENCE 0x000001a4 + +#define NV30_3D_DMA_QUERY 0x000001a8 + +#define NV30_3D_DMA_UNK1AC 0x000001ac + +#define NV30_3D_DMA_UNK1B0 0x000001b0 + +#define NV40_3D_DMA_COLOR2 0x000001b4 + +#define NV40_3D_DMA_COLOR3 0x000001b8 + +#define NV30_3D_RT_HORIZ 0x00000200 +#define NV30_3D_RT_HORIZ_X__MASK 0x0000ffff +#define NV30_3D_RT_HORIZ_X__SHIFT 0 +#define NV30_3D_RT_HORIZ_W__MASK 0xffff0000 +#define NV30_3D_RT_HORIZ_W__SHIFT 16 + +#define NV30_3D_RT_VERT 0x00000204 +#define NV30_3D_RT_VERT_Y__MASK 0x0000ffff +#define NV30_3D_RT_VERT_Y__SHIFT 0 +#define NV30_3D_RT_VERT_H__MASK 0xffff0000 +#define NV30_3D_RT_VERT_H__SHIFT 16 + +#define NV30_3D_RT_FORMAT 0x00000208 +#define NV30_3D_RT_FORMAT_COLOR__MASK 0x0000001f +#define NV30_3D_RT_FORMAT_COLOR__SHIFT 0 +#define NV30_3D_RT_FORMAT_COLOR_R5G6B5 0x00000003 +#define NV30_3D_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 +#define NV30_3D_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define NV30_3D_RT_FORMAT_COLOR_B8 0x00000009 +#define NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT 0x0000000b +#define NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT 0x0000000c +#define NV30_3D_RT_FORMAT_COLOR_R32_FLOAT 0x0000000d +#define NV30_3D_RT_FORMAT_COLOR_UNK0D 0x0000000d +#define NV30_3D_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f +#define NV30_3D_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 +#define NV30_3D_RT_FORMAT_ZETA__MASK 0x000000e0 +#define NV30_3D_RT_FORMAT_ZETA__SHIFT 5 +#define NV30_3D_RT_FORMAT_ZETA_Z16 0x00000020 +#define NV30_3D_RT_FORMAT_ZETA_Z24S8 0x00000040 +#define NV30_3D_RT_FORMAT_TYPE__MASK 0x00000f00 +#define NV30_3D_RT_FORMAT_TYPE__SHIFT 8 +#define NV30_3D_RT_FORMAT_TYPE_LINEAR 0x00000100 +#define NV30_3D_RT_FORMAT_TYPE_SWIZZLED 0x00000200 +#define NV30_3D_RT_FORMAT_LOG2_WIDTH__MASK 0x00ff0000 +#define NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT 16 +#define NV30_3D_RT_FORMAT_LOG2_HEIGHT__MASK 0xff000000 +#define NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT 24 + +#define NV30_3D_COLOR0_PITCH 0x0000020c +#define NV30_3D_COLOR0_PITCH_COLOR0__MASK 0x0000ffff +#define NV30_3D_COLOR0_PITCH_COLOR0__SHIFT 0 +#define NV30_3D_COLOR0_PITCH_ZETA__MASK 0xffff0000 +#define NV30_3D_COLOR0_PITCH_ZETA__SHIFT 16 + +#define NV40_3D_COLOR0_PITCH 0x0000020c + +#define NV30_3D_COLOR0_OFFSET 0x00000210 + +#define NV30_3D_ZETA_OFFSET 0x00000214 + +#define NV30_3D_COLOR1_OFFSET 0x00000218 + +#define NV30_3D_COLOR1_PITCH 0x0000021c + +#define NV30_3D_RT_ENABLE 0x00000220 +#define NV30_3D_RT_ENABLE_COLOR0 0x00000001 +#define NV30_3D_RT_ENABLE_COLOR1 0x00000002 +#define NV40_3D_RT_ENABLE_COLOR2 0x00000004 +#define NV40_3D_RT_ENABLE_COLOR3 0x00000008 +#define NV30_3D_RT_ENABLE_MRT 0x00000010 + +#define NV40_3D_ZETA_PITCH 0x0000022c + +#define NV30_3D_LMA_DEPTH_PITCH 0x0000022c + +#define NV30_3D_LMA_DEPTH_OFFSET 0x00000230 + +#define NV30_3D_TEX_UNITS_ENABLE 0x0000023c +#define NV30_3D_TEX_UNITS_ENABLE_TX0 0x00000001 +#define NV30_3D_TEX_UNITS_ENABLE_TX1 0x00000002 +#define NV30_3D_TEX_UNITS_ENABLE_TX2 0x00000004 +#define NV30_3D_TEX_UNITS_ENABLE_TX3 0x00000008 +#define NV30_3D_TEX_UNITS_ENABLE_TX4 0x00000010 +#define NV30_3D_TEX_UNITS_ENABLE_TX5 0x00000020 +#define NV30_3D_TEX_UNITS_ENABLE_TX6 0x00000040 +#define NV30_3D_TEX_UNITS_ENABLE_TX7 0x00000080 + +#define NV30_3D_TEX_MATRIX_ENABLE(i0) (0x00000240 + 0x4*(i0)) +#define NV30_3D_TEX_MATRIX_ENABLE__ESIZE 0x00000004 +#define NV30_3D_TEX_MATRIX_ENABLE__LEN 0x00000008 + +#define NV40_3D_COLOR2_PITCH 0x00000280 + +#define NV40_3D_COLOR3_PITCH 0x00000284 + +#define NV40_3D_COLOR2_OFFSET 0x00000288 + +#define NV40_3D_COLOR3_OFFSET 0x0000028c + +#define NV30_3D_VIEWPORT_TX_ORIGIN 0x000002b8 +#define NV30_3D_VIEWPORT_TX_ORIGIN_X__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_TX_ORIGIN_X__SHIFT 0 +#define NV30_3D_VIEWPORT_TX_ORIGIN_Y__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_TX_ORIGIN_Y__SHIFT 16 + +#define NV30_3D_VIEWPORT_CLIP_MODE 0x000002bc + +#define NV30_3D_VIEWPORT_CLIP_HORIZ(i0) (0x000002c0 + 0x8*(i0)) +#define NV30_3D_VIEWPORT_CLIP_HORIZ__ESIZE 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_HORIZ__LEN 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_HORIZ_L__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_CLIP_HORIZ_L__SHIFT 0 +#define NV30_3D_VIEWPORT_CLIP_HORIZ_R__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_CLIP_HORIZ_R__SHIFT 16 + +#define NV30_3D_VIEWPORT_CLIP_VERT(i0) (0x000002c4 + 0x8*(i0)) +#define NV30_3D_VIEWPORT_CLIP_VERT__ESIZE 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_VERT__LEN 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_VERT_T__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_CLIP_VERT_T__SHIFT 0 +#define NV30_3D_VIEWPORT_CLIP_VERT_D__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_CLIP_VERT_D__SHIFT 16 + +#define NV30_3D_DITHER_ENABLE 0x00000300 + +#define NV30_3D_ALPHA_FUNC_ENABLE 0x00000304 + +#define NV30_3D_ALPHA_FUNC_FUNC 0x00000308 +#define NV30_3D_ALPHA_FUNC_FUNC_NEVER 0x00000200 +#define NV30_3D_ALPHA_FUNC_FUNC_LESS 0x00000201 +#define NV30_3D_ALPHA_FUNC_FUNC_EQUAL 0x00000202 +#define NV30_3D_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 +#define NV30_3D_ALPHA_FUNC_FUNC_GREATER 0x00000204 +#define NV30_3D_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV30_3D_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 +#define NV30_3D_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 + +#define NV30_3D_ALPHA_FUNC_REF 0x0000030c + +#define NV30_3D_BLEND_FUNC_ENABLE 0x00000310 + +#define NV30_3D_BLEND_FUNC_SRC 0x00000314 +#define NV30_3D_BLEND_FUNC_SRC_RGB__MASK 0x0000ffff +#define NV30_3D_BLEND_FUNC_SRC_RGB__SHIFT 0 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE 0x00000001 +#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV30_3D_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV30_3D_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307 +#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308 +#define NV30_3D_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV30_3D_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA__MASK 0xffff0000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA__SHIFT 16 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 + +#define NV30_3D_BLEND_FUNC_DST 0x00000318 +#define NV30_3D_BLEND_FUNC_DST_RGB__MASK 0x0000ffff +#define NV30_3D_BLEND_FUNC_DST_RGB__SHIFT 0 +#define NV30_3D_BLEND_FUNC_DST_RGB_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE 0x00000001 +#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV30_3D_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV30_3D_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307 +#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308 +#define NV30_3D_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV30_3D_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV30_3D_BLEND_FUNC_DST_ALPHA__MASK 0xffff0000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA__SHIFT 16 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE 0x00010000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 + +#define NV30_3D_BLEND_COLOR 0x0000031c +#define NV30_3D_BLEND_COLOR_B__MASK 0x000000ff +#define NV30_3D_BLEND_COLOR_B__SHIFT 0 +#define NV30_3D_BLEND_COLOR_G__MASK 0x0000ff00 +#define NV30_3D_BLEND_COLOR_G__SHIFT 8 +#define NV30_3D_BLEND_COLOR_R__MASK 0x00ff0000 +#define NV30_3D_BLEND_COLOR_R__SHIFT 16 +#define NV30_3D_BLEND_COLOR_A__MASK 0xff000000 +#define NV30_3D_BLEND_COLOR_A__SHIFT 24 + +#define NV30_3D_BLEND_EQUATION 0x00000320 +#define NV30_3D_BLEND_EQUATION_FUNC_ADD 0x00008006 +#define NV30_3D_BLEND_EQUATION_MIN 0x00008007 +#define NV30_3D_BLEND_EQUATION_MAX 0x00008008 +#define NV30_3D_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a +#define NV30_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b + +#define NV40_3D_BLEND_EQUATION 0x00000320 +#define NV40_3D_BLEND_EQUATION_RGB__MASK 0x0000ffff +#define NV40_3D_BLEND_EQUATION_RGB__SHIFT 0 +#define NV40_3D_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006 +#define NV40_3D_BLEND_EQUATION_RGB_MIN 0x00008007 +#define NV40_3D_BLEND_EQUATION_RGB_MAX 0x00008008 +#define NV40_3D_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a +#define NV40_3D_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b +#define NV40_3D_BLEND_EQUATION_ALPHA__MASK 0xffff0000 +#define NV40_3D_BLEND_EQUATION_ALPHA__SHIFT 16 +#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_ADD 0x80060000 +#define NV40_3D_BLEND_EQUATION_ALPHA_MIN 0x80070000 +#define NV40_3D_BLEND_EQUATION_ALPHA_MAX 0x80080000 +#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x800a0000 +#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x800b0000 + +#define NV30_3D_COLOR_MASK 0x00000324 +#define NV30_3D_COLOR_MASK_B 0x000000ff +#define NV30_3D_COLOR_MASK_G 0x0000ff00 +#define NV30_3D_COLOR_MASK_R 0x00ff0000 +#define NV30_3D_COLOR_MASK_A 0xff000000 + +#define NV30_3D_STENCIL(i0) (0x00000328 + 0x20*(i0)) +#define NV30_3D_STENCIL__ESIZE 0x00000020 +#define NV30_3D_STENCIL__LEN 0x00000002 + +#define NV30_3D_STENCIL_ENABLE(i0) (0x00000328 + 0x20*(i0)) + +#define NV30_3D_STENCIL_MASK(i0) (0x0000032c + 0x20*(i0)) + +#define NV30_3D_STENCIL_FUNC_FUNC(i0) (0x00000330 + 0x20*(i0)) +#define NV30_3D_STENCIL_FUNC_FUNC_NEVER 0x00000200 +#define NV30_3D_STENCIL_FUNC_FUNC_LESS 0x00000201 +#define NV30_3D_STENCIL_FUNC_FUNC_EQUAL 0x00000202 +#define NV30_3D_STENCIL_FUNC_FUNC_LEQUAL 0x00000203 +#define NV30_3D_STENCIL_FUNC_FUNC_GREATER 0x00000204 +#define NV30_3D_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV30_3D_STENCIL_FUNC_FUNC_GEQUAL 0x00000206 +#define NV30_3D_STENCIL_FUNC_FUNC_ALWAYS 0x00000207 + +#define NV30_3D_STENCIL_FUNC_REF(i0) (0x00000334 + 0x20*(i0)) + +#define NV30_3D_STENCIL_FUNC_MASK(i0) (0x00000338 + 0x20*(i0)) + +#define NV30_3D_STENCIL_OP_FAIL(i0) (0x0000033c + 0x20*(i0)) +#define NV30_3D_STENCIL_OP_FAIL_ZERO 0x00000000 +#define NV30_3D_STENCIL_OP_FAIL_INVERT 0x0000150a +#define NV30_3D_STENCIL_OP_FAIL_KEEP 0x00001e00 +#define NV30_3D_STENCIL_OP_FAIL_REPLACE 0x00001e01 +#define NV30_3D_STENCIL_OP_FAIL_INCR 0x00001e02 +#define NV30_3D_STENCIL_OP_FAIL_DECR 0x00001e03 +#define NV30_3D_STENCIL_OP_FAIL_INCR_WRAP 0x00008507 +#define NV30_3D_STENCIL_OP_FAIL_DECR_WRAP 0x00008508 + +#define NV30_3D_STENCIL_OP_ZFAIL(i0) (0x00000340 + 0x20*(i0)) +#define NV30_3D_STENCIL_OP_ZFAIL_ZERO 0x00000000 +#define NV30_3D_STENCIL_OP_ZFAIL_INVERT 0x0000150a +#define NV30_3D_STENCIL_OP_ZFAIL_KEEP 0x00001e00 +#define NV30_3D_STENCIL_OP_ZFAIL_REPLACE 0x00001e01 +#define NV30_3D_STENCIL_OP_ZFAIL_INCR 0x00001e02 +#define NV30_3D_STENCIL_OP_ZFAIL_DECR 0x00001e03 +#define NV30_3D_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NV30_3D_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508 + +#define NV30_3D_STENCIL_OP_ZPASS(i0) (0x00000344 + 0x20*(i0)) +#define NV30_3D_STENCIL_OP_ZPASS_ZERO 0x00000000 +#define NV30_3D_STENCIL_OP_ZPASS_INVERT 0x0000150a +#define NV30_3D_STENCIL_OP_ZPASS_KEEP 0x00001e00 +#define NV30_3D_STENCIL_OP_ZPASS_REPLACE 0x00001e01 +#define NV30_3D_STENCIL_OP_ZPASS_INCR 0x00001e02 +#define NV30_3D_STENCIL_OP_ZPASS_DECR 0x00001e03 +#define NV30_3D_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507 +#define NV30_3D_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508 + +#define NV30_3D_SHADE_MODEL 0x00000368 +#define NV30_3D_SHADE_MODEL_FLAT 0x00001d00 +#define NV30_3D_SHADE_MODEL_SMOOTH 0x00001d01 + +#define NV30_3D_FOG_ENABLE 0x0000036c + +#define NV30_3D_FOG_COLOR 0x00000370 +#define NV30_3D_FOG_COLOR_R__MASK 0x000000ff +#define NV30_3D_FOG_COLOR_R__SHIFT 0 +#define NV30_3D_FOG_COLOR_G__MASK 0x0000ff00 +#define NV30_3D_FOG_COLOR_G__SHIFT 8 +#define NV30_3D_FOG_COLOR_B__MASK 0x00ff0000 +#define NV30_3D_FOG_COLOR_B__SHIFT 16 +#define NV30_3D_FOG_COLOR_A__MASK 0xff000000 +#define NV30_3D_FOG_COLOR_A__SHIFT 24 + +#define NV40_3D_MRT_COLOR_MASK 0x00000370 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_A 0x00000010 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_R 0x00000020 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_G 0x00000040 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_B 0x00000080 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_A 0x00000100 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_R 0x00000200 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_G 0x00000400 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_B 0x00000800 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_A 0x00001000 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_R 0x00002000 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_G 0x00004000 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_B 0x00008000 + +#define NV30_3D_COLOR_LOGIC_OP_ENABLE 0x00000374 + +#define NV30_3D_COLOR_LOGIC_OP_OP 0x00000378 +#define NV30_3D_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 +#define NV30_3D_COLOR_LOGIC_OP_OP_AND 0x00001501 +#define NV30_3D_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 +#define NV30_3D_COLOR_LOGIC_OP_OP_COPY 0x00001503 +#define NV30_3D_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 +#define NV30_3D_COLOR_LOGIC_OP_OP_NOOP 0x00001505 +#define NV30_3D_COLOR_LOGIC_OP_OP_XOR 0x00001506 +#define NV30_3D_COLOR_LOGIC_OP_OP_OR 0x00001507 +#define NV30_3D_COLOR_LOGIC_OP_OP_NOR 0x00001508 +#define NV30_3D_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 +#define NV30_3D_COLOR_LOGIC_OP_OP_INVERT 0x0000150a +#define NV30_3D_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b +#define NV30_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c +#define NV30_3D_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d +#define NV30_3D_COLOR_LOGIC_OP_OP_NAND 0x0000150e +#define NV30_3D_COLOR_LOGIC_OP_OP_SET 0x0000150f + +#define NV30_3D_NORMALIZE_ENABLE 0x0000037c + +#define NV30_3D_COLOR_MATERIAL 0x00000390 +#define NV30_3D_COLOR_MATERIAL_FRONT_EMISSION_ENABLE 0x00000001 +#define NV30_3D_COLOR_MATERIAL_FRONT_AMBIENT_ENABLE 0x00000004 +#define NV30_3D_COLOR_MATERIAL_FRONT_DIFFUSE_ENABLE 0x00000010 +#define NV30_3D_COLOR_MATERIAL_FRONT_SPECULAR_ENABLE 0x00000040 +#define NV30_3D_COLOR_MATERIAL_BACK_EMISSION_ENABLE 0x00000100 +#define NV30_3D_COLOR_MATERIAL_BACK_AMBIENT_ENABLE 0x00000400 +#define NV30_3D_COLOR_MATERIAL_BACK_DIFFUSE_ENABLE 0x00001000 +#define NV30_3D_COLOR_MATERIAL_BACK_SPECULAR_ENABLE 0x00004000 + +#define NV30_3D_DEPTH_RANGE_NEAR 0x00000394 + +#define NV30_3D_DEPTH_RANGE_FAR 0x00000398 + +#define NV30_3D_COLOR_MATERIAL_FRONT 0x000003a0 + + +#define NV30_3D_COLOR_MATERIAL_FRONT_R 0x000003a0 + +#define NV30_3D_COLOR_MATERIAL_FRONT_G 0x000003a4 + +#define NV30_3D_COLOR_MATERIAL_FRONT_B 0x000003a8 + +#define NV30_3D_COLOR_MATERIAL_FRONT_A 0x000003ac + +#define NV40_3D_MIPMAP_ROUNDING 0x000003b0 +#define NV40_3D_MIPMAP_ROUNDING_MODE__MASK 0x00100000 +#define NV40_3D_MIPMAP_ROUNDING_MODE__SHIFT 20 +#define NV40_3D_MIPMAP_ROUNDING_MODE_UP 0x00000000 +#define NV40_3D_MIPMAP_ROUNDING_MODE_DOWN 0x00100000 + +#define NV30_3D_LINE_WIDTH 0x000003b8 + +#define NV30_3D_LINE_SMOOTH_ENABLE 0x000003bc + + + +#define NV30_3D_TEX_GEN_MODE(i0, i1) (0x00000400 + 0x10*(i0) + 0x4*(i1)) +#define NV30_3D_TEX_GEN_MODE__ESIZE 0x00000004 +#define NV30_3D_TEX_GEN_MODE__LEN 0x00000004 +#define NV30_3D_TEX_GEN_MODE_FALSE 0x00000000 +#define NV30_3D_TEX_GEN_MODE_EYE_LINEAR 0x00002400 +#define NV30_3D_TEX_GEN_MODE_OBJECT_LINEAR 0x00002401 +#define NV30_3D_TEX_GEN_MODE_SPHERE_MAP 0x00002402 +#define NV30_3D_TEX_GEN_MODE_NORMAL_MAP 0x00008511 +#define NV30_3D_TEX_GEN_MODE_REFLECTION_MAP 0x00008512 + +#define NV30_3D_MODELVIEW_MATRIX(i0) (0x00000480 + 0x4*(i0)) +#define NV30_3D_MODELVIEW_MATRIX__ESIZE 0x00000004 +#define NV30_3D_MODELVIEW_MATRIX__LEN 0x00000010 + +#define NV30_3D_INVERSE_MODELVIEW_MATRIX(i0) (0x00000580 + 0x4*(i0)) +#define NV30_3D_INVERSE_MODELVIEW_MATRIX__ESIZE 0x00000004 +#define NV30_3D_INVERSE_MODELVIEW_MATRIX__LEN 0x0000000c + +#define NV30_3D_PROJECTION_MATRIX(i0) (0x00000680 + 0x4*(i0)) +#define NV30_3D_PROJECTION_MATRIX__ESIZE 0x00000004 +#define NV30_3D_PROJECTION_MATRIX__LEN 0x00000010 + + +#define NV30_3D_TEX_MATRIX(i0, i1) (0x000006c0 + 0x40*(i0) + 0x4*(i1)) +#define NV30_3D_TEX_MATRIX__ESIZE 0x00000004 +#define NV30_3D_TEX_MATRIX__LEN 0x00000010 + +#define NV30_3D_SCISSOR_HORIZ 0x000008c0 +#define NV30_3D_SCISSOR_HORIZ_X__MASK 0x0000ffff +#define NV30_3D_SCISSOR_HORIZ_X__SHIFT 0 +#define NV30_3D_SCISSOR_HORIZ_W__MASK 0xffff0000 +#define NV30_3D_SCISSOR_HORIZ_W__SHIFT 16 + +#define NV30_3D_SCISSOR_VERT 0x000008c4 +#define NV30_3D_SCISSOR_VERT_Y__MASK 0x0000ffff +#define NV30_3D_SCISSOR_VERT_Y__SHIFT 0 +#define NV30_3D_SCISSOR_VERT_H__MASK 0xffff0000 +#define NV30_3D_SCISSOR_VERT_H__SHIFT 16 + +#define NV30_3D_FOG_COORD_DIST 0x000008c8 + +#define NV30_3D_FOG_MODE 0x000008cc + +#define NV30_3D_FOG_EQUATION_CONSTANT 0x000008d0 + +#define NV30_3D_FOG_EQUATION_LINEAR 0x000008d4 + +#define NV30_3D_FOG_EQUATION_QUADRATIC 0x000008d8 + +#define NV30_3D_FP_ACTIVE_PROGRAM 0x000008e4 +#define NV30_3D_FP_ACTIVE_PROGRAM_DMA0 0x00000001 +#define NV30_3D_FP_ACTIVE_PROGRAM_DMA1 0x00000002 +#define NV30_3D_FP_ACTIVE_PROGRAM_OFFSET__MASK 0xfffffffc +#define NV30_3D_FP_ACTIVE_PROGRAM_OFFSET__SHIFT 2 + + +#define NV30_3D_RC_COLOR0 0x000008ec +#define NV30_3D_RC_COLOR0_B__MASK 0x000000ff +#define NV30_3D_RC_COLOR0_B__SHIFT 0 +#define NV30_3D_RC_COLOR0_G__MASK 0x0000ff00 +#define NV30_3D_RC_COLOR0_G__SHIFT 8 +#define NV30_3D_RC_COLOR0_R__MASK 0x00ff0000 +#define NV30_3D_RC_COLOR0_R__SHIFT 16 +#define NV30_3D_RC_COLOR0_A__MASK 0xff000000 +#define NV30_3D_RC_COLOR0_A__SHIFT 24 + +#define NV30_3D_RC_COLOR1 0x000008f0 +#define NV30_3D_RC_COLOR1_B__MASK 0x000000ff +#define NV30_3D_RC_COLOR1_B__SHIFT 0 +#define NV30_3D_RC_COLOR1_G__MASK 0x0000ff00 +#define NV30_3D_RC_COLOR1_G__SHIFT 8 +#define NV30_3D_RC_COLOR1_R__MASK 0x00ff0000 +#define NV30_3D_RC_COLOR1_R__SHIFT 16 +#define NV30_3D_RC_COLOR1_A__MASK 0xff000000 +#define NV30_3D_RC_COLOR1_A__SHIFT 24 + +#define NV30_3D_RC_FINAL0 0x000008f4 +#define NV30_3D_RC_FINAL0_D_INPUT__MASK 0x0000000f +#define NV30_3D_RC_FINAL0_D_INPUT__SHIFT 0 +#define NV30_3D_RC_FINAL0_D_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_FINAL0_D_INPUT_FOG 0x00000003 +#define NV30_3D_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_FINAL0_D_INPUT_SPARE0 0x0000000c +#define NV30_3D_RC_FINAL0_D_INPUT_SPARE1 0x0000000d +#define NV30_3D_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE__MASK 0x00000010 +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE__SHIFT 4 +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV30_3D_RC_FINAL0_D_MAPPING__MASK 0x000000e0 +#define NV30_3D_RC_FINAL0_D_MAPPING__SHIFT 5 +#define NV30_3D_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV30_3D_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV30_3D_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV30_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV30_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV30_3D_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV30_3D_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV30_3D_RC_FINAL0_C_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_FINAL0_C_INPUT__SHIFT 8 +#define NV30_3D_RC_FINAL0_C_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_FINAL0_C_INPUT_FOG 0x00000300 +#define NV30_3D_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_FINAL0_C_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_FINAL0_C_MAPPING__SHIFT 13 +#define NV30_3D_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_FINAL0_B_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_FINAL0_B_INPUT__SHIFT 16 +#define NV30_3D_RC_FINAL0_B_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_FINAL0_B_INPUT_FOG 0x00030000 +#define NV30_3D_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_FINAL0_B_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_FINAL0_B_MAPPING__SHIFT 21 +#define NV30_3D_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_FINAL0_A_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_FINAL0_A_INPUT__SHIFT 24 +#define NV30_3D_RC_FINAL0_A_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_FINAL0_A_INPUT_FOG 0x03000000 +#define NV30_3D_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_FINAL0_A_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_FINAL0_A_MAPPING__SHIFT 29 +#define NV30_3D_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_FINAL1 0x000008f8 +#define NV30_3D_RC_FINAL1_COLOR_SUM_CLAMP 0x00000080 +#define NV30_3D_RC_FINAL1_G_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_FINAL1_G_INPUT__SHIFT 8 +#define NV30_3D_RC_FINAL1_G_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_FINAL1_G_INPUT_FOG 0x00000300 +#define NV30_3D_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_FINAL1_G_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_FINAL1_G_MAPPING__SHIFT 13 +#define NV30_3D_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_FINAL1_F_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_FINAL1_F_INPUT__SHIFT 16 +#define NV30_3D_RC_FINAL1_F_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_FINAL1_F_INPUT_FOG 0x00030000 +#define NV30_3D_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_FINAL1_F_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_FINAL1_F_MAPPING__SHIFT 21 +#define NV30_3D_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_FINAL1_E_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_FINAL1_E_INPUT__SHIFT 24 +#define NV30_3D_RC_FINAL1_E_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_FINAL1_E_INPUT_FOG 0x03000000 +#define NV30_3D_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_FINAL1_E_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_FINAL1_E_MAPPING__SHIFT 29 +#define NV30_3D_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_ENABLE 0x000008fc +#define NV30_3D_RC_ENABLE_NUM_COMBINERS__MASK 0x0000000f +#define NV30_3D_RC_ENABLE_NUM_COMBINERS__SHIFT 0 +#define NV30_3D_RC_ENABLE_STAGE_CONSTANT_COLOR0 0x0000f000 +#define NV30_3D_RC_ENABLE_STAGE_CONSTANT_COLOR1 0x000f0000 + + +#define NV30_3D_RC_IN_ALPHA(i0) (0x00000900 + 0x20*(i0)) +#define NV30_3D_RC_IN_ALPHA_D_INPUT__MASK 0x0000000f +#define NV30_3D_RC_IN_ALPHA_D_INPUT__SHIFT 0 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__MASK 0x00000010 +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__SHIFT 4 +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING__MASK 0x000000e0 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING__SHIFT 5 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV30_3D_RC_IN_ALPHA_C_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT__SHIFT 8 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING__SHIFT 13 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT__SHIFT 16 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING__SHIFT 21 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT__SHIFT 24 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING__SHIFT 29 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_IN_RGB(i0) (0x00000904 + 0x20*(i0)) +#define NV30_3D_RC_IN_RGB_D_INPUT__MASK 0x0000000f +#define NV30_3D_RC_IN_RGB_D_INPUT__SHIFT 0 +#define NV30_3D_RC_IN_RGB_D_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_IN_RGB_D_INPUT_FOG 0x00000003 +#define NV30_3D_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c +#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d +#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE__MASK 0x00000010 +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE__SHIFT 4 +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV30_3D_RC_IN_RGB_D_MAPPING__MASK 0x000000e0 +#define NV30_3D_RC_IN_RGB_D_MAPPING__SHIFT 5 +#define NV30_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV30_3D_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV30_3D_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV30_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV30_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV30_3D_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV30_3D_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV30_3D_RC_IN_RGB_C_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_IN_RGB_C_INPUT__SHIFT 8 +#define NV30_3D_RC_IN_RGB_C_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_IN_RGB_C_INPUT_FOG 0x00000300 +#define NV30_3D_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_IN_RGB_C_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_IN_RGB_C_MAPPING__SHIFT 13 +#define NV30_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_IN_RGB_B_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_IN_RGB_B_INPUT__SHIFT 16 +#define NV30_3D_RC_IN_RGB_B_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_IN_RGB_B_INPUT_FOG 0x00030000 +#define NV30_3D_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_IN_RGB_B_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_IN_RGB_B_MAPPING__SHIFT 21 +#define NV30_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_IN_RGB_A_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_IN_RGB_A_INPUT__SHIFT 24 +#define NV30_3D_RC_IN_RGB_A_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_FOG 0x03000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING__SHIFT 29 +#define NV30_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_CONSTANT_COLOR0(i0) (0x00000908 + 0x20*(i0)) +#define NV30_3D_RC_CONSTANT_COLOR0_B__MASK 0x000000ff +#define NV30_3D_RC_CONSTANT_COLOR0_B__SHIFT 0 +#define NV30_3D_RC_CONSTANT_COLOR0_G__MASK 0x0000ff00 +#define NV30_3D_RC_CONSTANT_COLOR0_G__SHIFT 8 +#define NV30_3D_RC_CONSTANT_COLOR0_R__MASK 0x00ff0000 +#define NV30_3D_RC_CONSTANT_COLOR0_R__SHIFT 16 +#define NV30_3D_RC_CONSTANT_COLOR0_A__MASK 0xff000000 +#define NV30_3D_RC_CONSTANT_COLOR0_A__SHIFT 24 + +#define NV30_3D_RC_CONSTANT_COLOR1(i0) (0x0000090c + 0x20*(i0)) +#define NV30_3D_RC_CONSTANT_COLOR1_B__MASK 0x000000ff +#define NV30_3D_RC_CONSTANT_COLOR1_B__SHIFT 0 +#define NV30_3D_RC_CONSTANT_COLOR1_G__MASK 0x0000ff00 +#define NV30_3D_RC_CONSTANT_COLOR1_G__SHIFT 8 +#define NV30_3D_RC_CONSTANT_COLOR1_R__MASK 0x00ff0000 +#define NV30_3D_RC_CONSTANT_COLOR1_R__SHIFT 16 +#define NV30_3D_RC_CONSTANT_COLOR1_A__MASK 0xff000000 +#define NV30_3D_RC_CONSTANT_COLOR1_A__SHIFT 24 + +#define NV30_3D_RC_OUT_ALPHA(i0) (0x00000910 + 0x20*(i0)) +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT__MASK 0x0000000f +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT__SHIFT 0 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT__MASK 0x000000f0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT__SHIFT 4 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT__MASK 0x00000f00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT__SHIFT 8 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT 0x00001000 +#define NV30_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT 0x00002000 +#define NV30_3D_RC_OUT_ALPHA_MUX_SUM 0x00004000 +#define NV30_3D_RC_OUT_ALPHA_BIAS__MASK 0x00008000 +#define NV30_3D_RC_OUT_ALPHA_BIAS__SHIFT 15 +#define NV30_3D_RC_OUT_ALPHA_BIAS_NONE 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV30_3D_RC_OUT_ALPHA_SCALE__MASK 0x00030000 +#define NV30_3D_RC_OUT_ALPHA_SCALE__SHIFT 16 +#define NV30_3D_RC_OUT_ALPHA_SCALE_NONE 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00010000 +#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00020000 +#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00030000 + +#define NV30_3D_RC_OUT_RGB(i0) (0x00000914 + 0x20*(i0)) +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT__MASK 0x0000000f +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT__SHIFT 0 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT__MASK 0x000000f0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT__SHIFT 4 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT__MASK 0x00000f00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT__SHIFT 8 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_OUT_RGB_CD_DOT_PRODUCT 0x00001000 +#define NV30_3D_RC_OUT_RGB_AB_DOT_PRODUCT 0x00002000 +#define NV30_3D_RC_OUT_RGB_MUX_SUM 0x00004000 +#define NV30_3D_RC_OUT_RGB_BIAS__MASK 0x00008000 +#define NV30_3D_RC_OUT_RGB_BIAS__SHIFT 15 +#define NV30_3D_RC_OUT_RGB_BIAS_NONE 0x00000000 +#define NV30_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV30_3D_RC_OUT_RGB_SCALE__MASK 0x00030000 +#define NV30_3D_RC_OUT_RGB_SCALE__SHIFT 16 +#define NV30_3D_RC_OUT_RGB_SCALE_NONE 0x00000000 +#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00010000 +#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00020000 +#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00030000 + +#define NV30_3D_VIEWPORT_HORIZ 0x00000a00 +#define NV30_3D_VIEWPORT_HORIZ_X__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_HORIZ_X__SHIFT 0 +#define NV30_3D_VIEWPORT_HORIZ_W__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_HORIZ_W__SHIFT 16 + +#define NV30_3D_VIEWPORT_VERT 0x00000a04 +#define NV30_3D_VIEWPORT_VERT_Y__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_VERT_Y__SHIFT 0 +#define NV30_3D_VIEWPORT_VERT_H__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_VERT_H__SHIFT 16 + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION 0x00000a10 + + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10 + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14 + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18 + +#define NV30_3D_VIEWPORT_TRANSLATE 0x00000a20 + + +#define NV30_3D_VIEWPORT_TRANSLATE_X 0x00000a20 + +#define NV30_3D_VIEWPORT_TRANSLATE_Y 0x00000a24 + +#define NV30_3D_VIEWPORT_TRANSLATE_Z 0x00000a28 + +#define NV30_3D_VIEWPORT_TRANSLATE_W 0x00000a2c + +#define NV30_3D_VIEWPORT_SCALE 0x00000a30 + + +#define NV30_3D_VIEWPORT_SCALE_X 0x00000a30 + +#define NV30_3D_VIEWPORT_SCALE_Y 0x00000a34 + +#define NV30_3D_VIEWPORT_SCALE_Z 0x00000a38 + +#define NV30_3D_VIEWPORT_SCALE_W 0x00000a3c + +#define NV30_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000a60 + +#define NV30_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000a64 + +#define NV30_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000a68 + +#define NV30_3D_DEPTH_FUNC 0x00000a6c +#define NV30_3D_DEPTH_FUNC_NEVER 0x00000200 +#define NV30_3D_DEPTH_FUNC_LESS 0x00000201 +#define NV30_3D_DEPTH_FUNC_EQUAL 0x00000202 +#define NV30_3D_DEPTH_FUNC_LEQUAL 0x00000203 +#define NV30_3D_DEPTH_FUNC_GREATER 0x00000204 +#define NV30_3D_DEPTH_FUNC_NOTEQUAL 0x00000205 +#define NV30_3D_DEPTH_FUNC_GEQUAL 0x00000206 +#define NV30_3D_DEPTH_FUNC_ALWAYS 0x00000207 + +#define NV30_3D_DEPTH_WRITE_ENABLE 0x00000a70 + +#define NV30_3D_DEPTH_TEST_ENABLE 0x00000a74 + +#define NV30_3D_POLYGON_OFFSET_FACTOR 0x00000a78 + +#define NV30_3D_POLYGON_OFFSET_UNITS 0x00000a7c + +#define NV30_3D_VTX_ATTR_3I_XY(i0) (0x00000a80 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_3I_XY__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_3I_XY__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_3I_XY_X__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_3I_XY_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_3I_XY_Y__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_3I_XY_Y__SHIFT 16 + +#define NV30_3D_VTX_ATTR_3I_Z(i0) (0x00000a84 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_3I_Z__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_3I_Z__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_3I_Z_Z__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_3I_Z_Z__SHIFT 0 + +#define NV30_3D_TEX_FILTER_OPTIMIZATION(i0) (0x00000b00 + 0x4*(i0)) +#define NV30_3D_TEX_FILTER_OPTIMIZATION__ESIZE 0x00000004 +#define NV30_3D_TEX_FILTER_OPTIMIZATION__LEN 0x00000004 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR__MASK 0x0000001f +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR__SHIFT 0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_OFF 0x00000000 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_QUALITY 0x00000004 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_QUALITY 0x00000006 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_PERFORMANCE 0x00000008 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_PERFORMANCE 0x00000018 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE__MASK 0x000001c0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE__SHIFT 6 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_OFF 0x00000000 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_HIGH_QUALITY 0x000000c0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_QUALITY 0x000001c0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_PERFORMANCE 0x00000140 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN__MASK 0x00007c00 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN__SHIFT 10 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_OFF 0x00000000 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_PARTIAL 0x00002c00 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_FULL 0x00007c00 + +#define NV40_3D_UNK0B40(i0) (0x00000b40 + 0x4*(i0)) +#define NV40_3D_UNK0B40__ESIZE 0x00000004 +#define NV40_3D_UNK0B40__LEN 0x00000008 + +#define NV30_3D_VP_UPLOAD_INST(i0) (0x00000b80 + 0x4*(i0)) +#define NV30_3D_VP_UPLOAD_INST__ESIZE 0x00000004 +#define NV30_3D_VP_UPLOAD_INST__LEN 0x00000004 + + +#define NV30_3D_TEX_CLIP_PLANE(i0) (0x00000e00 + 0x10*(i0)) + + +#define NV30_3D_TEX_CLIP_PLANE_X(i0) (0x00000e00 + 0x10*(i0)) + +#define NV30_3D_TEX_CLIP_PLANE_Y(i0) (0x00000e04 + 0x10*(i0)) + +#define NV30_3D_TEX_CLIP_PLANE_Z(i0) (0x00000e08 + 0x10*(i0)) + +#define NV30_3D_TEX_CLIP_PLANE_W(i0) (0x00000e0c + 0x10*(i0)) + +#define NV30_3D_LIGHT 0x00001000 + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT(i0) (0x00001000 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(i0) (0x00001000 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(i0) (0x00001004 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(i0) (0x00001008 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE(i0) (0x0000100c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(i0) (0x0000100c + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(i0) (0x00001010 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(i0) (0x00001014 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR(i0) (0x00001018 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(i0) (0x00001018 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(i0) (0x0000101c + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(i0) (0x00001020 + 0x40*(i0)) + +#define NV30_3D_LIGHT_UNK24(i0) (0x00001024 + 0x40*(i0)) + +#define NV30_3D_LIGHT_HALF_VECTOR(i0) (0x00001028 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_HALF_VECTOR_X(i0) (0x00001028 + 0x40*(i0)) + +#define NV30_3D_LIGHT_HALF_VECTOR_Y(i0) (0x0000102c + 0x40*(i0)) + +#define NV30_3D_LIGHT_HALF_VECTOR_Z(i0) (0x00001030 + 0x40*(i0)) + +#define NV30_3D_LIGHT_DIRECTION(i0) (0x00001034 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_DIRECTION_X(i0) (0x00001034 + 0x40*(i0)) + +#define NV30_3D_LIGHT_DIRECTION_Y(i0) (0x00001038 + 0x40*(i0)) + +#define NV30_3D_LIGHT_DIRECTION_Z(i0) (0x0000103c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_SPOT_CUTOFF_A(i0) (0x00001200 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_CUTOFF_B(i0) (0x00001204 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_CUTOFF_C(i0) (0x00001208 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_DIR(i0) (0x0000120c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_SPOT_DIR_X(i0) (0x0000120c + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_DIR_Y(i0) (0x00001210 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_DIR_Z(i0) (0x00001214 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_CUTOFF_D(i0) (0x00001218 + 0x40*(i0)) + +#define NV30_3D_LIGHT_POSITION(i0) (0x0000121c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_POSITION_X(i0) (0x0000121c + 0x40*(i0)) + +#define NV30_3D_LIGHT_POSITION_Y(i0) (0x00001220 + 0x40*(i0)) + +#define NV30_3D_LIGHT_POSITION_Z(i0) (0x00001224 + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION(i0) (0x00001228 + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION_CONSTANT(i0) (0x00001228 + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION_LINEAR(i0) (0x0000122c + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION_QUADRATIC(i0) (0x00001230 + 0x40*(i0)) + +#define NV30_3D_FRONT_MATERIAL_SHININESS(i0) (0x00001400 + 0x4*(i0)) +#define NV30_3D_FRONT_MATERIAL_SHININESS__ESIZE 0x00000004 +#define NV30_3D_FRONT_MATERIAL_SHININESS__LEN 0x00000006 + +#define NV30_3D_ENABLED_LIGHTS 0x00001420 + +#define NV30_3D_VERTEX_TWO_SIDE_ENABLE 0x0000142c + +#define NV30_3D_FP_REG_CONTROL 0x00001450 +#define NV30_3D_FP_REG_CONTROL_UNK0__MASK 0x0000ffff +#define NV30_3D_FP_REG_CONTROL_UNK0__SHIFT 0 +#define NV30_3D_FP_REG_CONTROL_UNK1__MASK 0xffff0000 +#define NV30_3D_FP_REG_CONTROL_UNK1__SHIFT 16 + +#define NV30_3D_FLATSHADE_FIRST 0x00001454 + +#define NV30_3D_EDGEFLAG 0x0000145c +#define NV30_3D_EDGEFLAG_ENABLE 0x00000001 + +#define NV30_3D_VP_CLIP_PLANES_ENABLE 0x00001478 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 0x00000002 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 0x00000020 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 0x00000200 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 0x00002000 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4 0x00020000 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5 0x00200000 + +#define NV30_3D_POLYGON_STIPPLE_ENABLE 0x0000147c + +#define NV30_3D_POLYGON_STIPPLE_PATTERN(i0) (0x00001480 + 0x4*(i0)) +#define NV30_3D_POLYGON_STIPPLE_PATTERN__ESIZE 0x00000004 +#define NV30_3D_POLYGON_STIPPLE_PATTERN__LEN 0x00000020 + +#define NV30_3D_VTX_ATTR_3F(i0) (0x00001500 + 0x10*(i0)) +#define NV30_3D_VTX_ATTR_3F__ESIZE 0x00000010 +#define NV30_3D_VTX_ATTR_3F__LEN 0x00000010 + + +#define NV30_3D_VTX_ATTR_3F_X(i0) (0x00001500 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_3F_Y(i0) (0x00001504 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_3F_Z(i0) (0x00001508 + 0x10*(i0)) + + +#define NV30_3D_VP_CLIP_PLANE(i0, i1) (0x00001600 + 0x10*(i0) + 0x4*(i1)) +#define NV30_3D_VP_CLIP_PLANE__ESIZE 0x00000004 +#define NV30_3D_VP_CLIP_PLANE__LEN 0x00000004 + +#define NV30_3D_VTXBUF(i0) (0x00001680 + 0x4*(i0)) +#define NV30_3D_VTXBUF__ESIZE 0x00000004 +#define NV30_3D_VTXBUF__LEN 0x00000010 +#define NV30_3D_VTXBUF_OFFSET__MASK 0x0fffffff +#define NV30_3D_VTXBUF_OFFSET__SHIFT 0 +#define NV30_3D_VTXBUF_DMA1 0x80000000 + +#define NV40_3D_VTX_CACHE_INVALIDATE 0x00001714 + +#define NV30_3D_VTXFMT(i0) (0x00001740 + 0x4*(i0)) +#define NV30_3D_VTXFMT__ESIZE 0x00000004 +#define NV30_3D_VTXFMT__LEN 0x00000010 +#define NV30_3D_VTXFMT_TYPE__MASK 0x0000000f +#define NV30_3D_VTXFMT_TYPE__SHIFT 0 +#define NV30_3D_VTXFMT_TYPE_B8G8R8A8_UNORM 0x00000000 +#define NV30_3D_VTXFMT_TYPE_V16_SNORM 0x00000001 +#define NV30_3D_VTXFMT_TYPE_V32_FLOAT 0x00000002 +#define NV30_3D_VTXFMT_TYPE_V16_FLOAT 0x00000003 +#define NV30_3D_VTXFMT_TYPE_U8_UNORM 0x00000004 +#define NV30_3D_VTXFMT_TYPE_V16_SSCALED 0x00000005 +#define NV30_3D_VTXFMT_TYPE_U8_USCALED 0x00000007 +#define NV30_3D_VTXFMT_SIZE__MASK 0x000000f0 +#define NV30_3D_VTXFMT_SIZE__SHIFT 4 +#define NV30_3D_VTXFMT_STRIDE__MASK 0x0000ff00 +#define NV30_3D_VTXFMT_STRIDE__SHIFT 8 + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION 0x000017a0 + + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0 + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4 + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8 + +#define NV30_3D_COLOR_MATERIAL_BACK 0x000017b0 + + +#define NV30_3D_COLOR_MATERIAL_BACK_R 0x000017b0 + +#define NV30_3D_COLOR_MATERIAL_BACK_G 0x000017b4 + +#define NV30_3D_COLOR_MATERIAL_BACK_B 0x000017b8 + +#define NV30_3D_COLOR_MATERIAL_BACK_A 0x000017bc + +#define NV30_3D_QUERY_RESET 0x000017c8 + +#define NV30_3D_QUERY_ENABLE 0x000017cc + +#define NV30_3D_QUERY_GET 0x00001800 +#define NV30_3D_QUERY_GET_OFFSET__MASK 0x00ffffff +#define NV30_3D_QUERY_GET_OFFSET__SHIFT 0 +#define NV30_3D_QUERY_GET_UNK24__MASK 0xff000000 +#define NV30_3D_QUERY_GET_UNK24__SHIFT 24 + +#define NV30_3D_VERTEX_BEGIN_END 0x00001808 +#define NV30_3D_VERTEX_BEGIN_END_STOP 0x00000000 +#define NV30_3D_VERTEX_BEGIN_END_POINTS 0x00000001 +#define NV30_3D_VERTEX_BEGIN_END_LINES 0x00000002 +#define NV30_3D_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 +#define NV30_3D_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 +#define NV30_3D_VERTEX_BEGIN_END_TRIANGLES 0x00000005 +#define NV30_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 +#define NV30_3D_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 +#define NV30_3D_VERTEX_BEGIN_END_QUADS 0x00000008 +#define NV30_3D_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 +#define NV30_3D_VERTEX_BEGIN_END_POLYGON 0x0000000a + +#define NV30_3D_VB_ELEMENT_U16 0x0000180c +#define NV30_3D_VB_ELEMENT_U16_0__MASK 0x0000ffff +#define NV30_3D_VB_ELEMENT_U16_0__SHIFT 0 +#define NV30_3D_VB_ELEMENT_U16_1__MASK 0xffff0000 +#define NV30_3D_VB_ELEMENT_U16_1__SHIFT 16 + +#define NV30_3D_VB_ELEMENT_U32 0x00001810 + +#define NV30_3D_VB_VERTEX_BATCH 0x00001814 +#define NV30_3D_VB_VERTEX_BATCH_OFFSET__MASK 0x00ffffff +#define NV30_3D_VB_VERTEX_BATCH_OFFSET__SHIFT 0 +#define NV30_3D_VB_VERTEX_BATCH_COUNT__MASK 0xff000000 +#define NV30_3D_VB_VERTEX_BATCH_COUNT__SHIFT 24 + +#define NV30_3D_VERTEX_DATA 0x00001818 + +#define NV30_3D_IDXBUF_OFFSET 0x0000181c + +#define NV30_3D_IDXBUF_FORMAT 0x00001820 +#define NV30_3D_IDXBUF_FORMAT_DMA1 0x00000001 +#define NV30_3D_IDXBUF_FORMAT_TYPE__MASK 0x000000f0 +#define NV30_3D_IDXBUF_FORMAT_TYPE__SHIFT 4 +#define NV30_3D_IDXBUF_FORMAT_TYPE_U32 0x00000000 +#define NV30_3D_IDXBUF_FORMAT_TYPE_U16 0x00000010 + +#define NV30_3D_VB_INDEX_BATCH 0x00001824 +#define NV30_3D_VB_INDEX_BATCH_START__MASK 0x00ffffff +#define NV30_3D_VB_INDEX_BATCH_START__SHIFT 0 +#define NV30_3D_VB_INDEX_BATCH_COUNT__MASK 0xff000000 +#define NV30_3D_VB_INDEX_BATCH_COUNT__SHIFT 24 + +#define NV30_3D_POLYGON_MODE_FRONT 0x00001828 +#define NV30_3D_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NV30_3D_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NV30_3D_POLYGON_MODE_FRONT_FILL 0x00001b02 + +#define NV30_3D_POLYGON_MODE_BACK 0x0000182c +#define NV30_3D_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NV30_3D_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NV30_3D_POLYGON_MODE_BACK_FILL 0x00001b02 + +#define NV30_3D_CULL_FACE 0x00001830 +#define NV30_3D_CULL_FACE_FRONT 0x00000404 +#define NV30_3D_CULL_FACE_BACK 0x00000405 +#define NV30_3D_CULL_FACE_FRONT_AND_BACK 0x00000408 + +#define NV30_3D_FRONT_FACE 0x00001834 +#define NV30_3D_FRONT_FACE_CW 0x00000900 +#define NV30_3D_FRONT_FACE_CCW 0x00000901 + +#define NV30_3D_POLYGON_SMOOTH_ENABLE 0x00001838 + +#define NV30_3D_CULL_FACE_ENABLE 0x0000183c + +#define NV30_3D_TEX_PALETTE_OFFSET(i0) (0x00001840 + 0x4*(i0)) +#define NV30_3D_TEX_PALETTE_OFFSET__ESIZE 0x00000004 +#define NV30_3D_TEX_PALETTE_OFFSET__LEN 0x00000008 + +#define NV40_3D_TEX_SIZE1(i0) (0x00001840 + 0x4*(i0)) +#define NV40_3D_TEX_SIZE1__ESIZE 0x00000004 +#define NV40_3D_TEX_SIZE1__LEN 0x00000008 +#define NV40_3D_TEX_SIZE1_DEPTH__MASK 0xfff00000 +#define NV40_3D_TEX_SIZE1_DEPTH__SHIFT 20 +#define NV40_3D_TEX_SIZE1_PITCH__MASK 0x0000ffff +#define NV40_3D_TEX_SIZE1_PITCH__SHIFT 0 + +#define NV30_3D_VTX_ATTR_2F(i0) (0x00001880 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_2F__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_2F__LEN 0x00000010 + + +#define NV30_3D_VTX_ATTR_2F_X(i0) (0x00001880 + 0x8*(i0)) + +#define NV30_3D_VTX_ATTR_2F_Y(i0) (0x00001884 + 0x8*(i0)) + +#define NV30_3D_VTX_ATTR_2I(i0) (0x00001900 + 0x4*(i0)) +#define NV30_3D_VTX_ATTR_2I__ESIZE 0x00000004 +#define NV30_3D_VTX_ATTR_2I__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_2I_X__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_2I_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_2I_Y__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_2I_Y__SHIFT 16 + +#define NV30_3D_VTX_ATTR_4UB(i0) (0x00001940 + 0x4*(i0)) +#define NV30_3D_VTX_ATTR_4UB__ESIZE 0x00000004 +#define NV30_3D_VTX_ATTR_4UB__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_4UB_X__MASK 0x000000ff +#define NV30_3D_VTX_ATTR_4UB_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_4UB_Y__MASK 0x0000ff00 +#define NV30_3D_VTX_ATTR_4UB_Y__SHIFT 8 +#define NV30_3D_VTX_ATTR_4UB_Z__MASK 0x00ff0000 +#define NV30_3D_VTX_ATTR_4UB_Z__SHIFT 16 +#define NV30_3D_VTX_ATTR_4UB_W__MASK 0xff000000 +#define NV30_3D_VTX_ATTR_4UB_W__SHIFT 24 + +#define NV30_3D_VTX_ATTR_4I(i0) (0x00001980 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_4I__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_4I__LEN 0x00000010 + +#define NV30_3D_VTX_ATTR_4I_XY(i0) (0x00001980 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_4I_XY_X__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_4I_XY_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_4I_XY_Y__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_4I_XY_Y__SHIFT 16 + +#define NV30_3D_VTX_ATTR_4I_ZW(i0) (0x00001984 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_4I_ZW_Z__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_4I_ZW_Z__SHIFT 0 +#define NV30_3D_VTX_ATTR_4I_ZW_W__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_4I_ZW_W__SHIFT 16 + +#define NV30_3D_TEX_OFFSET(i0) (0x00001a00 + 0x20*(i0)) +#define NV30_3D_TEX_OFFSET__ESIZE 0x00000020 +#define NV30_3D_TEX_OFFSET__LEN 0x00000008 + +#define NV30_3D_TEX_FORMAT(i0) (0x00001a04 + 0x20*(i0)) +#define NV30_3D_TEX_FORMAT__ESIZE 0x00000020 +#define NV30_3D_TEX_FORMAT__LEN 0x00000008 +#define NV30_3D_TEX_FORMAT_DMA0 0x00000001 +#define NV30_3D_TEX_FORMAT_DMA1 0x00000002 +#define NV30_3D_TEX_FORMAT_CUBIC 0x00000004 +#define NV30_3D_TEX_FORMAT_NO_BORDER 0x00000008 +#define NV30_3D_TEX_FORMAT_DIMS__MASK 0x000000f0 +#define NV30_3D_TEX_FORMAT_DIMS__SHIFT 4 +#define NV30_3D_TEX_FORMAT_DIMS_1D 0x00000010 +#define NV30_3D_TEX_FORMAT_DIMS_2D 0x00000020 +#define NV30_3D_TEX_FORMAT_DIMS_3D 0x00000030 +#define NV30_3D_TEX_FORMAT_FORMAT__MASK 0x0000ff00 +#define NV30_3D_TEX_FORMAT_FORMAT__SHIFT 8 +#define NV30_3D_TEX_FORMAT_FORMAT_L8 0x00000000 +#define NV30_3D_TEX_FORMAT_FORMAT_I8 0x00000100 +#define NV30_3D_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200 +#define NV30_3D_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000400 +#define NV30_3D_TEX_FORMAT_FORMAT_R5G6B5 0x00000500 +#define NV30_3D_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000600 +#define NV30_3D_TEX_FORMAT_FORMAT_X8R8G8B8 0x00000700 +#define NV30_3D_TEX_FORMAT_FORMAT_INDEX8 0x00000b00 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT1 0x00000c00 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT3 0x00000e00 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT5 0x00000f00 +#define NV30_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000 +#define NV30_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100 +#define NV30_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200 +#define NV30_3D_TEX_FORMAT_FORMAT_L8_RECT 0x00001300 +#define NV30_3D_TEX_FORMAT_FORMAT_DSDT8_RECT 0x00001700 +#define NV30_3D_TEX_FORMAT_FORMAT_A8L8 0x00001a00 +#define NV30_3D_TEX_FORMAT_FORMAT_I8_RECT 0x00001b00 +#define NV30_3D_TEX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00 +#define NV30_3D_TEX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00 +#define NV30_3D_TEX_FORMAT_FORMAT_A8L8_RECT 0x00002000 +#define NV30_3D_TEX_FORMAT_FORMAT_Z24 0x00002a00 +#define NV30_3D_TEX_FORMAT_FORMAT_Z24_RECT 0x00002b00 +#define NV30_3D_TEX_FORMAT_FORMAT_Z16 0x00002c00 +#define NV30_3D_TEX_FORMAT_FORMAT_Z16_RECT 0x00002d00 +#define NV30_3D_TEX_FORMAT_FORMAT_DSDT8 0x00002800 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO16 0x00003300 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO16_RECT 0x00003600 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO8 0x00004400 +#define NV30_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO8_RECT 0x00004600 +#define NV30_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700 +#define NV30_3D_TEX_FORMAT_FORMAT_A16 0x00003200 +#define NV30_3D_TEX_FORMAT_FORMAT_A16_RECT 0x00003500 +#define NV30_3D_TEX_FORMAT_FORMAT_UNK3F 0x00003f00 +#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00 +#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00 +#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00 +#define NV40_3D_TEX_FORMAT_FORMAT__MASK 0x00001f00 +#define NV40_3D_TEX_FORMAT_FORMAT__SHIFT 8 +#define NV40_3D_TEX_FORMAT_FORMAT_L8 0x00000100 +#define NV40_3D_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200 +#define NV40_3D_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000300 +#define NV40_3D_TEX_FORMAT_FORMAT_R5G6B5 0x00000400 +#define NV40_3D_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000500 +#define NV40_3D_TEX_FORMAT_FORMAT_DXT1 0x00000600 +#define NV40_3D_TEX_FORMAT_FORMAT_DXT3 0x00000700 +#define NV40_3D_TEX_FORMAT_FORMAT_DXT5 0x00000800 +#define NV40_3D_TEX_FORMAT_FORMAT_A8L8 0x00000b00 +#define NV40_3D_TEX_FORMAT_FORMAT_Z24 0x00001000 +#define NV40_3D_TEX_FORMAT_FORMAT_Z16 0x00001200 +#define NV40_3D_TEX_FORMAT_FORMAT_A16 0x00001400 +#define NV40_3D_TEX_FORMAT_FORMAT_A16L16 0x00001500 +#define NV40_3D_TEX_FORMAT_FORMAT_HILO8 0x00001800 +#define NV40_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00001a00 +#define NV40_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00001b00 +#define NV40_3D_TEX_FORMAT_LINEAR 0x00002000 +#define NV40_3D_TEX_FORMAT_RECT 0x00004000 +#define NV40_3D_TEX_FORMAT_MIPMAP_COUNT__MASK 0x000f0000 +#define NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT 16 +#define NV30_3D_TEX_FORMAT_MIPMAP 0x00080000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_U__MASK 0x00f00000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT 20 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_V__MASK 0x0f000000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT 24 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_W__MASK 0xf0000000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT 28 + +#define NV30_3D_TEX_WRAP(i0) (0x00001a08 + 0x20*(i0)) +#define NV30_3D_TEX_WRAP__ESIZE 0x00000020 +#define NV30_3D_TEX_WRAP__LEN 0x00000008 +#define NV30_3D_TEX_WRAP_S__MASK 0x000000ff +#define NV30_3D_TEX_WRAP_S__SHIFT 0 +#define NV30_3D_TEX_WRAP_S_REPEAT 0x00000001 +#define NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002 +#define NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003 +#define NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER 0x00000004 +#define NV30_3D_TEX_WRAP_S_CLAMP 0x00000005 +#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006 +#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007 +#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP 0x00000008 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION__MASK 0x00000070 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION__SHIFT 4 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF 0x00000000 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_QUALITY 0x00000020 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_PERFORMANCE 0x00000030 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_HIGH_PERFORMANCE 0x00000070 +#define NV30_3D_TEX_WRAP_T__MASK 0x00000f00 +#define NV30_3D_TEX_WRAP_T__SHIFT 8 +#define NV30_3D_TEX_WRAP_T_REPEAT 0x00000100 +#define NV30_3D_TEX_WRAP_T_MIRRORED_REPEAT 0x00000200 +#define NV30_3D_TEX_WRAP_T_CLAMP_TO_EDGE 0x00000300 +#define NV30_3D_TEX_WRAP_T_CLAMP_TO_BORDER 0x00000400 +#define NV30_3D_TEX_WRAP_T_CLAMP 0x00000500 +#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP_TO_EDGE 0x00000600 +#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP_TO_BORDER 0x00000700 +#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP 0x00000800 +#define NV30_3D_TEX_WRAP_EXPAND_NORMAL 0x0000f000 +#define NV30_3D_TEX_WRAP_R__MASK 0x000f0000 +#define NV30_3D_TEX_WRAP_R__SHIFT 16 +#define NV30_3D_TEX_WRAP_R_REPEAT 0x00010000 +#define NV30_3D_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000 +#define NV30_3D_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000 +#define NV30_3D_TEX_WRAP_R_CLAMP_TO_BORDER 0x00040000 +#define NV30_3D_TEX_WRAP_R_CLAMP 0x00050000 +#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000 +#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000 +#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP 0x00080000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER__MASK 0x00f00000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER__SHIFT 20 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_NONE 0x00000000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_RED 0x00100000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_GREEN 0x00200000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_BLUE 0x00400000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_ALL 0x00f00000 +#define NV30_3D_TEX_WRAP_RCOMP__MASK 0xf0000000 +#define NV30_3D_TEX_WRAP_RCOMP__SHIFT 28 +#define NV30_3D_TEX_WRAP_RCOMP_NEVER 0x00000000 +#define NV30_3D_TEX_WRAP_RCOMP_GREATER 0x10000000 +#define NV30_3D_TEX_WRAP_RCOMP_EQUAL 0x20000000 +#define NV30_3D_TEX_WRAP_RCOMP_GEQUAL 0x30000000 +#define NV30_3D_TEX_WRAP_RCOMP_LESS 0x40000000 +#define NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL 0x50000000 +#define NV30_3D_TEX_WRAP_RCOMP_LEQUAL 0x60000000 +#define NV30_3D_TEX_WRAP_RCOMP_ALWAYS 0x70000000 + +#define NV30_3D_TEX_ENABLE(i0) (0x00001a0c + 0x20*(i0)) +#define NV30_3D_TEX_ENABLE__ESIZE 0x00000020 +#define NV30_3D_TEX_ENABLE__LEN 0x00000008 +#define NV30_3D_TEX_ENABLE_ANISO__MASK 0x00000030 +#define NV30_3D_TEX_ENABLE_ANISO__SHIFT 4 +#define NV30_3D_TEX_ENABLE_ANISO_NONE 0x00000000 +#define NV30_3D_TEX_ENABLE_ANISO_2X 0x00000010 +#define NV30_3D_TEX_ENABLE_ANISO_4X 0x00000020 +#define NV30_3D_TEX_ENABLE_ANISO_8X 0x00000030 +#define NV40_3D_TEX_ENABLE_ANISO__MASK 0x000000f0 +#define NV40_3D_TEX_ENABLE_ANISO__SHIFT 4 +#define NV40_3D_TEX_ENABLE_ANISO_NONE 0x00000000 +#define NV40_3D_TEX_ENABLE_ANISO_2X 0x00000010 +#define NV40_3D_TEX_ENABLE_ANISO_4X 0x00000020 +#define NV40_3D_TEX_ENABLE_ANISO_6X 0x00000030 +#define NV40_3D_TEX_ENABLE_ANISO_8X 0x00000040 +#define NV40_3D_TEX_ENABLE_ANISO_10X 0x00000050 +#define NV40_3D_TEX_ENABLE_ANISO_12X 0x00000060 +#define NV40_3D_TEX_ENABLE_ANISO_16X 0x00000070 +#define NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK 0x0003c000 +#define NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT 14 +#define NV40_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK 0x00038000 +#define NV40_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT 15 +#define NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK 0x3c000000 +#define NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT 26 +#define NV40_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK 0x38000000 +#define NV40_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT 27 +#define NV30_3D_TEX_ENABLE_ENABLE 0x40000000 +#define NV40_3D_TEX_ENABLE_ENABLE 0x80000000 + +#define NV30_3D_TEX_SWIZZLE(i0) (0x00001a10 + 0x20*(i0)) +#define NV30_3D_TEX_SWIZZLE__ESIZE 0x00000020 +#define NV30_3D_TEX_SWIZZLE__LEN 0x00000008 +#define NV30_3D_TEX_SWIZZLE_S1_W__MASK 0x00000003 +#define NV30_3D_TEX_SWIZZLE_S1_W__SHIFT 0 +#define NV30_3D_TEX_SWIZZLE_S1_W_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_W_Z 0x00000001 +#define NV30_3D_TEX_SWIZZLE_S1_W_Y 0x00000002 +#define NV30_3D_TEX_SWIZZLE_S1_W_X 0x00000003 +#define NV30_3D_TEX_SWIZZLE_S1_Z__MASK 0x0000000c +#define NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT 2 +#define NV30_3D_TEX_SWIZZLE_S1_Z_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_Z_Z 0x00000004 +#define NV30_3D_TEX_SWIZZLE_S1_Z_Y 0x00000008 +#define NV30_3D_TEX_SWIZZLE_S1_Z_X 0x0000000c +#define NV30_3D_TEX_SWIZZLE_S1_Y__MASK 0x00000030 +#define NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT 4 +#define NV30_3D_TEX_SWIZZLE_S1_Y_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_Y_Z 0x00000010 +#define NV30_3D_TEX_SWIZZLE_S1_Y_Y 0x00000020 +#define NV30_3D_TEX_SWIZZLE_S1_Y_X 0x00000030 +#define NV30_3D_TEX_SWIZZLE_S1_X__MASK 0x000000c0 +#define NV30_3D_TEX_SWIZZLE_S1_X__SHIFT 6 +#define NV30_3D_TEX_SWIZZLE_S1_X_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_X_Z 0x00000040 +#define NV30_3D_TEX_SWIZZLE_S1_X_Y 0x00000080 +#define NV30_3D_TEX_SWIZZLE_S1_X_X 0x000000c0 +#define NV30_3D_TEX_SWIZZLE_S0_W__MASK 0x00000300 +#define NV30_3D_TEX_SWIZZLE_S0_W__SHIFT 8 +#define NV30_3D_TEX_SWIZZLE_S0_W_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_W_ONE 0x00000100 +#define NV30_3D_TEX_SWIZZLE_S0_W_S1 0x00000200 +#define NV30_3D_TEX_SWIZZLE_S0_Z__MASK 0x00000c00 +#define NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT 10 +#define NV30_3D_TEX_SWIZZLE_S0_Z_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_Z_ONE 0x00000400 +#define NV30_3D_TEX_SWIZZLE_S0_Z_S1 0x00000800 +#define NV30_3D_TEX_SWIZZLE_S0_Y__MASK 0x00003000 +#define NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT 12 +#define NV30_3D_TEX_SWIZZLE_S0_Y_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_Y_ONE 0x00001000 +#define NV30_3D_TEX_SWIZZLE_S0_Y_S1 0x00002000 +#define NV30_3D_TEX_SWIZZLE_S0_X__MASK 0x0000c000 +#define NV30_3D_TEX_SWIZZLE_S0_X__SHIFT 14 +#define NV30_3D_TEX_SWIZZLE_S0_X_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_X_ONE 0x00004000 +#define NV30_3D_TEX_SWIZZLE_S0_X_S1 0x00008000 +#define NV30_3D_TEX_SWIZZLE_RECT_PITCH__MASK 0xffff0000 +#define NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT 16 + +#define NV30_3D_TEX_FILTER(i0) (0x00001a14 + 0x20*(i0)) +#define NV30_3D_TEX_FILTER__ESIZE 0x00000020 +#define NV30_3D_TEX_FILTER__LEN 0x00000008 +#define NV30_3D_TEX_FILTER_LOD_BIAS__MASK 0x00000f00 +#define NV30_3D_TEX_FILTER_LOD_BIAS__SHIFT 8 +#define NV30_3D_TEX_FILTER_MIN__MASK 0x000f0000 +#define NV30_3D_TEX_FILTER_MIN__SHIFT 16 +#define NV30_3D_TEX_FILTER_MIN_NEAREST 0x00010000 +#define NV30_3D_TEX_FILTER_MIN_LINEAR 0x00020000 +#define NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x00030000 +#define NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x00040000 +#define NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x00050000 +#define NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x00060000 +#define NV30_3D_TEX_FILTER_MAG__MASK 0x0f000000 +#define NV30_3D_TEX_FILTER_MAG__SHIFT 24 +#define NV30_3D_TEX_FILTER_MAG_NEAREST 0x01000000 +#define NV30_3D_TEX_FILTER_MAG_LINEAR 0x02000000 +#define NV30_3D_TEX_FILTER_SIGNED_BLUE 0x10000000 +#define NV30_3D_TEX_FILTER_SIGNED_GREEN 0x20000000 +#define NV30_3D_TEX_FILTER_SIGNED_RED 0x40000000 +#define NV30_3D_TEX_FILTER_SIGNED_ALPHA 0x80000000 + +#define NV30_3D_TEX_NPOT_SIZE(i0) (0x00001a18 + 0x20*(i0)) +#define NV30_3D_TEX_NPOT_SIZE__ESIZE 0x00000020 +#define NV30_3D_TEX_NPOT_SIZE__LEN 0x00000008 +#define NV30_3D_TEX_NPOT_SIZE_H__MASK 0x0000ffff +#define NV30_3D_TEX_NPOT_SIZE_H__SHIFT 0 +#define NV30_3D_TEX_NPOT_SIZE_W__MASK 0xffff0000 +#define NV30_3D_TEX_NPOT_SIZE_W__SHIFT 16 + +#define NV30_3D_TEX_BORDER_COLOR(i0) (0x00001a1c + 0x20*(i0)) +#define NV30_3D_TEX_BORDER_COLOR__ESIZE 0x00000020 +#define NV30_3D_TEX_BORDER_COLOR__LEN 0x00000008 +#define NV30_3D_TEX_BORDER_COLOR_B__MASK 0x000000ff +#define NV30_3D_TEX_BORDER_COLOR_B__SHIFT 0 +#define NV30_3D_TEX_BORDER_COLOR_G__MASK 0x0000ff00 +#define NV30_3D_TEX_BORDER_COLOR_G__SHIFT 8 +#define NV30_3D_TEX_BORDER_COLOR_R__MASK 0x00ff0000 +#define NV30_3D_TEX_BORDER_COLOR_R__SHIFT 16 +#define NV30_3D_TEX_BORDER_COLOR_A__MASK 0xff000000 +#define NV30_3D_TEX_BORDER_COLOR_A__SHIFT 24 + +#define NV30_3D_VTX_ATTR_4F(i0) (0x00001c00 + 0x10*(i0)) +#define NV30_3D_VTX_ATTR_4F__ESIZE 0x00000010 +#define NV30_3D_VTX_ATTR_4F__LEN 0x00000010 + + +#define NV30_3D_VTX_ATTR_4F_X(i0) (0x00001c00 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_4F_Y(i0) (0x00001c04 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_4F_Z(i0) (0x00001c08 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_4F_W(i0) (0x00001c0c + 0x10*(i0)) + +#define NV30_3D_FP_CONTROL 0x00001d60 +#define NV30_3D_FP_CONTROL_USED_REGS_MINUS1_DIV2__MASK 0x0000000f +#define NV30_3D_FP_CONTROL_USED_REGS_MINUS1_DIV2__SHIFT 0 +#define NV30_3D_FP_CONTROL_USES_KIL 0x00000080 +#define NV40_3D_FP_CONTROL_KIL 0x00000080 +#define NV40_3D_FP_CONTROL_TEMP_COUNT__MASK 0xff000000 +#define NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT 24 + +#define NV30_3D_DEPTH_CONTROL 0x00001d78 +#define NV30_3D_DEPTH_CONTROL_CLAMP 0x000000f0 + +#define NV30_3D_MULTISAMPLE_CONTROL 0x00001d7c +#define NV30_3D_MULTISAMPLE_CONTROL_ENABLE 0x00000001 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_COVERAGE 0x00000010 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_ONE 0x00000100 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE__MASK 0xffff0000 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE__SHIFT 16 + +#define NV30_3D_COORD_CONVENTIONS 0x00001d88 +#define NV30_3D_COORD_CONVENTIONS_HEIGHT__MASK 0x00000fff +#define NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT 0 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN__MASK 0x00001000 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN__SHIFT 12 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN_NORMAL 0x00000000 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED 0x00001000 +#define NV30_3D_COORD_CONVENTIONS_CENTER__MASK 0x00010000 +#define NV30_3D_COORD_CONVENTIONS_CENTER__SHIFT 16 +#define NV30_3D_COORD_CONVENTIONS_CENTER_HALF_INTEGER 0x00000000 +#define NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER 0x00010000 + +#define NV30_3D_CLEAR_DEPTH_VALUE 0x00001d8c + +#define NV30_3D_CLEAR_COLOR_VALUE 0x00001d90 +#define NV30_3D_CLEAR_COLOR_VALUE_B__MASK 0x000000ff +#define NV30_3D_CLEAR_COLOR_VALUE_B__SHIFT 0 +#define NV30_3D_CLEAR_COLOR_VALUE_G__MASK 0x0000ff00 +#define NV30_3D_CLEAR_COLOR_VALUE_G__SHIFT 8 +#define NV30_3D_CLEAR_COLOR_VALUE_R__MASK 0x00ff0000 +#define NV30_3D_CLEAR_COLOR_VALUE_R__SHIFT 16 +#define NV30_3D_CLEAR_COLOR_VALUE_A__MASK 0xff000000 +#define NV30_3D_CLEAR_COLOR_VALUE_A__SHIFT 24 + +#define NV30_3D_CLEAR_BUFFERS 0x00001d94 +#define NV30_3D_CLEAR_BUFFERS_DEPTH 0x00000001 +#define NV30_3D_CLEAR_BUFFERS_STENCIL 0x00000002 +#define NV30_3D_CLEAR_BUFFERS_COLOR_R 0x00000010 +#define NV30_3D_CLEAR_BUFFERS_COLOR_G 0x00000020 +#define NV30_3D_CLEAR_BUFFERS_COLOR_B 0x00000040 +#define NV30_3D_CLEAR_BUFFERS_COLOR_A 0x00000080 + +#define NV30_3D_DO_VERTICES 0x00001dac + +#define NV30_3D_LINE_STIPPLE_ENABLE 0x00001db4 + +#define NV30_3D_LINE_STIPPLE_PATTERN 0x00001db8 +#define NV30_3D_LINE_STIPPLE_PATTERN_FACTOR__MASK 0x0000ffff +#define NV30_3D_LINE_STIPPLE_PATTERN_FACTOR__SHIFT 0 +#define NV30_3D_LINE_STIPPLE_PATTERN_PATTERN__MASK 0xffff0000 +#define NV30_3D_LINE_STIPPLE_PATTERN_PATTERN__SHIFT 16 + +#define NV30_3D_BACK_MATERIAL_SHININESS(i0) (0x00001e20 + 0x4*(i0)) +#define NV30_3D_BACK_MATERIAL_SHININESS__ESIZE 0x00000004 +#define NV30_3D_BACK_MATERIAL_SHININESS__LEN 0x00000006 + +#define NV30_3D_VTX_ATTR_1F(i0) (0x00001e40 + 0x4*(i0)) +#define NV30_3D_VTX_ATTR_1F__ESIZE 0x00000004 +#define NV30_3D_VTX_ATTR_1F__LEN 0x00000010 + +#define NV30_3D_ENGINE 0x00001e94 +#define NV30_3D_ENGINE_FP 0x00000001 +#define NV30_3D_ENGINE_VP 0x00000002 +#define NV30_3D_ENGINE_FIXED 0x00000004 + +#define NV30_3D_VP_UPLOAD_FROM_ID 0x00001e9c + +#define NV30_3D_VP_START_FROM_ID 0x00001ea0 + +#define NV30_3D_POINT_PARAMETERS(i0) (0x00001ec0 + 0x4*(i0)) +#define NV30_3D_POINT_PARAMETERS__ESIZE 0x00000004 +#define NV30_3D_POINT_PARAMETERS__LEN 0x00000008 + +#define NV30_3D_POINT_SIZE 0x00001ee0 + +#define NV30_3D_POINT_PARAMETERS_ENABLE 0x00001ee4 + +#define NV30_3D_POINT_SPRITE 0x00001ee8 +#define NV30_3D_POINT_SPRITE_ENABLE 0x00000001 +#define NV30_3D_POINT_SPRITE_R_MODE__MASK 0x00000006 +#define NV30_3D_POINT_SPRITE_R_MODE__SHIFT 1 +#define NV30_3D_POINT_SPRITE_R_MODE_ZERO 0x00000000 +#define NV30_3D_POINT_SPRITE_R_MODE_R 0x00000002 +#define NV30_3D_POINT_SPRITE_R_MODE_S 0x00000004 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_0 0x00000100 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_1 0x00000200 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_2 0x00000400 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_3 0x00000800 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_4 0x00001000 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_5 0x00002000 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_6 0x00004000 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_7 0x00008000 + +#define NV30_3D_VP_UPLOAD_CONST_ID 0x00001efc + +#define NV30_3D_VP_UPLOAD_CONST(i0) (0x00001f00 + 0x10*(i0)) +#define NV30_3D_VP_UPLOAD_CONST__ESIZE 0x00000010 +#define NV30_3D_VP_UPLOAD_CONST__LEN 0x00000004 + + +#define NV30_3D_VP_UPLOAD_CONST_X(i0) (0x00001f00 + 0x10*(i0)) + +#define NV30_3D_VP_UPLOAD_CONST_Y(i0) (0x00001f04 + 0x10*(i0)) + +#define NV30_3D_VP_UPLOAD_CONST_Z(i0) (0x00001f08 + 0x10*(i0)) + +#define NV30_3D_VP_UPLOAD_CONST_W(i0) (0x00001f0c + 0x10*(i0)) + +#define NV30_3D_UNK1F80(i0) (0x00001f80 + 0x4*(i0)) +#define NV30_3D_UNK1F80__ESIZE 0x00000004 +#define NV30_3D_UNK1F80__LEN 0x00000010 + +#define NV40_3D_TEX_CACHE_CTL 0x00001fd8 + +#define NV40_3D_VP_ATTRIB_EN 0x00001ff0 + +#define NV40_3D_VP_RESULT_EN 0x00001ff4 + + +#endif /* NV30_40_3D_XML */ diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c index 0c3d43fd57..d6ede5b40a 100644 --- a/src/gallium/drivers/nvfx/nv30_fragtex.c +++ b/src/gallium/drivers/nvfx/nv30_fragtex.c @@ -14,11 +14,11 @@ nv30_sampler_state_init(struct pipe_context *pipe, if (cso->max_anisotropy >= 2) { if (cso->max_anisotropy >= 8) - ps->en |= NV34TCL_TX_ENABLE_ANISO_8X; + ps->en |= NV30_3D_TEX_ENABLE_ANISO_8X; else if (cso->max_anisotropy >= 4) - ps->en |= NV34TCL_TX_ENABLE_ANISO_4X; + ps->en |= NV30_3D_TEX_ENABLE_ANISO_4X; else if (cso->max_anisotropy >= 2) - ps->en |= NV34TCL_TX_ENABLE_ANISO_2X; + ps->en |= NV30_3D_TEX_ENABLE_ANISO_2X; } limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0)); @@ -27,7 +27,7 @@ nv30_sampler_state_init(struct pipe_context *pipe, ps->max_lod = (int)CLAMP(cso->max_lod, 0.0, 15.0); ps->min_lod = (int)CLAMP(cso->min_lod, 0.0, 15.0); - ps->en |= NV34TCL_TX_ENABLE_ENABLE; + ps->en |= NV30_3D_TEX_ENABLE_ENABLE; } void @@ -42,10 +42,10 @@ nv30_sampler_view_init(struct pipe_context *pipe, assert(tf->fmt[0] >= 0); txf = sv->u.init_fmt; - txf |= (level != sv->base.last_level ? NV34TCL_TX_FORMAT_MIPMAP : 0); - txf |= util_logbase2(u_minify(pt->width0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT; - txf |= util_logbase2(u_minify(pt->height0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT; - txf |= util_logbase2(u_minify(pt->depth0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT; + txf |= (level != sv->base.last_level ? NV30_3D_TEX_FORMAT_MIPMAP : 0); + txf |= util_logbase2(u_minify(pt->width0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT; + txf |= util_logbase2(u_minify(pt->height0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT; + txf |= util_logbase2(u_minify(pt->depth0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT; txf |= 0x10000; sv->u.nv30.fmt[0] = tf->fmt[0] | txf; @@ -53,7 +53,7 @@ nv30_sampler_view_init(struct pipe_context *pipe, sv->u.nv30.fmt[2] = tf->fmt[2] | txf; sv->u.nv30.fmt[3] = tf->fmt[3] | txf; - sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT); + sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT); if(pt->height0 <= 1 || util_format_is_compressed(sv->base.format)) sv->u.nv30.rect = -1; @@ -102,13 +102,13 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit) txf = sv->u.nv30.fmt[ps->compare + (use_rect ? 2 : 0)]; MARK_RING(chan, 9, 2); - OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_OFFSET(unit), 8)); OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0); OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR, - NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); + NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1); OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap); - OUT_RING(chan, ps->en | (min_lod << NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT) | (max_lod << NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT)); + OUT_RING(chan, ps->en | (min_lod << NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT) | (max_lod << NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT)); OUT_RING(chan, sv->swizzle); OUT_RING(chan, ps->filt | sv->filt); OUT_RING(chan, sv->npot_size); diff --git a/src/gallium/drivers/nvfx/nv30_vertprog.h b/src/gallium/drivers/nvfx/nv30_vertprog.h index 9a68f5c1fb..e8c16b0341 100644 --- a/src/gallium/drivers/nvfx/nv30_vertprog.h +++ b/src/gallium/drivers/nvfx/nv30_vertprog.h @@ -60,6 +60,9 @@ /* DWORD 0 */ +/* guess that this is the same as nv40 */ +#define NV30_VP_INST_INDEX_INPUT (1 << 27) + #define NV30_VP_INST_ADDR_REG_SELECT_1 (1 << 24) #define NV30_VP_INST_SRC2_ABS (1 << 23) /* guess */ #define NV30_VP_INST_SRC1_ABS (1 << 22) /* guess */ @@ -136,6 +139,9 @@ # define NV30_VP_INST_DEST_TC(n) (8+(n)) # define NV30_VP_INST_DEST_CLP(n) (17 + (n)) +/* guess that this is the same as nv40 */ +#define NV30_VP_INST_INDEX_CONST (1 << 1) + /* Useful to split the source selection regs into their pieces */ #define NV30_VP_SRC0_HIGH_SHIFT 6 #define NV30_VP_SRC0_HIGH_MASK 0x00007FC0 diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c index 106ce71a07..d4fb73702d 100644 --- a/src/gallium/drivers/nvfx/nv40_fragtex.c +++ b/src/gallium/drivers/nvfx/nv40_fragtex.c @@ -14,19 +14,19 @@ nv40_sampler_state_init(struct pipe_context *pipe, ps->wrap |= (1 << 5); if (cso->max_anisotropy >= 16) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_16X; else if (cso->max_anisotropy >= 12) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_12X; else if (cso->max_anisotropy >= 10) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_10X; else if (cso->max_anisotropy >= 8) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_8X; else if (cso->max_anisotropy >= 6) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_6X; else if (cso->max_anisotropy >= 4) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_4X; else - ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_2X; } limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0)); @@ -35,7 +35,7 @@ nv40_sampler_state_init(struct pipe_context *pipe, ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0); ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0); - ps->en |= NV40TCL_TEX_ENABLE_ENABLE; + ps->en |= NV40_3D_TEX_ENABLE_ENABLE; } void @@ -52,21 +52,21 @@ nv40_sampler_view_init(struct pipe_context *pipe, txf = sv->u.init_fmt; txf |= 0x8000; if(pt->target == PIPE_TEXTURE_CUBE) - txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT); + txf |= ((pt->last_level + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT); else - txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT); + txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT); if (!mt->linear_pitch) sv->u.nv40.npot_size2 = 0; else { sv->u.nv40.npot_size2 = mt->linear_pitch; - txf |= NV40TCL_TEX_FORMAT_LINEAR; + txf |= NV40_3D_TEX_FORMAT_LINEAR; } sv->u.nv40.fmt[0] = tf->fmt[4] | txf; sv->u.nv40.fmt[1] = tf->fmt[5] | txf; - sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40TCL_TEX_SIZE1_DEPTH_SHIFT); + sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40_3D_TEX_SIZE1_DEPTH__SHIFT); sv->lod_offset = (sv->base.first_level - level) * 256; sv->max_lod_limit = (sv->base.last_level - level) * 256; @@ -87,17 +87,17 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit) txf = sv->u.nv40.fmt[ps->compare] | ps->fmt; MARK_RING(chan, 11, 2); - OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_OFFSET(unit), 8)); OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0); OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR, - NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); + NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1); OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap); OUT_RING(chan, ps->en | (min_lod << 19) | (max_lod << 7)); OUT_RING(chan, sv->swizzle); OUT_RING(chan, ps->filt | sv->filt); OUT_RING(chan, sv->npot_size); OUT_RING(chan, ps->bcol); - OUT_RING(chan, RING_3D(NV40TCL_TEX_SIZE1(unit), 1)); + OUT_RING(chan, RING_3D(NV40_3D_TEX_SIZE1(unit), 1)); OUT_RING(chan, sv->u.nv40.npot_size2); nvfx->hw_txf[unit] = txf; diff --git a/src/gallium/drivers/nvfx/nv40_vertprog.h b/src/gallium/drivers/nvfx/nv40_vertprog.h index 3d0a1fe3d1..c1f2208f51 100644 --- a/src/gallium/drivers/nvfx/nv40_vertprog.h +++ b/src/gallium/drivers/nvfx/nv40_vertprog.h @@ -38,6 +38,7 @@ #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29) /* use address reg as index into attribs */ #define NV40_VP_INST_INDEX_INPUT (1 << 27) +#define NV40_VP_INST_SATURATE (1 << 26) #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25) #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24) #define NV40_VP_INST_SRC2_ABS (1 << 23) diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c index 5a2fa14c88..95834d2327 100644 --- a/src/gallium/drivers/nvfx/nvfx_context.c +++ b/src/gallium/drivers/nvfx/nvfx_context.c @@ -13,14 +13,14 @@ nvfx_flush(struct pipe_context *pipe, unsigned flags, struct nvfx_context *nvfx = nvfx_context(pipe); struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; /* XXX: we need to actually be intelligent here */ if (flags & PIPE_FLUSH_TEXTURE_CACHE) { - BEGIN_RING(chan, eng3d, 0x1fd8, 1); - OUT_RING (chan, 2); - BEGIN_RING(chan, eng3d, 0x1fd8, 1); - OUT_RING (chan, 1); + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(0x1fd8, 1)); + OUT_RING(chan, 2); + OUT_RING(chan, RING_3D(0x1fd8, 1)); + OUT_RING(chan, 1); } FIRE_RING(chan); @@ -76,6 +76,7 @@ nvfx_create(struct pipe_screen *pscreen, void *priv) nvfx->pipe.flush = nvfx_flush; nvfx->is_nv4x = screen->is_nv4x; + nvfx->use_nv4x = screen->use_nv4x; /* TODO: it seems that nv30 might have fixed function clipping usable with vertex programs * However, my code for that doesn't work, so use vp clipping for all cards, which works. */ diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h index 4c654bfa8b..6ef2a6945d 100644 --- a/src/gallium/drivers/nvfx/nvfx_context.h +++ b/src/gallium/drivers/nvfx/nvfx_context.h @@ -18,7 +18,7 @@ #include "nouveau/nouveau_winsys.h" #include "nouveau/nouveau_gldefs.h" - +#include "nv30-40_3d.xml.h" #include "nvfx_state.h" #define NOUVEAU_ERR(fmt, args...) \ @@ -141,22 +141,17 @@ struct nvfx_context { struct nvfx_screen *screen; unsigned is_nv4x; /* either 0 or ~0 */ + unsigned use_nv4x; /* either 0 or ~0 */ boolean use_vp_clipping; struct draw_context *draw; - struct blitter_context* blitter; + /* one is for user-requested operations, the other is for temporary copying inside them */ + struct blitter_context* blitter[2]; + unsigned blitters_in_use; struct list_head render_cache; /* HW state derived from pipe states */ struct nvfx_state state; - struct { - struct nvfx_vertex_program *vertprog; - - unsigned nr_attribs; - unsigned hw[PIPE_MAX_SHADER_INPUTS]; - unsigned draw[PIPE_MAX_SHADER_INPUTS]; - unsigned emit[PIPE_MAX_SHADER_INPUTS]; - } swtnl; enum { HW, SWTNL, SWRAST @@ -168,7 +163,7 @@ struct nvfx_context { struct pipe_scissor_state scissor; unsigned stipple[32]; struct pipe_clip_state clip; - struct nvfx_vertex_program *vertprog; + struct nvfx_pipe_vertex_program *vertprog; struct nvfx_pipe_fragment_program *fragprog; struct pipe_resource *constbuf[PIPE_SHADER_TYPES]; unsigned constbuf_nr[PIPE_SHADER_TYPES]; @@ -183,6 +178,7 @@ struct nvfx_context { struct nvfx_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS]; struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS]; struct nvfx_pipe_fragment_program* dummy_fs; + struct pipe_query* query; unsigned nr_samplers; unsigned nr_textures; @@ -199,13 +195,14 @@ struct nvfx_context { int use_vertex_buffers; unsigned hw_vtxelt_nr; - uint8_t hw_samplers; - uint32_t hw_txf[8]; + unsigned hw_samplers; + uint32_t hw_txf[16]; struct nvfx_render_target hw_rt[4]; struct nvfx_render_target hw_zeta; int hw_pointsprite_control; int hw_vp_output; struct nvfx_fragment_program* hw_fragprog; + struct nvfx_vertex_program* hw_vertprog; unsigned relocs_needed; }; @@ -324,6 +321,7 @@ extern void nvfx_init_transfer_functions(struct pipe_context *pipe); /* nvfx_vbo.c */ extern boolean nvfx_vbo_validate(struct nvfx_context *nvfx); +extern void nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx); extern void nvfx_vbo_relocate(struct nvfx_context *nvfx); extern void nvfx_idxbuf_validate(struct nvfx_context* nvfx); extern void nvfx_idxbuf_relocate(struct nvfx_context* nvfx); @@ -346,25 +344,25 @@ static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan, unsigned att { switch (ncomp) { case 4: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_4F_X(attrib), 4)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_4F_X(attrib), 4)); OUT_RING(chan, fui(v[0])); OUT_RING(chan, fui(v[1])); OUT_RING(chan, fui(v[2])); OUT_RING(chan, fui(v[3])); break; case 3: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_3F_X(attrib), 3)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_3F_X(attrib), 3)); OUT_RING(chan, fui(v[0])); OUT_RING(chan, fui(v[1])); OUT_RING(chan, fui(v[2])); break; case 2: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_2F_X(attrib), 2)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_2F_X(attrib), 2)); OUT_RING(chan, fui(v[0])); OUT_RING(chan, fui(v[1])); break; case 1: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_1F(attrib), 1)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_1F(attrib), 1)); OUT_RING(chan, fui(v[0])); break; } diff --git a/src/gallium/drivers/nvfx/nvfx_draw.c b/src/gallium/drivers/nvfx/nvfx_draw.c index 2601d5b8e2..61f888a8ea 100644 --- a/src/gallium/drivers/nvfx/nvfx_draw.c +++ b/src/gallium/drivers/nvfx/nvfx_draw.c @@ -1,6 +1,5 @@ #include "pipe/p_shader_tokens.h" #include "util/u_inlines.h" -#include "tgsi/tgsi_ureg.h" #include "util/u_pack_color.h" @@ -11,11 +10,6 @@ #include "nvfx_context.h" #include "nvfx_resource.h" -/* Simple, but crappy, swtnl path, hopefully we wont need to hit this very - * often at all. Uses "quadro style" vertex submission + a fixed vertex - * layout to avoid the need to generate a vertex program or vtxfmt. - */ - struct nvfx_render_stage { struct draw_stage stage; struct nvfx_context *nvfx; @@ -28,58 +22,18 @@ nvfx_render_stage(struct draw_stage *stage) return (struct nvfx_render_stage *)stage; } -static INLINE void -nvfx_render_vertex(struct nvfx_context *nvfx, const struct vertex_header *v) +static void +nvfx_render_flush(struct draw_stage *stage, unsigned flags) { - struct nvfx_screen *screen = nvfx->screen; - struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - unsigned i; + struct nvfx_render_stage *rs = nvfx_render_stage(stage); + struct nvfx_context *nvfx = rs->nvfx; + struct nouveau_channel *chan = nvfx->screen->base.channel; - for (i = 0; i < nvfx->swtnl.nr_attribs; i++) { - unsigned idx = nvfx->swtnl.draw[i]; - unsigned hw = nvfx->swtnl.hw[i]; - - WAIT_RING(chan, 5); - switch (nvfx->swtnl.emit[i]) { - case EMIT_OMIT: - break; - case EMIT_1F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 1); - break; - case EMIT_2F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 2); - break; - case EMIT_3F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 3); - break; - case EMIT_4F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 4); - break; - case 0xff: - BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4F_X(hw), 4); - OUT_RING (chan, fui(v->data[idx][0] / v->data[idx][3])); - OUT_RING (chan, fui(v->data[idx][1] / v->data[idx][3])); - OUT_RING (chan, fui(v->data[idx][2] / v->data[idx][3])); - OUT_RING (chan, fui(1.0f / v->data[idx][3])); - break; - case EMIT_4UB: - BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4UB(hw), 1); - OUT_RING (chan, pack_ub4(float_to_ubyte(v->data[idx][0]), - float_to_ubyte(v->data[idx][1]), - float_to_ubyte(v->data[idx][2]), - float_to_ubyte(v->data[idx][3]))); - case EMIT_4UB_BGRA: - BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4UB(hw), 1); - OUT_RING (chan, pack_ub4(float_to_ubyte(v->data[idx][2]), - float_to_ubyte(v->data[idx][1]), - float_to_ubyte(v->data[idx][0]), - float_to_ubyte(v->data[idx][3]))); - break; - default: - assert(0); - break; - } + if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) { + assert(AVAIL_RING(chan) >= 2); + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP); + rs->prim = NV30_3D_VERTEX_BEGIN_END_STOP; } } @@ -92,82 +46,87 @@ nvfx_render_prim(struct draw_stage *stage, struct prim_header *prim, struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - unsigned i; + boolean no_elements = nvfx->vertprog->draw_no_elements; + unsigned num_attribs = nvfx->vertprog->draw_elements; - /* Ensure there's room for 4xfloat32 + potentially 3 begin/end */ - if (AVAIL_RING(chan) < ((count * 20) + 6)) { - if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { - NOUVEAU_ERR("AIII, missed flush\n"); - assert(0); - } + /* we need to account the flush as well here even if it is done afterthis + * function + */ + if (AVAIL_RING(chan) < ((1 + count * num_attribs * 4) + 6 + 64)) { + nvfx_render_flush(stage, 0); FIRE_RING(chan); nvfx_state_emit(nvfx); + + assert(AVAIL_RING(chan) >= ((1 + count * num_attribs * 4) + 6 + 64)); } /* Switch primitive modes if necessary */ if (rs->prim != mode) { - if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); - OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); + if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) { + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP); } - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); + /* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */ + /* this seems to cause issues on nv3x, and also be unneeded there */ + if(nvfx->is_nv4x) + { + int i; + for(i = 0; i < 32; ++i) + { + OUT_RING(chan, RING_3D(0x1dac, 1)); + OUT_RING(chan, 0); + } + } + + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); OUT_RING (chan, mode); rs->prim = mode; } - /* Emit vertex data */ - for (i = 0; i < count; i++) - nvfx_render_vertex(nvfx, prim->v[i]); - - /* If it's likely we'll need to empty the push buffer soon, finish - * off the primitive now. - */ - if (AVAIL_RING(chan) < ((count * 20) + 6)) { - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); - OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); - rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP; + OUT_RING(chan, RING_3D_NI(NV30_3D_VERTEX_DATA, num_attribs * 4 * count)); + if(no_elements) { + OUT_RING(chan, 0); + OUT_RING(chan, 0); + OUT_RING(chan, 0); + OUT_RING(chan, 0); + } else { + for (unsigned i = 0; i < count; ++i) + { + struct vertex_header* v = prim->v[i]; + /* TODO: disable divide where it's causing the problem, and remove this hack */ + OUT_RING(chan, fui(v->data[0][0] / v->data[0][3])); + OUT_RING(chan, fui(v->data[0][1] / v->data[0][3])); + OUT_RING(chan, fui(v->data[0][2] / v->data[0][3])); + OUT_RING(chan, fui(1.0f / v->data[0][3])); + OUT_RINGp(chan, &v->data[1][0], 4 * (num_attribs - 1)); + } } } static void nvfx_render_point(struct draw_stage *draw, struct prim_header *prim) { - nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_POINTS, 1); + nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_POINTS, 1); } static void nvfx_render_line(struct draw_stage *draw, struct prim_header *prim) { - nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_LINES, 2); + nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_LINES, 2); } static void nvfx_render_tri(struct draw_stage *draw, struct prim_header *prim) { - nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_TRIANGLES, 3); -} - -static void -nvfx_render_flush(struct draw_stage *draw, unsigned flags) -{ - struct nvfx_render_stage *rs = nvfx_render_stage(draw); - struct nvfx_context *nvfx = rs->nvfx; - struct nvfx_screen *screen = nvfx->screen; - struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - - if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); - OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); - rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP; - } + nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_TRIANGLES, 3); } static void nvfx_render_reset_stipple_counter(struct draw_stage *draw) { + /* this doesn't really seem to work, but it matters rather little */ + nvfx_render_flush(draw, 0); } static void @@ -176,40 +135,11 @@ nvfx_render_destroy(struct draw_stage *draw) FREE(draw); } -static struct nvfx_vertex_program * -nvfx_create_drawvp(struct nvfx_context *nvfx) -{ - struct ureg_program *ureg; - uint i; - - ureg = ureg_create( TGSI_PROCESSOR_VERTEX ); - if (ureg == NULL) - return NULL; - - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0), ureg_DECL_vs_input(ureg, 0)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0), ureg_DECL_vs_input(ureg, 3)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 1), ureg_DECL_vs_input(ureg, 4)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_BCOLOR, 0), ureg_DECL_vs_input(ureg, 3)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_BCOLOR, 1), ureg_DECL_vs_input(ureg, 4)); - ureg_MOV(ureg, - ureg_writemask(ureg_DECL_output(ureg, TGSI_SEMANTIC_FOG, 1), TGSI_WRITEMASK_X), - ureg_DECL_vs_input(ureg, 5)); - for (i = 0; i < 8; ++i) - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, i), ureg_DECL_vs_input(ureg, 8 + i)); - - ureg_END( ureg ); - - return ureg_create_shader_and_destroy( ureg, &nvfx->pipe ); -} - struct draw_stage * nvfx_draw_render_stage(struct nvfx_context *nvfx) { struct nvfx_render_stage *render = CALLOC_STRUCT(nvfx_render_stage); - if (!nvfx->swtnl.vertprog) - nvfx->swtnl.vertprog = nvfx_create_drawvp(nvfx); - render->nvfx = nvfx; render->stage.draw = nvfx->draw; render->stage.point = nvfx_render_point; @@ -231,6 +161,7 @@ nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info if (!nvfx_state_validate_swtnl(nvfx)) return; + nvfx_state_emit(nvfx); /* these must be passed without adding the offsets */ @@ -256,62 +187,3 @@ nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info draw_flush(nvfx->draw); } - -static INLINE void -emit_attrib(struct nvfx_context *nvfx, unsigned hw, unsigned emit, - unsigned semantic, unsigned index) -{ - unsigned draw_out = draw_find_shader_output(nvfx->draw, semantic, index); - unsigned a = nvfx->swtnl.nr_attribs++; - - nvfx->swtnl.hw[a] = hw; - nvfx->swtnl.emit[a] = emit; - nvfx->swtnl.draw[a] = draw_out; -} - -void -nvfx_vtxfmt_validate(struct nvfx_context *nvfx) -{ - struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog; - unsigned colour = 0, texcoords = 0, fog = 0, i; - - /* Determine needed fragprog inputs */ - for (i = 0; i < pfp->info.num_inputs; i++) { - switch (pfp->info.input_semantic_name[i]) { - case TGSI_SEMANTIC_POSITION: - break; - case TGSI_SEMANTIC_COLOR: - colour |= (1 << pfp->info.input_semantic_index[i]); - break; - case TGSI_SEMANTIC_GENERIC: - texcoords |= (1 << pfp->info.input_semantic_index[i]); - break; - case TGSI_SEMANTIC_FOG: - fog = 1; - break; - default: - assert(0); - } - } - - nvfx->swtnl.nr_attribs = 0; - - /* Map draw vtxprog output to hw attribute IDs */ - for (i = 0; i < 2; i++) { - if (!(colour & (1 << i))) - continue; - emit_attrib(nvfx, 3 + i, EMIT_4F, TGSI_SEMANTIC_COLOR, i); - } - - for (i = 0; i < 8; i++) { - if (!(texcoords & (1 << i))) - continue; - emit_attrib(nvfx, 8 + i, EMIT_4F, TGSI_SEMANTIC_GENERIC, i); - } - - if (fog) { - emit_attrib(nvfx, 5, EMIT_1F, TGSI_SEMANTIC_FOG, 0); - } - - emit_attrib(nvfx, 0, 0xff, TGSI_SEMANTIC_POSITION, 0); -} diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c index 275672a31f..d97cab8db1 100644 --- a/src/gallium/drivers/nvfx/nvfx_fragprog.c +++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c @@ -1,3 +1,4 @@ +#include <float.h> #include "pipe/p_context.h" #include "pipe/p_defines.h" #include "pipe/p_state.h" @@ -14,9 +15,6 @@ #include "nvfx_shader.h" #include "nvfx_resource.h" -#define MAX_CONSTS 128 -#define MAX_IMM 32 - struct nvfx_fpc { struct nvfx_pipe_fragment_program* pfp; struct nvfx_fragment_program *fp; @@ -33,13 +31,9 @@ struct nvfx_fpc { unsigned inst_offset; unsigned have_const; - struct { - int pipe; - float vals[4]; - } consts[MAX_CONSTS]; - int nr_consts; + struct util_dynarray imm_data; - struct nvfx_reg imm[MAX_IMM]; + struct nvfx_reg* r_imm; unsigned nr_imm; unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */ @@ -72,19 +66,14 @@ release_temps(struct nvfx_fpc *fpc) fpc->r_temps_discard = 0ULL; } -static INLINE struct nvfx_reg -constant(struct nvfx_fpc *fpc, int pipe, float vals[4]) +static inline struct nvfx_reg +nvfx_fp_imm(struct nvfx_fpc *fpc, float a, float b, float c, float d) { - int idx; - - if (fpc->nr_consts == MAX_CONSTS) - assert(0); - idx = fpc->nr_consts++; + float v[4] = {a, b, c, d}; + int idx = fpc->imm_data.size >> 4; - fpc->consts[idx].pipe = pipe; - if (pipe == -1) - memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float)); - return nvfx_reg(NVFXSR_CONST, idx); + memcpy(util_dynarray_grow(&fpc->imm_data, sizeof(float) * 4), v, 4 * sizeof(float)); + return nvfx_reg(NVFXSR_IMM, idx); } static void @@ -121,26 +110,35 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src) //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index); util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset + pos + 1); break; + case NVFXSR_IMM: + if (!fpc->have_const) { + grow_insns(fpc, 4); + hw = &fp->insn[fpc->inst_offset]; + fpc->have_const = 1; + } + + memcpy(&fp->insn[fpc->inst_offset + 4], + (float*)fpc->imm_data.data + src.reg.index * 4, + sizeof(uint32_t) * 4); + + sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT); + break; case NVFXSR_CONST: if (!fpc->have_const) { grow_insns(fpc, 4); + hw = &fp->insn[fpc->inst_offset]; fpc->have_const = 1; } - hw = &fp->insn[fpc->inst_offset]; - if (fpc->consts[src.reg.index].pipe >= 0) { + { struct nvfx_fragment_program_data *fpd; fp->consts = realloc(fp->consts, ++fp->nr_consts * sizeof(*fpd)); fpd = &fp->consts[fp->nr_consts - 1]; fpd->offset = fpc->inst_offset + 4; - fpd->index = fpc->consts[src.reg.index].pipe; + fpd->index = src.reg.index; memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4); - } else { - memcpy(&fp->insn[fpc->inst_offset + 4], - fpc->consts[src.reg.index].vals, - sizeof(uint32_t) * 4); } sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT); @@ -207,7 +205,7 @@ nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn) memset(hw, 0, sizeof(uint32_t) * 4); if (insn.op == NVFX_FP_OP_OPCODE_KIL) - fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL; + fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL; hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT); hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT); hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT); @@ -408,11 +406,11 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc) } break; case TGSI_FILE_CONSTANT: - src.reg = constant(fpc, fsrc->Register.Index, NULL); + src.reg = nvfx_reg(NVFXSR_CONST, fsrc->Register.Index); break; case TGSI_FILE_IMMEDIATE: assert(fsrc->Register.Index < fpc->nr_imm); - src.reg = fpc->imm[fsrc->Register.Index]; + src.reg = fpc->r_imm[fsrc->Register.Index]; break; case TGSI_FILE_TEMPORARY: src.reg = fpc->r_temp[fsrc->Register.Index]; @@ -434,6 +432,9 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc) src.swz[1] = fsrc->Register.SwizzleY; src.swz[2] = fsrc->Register.SwizzleZ; src.swz[3] = fsrc->Register.SwizzleW; + src.indirect = 0; + src.indirect_reg = 0; + src.indirect_swz = 0; return src; } @@ -470,7 +471,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, { const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct nvfx_insn insn; - struct nvfx_src src[3], tmp, tmp2; + struct nvfx_src src[3], tmp; struct nvfx_reg dst; int mask, sat, unit = 0; int ai = -1, ci = -1, ii = -1; @@ -495,7 +496,21 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, switch (fsrc->Register.File) { case TGSI_FILE_INPUT: - if (ai == -1 || ai == fsrc->Register.Index) { + if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG && (0 + || fsrc->Register.SwizzleX == PIPE_SWIZZLE_ALPHA + || fsrc->Register.SwizzleY == PIPE_SWIZZLE_ALPHA + || fsrc->Register.SwizzleZ == PIPE_SWIZZLE_ALPHA + || fsrc->Register.SwizzleW == PIPE_SWIZZLE_ALPHA + )) { + /* hardware puts 0 in fogcoord.w, but GL/Gallium want 1 there */ + struct nvfx_src addend = nvfx_src(nvfx_fp_imm(fpc, 0, 0, 0, 1)); + addend.swz[0] = fsrc->Register.SwizzleX; + addend.swz[1] = fsrc->Register.SwizzleY; + addend.swz[2] = fsrc->Register.SwizzleZ; + addend.swz[3] = fsrc->Register.SwizzleW; + src[i] = nvfx_src(temp(fpc)); + nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none)); + } else if (ai == -1 || ai == fsrc->Register.Index) { ai = fsrc->Register.Index; src[i] = tgsi_src(fpc, fsrc); } else { @@ -629,7 +644,27 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_LG2: nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none)); break; -// case TGSI_OPCODE_LIT: + case TGSI_OPCODE_LIT: + if(!nvfx->is_nv4x) + nvfx_fp_emit(fpc, arith(sat, LIT_NV30, dst, mask, src[0], src[1], src[2])); + else { + /* we use FLT_MIN, so that log2 never gives -infinity, and thus multiplication by + * specular 0 always gives 0, so that ex2 gives 1, to satisfy the 0^0 = 1 requirement + * + * NOTE: if we start using half precision, we might need an fp16 FLT_MIN here instead + */ + struct nvfx_src maxs = nvfx_src(nvfx_fp_imm(fpc, 0, FLT_MIN, 0, 0)); + tmp = nvfx_src(temp(fpc)); + if (ci>= 0 || ii >= 0) { + nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, maxs, none, none)); + maxs = tmp; + } + nvfx_fp_emit(fpc, arith(0, MAX, tmp.reg, NVFX_FP_MASK_Y | NVFX_FP_MASK_W, swz(src[0], X, X, X, Y), swz(maxs, X, X, Y, Y), none)); + nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), none, none)); + nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), swz(src[0], W, W, W, W), none)); + nvfx_fp_emit(fpc, arith(sat, LITEX2_NV40, dst, mask, swz(tmp, Y, Y, W, W), none, none)); + } + break; case TGSI_OPCODE_LRP: if(!nvfx->is_nv4x) nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2])); @@ -735,12 +770,24 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SSG: - tmp = nvfx_src(temp(fpc)); - tmp2 = nvfx_src(temp(fpc)); - nvfx_fp_emit(fpc, arith(0, SGT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none)); - nvfx_fp_emit(fpc, arith(0, SLT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none)); - nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, tmp, neg(tmp2), none)); + { + struct nvfx_src minones = swz(nvfx_src(nvfx_fp_imm(fpc, -1, -1, -1, -1)), X, X, X, X); + + insn = arith(sat, MOV, dst, mask, src[0], none, none); + insn.cc_update = 1; + nvfx_fp_emit(fpc, insn); + + insn = arith(0, STR, dst, mask, none, none, none); + insn.cc_test = NVFX_COND_GT; + nvfx_fp_emit(fpc, insn); + + if(!sat) { + insn = arith(0, MOV, dst, mask, minones, none, none); + insn.cc_test = NVFX_COND_LT; + nvfx_fp_emit(fpc, insn); + } break; + } case TGSI_OPCODE_STR: nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none)); break; @@ -784,7 +831,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_IF: // MOVRC0 R31 (TR0.xyzw), R<src>: // IF (NE.xxxx) ELSE <else> END <end> - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_if(fpc, src[0]); break; @@ -792,7 +839,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_ELSE: { uint32_t *hw; - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; assert(util_dynarray_contains(&fpc->if_stack, unsigned)); hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)]; @@ -803,7 +850,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_ENDIF: { uint32_t *hw; - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; assert(util_dynarray_contains(&fpc->if_stack, unsigned)); hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)]; @@ -826,19 +873,19 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, break; case TGSI_OPCODE_CAL: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_cal(fpc, finst->Label.Label); break; case TGSI_OPCODE_RET: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_ret(fpc); break; case TGSI_OPCODE_BGNLOOP: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; /* TODO: we should support using two nested REPs to allow a > 255 iteration count */ nv40_fp_rep(fpc, 255, finst->Label.Label); @@ -848,7 +895,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, break; case TGSI_OPCODE_BRK: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_brk(fpc); break; @@ -903,7 +950,7 @@ nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case 2: hw = 3; break; case 3: hw = 4; break; } - if(hw > ((nvfx->is_nv4x) ? 4 : 2)) { + if(hw > ((nvfx->use_nv4x) ? 4 : 2)) { NOUVEAU_ERR("bad rcol index\n"); return FALSE; } @@ -924,19 +971,17 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc) struct tgsi_parse_context p; int high_temp = -1, i; struct util_semantic_set set; - float const0v[4] = {0, 0, 0, 0}; - struct nvfx_reg const0; + unsigned num_texcoords = nvfx->use_nv4x ? 10 : 8; fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT); - if(fpc->fp->num_slots > 8) + if(fpc->fp->num_slots > num_texcoords) return FALSE; - util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8); - util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, 8); + util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, num_texcoords); + util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, num_texcoords); memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input)); - const0 = constant(fpc, -1, const0v); - assert(const0.index == 0); + fpc->r_imm = CALLOC(fpc->pfp->info.immediate_count, sizeof(struct nvfx_reg)); tgsi_parse_init(&p, fpc->pfp->pipe.tokens); while (!tgsi_parse_end_of_tokens(&p)) { @@ -967,19 +1012,14 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc) case TGSI_TOKEN_TYPE_IMMEDIATE: { struct tgsi_full_immediate *imm; - float vals[4]; imm = &p.FullToken.FullImmediate; assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32); - assert(fpc->nr_imm < MAX_IMM); + assert(fpc->nr_imm < fpc->pfp->info.immediate_count); - vals[0] = imm->u[0].Float; - vals[1] = imm->u[1].Float; - vals[2] = imm->u[2].Float; - vals[3] = imm->u[3].Float; - fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals); - } + fpc->r_imm[fpc->nr_imm++] = nvfx_fp_imm(fpc, imm->u[0].Float, imm->u[1].Float, imm->u[2].Float, imm->u[3].Float); break; + } default: break; } @@ -1025,11 +1065,21 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx, if (!fpc) goto out_err; - fpc->max_temps = nvfx->is_nv4x ? 48 : 32; + fpc->max_temps = nvfx->use_nv4x ? 48 : 32; fpc->pfp = pfp; fpc->fp = fp; fpc->num_regs = 2; + for (unsigned i = 0; i < pfp->info.num_properties; ++i) { + if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) { + if(pfp->info.properties[i].data[0]) + fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED; + } else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) { + if(pfp->info.properties[i].data[0]) + fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER; + } + } + if (!nvfx_fragprog_prepare(nvfx, fpc)) goto out_err; @@ -1040,8 +1090,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx, { struct nvfx_reg reg = temp(fpc); struct nvfx_src sprite_input = nvfx_src(nvfx_reg(NVFXSR_RELOCATED, fp->num_slots)); - float v[4] = {1, -1, 0, 0}; - struct nvfx_src imm = nvfx_src(constant(fpc, -1, v)); + struct nvfx_src imm = nvfx_src(nvfx_fp_imm(fpc, 1, -1, 0, 0)); fpc->sprite_coord_temp = reg.index; fpc->r_temps_discard = 0ULL; @@ -1078,7 +1127,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx, if(!nvfx->is_nv4x) fp->fp_control |= (fpc->num_regs-1)/2; else - fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT; + fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT; /* Terminate final instruction */ if(fp->insn) @@ -1119,6 +1168,7 @@ out: FREE(fpc->r_temp); util_dynarray_fini(&fpc->if_stack); util_dynarray_fini(&fpc->label_relocs); + util_dynarray_fini(&fpc->imm_data); //util_dynarray_fini(&fpc->loop_stack); FREE(fpc); } @@ -1230,7 +1280,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) pfp->fps[key] = fp; } - vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog; + vp = nvfx->hw_vertprog; if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) { int sprite_real_input = -1; @@ -1450,17 +1500,17 @@ update: nvfx->hw_fragprog = fp; MARK_RING(chan, 8, 1); - OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1)); + OUT_RING(chan, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1)); OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0, - NV34TCL_FP_ACTIVE_PROGRAM_DMA1); - OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1)); + NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0, + NV30_3D_FP_ACTIVE_PROGRAM_DMA1); + OUT_RING(chan, RING_3D(NV30_3D_FP_CONTROL, 1)); OUT_RING(chan, fp->fp_control); if(!nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1)); + OUT_RING(chan, RING_3D(NV30_3D_FP_REG_CONTROL, 1)); OUT_RING(chan, (1<<16)|0x4); - OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_UNITS_ENABLE, 1)); OUT_RING(chan, fp->samplers); } } @@ -1470,7 +1520,7 @@ update: if(pointsprite_control != nvfx->hw_pointsprite_control) { WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_POINT_SPRITE, 1)); OUT_RING(chan, pointsprite_control); nvfx->hw_pointsprite_control = pointsprite_control; } @@ -1489,10 +1539,10 @@ nvfx_fragprog_relocate(struct nvfx_context *nvfx) unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART? fp_flags |= NOUVEAU_BO_DUMMY; MARK_RING(chan, 2, 2); - OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0); + OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0); OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0, - NV34TCL_FP_ACTIVE_PROGRAM_DMA1); + NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0, + NV30_3D_FP_ACTIVE_PROGRAM_DMA1); nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG; } diff --git a/src/gallium/drivers/nvfx/nvfx_fragtex.c b/src/gallium/drivers/nvfx/nvfx_fragtex.c index 6503c7afcb..1d6b4e24cb 100644 --- a/src/gallium/drivers/nvfx/nvfx_fragtex.c +++ b/src/gallium/drivers/nvfx/nvfx_fragtex.c @@ -12,12 +12,12 @@ nvfx_sampler_state_create(struct pipe_context *pipe, ps = MALLOC(sizeof(struct nvfx_sampler_state)); /* on nv30, we use this as an internal flag */ - ps->fmt = cso->normalized_coords ? 0 : NV40TCL_TEX_FORMAT_RECT; + ps->fmt = cso->normalized_coords ? 0 : NV40_3D_TEX_FORMAT_RECT; ps->en = 0; ps->filt = nvfx_tex_filter(cso) | 0x2000; /*voodoo*/ - ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) | - (nvfx_tex_wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) | - (nvfx_tex_wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT); + ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV30_3D_TEX_WRAP_S__SHIFT) | + (nvfx_tex_wrap_mode(cso->wrap_t) << NV30_3D_TEX_WRAP_T__SHIFT) | + (nvfx_tex_wrap_mode(cso->wrap_r) << NV30_3D_TEX_WRAP_R__SHIFT); ps->compare = FALSE; if(cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) @@ -80,21 +80,21 @@ nvfx_create_sampler_view(struct pipe_context *pipe, pipe_resource_reference(&sv->base.texture, pt); sv->base.context = pipe; - txf = NV34TCL_TX_FORMAT_NO_BORDER; + txf = NV30_3D_TEX_FORMAT_NO_BORDER; switch (pt->target) { case PIPE_TEXTURE_CUBE: - txf |= NV34TCL_TX_FORMAT_CUBIC; + txf |= NV30_3D_TEX_FORMAT_CUBIC; /* fall-through */ case PIPE_TEXTURE_2D: case PIPE_TEXTURE_RECT: - txf |= NV34TCL_TX_FORMAT_DIMS_2D; + txf |= NV30_3D_TEX_FORMAT_DIMS_2D; break; case PIPE_TEXTURE_3D: - txf |= NV34TCL_TX_FORMAT_DIMS_3D; + txf |= NV30_3D_TEX_FORMAT_DIMS_3D; break; case PIPE_TEXTURE_1D: - txf |= NV34TCL_TX_FORMAT_DIMS_1D; + txf |= NV30_3D_TEX_FORMAT_DIMS_1D; break; default: assert(0); @@ -102,14 +102,14 @@ nvfx_create_sampler_view(struct pipe_context *pipe, sv->u.init_fmt = txf; sv->swizzle = 0 - | (tf->src[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S0_Z_SHIFT) - | (tf->src[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S0_Y_SHIFT) - | (tf->src[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S0_X_SHIFT) - | (tf->src[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S0_W_SHIFT) - | (tf->comp[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S1_Z_SHIFT) - | (tf->comp[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S1_Y_SHIFT) - | (tf->comp[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S1_X_SHIFT) - | (tf->comp[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S1_W_SHIFT); + | (tf->src[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT) + | (tf->src[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT) + | (tf->src[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S0_X__SHIFT) + | (tf->src[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S0_W__SHIFT) + | (tf->comp[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT) + | (tf->comp[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT) + | (tf->comp[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S1_X__SHIFT) + | (tf->comp[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S1_W__SHIFT); sv->filt = tf->sign; sv->wrap = tf->wrap; @@ -118,18 +118,18 @@ nvfx_create_sampler_view(struct pipe_context *pipe, if (pt->target == PIPE_TEXTURE_CUBE) { sv->offset = 0; - sv->npot_size = (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | pt->height0; + sv->npot_size = (pt->width0 << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | pt->height0; } else { sv->offset = nvfx_subresource_offset(pt, 0, sv->base.first_level, 0); - sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | u_minify(pt->height0, sv->base.first_level); + sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | u_minify(pt->height0, sv->base.first_level); /* apparently, we need to ignore the t coordinate for 1D textures to fix piglit tex1d-2dborder */ if(pt->target == PIPE_TEXTURE_1D) { - sv->wrap_mask &=~ NV34TCL_TX_WRAP_T_MASK; - sv->wrap |= NV34TCL_TX_WRAP_T_REPEAT; + sv->wrap_mask &=~ NV30_3D_TEX_WRAP_T__MASK; + sv->wrap |= NV30_3D_TEX_WRAP_T_REPEAT; } } @@ -199,7 +199,7 @@ nvfx_fragtex_validate(struct nvfx_context *nvfx) } else { WAIT_RING(chan, 2); /* this is OK for nv40 too */ - OUT_RING(chan, RING_3D(NV34TCL_TX_ENABLE(unit), 1)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_ENABLE(unit), 1)); OUT_RING(chan, 0); nvfx->hw_samplers &= ~(1 << unit); } @@ -227,10 +227,10 @@ nvfx_fragtex_relocate(struct nvfx_context *nvfx) bo = mt->base.bo; MARK_RING(chan, 3, 3); - OUT_RELOC(chan, bo, RING_3D(NV34TCL_TX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0); + OUT_RELOC(chan, bo, RING_3D(NV30_3D_TEX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0); OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_DUMMY, 0, 0); OUT_RELOC(chan, bo, nvfx->hw_txf[unit], tex_flags | NOUVEAU_BO_OR | NOUVEAU_BO_DUMMY, - NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); + NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1); } nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX; } @@ -246,32 +246,32 @@ nvfx_init_sampling_functions(struct nvfx_context *nvfx) nvfx->pipe.sampler_view_destroy = nvfx_sampler_view_destroy; } -#define NV34TCL_TX_FORMAT_FORMAT_DXT1_RECT NV34TCL_TX_FORMAT_FORMAT_DXT1 -#define NV34TCL_TX_FORMAT_FORMAT_DXT3_RECT NV34TCL_TX_FORMAT_FORMAT_DXT3 -#define NV34TCL_TX_FORMAT_FORMAT_DXT5_RECT NV34TCL_TX_FORMAT_FORMAT_DXT5 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT1_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT1 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT3_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT3 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT5_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT5 -#define NV40TCL_TEX_FORMAT_FORMAT_HILO16 NV40TCL_TEX_FORMAT_FORMAT_A16L16 +#define NV40_3D_TEX_FORMAT_FORMAT_HILO16 NV40_3D_TEX_FORMAT_FORMAT_A16L16 -#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F 0x00004a00 -#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA16F -#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F 0x00004b00 -#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA32F -#define NV34TCL_TX_FORMAT_FORMAT_R32F 0x00004c00 -#define NV34TCL_TX_FORMAT_FORMAT_R32F_RECT NV34TCL_TX_FORMAT_FORMAT_R32F +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00004a00 +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA16F +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00004b00 +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA32F +#define NV30_3D_TEX_FORMAT_FORMAT_R32F 0x00004c00 +#define NV30_3D_TEX_FORMAT_FORMAT_R32F_RECT NV30_3D_TEX_FORMAT_FORMAT_R32F // TODO: guess! -#define NV40TCL_TEX_FORMAT_FORMAT_R32F 0x00001c00 +#define NV40_3D_TEX_FORMAT_FORMAT_R32F 0x00001c00 #define SRGB 0x00700000 #define __(m,tf,tfc,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign,wrap) \ [PIPE_FORMAT_##m] = { \ - {NV34TCL_TX_FORMAT_FORMAT_##tf, \ - NV34TCL_TX_FORMAT_FORMAT_##tfc, \ - NV34TCL_TX_FORMAT_FORMAT_##tf##_RECT, \ - NV34TCL_TX_FORMAT_FORMAT_##tfc##_RECT, \ - NV40TCL_TEX_FORMAT_FORMAT_##tf, \ - NV40TCL_TEX_FORMAT_FORMAT_##tfc}, \ + {NV30_3D_TEX_FORMAT_FORMAT_##tf, \ + NV30_3D_TEX_FORMAT_FORMAT_##tfc, \ + NV30_3D_TEX_FORMAT_FORMAT_##tf##_RECT, \ + NV30_3D_TEX_FORMAT_FORMAT_##tfc##_RECT, \ + NV40_3D_TEX_FORMAT_FORMAT_##tf, \ + NV40_3D_TEX_FORMAT_FORMAT_##tfc}, \ sign, wrap, \ {ts0z, ts0y, ts0x, ts0w, 0, 1}, {ts1z, ts1y, ts1x, ts1w, 0, 0} \ } @@ -293,7 +293,7 @@ nvfx_init_sampling_functions(struct nvfx_context *nvfx) #define Z 1 #define W 0 -#define SNORM ((NV34TCL_TX_FILTER_SIGNED_RED) | (NV34TCL_TX_FILTER_SIGNED_GREEN) | (NV34TCL_TX_FILTER_SIGNED_BLUE) | (NV34TCL_TX_FILTER_SIGNED_ALPHA)) +#define SNORM ((NV30_3D_TEX_FILTER_SIGNED_RED) | (NV30_3D_TEX_FILTER_SIGNED_GREEN) | (NV30_3D_TEX_FILTER_SIGNED_BLUE) | (NV30_3D_TEX_FILTER_SIGNED_ALPHA)) #define UNORM 0 struct nvfx_texture_format diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c index 0916aaa828..7677fde40c 100644 --- a/src/gallium/drivers/nvfx/nvfx_miptree.c +++ b/src/gallium/drivers/nvfx/nvfx_miptree.c @@ -214,6 +214,7 @@ nvfx_miptree_surface_del(struct pipe_surface *ps) if(!ns->temp) { + assert(!util_dirty_surface_is_dirty(&ns->base)); util_surfaces_detach(&((struct nvfx_miptree*)ps->texture)->surfaces, ps); pipe_resource_reference(&ps->texture, 0); FREE(ps); diff --git a/src/gallium/drivers/nvfx/nvfx_push.c b/src/gallium/drivers/nvfx/nvfx_push.c index ffe7e98357..ebf47e6ed3 100644 --- a/src/gallium/drivers/nvfx/nvfx_push.c +++ b/src/gallium/drivers/nvfx/nvfx_push.c @@ -29,7 +29,7 @@ emit_edgeflag(void *priv, boolean enabled) struct push_context* ctx = priv; struct nouveau_channel *chan = ctx->chan; - OUT_RING(chan, RING_3D(NV34TCL_EDGEFLAG_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_EDGEFLAG, 1)); OUT_RING(chan, enabled ? 1 : 0); } @@ -44,7 +44,7 @@ emit_vertices_lookup8(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run_elts8(ctx->translate, elts, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -64,7 +64,7 @@ emit_vertices_lookup16(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run_elts16(ctx->translate, elts, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -84,7 +84,7 @@ emit_vertices_lookup32(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run_elts(ctx->translate, elts, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -103,7 +103,7 @@ emit_vertices(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run(ctx->translate, start, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -141,13 +141,13 @@ emit_ranges(void* priv, unsigned start, unsigned vc, unsigned reg) static void emit_ib_ranges(void* priv, unsigned start, unsigned vc) { - emit_ranges(priv, start, vc, NV34TCL_VB_INDEX_BATCH); + emit_ranges(priv, start, vc, NV30_3D_VB_INDEX_BATCH); } static void emit_vb_ranges(void* priv, unsigned start, unsigned vc) { - emit_ranges(priv, start, vc, NV34TCL_VB_VERTEX_BATCH); + emit_ranges(priv, start, vc, NV30_3D_VB_VERTEX_BATCH); } static INLINE void @@ -159,7 +159,7 @@ emit_elt8(void* priv, unsigned start, unsigned vc) int idxbias = ctx->idxbias; if (vc & 1) { - OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VB_ELEMENT_U32, 1)); OUT_RING (chan, elts[0]); elts++; vc--; } @@ -168,7 +168,7 @@ emit_elt8(void* priv, unsigned start, unsigned vc) unsigned i; unsigned push = MIN2(vc, 2047 * 2); - OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1)); + OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U16, push >> 1)); for (i = 0; i < push; i+=2) OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias)); @@ -186,7 +186,7 @@ emit_elt16(void* priv, unsigned start, unsigned vc) int idxbias = ctx->idxbias; if (vc & 1) { - OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VB_ELEMENT_U32, 1)); OUT_RING (chan, elts[0]); elts++; vc--; } @@ -195,7 +195,7 @@ emit_elt16(void* priv, unsigned start, unsigned vc) unsigned i; unsigned push = MIN2(vc, 2047 * 2); - OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1)); + OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U16, push >> 1)); for (i = 0; i < push; i+=2) OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias)); @@ -215,7 +215,7 @@ emit_elt32(void* priv, unsigned start, unsigned vc) while (vc) { unsigned push = MIN2(vc, 2047); - OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U32, push)); + OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U32, push)); assert(AVAIL_RING(chan) >= push); if(idxbias) { @@ -379,10 +379,10 @@ nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) } } - OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); OUT_RING(chan, hw_mode); done = util_split_prim_next(&s, max_verts); - OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); OUT_RING(chan, 0); if(done) diff --git a/src/gallium/drivers/nvfx/nvfx_query.c b/src/gallium/drivers/nvfx/nvfx_query.c index 1dab20c41a..3935ffd7f9 100644 --- a/src/gallium/drivers/nvfx/nvfx_query.c +++ b/src/gallium/drivers/nvfx/nvfx_query.c @@ -49,9 +49,10 @@ nvfx_query_begin(struct pipe_context *pipe, struct pipe_query *pq) struct nvfx_query *q = nvfx_query(pq); struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; uint64_t tmp; + assert(!nvfx->query); + /* Happens when end_query() is called, then another begin_query() * without querying the result in-between. For now we'll wait for * the existing query to notify completion, but it could be better. @@ -71,27 +72,35 @@ nvfx_query_begin(struct pipe_context *pipe, struct pipe_query *pq) nouveau_notifier_reset(nvfx->screen->query, q->object->start); - BEGIN_RING(chan, eng3d, NV34TCL_QUERY_RESET, 1); - OUT_RING (chan, 1); - BEGIN_RING(chan, eng3d, NV34TCL_QUERY_UNK17CC, 1); - OUT_RING (chan, 1); + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_RESET, 1)); + OUT_RING(chan, 1); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 1); q->ready = FALSE; + + nvfx->query = pq; } static void nvfx_query_end(struct pipe_context *pipe, struct pipe_query *pq) { struct nvfx_context *nvfx = nvfx_context(pipe); - struct nvfx_screen *screen = nvfx->screen; - struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; + struct nouveau_channel *chan = nvfx->screen->base.channel; struct nvfx_query *q = nvfx_query(pq); - BEGIN_RING(chan, eng3d, NV34TCL_QUERY_GET, 1); - OUT_RING (chan, (0x01 << NV34TCL_QUERY_GET_UNK24_SHIFT) | - ((q->object->start * 32) << NV34TCL_QUERY_GET_OFFSET_SHIFT)); + assert(nvfx->query == pq); + + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_GET, 1)); + OUT_RING (chan, (0x01 << NV30_3D_QUERY_GET_UNK24__SHIFT) | + ((q->object->start * 32) << NV30_3D_QUERY_GET_OFFSET__SHIFT)); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 0); FIRE_RING(chan); + + nvfx->query = 0; } static boolean diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c index 65ca265d45..3f177b7ed0 100644 --- a/src/gallium/drivers/nvfx/nvfx_screen.c +++ b/src/gallium/drivers/nvfx/nvfx_screen.c @@ -4,15 +4,15 @@ #include "util/u_simple_screen.h" #include "nouveau/nouveau_screen.h" - +#include "nouveau/nv_object.xml.h" #include "nvfx_context.h" #include "nvfx_screen.h" #include "nvfx_resource.h" #include "nvfx_tex.h" -#define NV30TCL_CHIPSET_3X_MASK 0x00000003 -#define NV34TCL_CHIPSET_3X_MASK 0x00000010 -#define NV35TCL_CHIPSET_3X_MASK 0x000001e0 +#define NV30_3D_CHIPSET_3X_MASK 0x00000003 +#define NV34_3D_CHIPSET_3X_MASK 0x00000010 +#define NV35_3D_CHIPSET_3X_MASK 0x000001e0 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf #define NV4X_GRCLASS4497_CHIPSETS 0x00005450 @@ -25,10 +25,9 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) switch (param) { case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: - /* TODO: check this */ - return screen->is_nv4x ? 16 : 8; + return 16; case PIPE_CAP_NPOT_TEXTURES: - return !!screen->is_nv4x; + return screen->advertise_npot; case PIPE_CAP_TWO_SIDED_STENCIL: return 1; case PIPE_CAP_GLSL: @@ -38,7 +37,7 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_POINT_SPRITE: return 1; case PIPE_CAP_MAX_RENDER_TARGETS: - return screen->is_nv4x ? 4 : 2; + return screen->use_nv4x ? 4 : 2; case PIPE_CAP_OCCLUSION_QUERY: return 1; case PIPE_CAP_TIMER_QUERY: @@ -54,15 +53,13 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return 13; case PIPE_CAP_TEXTURE_MIRROR_CLAMP: - return !!screen->is_nv4x; + return !!screen->use_nv4x; case PIPE_CAP_TEXTURE_MIRROR_REPEAT: return 1; case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: return 0; /* We have 4 on nv40 - but unsupported currently */ - case PIPE_CAP_TGSI_CONT_SUPPORTED: - return 0; case PIPE_CAP_BLEND_EQUATION_SEPARATE: - return !!screen->is_nv4x; + return screen->advertise_blend_equation_separate; case PIPE_CAP_MAX_COMBINED_SAMPLERS: return 16; case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -75,59 +72,90 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - return 1; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: - return 0; - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: - return 4096; - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: - /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static - value (nv30:0/nv40:4) ? */ - return screen->is_nv4x ? 4 : 0; - case PIPE_CAP_MAX_FS_INPUTS: - return 10; - case PIPE_CAP_MAX_FS_CONSTS: - return screen->is_nv4x ? 224 : 32; - case PIPE_CAP_MAX_FS_TEMPS: - return 32; - case PIPE_CAP_MAX_FS_ADDRS: - return screen->is_nv4x ? 1 : 0; - case PIPE_CAP_MAX_FS_PREDS: - return screen->is_nv4x ? 1 : 0; - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - return screen->is_nv4x ? 512 : 256; - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - return screen->is_nv4x ? 512 : 0; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static - value (nv30:1/nv40:4) ? */ - return screen->is_nv4x ? 4 : 1; - case PIPE_CAP_MAX_VS_INPUTS: - return 16; - case PIPE_CAP_MAX_VS_CONSTS: - return 256; - case PIPE_CAP_MAX_VS_TEMPS: - return screen->is_nv4x ? 32 : 13; - case PIPE_CAP_MAX_VS_ADDRS: - return 2; - case PIPE_CAP_MAX_VS_PREDS: - return screen->is_nv4x ? 1 : 0; - case PIPE_CAP_GEOMETRY_SHADER4: - return 0; + return 1; case PIPE_CAP_DEPTH_CLAMP: return 0; // TODO: implement depth clamp default: - NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param); + NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param); return 0; } } +static int +nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param) +{ + struct nvfx_screen *screen = nvfx_screen(pscreen); + + switch(shader) { + case PIPE_SHADER_FRAGMENT: + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 4096; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static + value (nv30:0/nv40:4) ? */ + return screen->use_nv4x ? 4 : 0; + case PIPE_SHADER_CAP_MAX_INPUTS: + return screen->use_nv4x ? 12 : 10; + case PIPE_SHADER_CAP_MAX_CONSTS: + return screen->use_nv4x ? 224 : 32; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 32; + case PIPE_SHADER_CAP_MAX_ADDRS: + return screen->use_nv4x ? 1 : 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; /* we could expose these, but nothing uses them */ + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 0; + default: + break; + } + break; + case PIPE_SHADER_VERTEX: + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + return screen->use_nv4x ? 512 : 256; + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return screen->use_nv4x ? 512 : 0; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static + value (nv30:1/nv40:4) ? */ + return screen->use_nv4x ? 4 : 1; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 16; + case PIPE_SHADER_CAP_MAX_CONSTS: + /* - 6 is for clip planes; Gallium should be fixed to put + * them in the vertex shader itself, so we don't need to reserve these */ + return (screen->use_nv4x ? 468 : 256) - 6; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + return screen->use_nv4x ? 32 : 13; + case PIPE_SHADER_CAP_MAX_ADDRS: + return 2; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; /* we could expose these, but nothing uses them */ + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + default: + break; + } + break; + default: + break; + } + return 0; +} + static float nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param) { @@ -141,9 +169,9 @@ nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_POINT_WIDTH_AA: return 64.0; case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: - return screen->is_nv4x ? 16.0 : 8.0; + return screen->use_nv4x ? 16.0 : 8.0; case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: - return screen->is_nv4x ? 16.0 : 4.0; + return 15.0; default: NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param); return 0.0; @@ -168,6 +196,14 @@ nvfx_screen_is_format_supported(struct pipe_screen *pscreen, case PIPE_FORMAT_B8G8R8X8_UNORM: case PIPE_FORMAT_B5G6R5_UNORM: break; + case PIPE_FORMAT_R16G16B16A16_FLOAT: + if(!screen->advertise_fp16) + return FALSE; + break; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + if(!screen->advertise_fp32) + return FALSE; + break; default: return FALSE; } @@ -188,8 +224,11 @@ nvfx_screen_is_format_supported(struct pipe_screen *pscreen, struct nvfx_texture_format* tf = &nvfx_texture_formats[format]; if(util_format_is_s3tc(format) && !util_format_s3tc_enabled) return FALSE; - - if(screen->is_nv4x) + if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16) + return FALSE; + if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32) + return FALSE; + if(screen->use_nv4x) { if(tf->fmt[4] < 0) return FALSE; @@ -245,9 +284,9 @@ static void nv30_screen_init(struct nvfx_screen *screen) /* TODO: perhaps we should do some of this on nv40 too? */ for (i=1; i<8; i++) { - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1)); OUT_RING(chan, 0); - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1)); OUT_RING(chan, 0); } @@ -283,14 +322,14 @@ static void nv30_screen_init(struct nvfx_screen *screen) OUT_RING(chan, RING_3D(0x1d88, 1)); OUT_RING(chan, 0x00001200); - OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1)); OUT_RING(chan, 0); - OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2)); OUT_RING(chan, fui(0.0)); OUT_RING(chan, fui(1.0)); - OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1)); + OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1)); OUT_RING(chan, 0xffff0000); /* enables use of vp rather than fixed-function somehow */ @@ -302,10 +341,13 @@ static void nv40_screen_init(struct nvfx_screen *screen) { struct nouveau_channel *chan = screen->base.channel; - OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2)); + OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2)); OUT_RING(chan, screen->base.channel->vram->handle); OUT_RING(chan, screen->base.channel->vram->handle); + OUT_RING(chan, RING_3D(0x1450, 1)); + OUT_RING(chan, 0x00000004); + OUT_RING(chan, RING_3D(0x1ea4, 3)); OUT_RING(chan, 0x00000010); OUT_RING(chan, 0x01000100); @@ -316,7 +358,7 @@ static void nv40_screen_init(struct nvfx_screen *screen) OUT_RING(chan, 0x06144321); OUT_RING(chan, RING_3D(0x1fc8, 2)); OUT_RING(chan, 0xedcba987); - OUT_RING(chan, 0x00000021); + OUT_RING(chan, 0x0000006f); OUT_RING(chan, RING_3D(0x1fd0, 1)); OUT_RING(chan, 0x00171615); OUT_RING(chan, RING_3D(0x1fd4, 1)); @@ -325,9 +367,12 @@ static void nv40_screen_init(struct nvfx_screen *screen) OUT_RING(chan, RING_3D(0x1ef8, 1)); OUT_RING(chan, 0x0020ffff); OUT_RING(chan, RING_3D(0x1d64, 1)); - OUT_RING(chan, 0x00d30000); + OUT_RING(chan, 0x01d300d4); OUT_RING(chan, RING_3D(0x1e94, 1)); OUT_RING(chan, 0x00000001); + + OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1)); + OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN); } static unsigned @@ -344,19 +389,6 @@ nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen) vram_hack_default = 1; vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default); -#ifdef DEBUG - if(!vram_hack) - { - fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n" - "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n"); - } - else - { - fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n" - "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n"); - } -#endif - return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART; } @@ -396,29 +428,30 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) pscreen->winsys = ws; pscreen->destroy = nvfx_screen_destroy; pscreen->get_param = nvfx_screen_get_param; + pscreen->get_shader_param = nvfx_screen_get_shader_param; pscreen->get_paramf = nvfx_screen_get_paramf; pscreen->is_format_supported = nvfx_screen_is_format_supported; pscreen->context_create = nvfx_create; switch (dev->chipset & 0xf0) { case 0x30: - if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) - eng3d_class = 0x0397; - else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) - eng3d_class = 0x0697; - else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) - eng3d_class = 0x0497; + if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) + eng3d_class = NV30_3D; + else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) + eng3d_class = NV34_3D; + else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) + eng3d_class = NV35_3D; break; case 0x40: if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f))) - eng3d_class = NV40TCL; + eng3d_class = NV40_3D; else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f))) - eng3d_class = NV44TCL; + eng3d_class = NV44_3D; screen->is_nv4x = ~0; break; case 0x60: if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f))) - eng3d_class = NV44TCL; + eng3d_class = NV44_3D; screen->is_nv4x = ~0; break; } @@ -428,17 +461,37 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) return NULL; } - screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE); + screen->advertise_npot = !!screen->is_nv4x; + screen->advertise_blend_equation_separate = !!screen->is_nv4x; + screen->use_nv4x = screen->is_nv4x; + + if(screen->is_nv4x) { + if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE)) + screen->use_nv4x = 0; + if(!debug_get_bool_option("NVFX_NPOT", TRUE)) + screen->advertise_npot = 0; + if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE)) + screen->advertise_blend_equation_separate = 0; + } + + screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE); screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE); screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384); screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0")); screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0")); + /* We don't advertise these by default because filtering and blending doesn't work as + * it should, due to several restrictions. + * The only exception is fp16 on nv40. + */ + screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x); + screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0); + screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen); /* surely both nv3x and nv44 support index buffers too: find out how and test that */ - if(eng3d_class == NV40TCL) + if(eng3d_class == NV40_3D) screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags; if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags) @@ -487,8 +540,8 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) LIST_INITHEAD(&screen->query_list); /* Vtxprog resources */ - if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) || - nouveau_resource_init(&screen->vp_data_heap, 0, 256)) { + if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) || + nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) { nvfx_screen_destroy(pscreen); return NULL; } @@ -497,25 +550,25 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) /* Static eng3d initialisation */ /* note that we just started using the channel, so we must have space in the pushbuffer */ - OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1)); OUT_RING(chan, screen->sync->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1)); OUT_RING(chan, chan->vram->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->vram->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2)); OUT_RING(chan, 0); OUT_RING(chan, screen->query->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->vram->handle); diff --git a/src/gallium/drivers/nvfx/nvfx_screen.h b/src/gallium/drivers/nvfx/nvfx_screen.h index 1b79235ae0..b1f07187c7 100644 --- a/src/gallium/drivers/nvfx/nvfx_screen.h +++ b/src/gallium/drivers/nvfx/nvfx_screen.h @@ -15,10 +15,15 @@ struct nvfx_screen { struct nvfx_context *cur_ctx; unsigned is_nv4x; /* either 0 or ~0 */ + unsigned use_nv4x; /* either 0 or ~0 */ boolean force_swtnl; boolean trace_draw; unsigned vertex_buffer_reloc_flags; unsigned index_buffer_reloc_flags; + unsigned advertise_fp16; + unsigned advertise_fp32; + unsigned advertise_npot; + unsigned advertise_blend_equation_separate; /* HW graphics objects */ struct nouveau_grobj *eng3d; diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h index 35006eec3d..46406b2794 100644 --- a/src/gallium/drivers/nvfx/nvfx_shader.h +++ b/src/gallium/drivers/nvfx/nvfx_shader.h @@ -263,6 +263,7 @@ /* NV40 only fragment program opcodes */ #define NVFX_FP_OP_OPCODE_TXL_NV40 0x2F +#define NVFX_FP_OP_OPCODE_LITEX2_NV40 0x3C /* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/ #define NV40_FP_OP_BRA_OPCODE_BRK 0x0 @@ -378,8 +379,9 @@ #define NVFXSR_OUTPUT 1 #define NVFXSR_INPUT 2 #define NVFXSR_TEMP 3 -#define NVFXSR_CONST 4 -#define NVFXSR_RELOCATED 5 +#define NVFXSR_CONST 5 +#define NVFXSR_IMM 6 +#define NVFXSR_RELOCATED 7 #define NVFX_COND_FL 0 #define NVFX_COND_LT 1 @@ -414,14 +416,16 @@ #define abs(s) nvfx_src_abs((s)) struct nvfx_reg { - uint8_t type; + int8_t type; uint32_t index; }; struct nvfx_src { struct nvfx_reg reg; - /* src only */ + uint8_t indirect : 1; + uint8_t indirect_reg : 1; + uint8_t indirect_swz : 2; uint8_t negate : 1; uint8_t abs : 1; uint8_t swz[4]; @@ -483,6 +487,7 @@ nvfx_src(struct nvfx_reg reg) .abs = 0, .negate = 0, .swz = { 0, 1, 2, 3 }, + .indirect = 0, }; return temp; } diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c index 5bd7dc07f0..b767846a99 100644 --- a/src/gallium/drivers/nvfx/nvfx_state.c +++ b/src/gallium/drivers/nvfx/nvfx_state.c @@ -20,26 +20,26 @@ nvfx_blend_state_create(struct pipe_context *pipe, struct nouveau_statebuf_builder sb = sb_init(bso->sb); if (cso->rt[0].blend_enable) { - sb_method(sb, NV34TCL_BLEND_FUNC_ENABLE, 3); + sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 3); sb_data(sb, 1); sb_data(sb, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) | nvgl_blend_func(cso->rt[0].rgb_src_factor)); sb_data(sb, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 | nvgl_blend_func(cso->rt[0].rgb_dst_factor)); if(nvfx->screen->base.device->chipset < 0x40) { - sb_method(sb, NV34TCL_BLEND_EQUATION, 1); + sb_method(sb, NV30_3D_BLEND_EQUATION, 1); sb_data(sb, nvgl_blend_eqn(cso->rt[0].rgb_func)); } else { - sb_method(sb, NV40TCL_BLEND_EQUATION, 1); + sb_method(sb, NV40_3D_BLEND_EQUATION, 1); sb_data(sb, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 | nvgl_blend_eqn(cso->rt[0].rgb_func)); } } else { - sb_method(sb, NV34TCL_BLEND_FUNC_ENABLE, 1); + sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 1); sb_data(sb, 0); } - sb_method(sb, NV34TCL_COLOR_MASK, 1); + sb_method(sb, NV30_3D_COLOR_MASK, 1); sb_data(sb, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) | ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) | ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) | @@ -48,15 +48,15 @@ nvfx_blend_state_create(struct pipe_context *pipe, /* TODO: add NV40 MRT color mask */ if (cso->logicop_enable) { - sb_method(sb, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2); + sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 2); sb_data(sb, 1); sb_data(sb, nvgl_logicop_func(cso->logicop_func)); } else { - sb_method(sb, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1); + sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 1); sb_data(sb, 0); } - sb_method(sb, NV34TCL_DITHER_ENABLE, 1); + sb_method(sb, NV30_3D_DITHER_ENABLE, 1); sb_data(sb, cso->dither ? 1 : 0); bso->sb_len = sb_len(sb, bso->sb); @@ -94,64 +94,64 @@ nvfx_rasterizer_state_create(struct pipe_context *pipe, * sprite_coord_origin */ - sb_method(sb, NV34TCL_SHADE_MODEL, 1); - sb_data(sb, cso->flatshade ? NV34TCL_SHADE_MODEL_FLAT : - NV34TCL_SHADE_MODEL_SMOOTH); + sb_method(sb, NV30_3D_SHADE_MODEL, 1); + sb_data(sb, cso->flatshade ? NV30_3D_SHADE_MODEL_FLAT : + NV30_3D_SHADE_MODEL_SMOOTH); - sb_method(sb, NV34TCL_VERTEX_TWO_SIDE_ENABLE, 1); + sb_method(sb, NV30_3D_VERTEX_TWO_SIDE_ENABLE, 1); sb_data(sb, cso->light_twoside); - sb_method(sb, NV34TCL_LINE_WIDTH, 2); + sb_method(sb, NV30_3D_LINE_WIDTH, 2); sb_data(sb, (unsigned char)(cso->line_width * 8.0) & 0xff); sb_data(sb, cso->line_smooth ? 1 : 0); - sb_method(sb, NV34TCL_LINE_STIPPLE_ENABLE, 2); + sb_method(sb, NV30_3D_LINE_STIPPLE_ENABLE, 2); sb_data(sb, cso->line_stipple_enable ? 1 : 0); sb_data(sb, (cso->line_stipple_pattern << 16) | cso->line_stipple_factor); - sb_method(sb, NV34TCL_POINT_SIZE, 1); + sb_method(sb, NV30_3D_POINT_SIZE, 1); sb_data(sb, fui(cso->point_size)); - sb_method(sb, NV34TCL_POLYGON_MODE_FRONT, 6); + sb_method(sb, NV30_3D_POLYGON_MODE_FRONT, 6); sb_data(sb, nvgl_polygon_mode(cso->fill_front)); sb_data(sb, nvgl_polygon_mode(cso->fill_back)); switch (cso->cull_face) { case PIPE_FACE_FRONT: - sb_data(sb, NV34TCL_CULL_FACE_FRONT); + sb_data(sb, NV30_3D_CULL_FACE_FRONT); break; case PIPE_FACE_BACK: - sb_data(sb, NV34TCL_CULL_FACE_BACK); + sb_data(sb, NV30_3D_CULL_FACE_BACK); break; case PIPE_FACE_FRONT_AND_BACK: - sb_data(sb, NV34TCL_CULL_FACE_FRONT_AND_BACK); + sb_data(sb, NV30_3D_CULL_FACE_FRONT_AND_BACK); break; default: - sb_data(sb, NV34TCL_CULL_FACE_BACK); + sb_data(sb, NV30_3D_CULL_FACE_BACK); break; } if (cso->front_ccw) { - sb_data(sb, NV34TCL_FRONT_FACE_CCW); + sb_data(sb, NV30_3D_FRONT_FACE_CCW); } else { - sb_data(sb, NV34TCL_FRONT_FACE_CW); + sb_data(sb, NV30_3D_FRONT_FACE_CW); } sb_data(sb, cso->poly_smooth ? 1 : 0); sb_data(sb, (cso->cull_face != PIPE_FACE_NONE) ? 1 : 0); - sb_method(sb, NV34TCL_POLYGON_STIPPLE_ENABLE, 1); + sb_method(sb, NV30_3D_POLYGON_STIPPLE_ENABLE, 1); sb_data(sb, cso->poly_stipple_enable ? 1 : 0); - sb_method(sb, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3); + sb_method(sb, NV30_3D_POLYGON_OFFSET_POINT_ENABLE, 3); sb_data(sb, cso->offset_point); sb_data(sb, cso->offset_line); sb_data(sb, cso->offset_tri); if (cso->offset_point || cso->offset_line || cso->offset_tri) { - sb_method(sb, NV34TCL_POLYGON_OFFSET_FACTOR, 2); + sb_method(sb, NV30_3D_POLYGON_OFFSET_FACTOR, 2); sb_data(sb, fui(cso->offset_scale)); sb_data(sb, fui(cso->offset_units * 2)); } - sb_method(sb, NV34TCL_FLATSHADE_FIRST, 1); + sb_method(sb, NV30_3D_FLATSHADE_FIRST, 1); sb_data(sb, cso->flatshade_first); rsso->pipe = *cso; @@ -201,41 +201,41 @@ nvfx_depth_stencil_alpha_state_create(struct pipe_context *pipe, struct nvfx_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso)); struct nouveau_statebuf_builder sb = sb_init(zsaso->sb); - sb_method(sb, NV34TCL_DEPTH_FUNC, 1); + sb_method(sb, NV30_3D_DEPTH_FUNC, 1); sb_data (sb, nvgl_comparison_op(cso->depth.func)); - sb_method(sb, NV34TCL_ALPHA_FUNC_ENABLE, 3); + sb_method(sb, NV30_3D_ALPHA_FUNC_ENABLE, 3); sb_data (sb, cso->alpha.enabled ? 1 : 0); sb_data (sb, nvgl_comparison_op(cso->alpha.func)); sb_data (sb, float_to_ubyte(cso->alpha.ref_value)); if (cso->stencil[0].enabled) { - sb_method(sb, NV34TCL_STENCIL_FRONT_ENABLE, 3); + sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 3); sb_data (sb, cso->stencil[0].enabled ? 1 : 0); sb_data (sb, cso->stencil[0].writemask); sb_data (sb, nvgl_comparison_op(cso->stencil[0].func)); - sb_method(sb, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4); + sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(0), 4); sb_data (sb, cso->stencil[0].valuemask); sb_data (sb, nvgl_stencil_op(cso->stencil[0].fail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[0].zfail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[0].zpass_op)); } else { - sb_method(sb, NV34TCL_STENCIL_FRONT_ENABLE, 1); + sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 1); sb_data (sb, 0); } if (cso->stencil[1].enabled) { - sb_method(sb, NV34TCL_STENCIL_BACK_ENABLE, 3); + sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 3); sb_data (sb, cso->stencil[1].enabled ? 1 : 0); sb_data (sb, cso->stencil[1].writemask); sb_data (sb, nvgl_comparison_op(cso->stencil[1].func)); - sb_method(sb, NV34TCL_STENCIL_BACK_FUNC_MASK, 4); + sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(1), 4); sb_data (sb, cso->stencil[1].valuemask); sb_data (sb, nvgl_stencil_op(cso->stencil[1].fail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[1].zfail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[1].zpass_op)); } else { - sb_method(sb, NV34TCL_STENCIL_BACK_ENABLE, 1); + sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 1); sb_data (sb, 0); } diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h index e9c1f2c26d..8fafca1950 100644 --- a/src/gallium/drivers/nvfx/nvfx_state.h +++ b/src/gallium/drivers/nvfx/nvfx_state.h @@ -17,13 +17,8 @@ struct nvfx_vertex_program_data { }; struct nvfx_vertex_program { - struct pipe_shader_state pipe; unsigned long long id; - struct draw_vertex_shader *draw; - - boolean translated; - struct nvfx_vertex_program_exec *insns; unsigned nr_insns; struct nvfx_vertex_program_data *consts; @@ -46,6 +41,20 @@ struct nvfx_vertex_program { struct util_dynarray const_relocs; }; +#define NVFX_VP_FAILED ((struct nvfx_vertex_program*)-1) + +struct nvfx_pipe_vertex_program { + struct pipe_shader_state pipe; + struct tgsi_shader_info info; + + unsigned draw_elements; + boolean draw_no_elements; + struct draw_vertex_shader *draw_vs; + struct nvfx_vertex_program* draw_vp; + + struct nvfx_vertex_program* vp; +}; + struct nvfx_fragment_program_data { unsigned offset; unsigned index; @@ -62,6 +71,7 @@ struct nvfx_fragment_program { unsigned samplers; unsigned point_sprite_control; unsigned or; + unsigned coord_conventions; uint32_t *insn; int insn_len; diff --git a/src/gallium/drivers/nvfx/nvfx_state_blend.c b/src/gallium/drivers/nvfx/nvfx_state_blend.c deleted file mode 100644 index fe34e98364..0000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_blend.c +++ /dev/null @@ -1,22 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_blend_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - sb_emit(chan, nvfx->blend->sb, nvfx->blend->sb_len); -} - -void -nvfx_state_blend_colour_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - struct pipe_blend_color *bcol = &nvfx->blend_colour; - - WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_BLEND_COLOR, 1)); - OUT_RING(chan, ((float_to_ubyte(bcol->color[3]) << 24) | - (float_to_ubyte(bcol->color[0]) << 16) | - (float_to_ubyte(bcol->color[1]) << 8) | - (float_to_ubyte(bcol->color[2]) << 0))); -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c index 390bca8cdb..501fdd4430 100644 --- a/src/gallium/drivers/nvfx/nvfx_state_emit.c +++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c @@ -3,13 +3,191 @@ #include "nvfx_resource.h" #include "draw/draw_context.h" +void +nvfx_state_viewport_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel *chan = nvfx->screen->base.channel; + struct pipe_viewport_state *vpt = &nvfx->viewport; + + WAIT_RING(chan, 11); + if(nvfx->render_mode == HW) { + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TRANSLATE_X, 8)); + OUT_RINGf(chan, vpt->translate[0]); + OUT_RINGf(chan, vpt->translate[1]); + OUT_RINGf(chan, vpt->translate[2]); + OUT_RINGf(chan, vpt->translate[3]); + OUT_RINGf(chan, vpt->scale[0]); + OUT_RINGf(chan, vpt->scale[1]); + OUT_RINGf(chan, vpt->scale[2]); + OUT_RINGf(chan, vpt->scale[3]); + OUT_RING(chan, RING_3D(0x1d78, 1)); + OUT_RING(chan, 1); + } else { + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TRANSLATE_X, 8)); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 1.0f); + OUT_RINGf(chan, 1.0f); + OUT_RINGf(chan, 1.0f); + OUT_RINGf(chan, 1.0f); + OUT_RING(chan, RING_3D(0x1d78, 1)); + OUT_RING(chan, nvfx->is_nv4x ? 0x110 : 1); + } +} + +void +nvfx_state_scissor_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel *chan = nvfx->screen->base.channel; + struct pipe_rasterizer_state *rast = &nvfx->rasterizer->pipe; + struct pipe_scissor_state *s = &nvfx->scissor; + + if ((rast->scissor == 0 && nvfx->state.scissor_enabled == 0)) + return; + nvfx->state.scissor_enabled = rast->scissor; + + WAIT_RING(chan, 3); + OUT_RING(chan, RING_3D(NV30_3D_SCISSOR_HORIZ, 2)); + if (nvfx->state.scissor_enabled) { + OUT_RING(chan, ((s->maxx - s->minx) << 16) | s->minx); + OUT_RING(chan, ((s->maxy - s->miny) << 16) | s->miny); + } else { + OUT_RING(chan, 4096 << 16); + OUT_RING(chan, 4096 << 16); + } +} + +void +nvfx_state_sr_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + struct pipe_stencil_ref *sr = &nvfx->stencil_ref; + + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(NV30_3D_STENCIL_FUNC_REF(0), 1)); + OUT_RING(chan, sr->ref_value[0]); + OUT_RING(chan, RING_3D(NV30_3D_STENCIL_FUNC_REF(1), 1)); + OUT_RING(chan, sr->ref_value[1]); +} + +void +nvfx_state_blend_colour_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + struct pipe_blend_color *bcol = &nvfx->blend_colour; + + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_BLEND_COLOR, 1)); + OUT_RING(chan, ((float_to_ubyte(bcol->color[3]) << 24) | + (float_to_ubyte(bcol->color[0]) << 16) | + (float_to_ubyte(bcol->color[1]) << 8) | + (float_to_ubyte(bcol->color[2]) << 0))); +} + +void +nvfx_state_stipple_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel *chan = nvfx->screen->base.channel; + + WAIT_RING(chan, 33); + OUT_RING(chan, RING_3D(NV30_3D_POLYGON_STIPPLE_PATTERN(0), 32)); + OUT_RINGp(chan, nvfx->stipple, 32); +} + +static void +nvfx_coord_conventions_validate(struct nvfx_context* nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned value = nvfx->hw_fragprog->coord_conventions; + if(value & NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED) + value |= nvfx->framebuffer.height << NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT; + + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_COORD_CONVENTIONS, 1)); + OUT_RING(chan, value); +} + +static void +nvfx_ucp_validate(struct nvfx_context* nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned enables[7] = + { + 0, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5, + }; + + if(!nvfx->use_vp_clipping) + { + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANES_ENABLE, 1)); + OUT_RING(chan, 0); + + WAIT_RING(chan, 6 * 4 + 1); + OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANE(0, 0), nvfx->clip.nr * 4)); + OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nvfx->clip.nr * 4); + } + + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANES_ENABLE, 1)); + OUT_RING(chan, enables[nvfx->clip.nr]); +} + +static void +nvfx_vertprog_ucp_validate(struct nvfx_context* nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned i; + struct nvfx_vertex_program* vp = nvfx->hw_vertprog; + if(nvfx->clip.nr != vp->clip_nr) + { + unsigned idx; + WAIT_RING(chan, 14); + + /* remove last instruction bit */ + if(vp->clip_nr >= 0) + { + idx = vp->nr_insns - 7 + vp->clip_nr; + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1)); + OUT_RING(chan, vp->exec->start + idx); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4)); + OUT_RINGp (chan, vp->insns[idx].data, 4); + } + + /* set last instruction bit */ + idx = vp->nr_insns - 7 + nvfx->clip.nr; + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1)); + OUT_RING(chan, vp->exec->start + idx); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4)); + OUT_RINGp(chan, vp->insns[idx].data, 3); + OUT_RING(chan, vp->insns[idx].data[3] | 1); + vp->clip_nr = nvfx->clip.nr; + } + + // TODO: only do this for the ones changed + WAIT_RING(chan, 6 * 6); + for(i = 0; i < nvfx->clip.nr; ++i) + { + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5)); + OUT_RING(chan, vp->data->start + i); + OUT_RINGp (chan, nvfx->clip.ucp[i], 4); + } +} + static boolean nvfx_state_validate_common(struct nvfx_context *nvfx) { struct nouveau_channel* chan = nvfx->screen->base.channel; unsigned dirty; unsigned still_dirty = 0; - int all_swizzled = -1; + int new_fb_mode = -1; /* 1 = all swizzled, 0 = make all linear */ boolean flush_tex_cache = FALSE; unsigned render_temps; @@ -41,10 +219,10 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) if(nvfx->dirty & NVFX_NEW_FB) { nvfx->dirty &=~ NVFX_NEW_FB; - all_swizzled = nvfx_framebuffer_prepare(nvfx); + new_fb_mode = nvfx_framebuffer_prepare(nvfx); // TODO: make sure this doesn't happen, i.e. fbs have matching formats - assert(all_swizzled >= 0); + assert(new_fb_mode >= 0); } } @@ -52,7 +230,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) if(nvfx->render_mode == HW) { - if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_VERTCONST | NVFX_NEW_UCP)) + if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_VERTCONST)) { if(!nvfx_vertprog_validate(nvfx)) return FALSE; @@ -74,12 +252,10 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) } else { - /* TODO: this looks a bit misdesigned */ - if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP)) - nvfx_vertprog_validate(nvfx); - - if(dirty & (NVFX_NEW_ARRAYS | NVFX_NEW_INDEX | NVFX_NEW_FRAGPROG)) - nvfx_vtxfmt_validate(nvfx); + if(dirty & NVFX_NEW_VERTPROG) { + assert(nvfx_vertprog_validate(nvfx)); + nvfx_vbo_swtnl_validate(nvfx); + } } if(dirty & NVFX_NEW_RAST) @@ -92,72 +268,10 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) nvfx_state_stipple_validate(nvfx); if(nvfx->dirty & NVFX_NEW_UCP) - { - unsigned enables[7] = - { - 0, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5, - }; - - if(!nvfx->use_vp_clipping) - { - WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1)); - OUT_RING(chan, 0); - - WAIT_RING(chan, 6 * 4 + 1); - OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANE_A(0), nvfx->clip.nr * 4)); - OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nvfx->clip.nr * 4); - } - - WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1)); - OUT_RING(chan, enables[nvfx->clip.nr]); - } + nvfx_ucp_validate(nvfx); if(nvfx->use_vp_clipping && (nvfx->dirty & (NVFX_NEW_UCP | NVFX_NEW_VERTPROG))) - { - unsigned i; - struct nvfx_vertex_program* vp = nvfx->vertprog; - if(nvfx->clip.nr != vp->clip_nr) - { - unsigned idx; - WAIT_RING(chan, 14); - - /* remove last instruction bit */ - if(vp->clip_nr >= 0) - { - idx = vp->nr_insns - 7 + vp->clip_nr; - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1)); - OUT_RING(chan, vp->exec->start + idx); - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4)); - OUT_RINGp (chan, vp->insns[idx].data, 4); - } - - /* set last instruction bit */ - idx = vp->nr_insns - 7 + nvfx->clip.nr; - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1)); - OUT_RING(chan, vp->exec->start + idx); - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4)); - OUT_RINGp(chan, vp->insns[idx].data, 3); - OUT_RING(chan, vp->insns[idx].data[3] | 1); - vp->clip_nr = nvfx->clip.nr; - } - - // TODO: only do this for the ones changed - WAIT_RING(chan, 6 * 6); - for(i = 0; i < nvfx->clip.nr; ++i) - { - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_CONST_ID, 5)); - OUT_RING(chan, vp->data->start + i); - OUT_RINGp (chan, nvfx->clip.ucp[i], 4); - } - } + nvfx_vertprog_ucp_validate(nvfx); if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST | NVFX_NEW_VERTPROG | NVFX_NEW_SPRITE)) { @@ -168,20 +282,20 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) if(nvfx->is_nv4x) { - unsigned vp_output = nvfx->vertprog->or | nvfx->hw_fragprog->or; + unsigned vp_output = nvfx->hw_vertprog->or | nvfx->hw_fragprog->or; vp_output |= (1 << (nvfx->clip.nr + 6)) - (1 << 6); if(vp_output != nvfx->hw_vp_output) { WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV40TCL_VP_RESULT_EN, 1)); + OUT_RING(chan, RING_3D(NV40_3D_VP_RESULT_EN, 1)); OUT_RING(chan, vp_output); nvfx->hw_vp_output = vp_output; } } - if(all_swizzled >= 0) - nvfx_framebuffer_validate(nvfx, all_swizzled); + if(new_fb_mode >= 0) + nvfx_framebuffer_validate(nvfx, new_fb_mode); if(dirty & NVFX_NEW_BLEND) sb_emit(chan, nvfx->blend->sb, nvfx->blend->sb_len); @@ -199,28 +313,31 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) etracer, neverball, foobillard, glest totally misrender TODO: find the right fix */ - if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (all_swizzled >= 0)) + if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (new_fb_mode >= 0)) { nvfx_state_viewport_validate(nvfx); } - if(dirty & NVFX_NEW_ZSA || (all_swizzled >= 0)) + if(dirty & NVFX_NEW_ZSA || (new_fb_mode >= 0)) { WAIT_RING(chan, 3); - OUT_RING(chan, RING_3D(NV34TCL_DEPTH_WRITE_ENABLE, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DEPTH_WRITE_ENABLE, 2)); OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.writemask); OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.enabled); } + if((new_fb_mode >= 0) || (dirty & NVFX_NEW_FRAGPROG)) + nvfx_coord_conventions_validate(nvfx); + if(flush_tex_cache) { // TODO: what about nv30? if(nvfx->is_nv4x) { WAIT_RING(chan, 4); - OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1)); + OUT_RING(chan, RING_3D(NV40_3D_TEX_CACHE_CTL, 1)); OUT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1)); + OUT_RING(chan, RING_3D(NV40_3D_TEX_CACHE_CTL, 1)); OUT_RING(chan, 1); } } @@ -232,14 +349,18 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) { for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i) { - if(render_temps & (1 << i)) + if(render_temps & (1 << i)) { + assert(((struct nvfx_surface*)nvfx->framebuffer.cbufs[i])->temp); util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.cbufs[i]), (struct util_dirty_surface*)nvfx->framebuffer.cbufs[i]); + } } - if(render_temps & 0x80) + if(render_temps & 0x80) { + assert(((struct nvfx_surface*)nvfx->framebuffer.zsbuf)->temp); util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.zsbuf), (struct util_dirty_surface*)nvfx->framebuffer.zsbuf); + } } return TRUE; @@ -276,8 +397,6 @@ nvfx_state_relocate(struct nvfx_context *nvfx, unsigned relocs) boolean nvfx_state_validate(struct nvfx_context *nvfx) { - boolean was_sw = nvfx->fallback_swtnl ? TRUE : FALSE; - if (nvfx->render_mode != HW) { /* Don't even bother trying to go back to hw if none * of the states that caused swtnl previously have changed. @@ -296,9 +415,6 @@ nvfx_state_validate(struct nvfx_context *nvfx) if(!nvfx_state_validate_common(nvfx)) return FALSE; - if (was_sw) - NOUVEAU_ERR("swtnl->hw\n"); - return TRUE; } @@ -309,7 +425,11 @@ nvfx_state_validate_swtnl(struct nvfx_context *nvfx) /* Setup for swtnl */ if (nvfx->render_mode == HW) { - NOUVEAU_ERR("hw->swtnl 0x%08x\n", nvfx->fallback_swtnl); + static boolean warned = FALSE; + if(!warned) { + NOUVEAU_ERR("hw->swtnl 0x%08x\n", nvfx->fallback_swtnl); + warned = TRUE; + } nvfx->pipe.flush(&nvfx->pipe, 0, NULL); nvfx->dirty |= (NVFX_NEW_VIEWPORT | NVFX_NEW_VERTPROG | @@ -317,8 +437,11 @@ nvfx_state_validate_swtnl(struct nvfx_context *nvfx) nvfx->render_mode = SWTNL; } - if (nvfx->draw_dirty & NVFX_NEW_VERTPROG) - draw_bind_vertex_shader(draw, nvfx->vertprog->draw); + if (nvfx->draw_dirty & NVFX_NEW_VERTPROG) { + if(!nvfx->vertprog->draw_vs) + nvfx->vertprog->draw_vs = draw_create_vertex_shader(draw, &nvfx->vertprog->pipe); + draw_bind_vertex_shader(draw, nvfx->vertprog->draw_vs); + } if (nvfx->draw_dirty & NVFX_NEW_RAST) draw_set_rasterizer_state(draw, &nvfx->rasterizer->pipe, diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c index 3b869d43a1..4ffc4de452 100644 --- a/src/gallium/drivers/nvfx/nvfx_state_fb.c +++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c @@ -5,6 +5,7 @@ static inline boolean nvfx_surface_linear_renderable(struct pipe_surface* surf) { + /* TODO: precompute this in nvfx_surface creation */ return (surf->texture->flags & NVFX_RESOURCE_FLAG_LINEAR) && !(surf->offset & 63) && !(((struct nvfx_surface*)surf)->pitch & 63); @@ -13,13 +14,14 @@ nvfx_surface_linear_renderable(struct pipe_surface* surf) static inline boolean nvfx_surface_swizzled_renderable(struct pipe_framebuffer_state* fb, struct pipe_surface* surf) { - /* TODO: return FALSE if we have a format not supporting swizzled rendering (e.g. r8); currently those are not supported at all */ + /* TODO: precompute this in nvfx_surface creation */ return !((struct nvfx_miptree*)surf->texture)->linear_pitch && (surf->texture->target != PIPE_TEXTURE_3D || u_minify(surf->texture->depth0, surf->level) <= 1) && !(surf->offset & 127) && (surf->width == fb->width) && (surf->height == fb->height) - && !((struct nvfx_surface*)surf)->temp; + && !((struct nvfx_surface*)surf)->temp + && (surf->format == PIPE_FORMAT_B8G8R8A8_UNORM || surf->format == PIPE_FORMAT_B8G8R8X8_UNORM || surf->format == PIPE_FORMAT_B5G6R5_UNORM); } static boolean @@ -100,10 +102,10 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) unsigned w = fb->width; unsigned h = fb->height; - rt_enable = (NV34TCL_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1; - if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 | - NV40TCL_RT_ENABLE_COLOR2 | NV40TCL_RT_ENABLE_COLOR3)) - rt_enable |= NV34TCL_RT_ENABLE_MRT; + rt_enable = (NV30_3D_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1; + if (rt_enable & (NV30_3D_RT_ENABLE_COLOR1 | + NV40_3D_RT_ENABLE_COLOR2 | NV40_3D_RT_ENABLE_COLOR3)) + rt_enable |= NV30_3D_RT_ENABLE_MRT; nvfx->state.render_temps = 0; @@ -123,55 +125,63 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) if (prepare_result) { assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1))); - rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED | - (util_logbase2(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) | - (util_logbase2(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT); + rt_format = NV30_3D_RT_FORMAT_TYPE_SWIZZLED | + (util_logbase2(fb->width) << NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT) | + (util_logbase2(fb->height) << NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT); } else - rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR; + rt_format = NV30_3D_RT_FORMAT_TYPE_LINEAR; if(fb->nr_cbufs > 0) { switch (fb->cbufs[0]->format) { case PIPE_FORMAT_B8G8R8X8_UNORM: - rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8; + rt_format |= NV30_3D_RT_FORMAT_COLOR_X8R8G8B8; break; case PIPE_FORMAT_B8G8R8A8_UNORM: case 0: - rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8; + rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8; break; case PIPE_FORMAT_B5G6R5_UNORM: - rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5; + rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5; + break; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + rt_format |= NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT; + break; + case PIPE_FORMAT_R16G16B16A16_FLOAT: + rt_format |= NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT; break; default: assert(0); } } else if(fb->zsbuf && util_format_get_blocksize(fb->zsbuf->format) == 2) - rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5; + rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5; else - rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8; + rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8; if(fb->zsbuf) { switch (fb->zsbuf->format) { case PIPE_FORMAT_Z16_UNORM: - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16; break; case PIPE_FORMAT_S8_USCALED_Z24_UNORM: case PIPE_FORMAT_X8Z24_UNORM: case 0: - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8; break; default: assert(0); } } else if(fb->nr_cbufs && util_format_get_blocksize(fb->cbufs[0]->format) == 2) - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16; else - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8; + + MARK_RING(chan, 42, 10); - if ((rt_enable & NV34TCL_RT_ENABLE_COLOR0) || fb->zsbuf) { + if ((rt_enable & NV30_3D_RT_ENABLE_COLOR0) || fb->zsbuf) { struct nvfx_render_target *rt0 = &nvfx->hw_rt[0]; uint32_t pitch; - if(!(rt_enable & NV34TCL_RT_ENABLE_COLOR0)) + if(!(rt_enable & NV30_3D_RT_ENABLE_COLOR0)) rt0 = &nvfx->hw_zeta; pitch = rt0->pitch; @@ -186,23 +196,23 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) //printf("rendering to bo %p [%i] at offset %i with pitch %i\n", rt0->bo, rt0->bo->handle, rt0->offset, pitch); - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 1)); OUT_RELOC(chan, rt0->bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_COLOR0_PITCH, 2)); + OUT_RING(chan, RING_3D(NV30_3D_COLOR0_PITCH, 2)); OUT_RING(chan, pitch); OUT_RELOC(chan, rt0->bo, rt0->offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); } - if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) { - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1)); + if (rt_enable & NV30_3D_RT_ENABLE_COLOR1) { + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1)); OUT_RELOC(chan, nvfx->hw_rt[1].bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_COLOR1_OFFSET, 2)); + OUT_RING(chan, RING_3D(NV30_3D_COLOR1_OFFSET, 2)); OUT_RELOC(chan, nvfx->hw_rt[1].bo, nvfx->hw_rt[1].offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); @@ -211,71 +221,69 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) if(nvfx->is_nv4x) { - if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) { - OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 1)); + if (rt_enable & NV40_3D_RT_ENABLE_COLOR2) { + OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 1)); OUT_RELOC(chan, nvfx->hw_rt[2].bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV40TCL_COLOR2_OFFSET, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR2_OFFSET, 1)); OUT_RELOC(chan, nvfx->hw_rt[2].bo, nvfx->hw_rt[2].offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - OUT_RING(chan, RING_3D(NV40TCL_COLOR2_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR2_PITCH, 1)); OUT_RING(chan, nvfx->hw_rt[2].pitch); } - if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) { - OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR3, 1)); + if (rt_enable & NV40_3D_RT_ENABLE_COLOR3) { + OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR3, 1)); OUT_RELOC(chan, nvfx->hw_rt[3].bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV40TCL_COLOR3_OFFSET, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR3_OFFSET, 1)); OUT_RELOC(chan, nvfx->hw_rt[3].bo, nvfx->hw_rt[3].offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - OUT_RING(chan, RING_3D(NV40TCL_COLOR3_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR3_PITCH, 1)); OUT_RING(chan, nvfx->hw_rt[3].pitch); } } if (fb->zsbuf) { - OUT_RING(chan, RING_3D(NV34TCL_DMA_ZETA, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_ZETA, 1)); OUT_RELOC(chan, nvfx->hw_zeta.bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_ZETA_OFFSET, 1)); + OUT_RING(chan, RING_3D(NV30_3D_ZETA_OFFSET, 1)); /* TODO: reverse engineer LMA */ OUT_RELOC(chan, nvfx->hw_zeta.bo, nvfx->hw_zeta.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); if(nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_ZETA_PITCH, 1)); OUT_RING(chan, nvfx->hw_zeta.pitch); } } else if(nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_ZETA_PITCH, 1)); OUT_RING(chan, 64); } - OUT_RING(chan, RING_3D(NV34TCL_RT_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_RT_ENABLE, 1)); OUT_RING(chan, rt_enable); - OUT_RING(chan, RING_3D(NV34TCL_RT_HORIZ, 3)); + OUT_RING(chan, RING_3D(NV30_3D_RT_HORIZ, 3)); OUT_RING(chan, (w << 16) | 0); OUT_RING(chan, (h << 16) | 0); OUT_RING(chan, rt_format); - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_HORIZ, 2)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_HORIZ, 2)); OUT_RING(chan, (w << 16) | 0); OUT_RING(chan, (h << 16) | 0); - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(0), 2)); OUT_RING(chan, ((w - 1) << 16) | 0); OUT_RING(chan, ((h - 1) << 16) | 0); - OUT_RING(chan, RING_3D(0x1d88, 1)); - OUT_RING(chan, (1 << 12) | h); if(!nvfx->is_nv4x) { /* Wonder why this is needed, context should all be set to zero on init */ /* TODO: we can most likely remove this, after putting it in context init */ - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TX_ORIGIN, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TX_ORIGIN, 1)); OUT_RING(chan, 0); } nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER; @@ -291,22 +299,22 @@ nvfx_framebuffer_relocate(struct nvfx_context *nvfx) #define DO_(var, pfx, name) \ if(var.bo) { \ - OUT_RELOC(chan, var.bo, RING_3D(pfx##TCL_DMA_##name, 1), rt_flags, 0, 0); \ + OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_DMA_##name, 1), rt_flags, 0, 0); \ OUT_RELOC(chan, var.bo, 0, \ rt_flags | NOUVEAU_BO_OR, \ chan->vram->handle, chan->gart->handle); \ - OUT_RELOC(chan, var.bo, RING_3D(pfx##TCL_##name##_OFFSET, 1), rt_flags, 0, 0); \ + OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_##name##_OFFSET, 1), rt_flags, 0, 0); \ OUT_RELOC(chan, var.bo, \ var.offset, rt_flags | NOUVEAU_BO_LOW, \ 0, 0); \ } #define DO(pfx, num) DO_(nvfx->hw_rt[num], pfx, COLOR##num) - DO(NV34, 0); - DO(NV34, 1); + DO(NV30, 0); + DO(NV30, 1); DO(NV40, 2); DO(NV40, 3); - DO_(nvfx->hw_zeta, NV34, ZETA); + DO_(nvfx->hw_zeta, NV30, ZETA); nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER; } diff --git a/src/gallium/drivers/nvfx/nvfx_state_rasterizer.c b/src/gallium/drivers/nvfx/nvfx_state_rasterizer.c deleted file mode 100644 index 7f14ae85d5..0000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_rasterizer.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_rasterizer_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - sb_emit(chan, nvfx->rasterizer->sb, nvfx->rasterizer->sb_len); -} - diff --git a/src/gallium/drivers/nvfx/nvfx_state_scissor.c b/src/gallium/drivers/nvfx/nvfx_state_scissor.c deleted file mode 100644 index 9077266120..0000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_scissor.c +++ /dev/null @@ -1,23 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_scissor_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel *chan = nvfx->screen->base.channel; - struct pipe_rasterizer_state *rast = &nvfx->rasterizer->pipe; - struct pipe_scissor_state *s = &nvfx->scissor; - - if ((rast->scissor == 0 && nvfx->state.scissor_enabled == 0)) - return; - nvfx->state.scissor_enabled = rast->scissor; - - WAIT_RING(chan, 3); - OUT_RING(chan, RING_3D(NV34TCL_SCISSOR_HORIZ, 2)); - if (nvfx->state.scissor_enabled) { - OUT_RING(chan, ((s->maxx - s->minx) << 16) | s->minx); - OUT_RING(chan, ((s->maxy - s->miny) << 16) | s->miny); - } else { - OUT_RING(chan, 4096 << 16); - OUT_RING(chan, 4096 << 16); - } -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_stipple.c b/src/gallium/drivers/nvfx/nvfx_state_stipple.c deleted file mode 100644 index b76e9dd382..0000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_stipple.c +++ /dev/null @@ -1,11 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_stipple_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel *chan = nvfx->screen->base.channel; - - WAIT_RING(chan, 33); - OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32)); - OUT_RINGp(chan, nvfx->stipple, 32); -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_viewport.c b/src/gallium/drivers/nvfx/nvfx_state_viewport.c deleted file mode 100644 index e983b16f32..0000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_viewport.c +++ /dev/null @@ -1,35 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_viewport_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel *chan = nvfx->screen->base.channel; - struct pipe_viewport_state *vpt = &nvfx->viewport; - - WAIT_RING(chan, 11); - if(nvfx->render_mode == HW) { - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TRANSLATE_X, 8)); - OUT_RINGf(chan, vpt->translate[0]); - OUT_RINGf(chan, vpt->translate[1]); - OUT_RINGf(chan, vpt->translate[2]); - OUT_RINGf(chan, vpt->translate[3]); - OUT_RINGf(chan, vpt->scale[0]); - OUT_RINGf(chan, vpt->scale[1]); - OUT_RINGf(chan, vpt->scale[2]); - OUT_RINGf(chan, vpt->scale[3]); - OUT_RING(chan, RING_3D(0x1d78, 1)); - OUT_RING(chan, 1); - } else { - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TRANSLATE_X, 8)); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 1.0f); - OUT_RINGf(chan, 1.0f); - OUT_RINGf(chan, 1.0f); - OUT_RINGf(chan, 1.0f); - OUT_RING(chan, RING_3D(0x1d78, 1)); - OUT_RING(chan, nvfx->is_nv4x ? 0x110 : 1); - } -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_zsa.c b/src/gallium/drivers/nvfx/nvfx_state_zsa.c deleted file mode 100644 index 608605d32b..0000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_zsa.c +++ /dev/null @@ -1,21 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_zsa_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - sb_emit(chan, nvfx->zsa->sb, nvfx->zsa->sb_len); -} - -void -nvfx_state_sr_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - struct pipe_stencil_ref *sr = &nvfx->stencil_ref; - - WAIT_RING(chan, 4); - OUT_RING(chan, RING_3D(NV34TCL_STENCIL_FRONT_FUNC_REF, 1)); - OUT_RING(chan, sr->ref_value[0]); - OUT_RING(chan, RING_3D(NV34TCL_STENCIL_BACK_FUNC_REF, 1)); - OUT_RING(chan, sr->ref_value[1]); -} diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c index a5931b6e15..70adebc1be 100644 --- a/src/gallium/drivers/nvfx/nvfx_surface.c +++ b/src/gallium/drivers/nvfx/nvfx_surface.c @@ -47,6 +47,9 @@ static INLINE void nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format) { unsigned bits = util_format_get_blocksizebits(format); + unsigned shift = 0; + rgn->one_bits = 0; + switch(bits) { case 8: @@ -54,43 +57,28 @@ nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format) break; case 16: rgn->bpps = 1; + if(format == PIPE_FORMAT_B5G5R5X1_UNORM) + rgn->one_bits = 1; break; case 32: rgn->bpps = 2; + if(format == PIPE_FORMAT_R8G8B8X8_UNORM || format == PIPE_FORMAT_B8G8R8X8_UNORM) + rgn->one_bits = 8; + break; + case 64: + rgn->bpps = 2; + shift = 1; + break; + case 128: + rgn->bpps = 2; + shift = 2; break; - default: - { - int shift; - assert(util_is_power_of_two(bits)); - shift = util_logbase2(bits) - 3; - assert(shift >= 2); - rgn->bpps = 2; - shift -= 2; - - rgn->x = util_format_get_nblocksx(format, rgn->x) << shift; - rgn->y = util_format_get_nblocksy(format, rgn->y); - } } -} -static INLINE void -nvfx_region_fixup_swizzled(struct nv04_region* rgn, unsigned zslice, unsigned width, unsigned height, unsigned depth) -{ - // TODO: move this code to surface creation? - if((depth <= 1) && (height <= 1 || width <= 2)) - rgn->pitch = width << rgn->bpps; - else if(depth > 1 && height <= 2 && width <= 2) - { - rgn->pitch = width << rgn->bpps; - rgn->offset += (zslice * width * height) << rgn->bpps; - } - else - { - rgn->pitch = 0; - rgn->z = zslice; - rgn->w = width; - rgn->h = height; - rgn->d = depth; + if(shift) { + rgn->x = util_format_get_nblocksx(format, rgn->x) << shift; + rgn->y = util_format_get_nblocksy(format, rgn->y); + rgn->w <<= shift; } } @@ -100,7 +88,6 @@ nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, rgn->x = x; rgn->y = y; rgn->z = 0; - nvfx_region_set_format(rgn, surf->base.base.format); if(surf->temp) { @@ -113,11 +100,22 @@ nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, } else { rgn->bo = ((struct nvfx_resource*)surf->base.base.texture)->bo; rgn->offset = surf->base.base.offset; - rgn->pitch = surf->pitch; - if(!(surf->base.base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR)) - nvfx_region_fixup_swizzled(rgn, surf->base.base.zslice, surf->base.base.width, surf->base.base.height, u_minify(surf->base.base.texture->depth0, surf->base.base.level)); + if(surf->base.base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR) + rgn->pitch = surf->pitch; + else + { + rgn->pitch = 0; + rgn->z = surf->base.base.zslice; + rgn->w = surf->base.base.width; + rgn->h = surf->base.base.height; + rgn->d = u_minify(surf->base.base.texture->depth0, surf->base.base.level); + } } + + nvfx_region_set_format(rgn, surf->base.base.format); + if(!rgn->pitch) + nv04_region_try_to_linearize(rgn); } static INLINE void @@ -135,67 +133,50 @@ nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* rgn->bo = ((struct nvfx_resource*)pt)->bo; rgn->offset = nvfx_subresource_offset(pt, sub.face, sub.level, z); - rgn->pitch = nvfx_subresource_pitch(pt, sub.level); rgn->x = x; rgn->y = y; - rgn->z = 0; - nvfx_region_set_format(rgn, pt->format); - if(!(pt->flags & NVFX_RESOURCE_FLAG_LINEAR)) - nvfx_region_fixup_swizzled(rgn, z, u_minify(pt->width0, sub.level), u_minify(pt->height0, sub.level), u_minify(pt->depth0, sub.level)); -} - -// TODO: actually test this for all formats, it's probably wrong for some... - -static INLINE int -nvfx_surface_format(enum pipe_format format) -{ - switch(util_format_get_blocksize(format)) { - case 1: - return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8; - case 2: - //return NV04_CONTEXT_SURFACES_2D_FORMAT_Y16; - return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5; - case 4: - //if(format == PIPE_FORMAT_B8G8R8X8_UNORM || format == PIPE_FORMAT_B8G8R8A8_UNORM) - return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8; - //else - // return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32; - default: - return -1; + if(pt->flags & NVFX_RESOURCE_FLAG_LINEAR) + { + rgn->pitch = nvfx_subresource_pitch(pt, sub.level); + rgn->z = 0; } -} - -static INLINE int -nv04_scaled_image_format(enum pipe_format format) -{ - switch(util_format_get_blocksize(format)) { - case 1: - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8; - case 2: - //if(format == PIPE_FORMAT_B5G5R5A1_UNORM) - // return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5; - //else - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5; - case 4: - if(format == PIPE_FORMAT_B8G8R8X8_UNORM) - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8; - else - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8; - default: - return -1; + else + { + rgn->pitch = 0; + rgn->z = z; + rgn->w = u_minify(pt->width0, sub.level); + rgn->h = u_minify(pt->height0, sub.level); + rgn->d = u_minify(pt->depth0, sub.level); } + + nvfx_region_set_format(rgn, pt->format); + if(!rgn->pitch) + nv04_region_try_to_linearize(rgn); } -// XXX: must save index buffer too! +// don't save index buffer because blitter doesn't setit static struct blitter_context* nvfx_get_blitter(struct pipe_context* pipe, int copy) { struct nvfx_context* nvfx = nvfx_context(pipe); + struct blitter_context** pblitter; + struct blitter_context* blitter; + + assert(nvfx->blitters_in_use < Elements(nvfx->blitter)); - struct blitter_context* blitter = nvfx->blitter; - if(!blitter) - nvfx->blitter = blitter = util_blitter_create(pipe); + if(nvfx->query && !nvfx->blitters_in_use) + { + struct nouveau_channel* chan = nvfx->screen->base.channel; + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 0); + } + + pblitter = &nvfx->blitter[nvfx->blitters_in_use++]; + if(!*pblitter) + *pblitter = util_blitter_create(pipe); + blitter = *pblitter; util_blitter_save_blend(blitter, nvfx->blend); util_blitter_save_depth_stencil_alpha(blitter, nvfx->zsa); @@ -218,6 +199,22 @@ nvfx_get_blitter(struct pipe_context* pipe, int copy) return blitter; } +static inline void +nvfx_put_blitter(struct pipe_context* pipe, struct blitter_context* blitter) +{ + struct nvfx_context* nvfx = nvfx_context(pipe); + --nvfx->blitters_in_use; + assert(nvfx->blitters_in_use >= 0); + + if(nvfx->query && !nvfx->blitters_in_use) + { + struct nouveau_channel* chan = nvfx->screen->base.channel; + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 1); + } +} + static unsigned nvfx_region_clone(struct nv04_2d_context* ctx, struct nv04_region* rgn, unsigned w, unsigned h, boolean for_read) { @@ -269,16 +266,21 @@ nvfx_resource_copy_region(struct pipe_context *pipe, if((!dst_to_gpu || !src_on_gpu) && small) ret = -1; /* use the CPU */ else - ret = nv04_region_copy_2d(ctx, &dst, &src, w, h, - dstr->target == PIPE_BUFFER ? -1 : nvfx_surface_format(dstr->format), - dstr->target == PIPE_BUFFER ? -1 : nv04_scaled_image_format(dstr->format), - dst_to_gpu, src_on_gpu); + ret = nv04_region_copy_2d(ctx, &dst, &src, w, h, dst_to_gpu, src_on_gpu); if(!ret) {} - else if(ret > 0 && dstr->bind & PIPE_BIND_RENDER_TARGET && srcr->bind & PIPE_BIND_SAMPLER_VIEW) + else if(ret > 0 + && dstr->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL) + && srcr->bind & PIPE_BIND_SAMPLER_VIEW) { + /* this currently works because we hack the bind flags on resource creation to be + * the maximum set that the resource type actually supports + * + * TODO: perhaps support reinterpreting the formats + */ struct blitter_context* blitter = nvfx_get_blitter(pipe, 1); util_blitter_copy_region(blitter, dstr, subdst, dstx, dsty, dstz, srcr, subsrc, srcx, srcy, srcz, w, h, TRUE); + nvfx_put_blitter(pipe, blitter); } else { @@ -371,11 +373,19 @@ nvfx_surface_copy_temp(struct pipe_context* pipe, struct pipe_surface* surf, int struct nvfx_surface* ns = (struct nvfx_surface*)surf; struct pipe_subresource tempsr, surfsr; struct nvfx_context* nvfx = nvfx_context(pipe); + struct nvfx_miptree* temp; + unsigned use_vertex_buffers; + boolean use_index_buffer; + unsigned base_vertex; + + /* temporarily detach the temp, so it isn't used in place of the actual resource */ + temp = ns->temp; + ns->temp = 0; // TODO: we really should do this validation before setting these variable in draw calls - unsigned use_vertex_buffers = nvfx->use_vertex_buffers; - boolean use_index_buffer = nvfx->use_index_buffer; - unsigned base_vertex = nvfx->base_vertex; + use_vertex_buffers = nvfx->use_vertex_buffers; + use_index_buffer = nvfx->use_index_buffer; + base_vertex = nvfx->base_vertex; tempsr.face = 0; tempsr.level = 0; @@ -383,9 +393,16 @@ nvfx_surface_copy_temp(struct pipe_context* pipe, struct pipe_surface* surf, int surfsr.level = surf->level; if(to_temp) - nvfx_resource_copy_region(pipe, &ns->temp->base.base, tempsr, 0, 0, 0, surf->texture, surfsr, 0, 0, surf->zslice, surf->width, surf->height); + nvfx_resource_copy_region(pipe, &temp->base.base, tempsr, 0, 0, 0, surf->texture, surfsr, 0, 0, surf->zslice, surf->width, surf->height); else - nvfx_resource_copy_region(pipe, surf->texture, surfsr, 0, 0, surf->zslice, &ns->temp->base.base, tempsr, 0, 0, 0, surf->width, surf->height); + nvfx_resource_copy_region(pipe, surf->texture, surfsr, 0, 0, surf->zslice, &temp->base.base, tempsr, 0, 0, 0, surf->width, surf->height); + + /* If this triggers, it probably means we attempted to use the blitter + * but failed due to non-renderability of the target. + * Obviously, this would lead to infinite recursion if supported. */ + assert(!ns->temp); + + ns->temp = temp; nvfx->use_vertex_buffers = use_vertex_buffers; nvfx->use_index_buffer = use_index_buffer; @@ -409,6 +426,8 @@ nvfx_surface_create_temp(struct pipe_context* pipe, struct pipe_surface* surf) template.nr_samples = surf->texture->nr_samples; template.flags = NVFX_RESOURCE_FLAG_LINEAR; + assert(!ns->temp && !util_dirty_surface_is_dirty(&ns->base)); + ns->temp = (struct nvfx_miptree*)nvfx_miptree_create(pipe->screen, &template); nvfx_surface_copy_temp(pipe, surf, 1); } @@ -420,11 +439,10 @@ nvfx_surface_flush(struct pipe_context* pipe, struct pipe_surface* surf) struct nvfx_surface* ns = (struct nvfx_surface*)surf; boolean bound = FALSE; - /* must be done before the copy, otherwise the copy will use the temp as destination */ - util_dirty_surface_set_clean(nvfx_surface_get_dirty_surfaces(surf), &ns->base); - nvfx_surface_copy_temp(pipe, surf, 0); + util_dirty_surface_set_clean(nvfx_surface_get_dirty_surfaces(surf), &ns->base); + if(nvfx->framebuffer.zsbuf == surf) bound = TRUE; else @@ -459,6 +477,7 @@ nvfx_clear_render_target(struct pipe_context *pipe, // TODO: probably should use hardware clear here instead if possible struct blitter_context* blitter = nvfx_get_blitter(pipe, 0); util_blitter_clear_render_target(blitter, dst, rgba, dstx, dsty, width, height); + nvfx_put_blitter(pipe, blitter); } } @@ -477,6 +496,7 @@ nvfx_clear_depth_stencil(struct pipe_context *pipe, // TODO: probably should use hardware clear here instead if possible struct blitter_context* blitter = nvfx_get_blitter(pipe, 0); util_blitter_clear_depth_stencil(blitter, dst, clear_flags, depth, stencil, dstx, dsty, width, height); + nvfx_put_blitter(pipe, blitter); } } diff --git a/src/gallium/drivers/nvfx/nvfx_surface.h b/src/gallium/drivers/nvfx/nvfx_surface.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/gallium/drivers/nvfx/nvfx_surface.h diff --git a/src/gallium/drivers/nvfx/nvfx_tex.h b/src/gallium/drivers/nvfx/nvfx_tex.h index 34be936a89..2f2d737808 100644 --- a/src/gallium/drivers/nvfx/nvfx_tex.h +++ b/src/gallium/drivers/nvfx/nvfx_tex.h @@ -4,7 +4,7 @@ #include "util/u_math.h" #include "pipe/p_defines.h" #include "pipe/p_state.h" -#include <nouveau/nouveau_class.h> + static inline unsigned nvfx_tex_wrap_mode(unsigned wrap) { @@ -12,36 +12,36 @@ nvfx_tex_wrap_mode(unsigned wrap) { switch (wrap) { case PIPE_TEX_WRAP_REPEAT: - ret = NV34TCL_TX_WRAP_S_REPEAT; + ret = NV30_3D_TEX_WRAP_S_REPEAT; break; case PIPE_TEX_WRAP_MIRROR_REPEAT: - ret = NV34TCL_TX_WRAP_S_MIRRORED_REPEAT; + ret = NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT; break; case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - ret = NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE; + ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE; break; case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - ret = NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER; + ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER; break; case PIPE_TEX_WRAP_CLAMP: - ret = NV34TCL_TX_WRAP_S_CLAMP; + ret = NV30_3D_TEX_WRAP_S_CLAMP; break; case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: - ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE; + ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE; break; case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: - ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER; + ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER; break; case PIPE_TEX_WRAP_MIRROR_CLAMP: - ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP; + ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP; break; default: assert(0); - ret = NV34TCL_TX_WRAP_S_REPEAT; + ret = NV30_3D_TEX_WRAP_S_REPEAT; break; } - return ret >> NV34TCL_TX_WRAP_S_SHIFT; + return ret >> NV30_3D_TEX_WRAP_S__SHIFT; } static inline unsigned @@ -49,21 +49,21 @@ nvfx_tex_wrap_compare_mode(unsigned func) { switch (func) { case PIPE_FUNC_NEVER: - return NV34TCL_TX_WRAP_RCOMP_NEVER; + return NV30_3D_TEX_WRAP_RCOMP_NEVER; case PIPE_FUNC_GREATER: - return NV34TCL_TX_WRAP_RCOMP_GREATER; + return NV30_3D_TEX_WRAP_RCOMP_GREATER; case PIPE_FUNC_EQUAL: - return NV34TCL_TX_WRAP_RCOMP_EQUAL; + return NV30_3D_TEX_WRAP_RCOMP_EQUAL; case PIPE_FUNC_GEQUAL: - return NV34TCL_TX_WRAP_RCOMP_GEQUAL; + return NV30_3D_TEX_WRAP_RCOMP_GEQUAL; case PIPE_FUNC_LESS: - return NV34TCL_TX_WRAP_RCOMP_LESS; + return NV30_3D_TEX_WRAP_RCOMP_LESS; case PIPE_FUNC_NOTEQUAL: - return NV34TCL_TX_WRAP_RCOMP_NOTEQUAL; + return NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL; case PIPE_FUNC_LEQUAL: - return NV34TCL_TX_WRAP_RCOMP_LEQUAL; + return NV30_3D_TEX_WRAP_RCOMP_LEQUAL; case PIPE_FUNC_ALWAYS: - return NV34TCL_TX_WRAP_RCOMP_ALWAYS; + return NV30_3D_TEX_WRAP_RCOMP_ALWAYS; default: assert(0); return 0; @@ -75,11 +75,11 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso) unsigned filter = 0; switch (cso->mag_img_filter) { case PIPE_TEX_FILTER_LINEAR: - filter |= NV34TCL_TX_FILTER_MAGNIFY_LINEAR; + filter |= NV30_3D_TEX_FILTER_MAG_LINEAR; break; case PIPE_TEX_FILTER_NEAREST: default: - filter |= NV34TCL_TX_FILTER_MAGNIFY_NEAREST; + filter |= NV30_3D_TEX_FILTER_MAG_NEAREST; break; } @@ -87,14 +87,14 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso) case PIPE_TEX_FILTER_LINEAR: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; + filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; + filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR; + filter |= NV30_3D_TEX_FILTER_MIN_LINEAR; break; } break; @@ -102,14 +102,14 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso) default: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; + filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; + filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST; + filter |= NV30_3D_TEX_FILTER_MIN_NEAREST; break; } break; diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c index e6e9a8f2e4..597664e771 100644 --- a/src/gallium/drivers/nvfx/nvfx_vbo.c +++ b/src/gallium/drivers/nvfx/nvfx_vbo.c @@ -9,7 +9,7 @@ #include "nvfx_resource.h" #include "nouveau/nouveau_channel.h" -#include "nouveau/nouveau_class.h" + #include "nouveau/nouveau_pushbuf.h" static inline unsigned @@ -266,7 +266,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) } - OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements)); + OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements)); if(nvfx->use_vertex_buffers) { unsigned idx = 0; @@ -281,7 +281,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) idx = ve->idx; } - OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT)); + OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV30_3D_VTXFMT_STRIDE__SHIFT)); ++idx; } if(idx != nvfx->vtxelt->num_elements) @@ -291,7 +291,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) OUT_RINGp(chan, nvfx->vtxelt->vtxfmt, nvfx->vtxelt->num_elements); for(i = nvfx->vtxelt->num_elements; i < elements; ++i) - OUT_RING(chan, NV34TCL_VTXFMT_TYPE_32_FLOAT); + OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT); if(nvfx->is_nv4x) { unsigned i; @@ -302,7 +302,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) } } - OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements)); + OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements)); if(nvfx->use_vertex_buffers) { unsigned idx = 0; @@ -317,7 +317,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride, vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, - 0, NV34TCL_VTXBUF_ADDRESS_DMA1); + 0, NV30_3D_VTXBUF_DMA1); ++idx; } @@ -339,6 +339,44 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) } void +nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned num_outputs = nvfx->vertprog->draw_elements; + int elements = MAX2(num_outputs, nvfx->hw_vtxelt_nr); + + if (!elements) + return; + + WAIT_RING(chan, (1 + 6 + 1 + 2) + elements * 2); + + OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements)); + for(unsigned i = 0; i < num_outputs; ++i) + OUT_RING(chan, (4 << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT); + for(unsigned i = num_outputs; i < elements; ++i) + OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT); + + if(nvfx->is_nv4x) { + unsigned i; + /* seems to be some kind of cache flushing */ + for(i = 0; i < 3; ++i) { + OUT_RING(chan, RING_3D(0x1718, 1)); + OUT_RING(chan, 0); + } + } + + OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements)); + for (unsigned i = 0; i < elements; i++) + OUT_RING(chan, 0); + + OUT_RING(chan, RING_3D(0x1710, 1)); + OUT_RING(chan, 0); + + nvfx->hw_vtxelt_nr = num_outputs; + nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF; +} + +void nvfx_vbo_relocate(struct nvfx_context *nvfx) { struct nouveau_channel* chan; @@ -357,11 +395,11 @@ nvfx_vbo_relocate(struct nvfx_context *nvfx) struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index]; struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo; - OUT_RELOC(chan, bo, RING_3D(NV34TCL_VTXBUF_ADDRESS(ve->idx), 1), + OUT_RELOC(chan, bo, RING_3D(NV30_3D_VTXBUF(ve->idx), 1), vb_flags, 0, 0); OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride, vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, - 0, NV34TCL_VTXBUF_ADDRESS_DMA1); + 0, NV30_3D_VTXBUF_DMA1); } nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF; } @@ -370,7 +408,7 @@ static void nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags) { struct nouveau_channel* chan = nvfx->screen->base.channel; - unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV34TCL_IDXBUF_FORMAT_TYPE_U16 : NV34TCL_IDXBUF_FORMAT_TYPE_U32; + unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV30_3D_IDXBUF_FORMAT_TYPE_U16 : NV30_3D_IDXBUF_FORMAT_TYPE_U32; struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf.buffer)->bo; ib_flags |= nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD; @@ -378,12 +416,12 @@ nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags) MARK_RING(chan, 3, 3); if(ib_flags & NOUVEAU_BO_DUMMY) - OUT_RELOC(chan, bo, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2), ib_flags, 0, 0); + OUT_RELOC(chan, bo, RING_3D(NV30_3D_IDXBUF_OFFSET, 2), ib_flags, 0, 0); else - OUT_RING(chan, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2)); + OUT_RING(chan, RING_3D(NV30_3D_IDXBUF_OFFSET, 2)); OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0); OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR, - 0, NV34TCL_IDXBUF_FORMAT_DMA1); + 0, NV30_3D_IDXBUF_FORMAT_DMA1); nvfx->relocs_needed &=~ NVFX_RELOCATE_IDXBUF; } @@ -401,27 +439,27 @@ nvfx_idxbuf_relocate(struct nvfx_context* nvfx) unsigned nvfx_vertex_formats[PIPE_FORMAT_COUNT] = { - [PIPE_FORMAT_R32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R32G32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R32G32B32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R16G16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R16G16B16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8B8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8B8A8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8B8A8_USCALED] = NV34TCL_VTXFMT_TYPE_8_USCALED, - [PIPE_FORMAT_R16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16G16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16G16B16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16G16B16A16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, - [PIPE_FORMAT_R16G16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, - [PIPE_FORMAT_R16G16B16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, - [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, + [PIPE_FORMAT_R32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R32G32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R32G32B32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R16G16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R16G16B16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8B8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8B8A8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8B8A8_USCALED] = NV30_3D_VTXFMT_TYPE_U8_USCALED, + [PIPE_FORMAT_R16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16G16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16G16B16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16G16B16A16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, + [PIPE_FORMAT_R16G16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, + [PIPE_FORMAT_R16G16B16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, + [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, }; static void * @@ -476,7 +514,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, if(ve->instance_divisor) { struct nvfx_low_frequency_element* lfve; - cso->vtxfmt[i] = NV34TCL_VTXFMT_TYPE_32_FLOAT; + cso->vtxfmt[i] = NV30_3D_VTXFMT_TYPE_V32_FLOAT; //if(ve->frequency == PIPE_ELEMENT_FREQUENCY_CONSTANT) if(0) @@ -511,14 +549,14 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, if(type) { transkey.element[idx].output_format = ve->src_format; - cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type; + cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | type; } else { unsigned float32[4] = {PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT}; transkey.element[idx].output_format = float32[ncomp - 1]; cso->needs_translate = TRUE; - cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | NV34TCL_VTXFMT_TYPE_32_FLOAT; + cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT; } transkey.element[idx].output_offset = transkey.output_stride; transkey.output_stride += (util_format_get_stride(transkey.element[idx].output_format, 1) + 3) & ~3; @@ -527,7 +565,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, cso->translate = translate_create(&transkey); cso->vertex_length = transkey.output_stride >> 2; - cso->max_vertices_per_packet = 2047 / cso->vertex_length; + cso->max_vertices_per_packet = 2047 / MAX2(cso->vertex_length, 1); return (void *)cso; } diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c index ea7e88c561..23f045ecf6 100644 --- a/src/gallium/drivers/nvfx/nvfx_vertprog.c +++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c @@ -8,6 +8,7 @@ #include "tgsi/tgsi_parse.h" #include "tgsi/tgsi_dump.h" #include "tgsi/tgsi_util.h" +#include "tgsi/tgsi_ureg.h" #include "draw/draw_context.h" @@ -37,7 +38,9 @@ struct nvfx_loop_entry struct nvfx_vpc { struct nvfx_context* nvfx; + struct pipe_shader_state pipe; struct nvfx_vertex_program *vp; + struct tgsi_shader_info* info; struct nvfx_vertex_program_exec *vpi; @@ -46,6 +49,8 @@ struct nvfx_vpc { struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS]; struct nvfx_reg *r_address; struct nvfx_reg *r_temp; + struct nvfx_reg *r_const; + struct nvfx_reg r_0_1; struct nvfx_reg *imm; unsigned nr_imm; @@ -105,8 +110,8 @@ constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w) return nvfx_reg(NVFXSR_CONST, idx); } -#define arith(s,o,d,m,s0,s1,s2) \ - nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2)) +#define arith(s,t,o,d,m,s0,s1,s2) \ + nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2)) static void emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src) @@ -152,6 +157,18 @@ emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) | (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT))); + if(src.indirect) { + if(src.reg.type == NVFXSR_CONST) + hw[3] |= NVFX_VP(INST_INDEX_CONST); + else if(src.reg.type == NVFXSR_INPUT) + hw[0] |= NVFX_VP(INST_INDEX_INPUT); + else + assert(0); + if(src.indirect_reg) + hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1); + hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT); + } + switch (pos) { case 0: hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >> @@ -279,6 +296,13 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn) if(insn.cc_update) hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE); + if(insn.sat) + { + assert(nvfx->use_nv4x); + if(nvfx->use_nv4x) + hw[0] |= NV40_VP_INST_SATURATE; + } + if(!nvfx->is_nv4x) { if(slot == 0) hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT); @@ -317,6 +341,9 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn) emit_src(nvfx, vpc, hw, 0, insn.src[0]); emit_src(nvfx, vpc, hw, 1, insn.src[1]); emit_src(nvfx, vpc, hw, 2, insn.src[2]); + +// if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL) +// hw[3] |= NV40_VP_INST_SCA_RESULT; } static inline struct nvfx_src @@ -328,7 +355,7 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index); break; case TGSI_FILE_CONSTANT: - src.reg = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0); + src.reg = vpc->r_const[fsrc->Register.Index]; break; case TGSI_FILE_IMMEDIATE: src.reg = vpc->imm[fsrc->Register.Index]; @@ -339,7 +366,7 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { default: NOUVEAU_ERR("bad src file\n"); src.reg.index = 0; - src.reg.type = 0; + src.reg.type = -1; break; } @@ -349,6 +376,22 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { src.swz[1] = fsrc->Register.SwizzleY; src.swz[2] = fsrc->Register.SwizzleZ; src.swz[3] = fsrc->Register.SwizzleW; + src.indirect = 0; + + if(fsrc->Register.Indirect) { + if(fsrc->Indirect.File == TGSI_FILE_ADDRESS && + (fsrc->Register.File == TGSI_FILE_CONSTANT || fsrc->Register.File == TGSI_FILE_INPUT)) + { + src.indirect = 1; + src.indirect_reg = fsrc->Indirect.Index; + src.indirect_swz = fsrc->Indirect.SwizzleX; + } + else + { + src.reg.index = 0; + src.reg.type = -1; + } + } return src; } @@ -397,16 +440,16 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, { struct nvfx_src src[3], tmp; struct nvfx_reg dst; + struct nvfx_reg final_dst; struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct nvfx_insn insn; struct nvfx_relocation reloc; struct nvfx_loop_entry loop; + boolean sat = FALSE; int mask; int ai = -1, ci = -1, ii = -1; int i; - - if (finst->Instruction.Opcode == TGSI_OPCODE_END) - return TRUE; + unsigned sub_depth = 0; for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { const struct tgsi_full_src_register *fsrc; @@ -429,7 +472,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, src[i] = tgsi_src(vpc, fsrc); } else { src[i] = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); } break; case TGSI_FILE_CONSTANT: @@ -439,7 +482,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, src[i] = tgsi_src(vpc, fsrc); } else { src[i] = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); } break; case TGSI_FILE_IMMEDIATE: @@ -449,7 +492,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, src[i] = tgsi_src(vpc, fsrc); } else { src[i] = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); } break; case TGSI_FILE_TEMPORARY: @@ -461,161 +504,178 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, } } - dst = tgsi_dst(vpc, &finst->Dst[0]); + for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { + if(src[i].reg.type < 0) + return FALSE; + } + + if(finst->Dst[0].Register.File == TGSI_FILE_ADDRESS && + finst->Instruction.Opcode != TGSI_OPCODE_ARL) + return FALSE; + + final_dst = dst = tgsi_dst(vpc, &finst->Dst[0]); mask = tgsi_mask(finst->Dst[0].Register.WriteMask); + if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE) + { + assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL); + if(nvfx->use_nv4x) + sat = TRUE; + else if(dst.type != NVFXSR_TEMP) + dst = temp(vpc); + } switch (finst->Instruction.Opcode) { case TGSI_OPCODE_ABS: - nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, abs(src[0]), none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none, none)); break; case TGSI_OPCODE_ADD: - nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, src[1])); + nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); break; case TGSI_OPCODE_ARL: - nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_CMP: - insn = arith(VEC, MOV, none.reg, mask, src[0], none, none); + insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); insn.cc_update = 1; nvfx_vp_emit(vpc, insn); - insn = arith(VEC, MOV, dst, mask, src[2], none, none); + insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); insn.cc_test = NVFX_COND_GE; nvfx_vp_emit(vpc, insn); - insn = arith(VEC, MOV, dst, mask, src[1], none, none); + insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none); insn.cc_test = NVFX_COND_LT; nvfx_vp_emit(vpc, insn); break; case TGSI_OPCODE_COS: - nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_DP2: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none)); - nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none)); + nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y))); break; case TGSI_OPCODE_DP3: - nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DP3, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_DP4: - nvfx_vp_emit(vpc, arith(VEC, DP4, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DP4, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_DPH: - nvfx_vp_emit(vpc, arith(VEC, DPH, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DPH, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_DST: - nvfx_vp_emit(vpc, arith(VEC, DST, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DST, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_EX2: - nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_EXP: - nvfx_vp_emit(vpc, arith(SCA, EXP, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, EXP, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_FLR: - nvfx_vp_emit(vpc, arith(VEC, FLR, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, FLR, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_FRC: - nvfx_vp_emit(vpc, arith(VEC, FRC, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_LG2: - nvfx_vp_emit(vpc, arith(SCA, LG2, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, LG2, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_LIT: - nvfx_vp_emit(vpc, arith(SCA, LIT, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, LIT, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_LOG: - nvfx_vp_emit(vpc, arith(SCA, LOG, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, LOG, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_LRP: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2])); - nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], tmp)); + nvfx_vp_emit(vpc, arith(0, VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2])); + nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], tmp)); break; case TGSI_OPCODE_MAD: - nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], src[2])); + nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], src[2])); break; case TGSI_OPCODE_MAX: - nvfx_vp_emit(vpc, arith(VEC, MAX, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MAX, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_MIN: - nvfx_vp_emit(vpc, arith(VEC, MIN, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MIN, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_MOV: - nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_MUL: - nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MUL, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_NOP: break; case TGSI_OPCODE_POW: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X))); - nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none)); - nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X))); + nvfx_vp_emit(vpc, arith(0, SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X))); + nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none)); + nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X))); break; case TGSI_OPCODE_RCP: - nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, RCP, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_RSQ: - nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0]))); + nvfx_vp_emit(vpc, arith(sat, SCA, RSQ, dst, mask, none, none, abs(src[0]))); break; case TGSI_OPCODE_SEQ: - nvfx_vp_emit(vpc, arith(VEC, SEQ, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SFL: - nvfx_vp_emit(vpc, arith(VEC, SFL, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SFL, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SGE: - nvfx_vp_emit(vpc, arith(VEC, SGE, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SGE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SGT: - nvfx_vp_emit(vpc, arith(VEC, SGT, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SGT, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SIN: - nvfx_vp_emit(vpc, arith(SCA, SIN, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, SIN, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_SLE: - nvfx_vp_emit(vpc, arith(VEC, SLE, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SLE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SLT: - nvfx_vp_emit(vpc, arith(VEC, SLT, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SLT, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SNE: - nvfx_vp_emit(vpc, arith(VEC, SNE, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SNE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SSG: - nvfx_vp_emit(vpc, arith(VEC, SSG, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SSG, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_STR: - nvfx_vp_emit(vpc, arith(VEC, STR, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, STR, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SUB: - nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1]))); + nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, neg(src[1]))); break; case TGSI_OPCODE_TRUNC: tmp = nvfx_src(temp(vpc)); - insn = arith(VEC, MOV, none.reg, mask, src[0], none, none); + insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); insn.cc_update = 1; nvfx_vp_emit(vpc, insn); - nvfx_vp_emit(vpc, arith(VEC, FLR, tmp.reg, mask, abs(src[0]), none, none)); - nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, tmp, none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, abs(src[0]), none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, tmp, none, none)); - insn = arith(VEC, MOV, dst, mask, neg(tmp), none, none); + insn = arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none); insn.cc_test = NVFX_COND_LT; nvfx_vp_emit(vpc, insn); break; case TGSI_OPCODE_XPD: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none)); - nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp))); + nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp))); break; case TGSI_OPCODE_IF: - insn = arith(VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none); + insn = arith(0, VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none); insn.cc_update = 1; nvfx_vp_emit(vpc, insn); @@ -623,7 +683,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = finst->Label.Label + 1; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - insn = arith(SCA, BRA, none.reg, 0, none, none, none); + insn = arith(0, SCA, BRA, none.reg, 0, none, none, none); insn.cc_test = NVFX_COND_EQ; insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0; nvfx_vp_emit(vpc, insn); @@ -637,20 +697,31 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); if(finst->Instruction.Opcode == TGSI_OPCODE_CAL) - insn = arith(SCA, CAL, none.reg, 0, none, none, none); + insn = arith(0, SCA, CAL, none.reg, 0, none, none, none); else - insn = arith(SCA, BRA, none.reg, 0, none, none, none); + insn = arith(0, SCA, BRA, none.reg, 0, none, none, none); nvfx_vp_emit(vpc, insn); break; case TGSI_OPCODE_RET: - tmp = none; - tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0; - nvfx_vp_emit(vpc, arith(SCA, RET, none.reg, 0, none, none, tmp)); + if(sub_depth || !nvfx->use_vp_clipping) { + tmp = none; + tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0; + nvfx_vp_emit(vpc, arith(0, SCA, RET, none.reg, 0, none, none, tmp)); + } else { + reloc.location = vpc->vp->nr_insns; + reloc.target = vpc->info->num_instructions; + util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); + } break; case TGSI_OPCODE_BGNSUB: + ++sub_depth; + break; case TGSI_OPCODE_ENDSUB: + --sub_depth; + break; case TGSI_OPCODE_ENDIF: /* nothing to do here */ break; @@ -668,7 +739,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = loop.cont_target; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none)); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); break; case TGSI_OPCODE_CONT: @@ -678,7 +749,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = loop.cont_target; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none)); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); break; case TGSI_OPCODE_BRK: @@ -688,7 +759,24 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = loop.brk_target; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none)); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); + break; + + case TGSI_OPCODE_END: + assert(!sub_depth); + if(nvfx->use_vp_clipping) { + if(idx != (vpc->info->num_instructions - 1)) { + reloc.location = vpc->vp->nr_insns; + reloc.target = vpc->info->num_instructions; + util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); + } + } else { + if(vpc->vp->nr_insns) + vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; + nvfx_vp_emit(vpc, arith(0, VEC, NOP, none.reg, 0, none, none, none)); + vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; + } break; default: @@ -696,6 +784,14 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, return FALSE; } + if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE && !nvfx->use_nv4x) + { + if(!vpc->r_0_1.type) + vpc->r_0_1 = constant(vpc, -1, 0, 1, 0, 0); + nvfx_vp_emit(vpc, arith(0, VEC, MAX, dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), X, X, X, X), none)); + nvfx_vp_emit(vpc, arith(0, VEC, MIN, final_dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), Y, Y, Y, Y), none)); + } + release_temps(vpc); return TRUE; } @@ -741,8 +837,13 @@ nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, hw = NVFX_VP(INST_DEST_PSZ); break; case TGSI_SEMANTIC_GENERIC: - hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf) - + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0); + hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf) - NVFX_FP_OP_INPUT_SRC_TC(0); + if(hw <= 8) + hw = NVFX_VP(INST_DEST_TC(hw)); + else if(hw == 9) /* TODO: this is correct, but how does this overlapping work exactly? */ + hw = NV40_VP_INST_DEST_PSZ; + else + assert(0); break; case TGSI_SEMANTIC_EDGEFLAG: /* not really an error just a fallback */ @@ -761,22 +862,23 @@ static boolean nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) { struct tgsi_parse_context p; - int high_temp = -1, high_addr = -1, nr_imm = 0, i; + int high_const = -1, high_temp = -1, high_addr = -1, nr_imm = 0, i; struct util_semantic_set set; - unsigned char sem_layout[8]; + unsigned char sem_layout[10]; unsigned num_outputs; + unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8; - num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT); + num_outputs = util_semantic_set_from_program_file(&set, vpc->pipe.tokens, TGSI_FILE_OUTPUT); - if(num_outputs > 8) { + if(num_outputs > num_texcoords) { NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs); return FALSE; } - util_semantic_layout_from_set(sem_layout, &set, 8, 8); + util_semantic_layout_from_set(sem_layout, &set, num_texcoords, num_texcoords); /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */ memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input)); - for(int i = 0; i < 8; ++i) { + for(int i = 0; i < num_texcoords; ++i) { if(sem_layout[i] == 0xff) continue; //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i); @@ -784,7 +886,7 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) } vpc->vp->sprite_fp_input = -1; - for(int i = 0; i < 8; ++i) + for(int i = 0; i < num_texcoords; ++i) { if(sem_layout[i] == 0xff) { @@ -793,7 +895,7 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) } } - tgsi_parse_init(&p, vpc->vp->pipe.tokens); + tgsi_parse_init(&p, vpc->pipe.tokens); while (!tgsi_parse_end_of_tokens(&p)) { const union tgsi_full_token *tok = &p.FullToken; @@ -814,14 +916,18 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) fdec->Range.Last; } break; -#if 0 /* this would be nice.. except gallium doesn't track it */ case TGSI_FILE_ADDRESS: if (fdec->Range.Last > high_addr) { high_addr = fdec->Range.Last; } break; -#endif + case TGSI_FILE_CONSTANT: + if (fdec->Range.Last > high_const) { + high_const = + fdec->Range.Last; + } + break; case TGSI_FILE_OUTPUT: if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec)) return FALSE; @@ -831,23 +937,6 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) } } break; -#if 1 /* yay, parse instructions looking for address regs instead */ - case TGSI_TOKEN_TYPE_INSTRUCTION: - { - const struct tgsi_full_instruction *finst; - const struct tgsi_full_dst_register *fdst; - - finst = &p.FullToken.FullInstruction; - fdst = &finst->Dst[0]; - - if (fdst->Register.File == TGSI_FILE_ADDRESS) { - if (fdst->Register.Index > high_addr) - high_addr = fdst->Register.Index; - } - - } - break; -#endif default: break; } @@ -868,7 +957,13 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) if (++high_addr) { vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg)); for (i = 0; i < high_addr; i++) - vpc->r_address[i] = temp(vpc); + vpc->r_address[i] = nvfx_reg(NVFXSR_TEMP, i); + } + + if(++high_const) { + vpc->r_const = CALLOC(high_const, sizeof(struct nvfx_reg)); + for (i = 0; i < high_const; i++) + vpc->r_const[i] = constant(vpc, i, 0, 0, 0, 0); } vpc->r_temps_discard = 0; @@ -877,21 +972,36 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE) -static void -nvfx_vertprog_translate(struct nvfx_context *nvfx, - struct nvfx_vertex_program *vp) +static struct nvfx_vertex_program* +nvfx_vertprog_translate(struct nvfx_context *nvfx, const struct pipe_shader_state* vps, const struct tgsi_shader_info* info) { struct tgsi_parse_context parse; + struct nvfx_vertex_program* vp = NULL; struct nvfx_vpc *vpc = NULL; struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct util_dynarray insns; int i; - vpc = CALLOC(1, sizeof(struct nvfx_vpc)); + tgsi_parse_init(&parse, vps->tokens); + + vp = CALLOC_STRUCT(nvfx_vertex_program); + if(!vp) + goto out_err; + + vpc = CALLOC_STRUCT(nvfx_vpc); if (!vpc) - return; + goto out_err; + vpc->nvfx = nvfx; vpc->vp = vp; + vpc->pipe = *vps; + vpc->info = info; + + { + // TODO: use a 64-bit atomic here! + static unsigned long long id = 0; + vp->id = ++id; + } /* reserve space for ucps */ if(nvfx->use_vp_clipping) @@ -902,7 +1012,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, if (!nvfx_vertprog_prepare(nvfx, vpc)) { FREE(vpc); - return; + return NULL; } /* Redirect post-transform vertex position to a temp if user clip @@ -915,8 +1025,6 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, vpc->r_temps_discard = 0; } - tgsi_parse_init(&parse, vp->pipe.tokens); - util_dynarray_init(&insns); while (!tgsi_parse_end_of_tokens(&parse)) { tgsi_parse_token(&parse); @@ -977,7 +1085,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, NVFX_VP(INST_DEST_POS)); struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]); - nvfx_vp_emit(vpc, arith(VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none)); } /* Insert code to handle user clip planes */ @@ -1003,22 +1111,14 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, else mask = NVFX_VP_MASK_X; - nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none)); + nvfx_vp_emit(vpc, arith(0, VEC, DP4, cdst, mask, htmp, ceqn, none)); } } - else - { - if(vp->nr_insns) - vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; - - nvfx_vp_emit(vpc, arith(VEC, NOP, none.reg, 0, none, none, none)); - vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; - } if(debug_get_option_nvfx_dump_vp()) { debug_printf("\n"); - tgsi_dump(vp->pipe.tokens, 0); + tgsi_dump(vpc->pipe.tokens, 0); debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x"); for (i = 0; i < vp->nr_insns; i++) @@ -1028,18 +1128,51 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, vp->clip_nr = -1; vp->exec_start = -1; - vp->translated = TRUE; -out_err: + +out: tgsi_parse_free(&parse); - util_dynarray_fini(&vpc->label_relocs); - util_dynarray_fini(&vpc->loop_stack); - if (vpc->r_temp) + if(vpc) { + util_dynarray_fini(&vpc->label_relocs); + util_dynarray_fini(&vpc->loop_stack); FREE(vpc->r_temp); - if (vpc->r_address) FREE(vpc->r_address); - if (vpc->imm) + FREE(vpc->r_const); FREE(vpc->imm); - FREE(vpc); + FREE(vpc); + } + return vp; + +out_err: + FREE(vp); + vp = NULL; + goto out; +} + +static struct nvfx_vertex_program* +nvfx_vertprog_translate_draw_vp(struct nvfx_context *nvfx, struct nvfx_pipe_vertex_program* pvp) +{ + struct nvfx_vertex_program* vp = NULL; + struct pipe_shader_state vps; + struct tgsi_shader_info info; + struct ureg_program *ureg = NULL; + unsigned num_outputs = MIN2(pvp->info.num_outputs, 16); + + ureg = ureg_create( TGSI_PROCESSOR_VERTEX ); + if(ureg == NULL) + return 0; + + for (unsigned i = 0; i < num_outputs; i++) + ureg_MOV(ureg, ureg_DECL_output(ureg, pvp->info.output_semantic_name[i], pvp->info.output_semantic_index[i]), ureg_DECL_vs_input(ureg, i)); + + ureg_END( ureg ); + + vps.tokens = ureg_get_tokens(ureg, 0); + tgsi_scan_shader(vps.tokens, &info); + vp = nvfx_vertprog_translate(nvfx, &vps, &info); + ureg_free_tokens(vps.tokens); + ureg_destroy(ureg); + + return vp; } boolean @@ -1047,31 +1180,44 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) { struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - struct nvfx_vertex_program *vp; + struct nvfx_pipe_vertex_program *pvp = nvfx->vertprog; + struct nvfx_vertex_program* vp; struct pipe_resource *constbuf; boolean upload_code = FALSE, upload_data = FALSE; int i; if (nvfx->render_mode == HW) { - vp = nvfx->vertprog; - constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX]; - } else { - vp = nvfx->swtnl.vertprog; - constbuf = NULL; - } - - /* Translate TGSI shader into hw bytecode */ - if (!vp->translated) - { nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG; - nvfx_vertprog_translate(nvfx, vp); - if (!vp->translated) { + vp = pvp->vp; + + if(!vp) { + vp = nvfx_vertprog_translate(nvfx, &pvp->pipe, &pvp->info); + if(!vp) + vp = NVFX_VP_FAILED; + pvp->vp = vp; + } + + if(vp == NVFX_VP_FAILED) { nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG; return FALSE; } + + constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX]; + } else { + vp = pvp->draw_vp; + if(!vp) + { + pvp->draw_vp = vp = nvfx_vertprog_translate_draw_vp(nvfx, pvp); + if(!vp) { + _debug_printf("Error: unable to create a swtnl passthrough vertex shader: aborting."); + abort(); + } + } + constbuf = NULL; } + nvfx->hw_vertprog = vp; + /* Allocate hw vtxprog exec slots */ if (!vp->exec) { struct nouveau_resource *heap = nvfx->screen->vp_exec_heap; @@ -1116,6 +1262,8 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) } } + //printf("start at %u nc %u\n", vp->data->start, vp->nr_consts); + /*XXX: handle this some day */ assert(vp->data->start >= vp->data_start_min); @@ -1161,6 +1309,8 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->const_relocs.data + i); struct nvfx_vertex_program_exec *vpi = &vp->insns[reloc->location]; + //printf("reloc %i to %i + %i\n", reloc->location, vp->data->start, reloc->target); + vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK); vpi->data[1] |= (reloc->target + vp->data->start) << @@ -1178,6 +1328,18 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) if (constbuf) map = (float*)nvfx_buffer(constbuf)->data; + /* + * WAIT_RING(chan, 512 * 6); + for (i = 0; i < 512; i++) { + float v[4] = {0.1, 0,2, 0.3, 0.4}; + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5)); + OUT_RING(chan, i); + OUT_RINGp(chan, (uint32_t *)v, 4); + printf("frob %i\n", i); + } + */ + + WAIT_RING(chan, 6 * vp->nr_consts); for (i = nvfx->use_vp_clipping ? 6 : 0; i < vp->nr_consts; i++) { struct nvfx_vertex_program_data *vpd = &vp->consts[i]; @@ -1190,19 +1352,23 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) 4 * sizeof(float)); } - BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5); - OUT_RING (chan, i + vp->data->start); - OUT_RINGp (chan, (uint32_t *)vpd->value, 4); + //printf("upload into %i + %i: %f %f %f %f\n", vp->data->start, i, vpd->value[0], vpd->value[1], vpd->value[2], vpd->value[3]); + + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5)); + OUT_RING(chan, i + vp->data->start); + OUT_RINGp(chan, (uint32_t *)vpd->value, 4); } } /* Upload vtxprog */ if (upload_code) { - BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1); - OUT_RING (chan, vp->exec->start); + WAIT_RING(chan, 2 + 5 * vp->nr_insns); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1)); + OUT_RING(chan, vp->exec->start); for (i = 0; i < vp->nr_insns; i++) { - BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4); - OUT_RINGp (chan, vp->insns[i].data, 4); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4)); + //printf("%08x %08x %08x %08x\n", vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]); + OUT_RINGp(chan, vp->insns[i].data, 4); } vp->clip_nr = -1; } @@ -1210,10 +1376,10 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) if(nvfx->dirty & (NVFX_NEW_VERTPROG)) { WAIT_RING(chan, 6); - OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VP_START_FROM_ID, 1)); OUT_RING(chan, vp->exec->start); if(nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 1)); + OUT_RING(chan, RING_3D(NV40_3D_VP_ATTRIB_EN, 1)); OUT_RING(chan, vp->ir); } } @@ -1235,24 +1401,21 @@ nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp) util_dynarray_fini(&vp->branch_relocs); util_dynarray_fini(&vp->const_relocs); + FREE(vp); } static void * -nvfx_vp_state_create(struct pipe_context *pipe, - const struct pipe_shader_state *cso) +nvfx_vp_state_create(struct pipe_context *pipe, const struct pipe_shader_state *cso) { - struct nvfx_context *nvfx = nvfx_context(pipe); - struct nvfx_vertex_program *vp; + struct nvfx_pipe_vertex_program *pvp; - // TODO: use a 64-bit atomic here! - static unsigned long long id = 0; + pvp = CALLOC(1, sizeof(struct nvfx_pipe_vertex_program)); + pvp->pipe.tokens = tgsi_dup_tokens(cso->tokens); + tgsi_scan_shader(pvp->pipe.tokens, &pvp->info); + pvp->draw_elements = MAX2(1, MIN2(pvp->info.num_outputs, 16)); + pvp->draw_no_elements = pvp->info.num_outputs == 0; - vp = CALLOC(1, sizeof(struct nvfx_vertex_program)); - vp->pipe.tokens = tgsi_dup_tokens(cso->tokens); - vp->draw = draw_create_vertex_shader(nvfx->draw, &vp->pipe); - vp->id = ++id; - - return (void *)vp; + return (void *)pvp; } static void @@ -1268,13 +1431,17 @@ nvfx_vp_state_bind(struct pipe_context *pipe, void *hwcso) static void nvfx_vp_state_delete(struct pipe_context *pipe, void *hwcso) { - struct nvfx_context *nvfx = nvfx_context(pipe); - struct nvfx_vertex_program *vp = hwcso; - - draw_delete_vertex_shader(nvfx->draw, vp->draw); - nvfx_vertprog_destroy(nvfx, vp); - FREE((void*)vp->pipe.tokens); - FREE(vp); + struct nvfx_context *nvfx = nvfx_context(pipe); + struct nvfx_pipe_vertex_program *pvp = hwcso; + + if(pvp->draw_vs) + draw_delete_vertex_shader(nvfx->draw, pvp->draw_vs); + if(pvp->vp && pvp->vp != NVFX_VP_FAILED) + nvfx_vertprog_destroy(nvfx, pvp->vp); + if(pvp->draw_vp) + nvfx_vertprog_destroy(nvfx, pvp->draw_vp); + FREE((void*)pvp->pipe.tokens); + FREE(pvp); } void |