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path: root/src/gallium/drivers/r300/r300_render.c
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Diffstat (limited to 'src/gallium/drivers/r300/r300_render.c')
-rw-r--r--src/gallium/drivers/r300/r300_render.c189
1 files changed, 166 insertions, 23 deletions
diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index ee43421cdb..cd4971ae13 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -26,8 +26,9 @@
#include "draw/draw_context.h"
#include "draw/draw_vbuf.h"
-#include "pipe/p_inlines.h"
+#include "util/u_inlines.h"
+#include "util/u_format.h"
#include "util/u_memory.h"
#include "util/u_prim.h"
@@ -114,6 +115,97 @@ static uint32_t r300_provoking_vertex_fixes(struct r300_context *r300,
return color_control;
}
+static boolean immd_is_good_idea(struct r300_context *r300,
+ unsigned count)
+{
+ return count <= 4;
+}
+
+static void r300_emit_draw_arrays_immediate(struct r300_context *r300,
+ unsigned mode,
+ unsigned start,
+ unsigned count)
+{
+ struct pipe_vertex_element* velem;
+ struct pipe_vertex_buffer* vbuf;
+ unsigned vertex_element_count = r300->vertex_element_count;
+ unsigned i, v, vbi, dw, elem_offset;
+
+ /* Size of the vertex, in dwords. */
+ unsigned vertex_size = 0;
+
+ /* Offsets of the attribute, in dwords, from the start of the vertex. */
+ unsigned offset[PIPE_MAX_ATTRIBS];
+
+ /* Size of the vertex element, in dwords. */
+ unsigned size[PIPE_MAX_ATTRIBS];
+
+ /* Stride to the same attrib in the next vertex in the vertex buffer,
+ * in dwords. */
+ unsigned stride[PIPE_MAX_ATTRIBS] = {0};
+
+ /* Mapped vertex buffers. */
+ uint32_t* map[PIPE_MAX_ATTRIBS] = {0};
+
+ CS_LOCALS(r300);
+
+ /* Calculate the vertex size, offsets, strides etc. and map the buffers. */
+ for (i = 0; i < vertex_element_count; i++) {
+ velem = &r300->vertex_element[i];
+ offset[i] = velem->src_offset / 4;
+ size[i] = util_format_get_blocksize(velem->src_format) / 4;
+ vertex_size += size[i];
+ vbi = velem->vertex_buffer_index;
+
+ /* Map the buffer. */
+ if (!map[vbi]) {
+ vbuf = &r300->vertex_buffer[vbi];
+ map[vbi] = (uint32_t*)pipe_buffer_map(r300->context.screen,
+ vbuf->buffer,
+ PIPE_BUFFER_USAGE_CPU_READ);
+ map[vbi] += vbuf->buffer_offset / 4;
+ stride[vbi] = vbuf->stride / 4;
+ }
+ }
+
+ r300_emit_dirty_state(r300);
+
+ BEGIN_CS(10 + count * vertex_size);
+ OUT_CS_REG(R300_GA_COLOR_CONTROL,
+ r300_provoking_vertex_fixes(r300, mode));
+ OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_size);
+ OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0);
+ OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, count - 1);
+ OUT_CS_PKT3(R300_PACKET3_3D_DRAW_IMMD_2, count * vertex_size);
+ OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED | (count << 16) |
+ r300_translate_primitive(mode));
+
+ /* Emit vertices. */
+ for (v = 0; v < count; v++) {
+ for (i = 0; i < vertex_element_count; i++) {
+ velem = &r300->vertex_element[i];
+ vbi = velem->vertex_buffer_index;
+ elem_offset = offset[i] + stride[vbi] * (v + start);
+
+ for (dw = 0; dw < size[i]; dw++) {
+ OUT_CS(map[vbi][elem_offset + dw]);
+ }
+ }
+ }
+ END_CS;
+
+ /* Unmap buffers. */
+ for (i = 0; i < vertex_element_count; i++) {
+ vbi = r300->vertex_element[i].vertex_buffer_index;
+
+ if (map[vbi]) {
+ vbuf = &r300->vertex_buffer[vbi];
+ pipe_buffer_unmap(r300->context.screen, vbuf->buffer);
+ map[vbi] = NULL;
+ }
+ }
+}
+
static void r300_emit_draw_arrays(struct r300_context *r300,
unsigned mode,
unsigned count)
@@ -183,17 +275,18 @@ static void r300_emit_draw_elements(struct r300_context *r300,
END_CS;
}
-
static boolean r300_setup_vertex_buffers(struct r300_context *r300)
{
struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
struct pipe_vertex_element *velem = r300->vertex_element;
+ struct pipe_buffer *pbuf;
validate:
for (int i = 0; i < r300->vertex_element_count; i++) {
- if (!r300->winsys->add_buffer(r300->winsys,
- vbuf[velem[i].vertex_buffer_index].buffer,
- RADEON_GEM_DOMAIN_GTT, 0)) {
+ pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
+
+ if (!r300->winsys->add_buffer(r300->winsys, pbuf,
+ RADEON_GEM_DOMAIN_GTT, 0)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
@@ -207,17 +300,49 @@ validate:
return TRUE;
}
+static void r300_shorten_ubyte_elts(struct r300_context* r300,
+ struct pipe_buffer** elts,
+ unsigned count)
+{
+ struct pipe_screen* screen = r300->context.screen;
+ struct pipe_buffer* new_elts;
+ unsigned char *in_map;
+ unsigned short *out_map;
+ unsigned i;
+
+ new_elts = screen->buffer_create(screen, 32,
+ PIPE_BUFFER_USAGE_INDEX |
+ PIPE_BUFFER_USAGE_CPU_WRITE |
+ PIPE_BUFFER_USAGE_GPU_READ,
+ 2 * count);
+
+ in_map = pipe_buffer_map(screen, *elts, PIPE_BUFFER_USAGE_CPU_READ);
+ out_map = pipe_buffer_map(screen, new_elts, PIPE_BUFFER_USAGE_CPU_WRITE);
+
+ for (i = 0; i < count; i++) {
+ *out_map = (unsigned short)*in_map;
+ in_map++;
+ out_map++;
+ }
+
+ pipe_buffer_unmap(screen, *elts);
+ pipe_buffer_unmap(screen, new_elts);
+
+ *elts = new_elts;
+}
+
/* This is the fast-path drawing & emission for HW TCL. */
void r300_draw_range_elements(struct pipe_context* pipe,
- struct pipe_buffer* indexBuffer,
- unsigned indexSize,
- unsigned minIndex,
- unsigned maxIndex,
- unsigned mode,
- unsigned start,
- unsigned count)
+ struct pipe_buffer* indexBuffer,
+ unsigned indexSize,
+ unsigned minIndex,
+ unsigned maxIndex,
+ unsigned mode,
+ unsigned start,
+ unsigned count)
{
struct r300_context* r300 = r300_context(pipe);
+ struct pipe_buffer* orgIndexBuffer = indexBuffer;
if (!u_trim_pipe_prim(mode, &count)) {
return;
@@ -232,17 +357,24 @@ void r300_draw_range_elements(struct pipe_context* pipe,
r300_update_derived_state(r300);
+ r300_emit_buffer_validate(r300);
+
if (!r300_setup_vertex_buffers(r300)) {
return;
}
+ if (indexSize == 1) {
+ r300_shorten_ubyte_elts(r300, &indexBuffer, count);
+ indexSize = 2;
+ }
+
if (!r300->winsys->add_buffer(r300->winsys, indexBuffer,
RADEON_GEM_DOMAIN_GTT, 0)) {
- return;
+ goto cleanup;
}
if (!r300->winsys->validate(r300->winsys)) {
- return;
+ goto cleanup;
}
r300_emit_dirty_state(r300);
@@ -251,6 +383,11 @@ void r300_draw_range_elements(struct pipe_context* pipe,
r300_emit_draw_elements(r300, indexBuffer, indexSize, minIndex, maxIndex,
mode, start, count);
+
+cleanup:
+ if (indexBuffer != orgIndexBuffer) {
+ pipe->screen->buffer_destroy(indexBuffer);
+ }
}
/* Simple helpers for context setup. Should probably be moved to util. */
@@ -264,7 +401,7 @@ void r300_draw_elements(struct pipe_context* pipe,
}
void r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
- unsigned start, unsigned count)
+ unsigned start, unsigned count)
{
struct r300_context* r300 = r300_context(pipe);
@@ -281,15 +418,19 @@ void r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
r300_update_derived_state(r300);
- if (!r300_setup_vertex_buffers(r300)) {
- return;
- }
-
- r300_emit_dirty_state(r300);
+ r300_emit_buffer_validate(r300);
- r300_emit_aos(r300, start);
+ if (immd_is_good_idea(r300, count)) {
+ r300_emit_draw_arrays_immediate(r300, mode, start, count);
+ } else {
+ if (!r300_setup_vertex_buffers(r300)) {
+ return;
+ }
- r300_emit_draw_arrays(r300, mode, count);
+ r300_emit_dirty_state(r300);
+ r300_emit_aos(r300, start);
+ r300_emit_draw_arrays(r300, mode, count);
+ }
}
/****************************************************************************
@@ -321,6 +462,7 @@ void r300_swtcl_draw_arrays(struct pipe_context* pipe,
draw_set_mapped_constant_buffer(r300->draw,
PIPE_SHADER_VERTEX,
+ 0,
r300->shader_constants[PIPE_SHADER_VERTEX].constants,
r300->shader_constants[PIPE_SHADER_VERTEX].count *
(sizeof(float) * 4));
@@ -365,6 +507,7 @@ void r300_swtcl_draw_range_elements(struct pipe_context* pipe,
draw_set_mapped_constant_buffer(r300->draw,
PIPE_SHADER_VERTEX,
+ 0,
r300->shader_constants[PIPE_SHADER_VERTEX].constants,
r300->shader_constants[PIPE_SHADER_VERTEX].count *
(sizeof(float) * 4));
@@ -416,7 +559,7 @@ r300_render_get_vertex_info(struct vbuf_render* render)
r300_update_derived_state(r300);
- return &r300->vertex_info->vinfo;
+ return (struct vertex_info*)r300->vertex_format_state.state;
}
static boolean r300_render_allocate_vertices(struct vbuf_render* render,
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-09 07:44:54 +0000