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path: root/src/gallium/drivers/r600/r600_asm.c
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Diffstat (limited to 'src/gallium/drivers/r600/r600_asm.c')
-rw-r--r--src/gallium/drivers/r600/r600_asm.c117
1 files changed, 96 insertions, 21 deletions
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index d13da0ef63..ba1471eb78 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -23,6 +23,7 @@
#include <stdio.h>
#include <errno.h>
#include "util/u_memory.h"
+#include "pipe/p_shader_tokens.h"
#include "r600_pipe.h"
#include "r600_sq.h"
#include "r600_opcodes.h"
@@ -55,8 +56,8 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
- return 2;
-
+ return 2;
+
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
@@ -74,7 +75,7 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
};
-
+
return 3;
}
@@ -137,20 +138,20 @@ int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
case CHIP_RV635:
case CHIP_RS780:
case CHIP_RS880:
- bc->chiprev = 0;
+ bc->chiprev = CHIPREV_R600;
break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
case CHIP_RV740:
- bc->chiprev = 1;
+ bc->chiprev = CHIPREV_R700;
break;
case CHIP_CEDAR:
case CHIP_REDWOOD:
case CHIP_JUNIPER:
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
- bc->chiprev = 2;
+ bc->chiprev = CHIPREV_EVERGREEN;
break;
default:
R600_ERR("unknown family %d\n", bc->family);
@@ -199,9 +200,9 @@ const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
SQ_ALU_VEC_012}; //111
const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
- SQ_ALU_SCL_122, //001
+ SQ_ALU_SCL_122, //001
SQ_ALU_SCL_122, //010
-
+
SQ_ALU_SCL_221, //011
SQ_ALU_SCL_212, //100
SQ_ALU_SCL_122, //101
@@ -592,10 +593,34 @@ int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
/* common to all 3 families */
static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
{
- bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
- S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
- S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
- S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
+ unsigned fetch_resource_start = 0;
+
+ /* check if we are fetch shader */
+ /* fetch shader can also access vertex resource,
+ * first fetch shader resource is at 160
+ */
+ if (bc->type == -1) {
+ switch (bc->chiprev) {
+ /* r600 */
+ case CHIPREV_R600:
+ /* r700 */
+ case CHIPREV_R700:
+ fetch_resource_start = 160;
+ break;
+ /* evergreen */
+ case CHIPREV_EVERGREEN:
+ fetch_resource_start = 0;
+ break;
+ default:
+ fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
+ __FILE__, __func__, __LINE__, bc->chiprev);
+ break;
+ }
+ }
+ bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
+ S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
+ S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
+ S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
@@ -678,8 +703,8 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
- S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
- S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
+ S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
+ S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
}
if (alu->last) {
if (alu->nliteral && !alu->literal_added) {
@@ -701,11 +726,16 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
- S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
+ S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode) |
+ S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache0_bank) |
+ S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache1_bank);
bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
+ S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache1_mode) |
+ S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache0_addr) |
+ S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache1_addr) |
S_SQ_CF_ALU_WORD1_BARRIER(1) |
- S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == 0 ? cf->r6xx_uses_waterfall : 0) |
+ S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
break;
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
@@ -737,6 +767,8 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
S_SQ_CF_WORD1_BARRIER(1) |
@@ -761,7 +793,10 @@ int r600_bc_build(struct r600_bc *bc)
int r;
if (bc->callstack[0].max > 0)
- bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
+ bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
+ if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
+ bc->nstack = 1;
+ }
/* first path compute addr of each CF block */
/* addr start after all the CF instructions */
@@ -790,6 +825,8 @@ int r600_bc_build(struct r600_bc *bc)
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
@@ -805,7 +842,7 @@ int r600_bc_build(struct r600_bc *bc)
return -ENOMEM;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
addr = cf->addr;
- if (bc->chiprev == 2)
+ if (bc->chiprev == CHIPREV_EVERGREEN)
r = eg_bc_cf_build(bc, cf);
else
r = r600_bc_cf_build(bc, cf);
@@ -816,11 +853,11 @@ int r600_bc_build(struct r600_bc *bc)
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
switch(bc->chiprev) {
- case 0:
+ case CHIPREV_R600:
r = r600_bc_alu_build(bc, alu, addr);
break;
- case 1:
- case 2: /* eg alu is same encoding as r700 */
+ case CHIPREV_R700:
+ case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
r = r700_bc_alu_build(bc, alu, addr);
break;
default:
@@ -863,6 +900,8 @@ int r600_bc_build(struct r600_bc *bc)
case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
@@ -871,3 +910,39 @@ int r600_bc_build(struct r600_bc *bc)
}
return 0;
}
+
+void r600_bc_clear(struct r600_bc *bc)
+{
+ struct r600_bc_cf *cf = NULL, *next_cf;
+
+ free(bc->bytecode);
+ bc->bytecode = NULL;
+
+ LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
+ struct r600_bc_alu *alu = NULL, *next_alu;
+ struct r600_bc_tex *tex = NULL, *next_tex;
+ struct r600_bc_tex *vtx = NULL, *next_vtx;
+
+ LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
+ free(alu);
+ }
+
+ LIST_INITHEAD(&cf->alu);
+
+ LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
+ free(tex);
+ }
+
+ LIST_INITHEAD(&cf->tex);
+
+ LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
+ free(vtx);
+ }
+
+ LIST_INITHEAD(&cf->vtx);
+
+ free(cf);
+ }
+
+ LIST_INITHEAD(&cf->list);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-01 05:12:23 +0000