diff options
Diffstat (limited to 'src/gallium/drivers/r600/r600_hw_states.c')
| -rw-r--r-- | src/gallium/drivers/r600/r600_hw_states.c | 252 |
1 files changed, 159 insertions, 93 deletions
diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c index bca78ee8de..271bd1ac50 100644 --- a/src/gallium/drivers/r600/r600_hw_states.c +++ b/src/gallium/drivers/r600/r600_hw_states.c @@ -197,7 +197,7 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta float offset_units = 0, offset_scale = 0; char depth = 0; unsigned offset_db_fmt_cntl = 0; - unsigned tmp; + unsigned point_size; unsigned prov_vtx = 1; if (rctx->clip) @@ -232,7 +232,8 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta rctx->flat_shade = state->flatshade; radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0); - rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; + rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = + S_0286D4_FLAT_SHADE_ENA(1); if (state->sprite_coord_enable) { rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_PNT_SPRITE_ENA(1) | @@ -247,9 +248,18 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta } rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0; if (clip) { - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1); - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp); - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp); + /* Clip plane enable bits are stashed in the lower six bits of + * PA_CL_CLIP_CNTL, so just set all of the corresponding bits with a + * pinch of bit twiddling. + * + * PS_UCP_MODE 3 is "expand and clip as trifan," which is the same + * setting that we use on r300-r500. I believe that fglrx always uses + * this mode as well. */ + rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = + ((1 << clip->nr) - 1) | + S_028810_PS_UCP_MODE(3) | + S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp) | + S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp); } rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = S_028814_PROVOKING_VTX_LAST(prov_vtx) | @@ -263,18 +273,24 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; - /* point size 12.4 fixed point */ - tmp = (unsigned)(state->point_size * 8.0); - rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp); - rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000; - rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; + /* Point size for PA_SU_POINT_SIZE and PA_SU_POINT_MINMAX is fixed-point, + * 12.4. + * + * For some reason, maximum point size is set to 0x8000 (2048.0) instead + * of the maximum value 0xFFF0 (4095.0). */ + point_size = (unsigned)(state->point_size * 8.0); + rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = + S_028A00_HEIGHT(point_size) | S_028A00_WIDTH(point_size); + rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = + S_028A04_MIN_SIZE(0) | S_028A04_MAX_SIZE(0x8000); + rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = S_028A08_WIDTH(8); rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; - rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; - rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = S_028C00_LAST_PIXEL(1); + rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = fui(1); + rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = fui(1); + rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = fui(1); + rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = fui(1); rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl; rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale); @@ -314,7 +330,8 @@ static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate) rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = + S_02820C_CLIP_RULE(0xFFFF); rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; @@ -339,15 +356,22 @@ static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate struct r600_screen *rscreen = rctx->screen; radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0); - rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; - rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = fui(0); + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = fui(1); rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]); rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]); rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]); rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]); rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]); rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]); - rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; + rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = + S_028818_VPORT_X_SCALE_ENA(1) | + S_028818_VPORT_X_OFFSET_ENA(1) | + S_028818_VPORT_Y_SCALE_ENA(1) | + S_028818_VPORT_Y_OFFSET_ENA(1) | + S_028818_VPORT_Z_SCALE_ENA(1) | + S_028818_VPORT_Z_OFFSET_ENA(1) | + S_028818_VTX_W0_FMT(1); radeon_state_pm4(rstate); } @@ -368,9 +392,8 @@ static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate) } radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0); - db_shader_control = 0; - db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1); - db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); + db_shader_control = S_02880C_DUAL_EXPORT_ENABLE(1) | + S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); rshader = &rctx->ps_shader->shader; if (rshader->uses_kill) @@ -384,35 +407,37 @@ static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate) db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func); - /* set stencil enable */ + /* set stencil enable */ if (state->stencil[0].enabled) { - db_depth_control |= S_028800_STENCIL_ENABLE(1); - db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); - db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); - db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); - db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); + db_depth_control |= S_028800_STENCIL_ENABLE(1) | + S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)) | + S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)) | + S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)) | + S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | - S_028430_STENCILWRITEMASK(state->stencil[0].writemask); - stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]); + S_028430_STENCILWRITEMASK(state->stencil[0].writemask) | + S_028430_STENCILREF(stencil_ref->ref_value[0]); + if (state->stencil[1].enabled) { - db_depth_control |= S_028800_BACKFACE_ENABLE(1); - db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); - db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); - db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); - db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); - stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | - S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); - stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]); + db_depth_control |= S_028800_BACKFACE_ENABLE(1) | + S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)) | + S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)) | + S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)) | + S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); + stencil_ref_mask_bf = + S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | + S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask) | + S_028430_STENCILREF(stencil_ref->ref_value[1]); } } alpha_test_control = 0; alpha_ref = 0; if (state->alpha.enabled) { - alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); - alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); + alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func) | + S_028410_ALPHA_TEST_ENABLE(1); alpha_ref = fui(state->alpha.ref_value); } @@ -422,22 +447,22 @@ static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate) S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); - query_running = false; + query_running = FALSE; LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) { if (rquery->state & R600_QUERY_STATE_STARTED) { - query_running = true; + query_running = TRUE; } } if (query_running) { db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); - if (rscreen->chip_class == R700) + if (radeon_get_family_class(rscreen->rw) == R700) db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); } rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; - rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; + rstate->states[R600_DSA__DB_DEPTH_CLEAR] = fui(1); rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control; rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask; rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf; @@ -515,7 +540,7 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, struct r600_context *rctx = r600_context(ctx); struct r600_screen *rscreen = rctx->screen; const struct util_format_description *desc; - struct r600_resource_texture *tmp; + struct r600_resource_texture *texture; struct r600_resource *rbuffer; unsigned format; uint32_t word4 = 0, yuv_format = 0, pitch = 0; @@ -539,15 +564,15 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, return; } radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS); - tmp = (struct r600_resource_texture*)view->texture; - rbuffer = &tmp->resource; - if (tmp->depth) { - r = r600_texture_from_depth(ctx, tmp, view->first_level); + texture = (struct r600_resource_texture*)view->texture; + rbuffer = &texture->resource; + if (texture->depth) { + r = r600_texture_from_depth(ctx, texture, view->first_level); if (r) { return; } - radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed); - radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed); + radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], texture->uncompressed); + radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], texture->uncompressed); } else { radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo); radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo); @@ -558,8 +583,7 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; - pitch = (tmp->pitch[0] / tmp->bpt); - pitch = (pitch + 0x7) & ~0x7; + pitch = align(texture->pitch[0] / texture->bpt, 8); /* FIXME properly handle first level != 0 */ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = @@ -572,8 +596,8 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, S_038004_TEX_HEIGHT(view->texture->height0 - 1) | S_038004_TEX_DEPTH(view->texture->depth0 - 1) | S_038004_DATA_FORMAT(format); - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8; - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = texture->offset[0] >> 8; + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = texture->offset[1] >> 8; rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | @@ -594,15 +618,17 @@ static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate) struct r600_screen *rscreen = rctx->screen; const struct pipe_blend_state *pbs = &rctx->blend->state.blend; int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs; - uint32_t color_control, target_mask, shader_mask; + uint32_t color_control, target_mask, shader_mask, shader_control; int i; target_mask = 0; shader_mask = 0; + shader_control = 0; color_control = S_028808_PER_MRT_BLEND(1); for (i = 0; i < nr_cbufs; i++) { shader_mask |= 0xf << (i * 4); + shader_control |= (1 << i); } if (pbs->logicop_enable) { @@ -630,6 +656,8 @@ static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate) rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask; rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask; rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control; + if (radeon_get_family_class(rscreen->rw) == R700) + rstate->states[R600_CB_CNTL__CB_SHADER_CONTROL] = shader_control; rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000; rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000; rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000; @@ -831,21 +859,35 @@ static void r600_init_config(struct r600_context *rctx) rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000; if (family >= CHIP_RV770) { - rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000; + rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = + S_008D8C_VS_PC_LIMIT_ENABLE(1); rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002; rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000; - rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204; + rctx->config.states[R600_CONFIG__DB_WATERMARKS] = + S_009838_DEPTH_FREE(4) | + S_009838_DEPTH_FLUSH(16) | + S_009838_DEPTH_PENDING_FREE(4) | + S_009838_DEPTH_CACHELINE_FREE(4); rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000; - rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000; + rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00500000 | + S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | + S_028A4C_FORCE_EOV_REZ_ENABLE(1); } else { rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000; - rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003; + rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002 | + S_009508_DISABLE_CUBE_WRAP(1); rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000; - rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204; - rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001; - rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010; + rctx->config.states[R600_CONFIG__DB_WATERMARKS] = + S_009838_DEPTH_FREE(4) | + S_009838_DEPTH_FLUSH(16) | + S_009838_DEPTH_PENDING_FREE(4) | + S_009838_DEPTH_CACHELINE_FREE(16); + rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = + S_0286C8_PS_GROUPING(1); + rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = + S_028A4C_WALK_ORDER_ENABLE(1) | + S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); } - rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003; rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000; rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000; rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000; @@ -869,7 +911,7 @@ static void r600_init_config(struct r600_context *rctx) rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000; rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000; rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001; + rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = S_028AB4_REUSE_OFF(1); rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000; rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000; radeon_state_pm4(&rctx->config); @@ -943,21 +985,24 @@ static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state * const struct pipe_rasterizer_state *rasterizer; struct r600_shader *rshader = &rpshader->shader; unsigned i, tmp, exports_ps, num_cout; - boolean have_pos = FALSE; + boolean have_pos = FALSE, have_face = FALSE; rasterizer = &rctx->rasterizer->state.rasterizer; radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS); for (i = 0; i < rshader->ninput; i++) { - tmp = S_028644_SEMANTIC(i); - tmp |= S_028644_SEL_CENTROID(1); + tmp = S_028644_SEMANTIC(i) | S_028644_SEL_CENTROID(1); if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) have_pos = TRUE; if (rshader->input[i].name == TGSI_SEMANTIC_COLOR || - rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || - rshader->input[i].name == TGSI_SEMANTIC_POSITION) { + rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || + rshader->input[i].name == TGSI_SEMANTIC_POSITION) { tmp |= S_028644_FLAT_SHADE(rshader->flat_shade); } + + if (rshader->input[i].name == TGSI_SEMANTIC_FACE) + have_face = TRUE; + if (rasterizer->sprite_coord_enable & (1 << i)) { tmp |= S_028644_PT_SPRITE_TEX(1); } @@ -968,25 +1013,33 @@ static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state * num_cout = 0; for (i = 0; i < rshader->noutput; i++) { if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) - exports_ps |= 1; + exports_ps |= S_028854_EXPORT_Z(1); else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { - exports_ps |= (1 << (num_cout+1)); num_cout++; } } - if (!exports_ps) { - /* always at least export 1 component per pixel */ - exports_ps = 2; + exports_ps |= S_028854_EXPORT_COLORS(num_cout); + if (exports_ps == 0) { + /* Always at least export 1 color component per pixel. */ + exports_ps = S_028854_EXPORT_COLORS(1); } - state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) | - S_0286CC_PERSP_GRADIENT_ENA(1); + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = + S_0286CC_NUM_INTERP(rshader->ninput) | + S_0286CC_PERSP_GRADIENT_ENA(1); + if (have_pos) { - state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1) | - S_0286CC_BARYC_SAMPLE_CNTL(1); - state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1; + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= + S_0286CC_POSITION_ENA(1) | + S_0286CC_BARYC_SAMPLE_CNTL(1); + state->states[R600_PS_SHADER__SPI_INPUT_Z] |= + S_0286D8_PROVIDE_Z_TO_SPI(1); } - state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000; - state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) | + + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = + S_0286D0_FRONT_FACE_ENA(have_face); + + state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = + S_028868_NUM_GPRS(rshader->bc.ngpr) | S_028868_STACK_SIZE(rshader->bc.nstack); state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps; radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo); @@ -1011,8 +1064,10 @@ static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state * tmp = i << ((i & 3) * 8); state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp; } - state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2); - state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) | + state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = + S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2); + state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = + S_028868_NUM_GPRS(rshader->bc.ngpr) | S_028868_STACK_SIZE(rshader->bc.nstack); radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo); radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo); @@ -1151,20 +1206,31 @@ static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resou static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level) { struct radeon_state *rstate = &rtexture->viewport[level]; + float width, height; radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0); + width = rtexture->width[level] * 0.5; + height = rtexture->height[level] * 0.5; + /* set states (most default value are 0 and struct already * initialized to 0, thus avoid resetting them) */ - rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000; - rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000; - rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; - rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; + rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(width); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(width); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(height); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(height); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(0.5); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(0.5); + rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = + S_028818_VPORT_X_SCALE_ENA(1) | + S_028818_VPORT_X_OFFSET_ENA(1) | + S_028818_VPORT_Y_SCALE_ENA(1) | + S_028818_VPORT_Y_OFFSET_ENA(1) | + S_028818_VPORT_Z_SCALE_ENA(1) | + S_028818_VPORT_Z_OFFSET_ENA(1) | + S_028818_VTX_W0_FMT(1); + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = fui(1); radeon_state_pm4(rstate); } @@ -1272,7 +1338,7 @@ void r600_set_constant_buffer_mem(struct pipe_context *ctx, nconstant = buffer->width0 / 16; size = ALIGN_DIVUP(nconstant, 16); - + radeon_state_init(rstate, rscreen->rw, type, 0, shader_class); rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size; rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0; |