1 files changed, 208 insertions, 34 deletions

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 4ebd5b754b..8ecd434a43 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -31,6 +31,7 @@
 #include <util/u_inlines.h>
 #include <util/u_memory.h>
 #include "state_tracker/drm_driver.h"
+#include "pipebuffer/pb_buffer.h"
 #include "r600_pipe.h"
 #include "r600_resource.h"
 #include "r600_state_inlines.h"
@@ -39,8 +40,8 @@
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
-/* Copy from a tiled texture to a detiled one. */
-static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+/* Copy from a full GPU texture to a transfer's staging one. */
+static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
 {
 	struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
 	struct pipe_resource *texture = transfer->resource;
@@ -48,15 +49,15 @@ static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_t
 
 	subdst.face = 0;
 	subdst.level = 0;
-	ctx->resource_copy_region(ctx, rtransfer->linear_texture,
+	ctx->resource_copy_region(ctx, rtransfer->staging_texture,
 				subdst, 0, 0, 0, texture, transfer->sr,
 				transfer->box.x, transfer->box.y, transfer->box.z,
 				transfer->box.width, transfer->box.height);
 }
 
 
-/* Copy from a detiled texture to a tiled one. */
-static void r600_copy_into_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+/* Copy from a transfer's staging texture to a full GPU one. */
+static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
 {
 	struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
 	struct pipe_resource *texture = transfer->resource;
@@ -66,7 +67,7 @@ static void r600_copy_into_tiled_texture(struct pipe_context *ctx, struct r600_t
 	subsrc.level = 0;
 	ctx->resource_copy_region(ctx, texture, transfer->sr,
 				  transfer->box.x, transfer->box.y, transfer->box.z,
-				  rtransfer->linear_texture, subsrc,
+				  rtransfer->staging_texture, subsrc,
 				  0, 0, 0,
 				  transfer->box.width, transfer->box.height);
 
@@ -108,11 +109,11 @@ static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
 	case V_038000_ARRAY_2D_TILED_THIN1:
 		p_align = MAX2(rscreen->tiling_info->num_banks,
 			       (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
-				rscreen->tiling_info->num_banks));
+				rscreen->tiling_info->num_banks)) * 8;
 		break;
-	case 0:
+	case V_038000_ARRAY_LINEAR_GENERAL:
 	default:
-		p_align = 64;
+		p_align = rscreen->tiling_info->group_bytes / pixsize;
 		break;
 	}
 	return p_align;
@@ -138,6 +139,29 @@ static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 	return h_align;
 }
 
+static unsigned r600_get_base_alignment(struct pipe_screen *screen,
+					enum pipe_format format,
+					unsigned array_mode)
+{
+	struct r600_screen* rscreen = (struct r600_screen *)screen;
+	unsigned pixsize = util_format_get_blocksize(format);
+	int p_align = r600_get_pixel_alignment(screen, format, array_mode);
+	int h_align = r600_get_height_alignment(screen, array_mode);
+	int b_align;
+
+	switch (array_mode) {
+	case V_038000_ARRAY_2D_TILED_THIN1:
+		b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
+			       p_align * pixsize * h_align);
+		break;
+	case V_038000_ARRAY_1D_TILED_THIN1:
+	default:
+		b_align = rscreen->tiling_info->group_bytes;
+		break;
+	}
+	return b_align;
+}
+
 static unsigned mip_minify(unsigned size, unsigned level)
 {
 	unsigned val;
@@ -151,11 +175,12 @@ static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 					struct r600_resource_texture *rtex,
 					unsigned level)
 {
+	struct r600_screen* rscreen = (struct r600_screen *)screen;
 	struct pipe_resource *ptex = &rtex->resource.base.b;
 	struct radeon *radeon = (struct radeon *)screen->winsys;
 	enum chip_class chipc = r600_get_family_class(radeon);
 	unsigned width, stride, tile_width;
-	
+
 	if (rtex->pitch_override)
 		return rtex->pitch_override;
 
@@ -166,8 +191,7 @@ static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 		width = align(width, tile_width);
 	}
 	stride = util_format_get_stride(ptex->format, width);
-	if (chipc == EVERGREEN)
-		stride = align(stride, 512);
+
 	return stride;
 }
 
@@ -252,6 +276,9 @@ static void r600_setup_miptree(struct pipe_screen *screen,
 		}
 		else
 			size = layer_size * u_minify(ptex->depth0, i);
+		/* align base image and start of miptree */
+		if ((i == 0) || (i == 1))
+			offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 		rtex->offset[i] = offset;
 		rtex->layer_size[i] = layer_size;
 		rtex->pitch_in_bytes[i] = pitch;
@@ -283,7 +310,6 @@ r600_texture_create_object(struct pipe_screen *screen,
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
 	resource->bo = bo;
-	resource->domain = r600_domain_from_usage(resource->base.b.bind);
 	rtex->pitch_override = pitch_in_bytes_override;
 
 	if (array_mode)
@@ -293,7 +319,10 @@ r600_texture_create_object(struct pipe_screen *screen,
 	resource->size = rtex->size;
 
 	if (!resource->bo) {
-		resource->bo = r600_bo(radeon, rtex->size, 4096, 0);
+		struct pipe_resource *ptex = &rtex->resource.base.b;
+		int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
+
+		resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 		if (!resource->bo) {
 			FREE(rtex);
 			return NULL;
@@ -306,8 +335,14 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 						const struct pipe_resource *templ)
 {
 	unsigned array_mode = 0;
+        static int force_tiling = -1;
 
-	if (debug_get_bool_option("R600_FORCE_TILING", FALSE)) {
+        /* Would like some magic "get_bool_option_once" routine.
+	 */
+	if (force_tiling == -1)
+                force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
+
+	if (force_tiling) {
 		if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 		    !(templ->bind & PIPE_BIND_SCANOUT)) {
 			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
@@ -335,6 +370,18 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	FREE(rtex);
 }
 
+static boolean r600_texture_get_handle(struct pipe_screen* screen,
+                                       struct pipe_resource *ptex,
+                                       struct winsys_handle *whandle)
+{
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+	struct r600_resource *resource = &rtex->resource;
+	struct radeon *radeon = (struct radeon *)screen->winsys;
+
+	return r600_bo_get_winsys_handle(radeon, resource->bo,
+			rtex->pitch_in_bytes[0], whandle);
+}
+
 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 						struct pipe_resource *texture,
 						unsigned face, unsigned level,
@@ -434,10 +481,59 @@ int r600_texture_depth_flush(struct pipe_context *ctx,
 	}
 
 out:
+	/* XXX: only do this if the depth texture has actually changed:
+	 */
 	r600_blit_uncompress_depth_ptr(ctx, rtex);
 	return 0;
 }
 
+/* Needs adjustment for pixelformat:
+ */
+static INLINE unsigned u_box_volume( const struct pipe_box *box )
+{
+        return box->width * box->depth * box->height;
+};
+
+
+/* Figure out whether u_blitter will fallback to a transfer operation.
+ * If so, don't use a staging resource.
+ */
+static boolean permit_hardware_blit(struct pipe_screen *screen,
+                                    struct pipe_resource *res)
+{
+        unsigned bind;
+
+        if (util_format_is_depth_or_stencil(res->format))
+                bind = PIPE_BIND_DEPTH_STENCIL;
+        else
+                bind = PIPE_BIND_RENDER_TARGET;
+
+	/* See r600_resource_copy_region: there is something wrong
+         * with depth resource copies at the moment so avoid them for
+         * now.
+         */
+	if (util_format_get_component_bits(res->format,
+                                           UTIL_FORMAT_COLORSPACE_ZS,
+                                           0) != 0)
+                return FALSE;
+
+        if (!screen->is_format_supported(screen,
+                                         res->format,
+                                         res->target,
+                                         res->nr_samples,
+                                         bind, 0))
+                return FALSE;
+
+        if (!screen->is_format_supported(screen,
+                                         res->format,
+                                         res->target,
+                                         res->nr_samples,
+                                         PIPE_BIND_SAMPLER_VIEW, 0))
+                return FALSE;
+
+        return TRUE;
+}
+
 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 						struct pipe_resource *texture,
 						struct pipe_subresource sr,
@@ -448,6 +544,36 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	struct pipe_resource resource;
 	struct r600_transfer *trans;
 	int r;
+	boolean use_staging_texture = FALSE;
+
+	/* We cannot map a tiled texture directly because the data is
+	 * in a different order, therefore we do detiling using a blit.
+	 *
+	 * Also, use a temporary in GTT memory for read transfers, as
+	 * the CPU is much happier reading out of cached system memory
+	 * than uncached VRAM.
+	 */
+	if (rtex->tiled)
+		use_staging_texture = TRUE;
+
+	if ((usage & PIPE_TRANSFER_READ) &&
+            u_box_volume(box) > 1024)
+                use_staging_texture = TRUE;
+
+        /* XXX: Use a staging texture for uploads if the underlying BO
+         * is busy.  No interface for checking that currently? so do
+         * it eagerly whenever the transfer doesn't require a readback
+         * and might block.
+         */
+        if ((usage & PIPE_TRANSFER_WRITE) &&
+            !(usage & (PIPE_TRANSFER_READ |
+                       PIPE_TRANSFER_DONTBLOCK |
+                       PIPE_TRANSFER_UNSYNCHRONIZED)))
+                use_staging_texture = TRUE;
+
+        if (!permit_hardware_blit(ctx->screen, texture) ||
+            (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
+                use_staging_texture = FALSE;
 
 	trans = CALLOC_STRUCT(r600_transfer);
 	if (trans == NULL)
@@ -457,6 +583,10 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans->transfer.usage = usage;
 	trans->transfer.box = *box;
 	if (rtex->depth) {
+                /* XXX: only readback the rectangle which is being mapped?
+                 */
+                /* XXX: when discard is true, no need to read back from depth texture
+                 */
 		r = r600_texture_depth_flush(ctx, texture);
 		if (r < 0) {
 			R600_ERR("failed to create temporary texture to hold untiled copy\n");
@@ -464,7 +594,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 			FREE(trans);
 			return NULL;
 		}
-	} else if (rtex->tiled) {
+	} else if (use_staging_texture) {
 		resource.target = PIPE_TEXTURE_2D;
 		resource.format = texture->format;
 		resource.width0 = box->width;
@@ -472,7 +602,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 		resource.depth0 = 1;
 		resource.last_level = 0;
 		resource.nr_samples = 0;
-		resource.usage = PIPE_USAGE_DYNAMIC;
+		resource.usage = PIPE_USAGE_STAGING;
 		resource.bind = 0;
 		resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 		/* For texture reading, the temporary (detiled) texture is used as
@@ -486,8 +616,8 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 			resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 		}
 		/* Create the temporary texture. */
-		trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
-		if (trans->linear_texture == NULL) {
+		trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
+		if (trans->staging_texture == NULL) {
 			R600_ERR("failed to create temporary texture to hold untiled copy\n");
 			pipe_resource_reference(&trans->transfer.resource, NULL);
 			FREE(trans);
@@ -495,11 +625,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 		}
 
 		trans->transfer.stride =
-		  ((struct r600_resource_texture *)trans->linear_texture)->pitch_in_bytes[0];
+                        ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 		if (usage & PIPE_TRANSFER_READ) {
-			/* We cannot map a tiled texture directly because the data is
-			 * in a different order, therefore we do detiling using a blit. */
-			r600_copy_from_tiled_texture(ctx, trans);
+			r600_copy_to_staging_texture(ctx, trans);
 			/* Always referenced in the blit. */
 			ctx->flush(ctx, 0, NULL);
 		}
@@ -516,11 +644,11 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 
-	if (rtransfer->linear_texture) {
+	if (rtransfer->staging_texture) {
 		if (transfer->usage & PIPE_TRANSFER_WRITE) {
-			r600_copy_into_tiled_texture(ctx, rtransfer);
+			r600_copy_from_staging_texture(ctx, rtransfer);
 		}
-		pipe_resource_reference(&rtransfer->linear_texture, NULL);
+		pipe_resource_reference(&rtransfer->staging_texture, NULL);
 	}
 	if (rtex->flushed_depth_texture) {
 		pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
@@ -537,10 +665,11 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 	enum pipe_format format = transfer->resource->format;
 	struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 	unsigned offset = 0;
+	unsigned usage = 0;
 	char *map;
 
-	if (rtransfer->linear_texture) {
-		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
+	if (rtransfer->staging_texture) {
+		bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 	} else {
 		struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 
@@ -553,7 +682,30 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 			transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 			transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 	}
-	map = r600_bo_map(radeon, bo, 0, ctx);
+
+	if (transfer->usage & PIPE_TRANSFER_WRITE) {
+		usage |= PB_USAGE_CPU_WRITE;
+
+		if (transfer->usage & PIPE_TRANSFER_DISCARD) {
+		}
+
+		if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
+		}
+	}
+
+	if (transfer->usage & PIPE_TRANSFER_READ) {
+		usage |= PB_USAGE_CPU_READ;
+	}
+
+	if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
+		usage |= PB_USAGE_DONTBLOCK;
+	}
+
+	if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
+		usage |= PB_USAGE_UNSYNCHRONIZED;
+	}
+
+	map = r600_bo_map(radeon, bo, usage, ctx);
 	if (!map) {
 		return NULL;
 	}
@@ -568,8 +720,8 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 	struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 	struct r600_bo *bo;
 
-	if (rtransfer->linear_texture) {
-		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
+	if (rtransfer->staging_texture) {
+		bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 	} else {
 		struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 
@@ -584,7 +736,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 
 struct u_resource_vtbl r600_texture_vtbl =
 {
-	u_default_resource_get_handle,	/* get_handle */
+	r600_texture_get_handle,	/* get_handle */
 	r600_texture_destroy,		/* resource_destroy */
 	r600_texture_is_referenced,	/* is_resource_referenced */
 	r600_texture_get_transfer,	/* get_transfer */
@@ -689,7 +841,7 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 			result = FMT_24_8;
 			goto out_word4;
 		case PIPE_FORMAT_S8_USCALED:
-			result = V_0280A0_COLOR_8;
+			result = FMT_8;
 			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 			goto out_word4;
 		default:
@@ -718,7 +870,29 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 
 	/* S3TC formats. TODO */
 	if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
-		goto out_unknown;
+                static int r600_enable_s3tc = -1;
+
+                if (r600_enable_s3tc == -1)
+                        r600_enable_s3tc = 
+                                debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
+
+                if (!r600_enable_s3tc)
+                        goto out_unknown;
+
+		switch (format) {
+		case PIPE_FORMAT_DXT1_RGB:
+		case PIPE_FORMAT_DXT1_RGBA:
+                        result = FMT_BC1;
+                        goto out_word4;
+		case PIPE_FORMAT_DXT3_RGBA:
+                        result = FMT_BC2;
+                        goto out_word4;
+		case PIPE_FORMAT_DXT5_RGBA:
+                        result = FMT_BC3;
+                        goto out_word4;
+                default:
+                        goto out_unknown;
+                }
 	}