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-rw-r--r--src/gallium/drivers/cell/ppu/cell_draw_arrays.c6
-rw-r--r--src/gallium/drivers/cell/ppu/cell_gen_fragment.c2
-rw-r--r--src/gallium/drivers/cell/ppu/cell_state_emit.c2
-rw-r--r--src/gallium/drivers/cell/ppu/cell_state_shader.c2
-rw-r--r--src/gallium/drivers/cell/ppu/cell_texture.c81
-rw-r--r--src/gallium/drivers/cell/spu/Makefile5
-rw-r--r--src/gallium/drivers/cell/spu/spu_per_fragment_op.c2
-rw-r--r--src/gallium/drivers/cell/spu/spu_tri.c179
-rw-r--r--src/gallium/drivers/i915simple/i915_fpc_translate.c2
-rw-r--r--src/gallium/drivers/i965simple/brw_vs_emit.c2
-rw-r--r--src/gallium/drivers/nouveau/nouveau_bo.h53
-rw-r--r--src/gallium/drivers/nouveau/nouveau_channel.h40
-rw-r--r--src/gallium/drivers/nouveau/nouveau_class.h8006
-rw-r--r--src/gallium/drivers/nouveau/nouveau_device.h30
-rw-r--r--src/gallium/drivers/nouveau/nouveau_grobj.h35
-rw-r--r--src/gallium/drivers/nouveau/nouveau_notifier.h43
-rw-r--r--src/gallium/drivers/nouveau/nouveau_pushbuf.h32
-rw-r--r--src/gallium/drivers/nouveau/nouveau_resource.h37
-rw-r--r--src/gallium/drivers/nouveau/nouveau_stateobj.h5
-rw-r--r--src/gallium/drivers/nouveau/nouveau_winsys.h4
-rw-r--r--src/gallium/drivers/nv04/Makefile1
-rw-r--r--src/gallium/drivers/nv04/nv04_miptree.c26
-rw-r--r--src/gallium/drivers/nv04/nv04_screen.c13
-rw-r--r--src/gallium/drivers/nv04/nv04_screen.h2
-rw-r--r--src/gallium/drivers/nv04/nv04_surface.c18
-rw-r--r--src/gallium/drivers/nv04/nv04_surface_2d.c448
-rw-r--r--src/gallium/drivers/nv04/nv04_surface_2d.h29
-rw-r--r--src/gallium/drivers/nv10/nv10_miptree.c26
-rw-r--r--src/gallium/drivers/nv10/nv10_screen.c12
-rw-r--r--src/gallium/drivers/nv10/nv10_screen.h2
-rw-r--r--src/gallium/drivers/nv10/nv10_surface.c18
-rw-r--r--src/gallium/drivers/nv20/nv20_miptree.c57
-rw-r--r--src/gallium/drivers/nv20/nv20_screen.c12
-rw-r--r--src/gallium/drivers/nv20/nv20_screen.h2
-rw-r--r--src/gallium/drivers/nv20/nv20_surface.c18
-rw-r--r--src/gallium/drivers/nv20/nv20_vertprog.c2
-rw-r--r--src/gallium/drivers/nv30/nv30_miptree.c68
-rw-r--r--src/gallium/drivers/nv30/nv30_screen.c27
-rw-r--r--src/gallium/drivers/nv30/nv30_screen.h2
-rw-r--r--src/gallium/drivers/nv30/nv30_surface.c21
-rw-r--r--src/gallium/drivers/nv30/nv30_vertprog.c2
-rw-r--r--src/gallium/drivers/nv40/nv40_miptree.c65
-rw-r--r--src/gallium/drivers/nv40/nv40_screen.c29
-rw-r--r--src/gallium/drivers/nv40/nv40_screen.h2
-rw-r--r--src/gallium/drivers/nv40/nv40_surface.c21
-rw-r--r--src/gallium/drivers/nv40/nv40_vertprog.c2
-rw-r--r--src/gallium/drivers/nv50/nv50_clear.c28
-rw-r--r--src/gallium/drivers/nv50/nv50_context.c2
-rw-r--r--src/gallium/drivers/nv50/nv50_context.h9
-rw-r--r--src/gallium/drivers/nv50/nv50_miptree.c34
-rw-r--r--src/gallium/drivers/nv50/nv50_program.c23
-rw-r--r--src/gallium/drivers/nv50/nv50_query.c25
-rw-r--r--src/gallium/drivers/nv50/nv50_screen.c24
-rw-r--r--src/gallium/drivers/nv50/nv50_screen.h1
-rw-r--r--src/gallium/drivers/nv50/nv50_state_validate.c12
-rw-r--r--src/gallium/drivers/nv50/nv50_surface.c152
-rw-r--r--src/gallium/drivers/nv50/nv50_tex.c6
-rw-r--r--src/gallium/drivers/nv50/nv50_vbo.c81
-rw-r--r--src/gallium/drivers/r300/Makefile22
-rw-r--r--src/gallium/drivers/r300/SConscript17
-rw-r--r--src/gallium/drivers/r300/r300_chipset.c348
-rw-r--r--src/gallium/drivers/r300/r300_chipset.h79
-rw-r--r--src/gallium/drivers/r300/r300_clear.c33
-rw-r--r--src/gallium/drivers/r300/r300_clear.h27
-rw-r--r--src/gallium/drivers/r300/r300_context.c142
-rw-r--r--src/gallium/drivers/r300/r300_context.h252
-rw-r--r--src/gallium/drivers/r300/r300_cs.h123
-rw-r--r--src/gallium/drivers/r300/r300_cs_inlines.h50
-rw-r--r--src/gallium/drivers/r300/r300_emit.c266
-rw-r--r--src/gallium/drivers/r300/r300_emit.h59
-rw-r--r--src/gallium/drivers/r300/r300_flush.c42
-rw-r--r--src/gallium/drivers/r300/r300_flush.h33
-rw-r--r--src/gallium/drivers/r300/r300_reg.h3250
-rw-r--r--src/gallium/drivers/r300/r300_screen.c282
-rw-r--r--src/gallium/drivers/r300/r300_screen.h52
-rw-r--r--src/gallium/drivers/r300/r300_state.c852
-rw-r--r--src/gallium/drivers/r300/r300_state_derived.c134
-rw-r--r--src/gallium/drivers/r300/r300_state_derived.h33
-rw-r--r--src/gallium/drivers/r300/r300_state_shader.c53
-rw-r--r--src/gallium/drivers/r300/r300_state_shader.h83
-rw-r--r--src/gallium/drivers/r300/r300_surface.c327
-rw-r--r--src/gallium/drivers/r300/r300_surface.h59
-rw-r--r--src/gallium/drivers/r300/r300_swtcl_emit.c164
-rw-r--r--src/gallium/drivers/r300/r300_texture.c193
-rw-r--r--src/gallium/drivers/r300/r300_texture.h34
-rw-r--r--src/gallium/drivers/r300/r300_winsys.h94
-rw-r--r--src/gallium/drivers/softpipe/Makefile2
-rw-r--r--src/gallium/drivers/softpipe/SConscript2
-rw-r--r--src/gallium/drivers/softpipe/sp_context.h31
-rw-r--r--src/gallium/drivers/softpipe/sp_draw_arrays.c10
-rw-r--r--src/gallium/drivers/softpipe/sp_fs_exec.c2
-rw-r--r--src/gallium/drivers/softpipe/sp_fs_sse.c2
-rw-r--r--src/gallium/drivers/softpipe/sp_headers.h95
-rw-r--r--src/gallium/drivers/softpipe/sp_quad.h81
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_alpha_test.c2
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_blend.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_bufloop.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_colormask.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_coverage.c9
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_depth_test.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_earlyz.c2
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_fs.c2
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_occlusion.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_output.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_pipe.c (renamed from src/gallium/drivers/softpipe/sp_quad.c)0
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_pipe.h74
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_stencil.c4
-rw-r--r--src/gallium/drivers/softpipe/sp_quad_stipple.c27
-rw-r--r--src/gallium/drivers/softpipe/sp_setup.c38
-rw-r--r--src/gallium/drivers/softpipe/sp_tex_sample.c2
-rw-r--r--src/gallium/drivers/softpipe/sp_texture.c2
111 files changed, 8605 insertions, 8799 deletions
diff --git a/src/gallium/drivers/cell/ppu/cell_draw_arrays.c b/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
index 67949b73dd..644496db40 100644
--- a/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
+++ b/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
@@ -51,7 +51,7 @@ cell_map_constant_buffers(struct cell_context *sp)
struct pipe_winsys *ws = sp->pipe.winsys;
uint i;
for (i = 0; i < 2; i++) {
- if (sp->constants[i].size) {
+ if (sp->constants[i].buffer && sp->constants[i].buffer->size) {
sp->mapped_constants[i] = ws->buffer_map(ws, sp->constants[i].buffer,
PIPE_BUFFER_USAGE_CPU_READ);
cell_flush_buffer_range(sp, sp->mapped_constants[i],
@@ -61,7 +61,7 @@ cell_map_constant_buffers(struct cell_context *sp)
draw_set_mapped_constant_buffer(sp->draw,
sp->mapped_constants[PIPE_SHADER_VERTEX],
- sp->constants[PIPE_SHADER_VERTEX].size);
+ sp->constants[PIPE_SHADER_VERTEX].buffer->size);
}
static void
@@ -70,7 +70,7 @@ cell_unmap_constant_buffers(struct cell_context *sp)
struct pipe_winsys *ws = sp->pipe.winsys;
uint i;
for (i = 0; i < 2; i++) {
- if (sp->constants[i].size)
+ if (sp->constants[i].buffer && sp->constants[i].buffer->size)
ws->buffer_unmap(ws, sp->constants[i].buffer);
sp->mapped_constants[i] = NULL;
}
diff --git a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c
index 9bdc71b676..66d4b3b6a3 100644
--- a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c
+++ b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c
@@ -161,7 +161,7 @@ gen_alpha_test(const struct pipe_depth_stencil_alpha_state *dsa,
if ((dsa->alpha.func != PIPE_FUNC_NEVER) &&
(dsa->alpha.func != PIPE_FUNC_ALWAYS)) {
/* load/splat the alpha reference float value */
- spe_load_float(f, ref_reg, dsa->alpha.ref);
+ spe_load_float(f, ref_reg, dsa->alpha.ref_value);
}
/* emit code to do the alpha comparison, updating 'mask' */
diff --git a/src/gallium/drivers/cell/ppu/cell_state_emit.c b/src/gallium/drivers/cell/ppu/cell_state_emit.c
index 39b85faeb8..ff529fe22c 100644
--- a/src/gallium/drivers/cell/ppu/cell_state_emit.c
+++ b/src/gallium/drivers/cell/ppu/cell_state_emit.c
@@ -239,7 +239,7 @@ cell_emit_state(struct cell_context *cell)
if (cell->dirty & (CELL_NEW_FS_CONSTANTS)) {
const uint shader = PIPE_SHADER_FRAGMENT;
- const uint num_const = cell->constants[shader].size / sizeof(float);
+ const uint num_const = cell->constants[shader].buffer->size / sizeof(float);
uint i, j;
float *buf = cell_batch_alloc16(cell, ROUNDUP16(32 + num_const * sizeof(float)));
uint32_t *ibuf = (uint32_t *) buf;
diff --git a/src/gallium/drivers/cell/ppu/cell_state_shader.c b/src/gallium/drivers/cell/ppu/cell_state_shader.c
index 990f23e170..bf517ea563 100644
--- a/src/gallium/drivers/cell/ppu/cell_state_shader.c
+++ b/src/gallium/drivers/cell/ppu/cell_state_shader.c
@@ -186,7 +186,6 @@ cell_set_constant_buffer(struct pipe_context *pipe,
const struct pipe_constant_buffer *buf)
{
struct cell_context *cell = cell_context(pipe);
- struct pipe_winsys *ws = pipe->winsys;
assert(shader < PIPE_SHADER_TYPES);
assert(index == 0);
@@ -197,7 +196,6 @@ cell_set_constant_buffer(struct pipe_context *pipe,
pipe_buffer_reference(pipe->screen,
&cell->constants[shader].buffer,
buf->buffer);
- cell->constants[shader].size = buf->size;
if (shader == PIPE_SHADER_VERTEX)
cell->dirty |= CELL_NEW_VS_CONSTANTS;
diff --git a/src/gallium/drivers/cell/ppu/cell_texture.c b/src/gallium/drivers/cell/ppu/cell_texture.c
index 4f16e2c6af..9ba995ab7d 100644
--- a/src/gallium/drivers/cell/ppu/cell_texture.c
+++ b/src/gallium/drivers/cell/ppu/cell_texture.c
@@ -307,9 +307,8 @@ cell_twiddle_texture(struct pipe_screen *screen,
const uint texHeight = ct->base.height[level];
const uint bufWidth = align(texWidth, TILE_SIZE);
const uint bufHeight = align(texHeight, TILE_SIZE);
- const void *map = pipe_buffer_map(screen, surface->buffer,
- PIPE_BUFFER_USAGE_CPU_READ);
- const uint *src = (const uint *) ((const ubyte *) map + surface->offset);
+ const void *map = screen->surface_map(screen, surface, PIPE_BUFFER_USAGE_CPU_READ);
+ const uint *src = (const uint *) map;
switch (ct->base.format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
@@ -324,12 +323,12 @@ cell_twiddle_texture(struct pipe_screen *screen,
/* allocate buffer for tiled data now */
struct pipe_winsys *ws = screen->winsys;
uint bytes = bufWidth * bufHeight * 4 * numFaces;
- ct->tiled_buffer[level] = ws->buffer_create(ws, 16,
- PIPE_BUFFER_USAGE_PIXEL,
- bytes);
+ ct->tiled_buffer[level] =
+ ws->buffer_create(ws, 16, PIPE_BUFFER_USAGE_PIXEL, bytes);
/* and map it */
- ct->tiled_mapped[level] = ws->buffer_map(ws, ct->tiled_buffer[level],
- PIPE_BUFFER_USAGE_GPU_READ);
+ ct->tiled_mapped[level] =
+ ws->buffer_map(ws, ct->tiled_buffer[level],
+ PIPE_BUFFER_USAGE_GPU_READ);
}
dst = (uint *) ((ubyte *) ct->tiled_mapped[level] + offset);
@@ -338,11 +337,11 @@ cell_twiddle_texture(struct pipe_screen *screen,
}
break;
default:
- printf("Cell: twiddle unsupported texture format %s\n", pf_name(ct->base.format));
- ;
+ printf("Cell: twiddle unsupported texture format %s\n",
+ pf_name(ct->base.format));
}
- pipe_buffer_unmap(screen, surface->buffer);
+ screen->surface_unmap(screen, surface);
}
@@ -357,8 +356,7 @@ cell_untwiddle_texture(struct pipe_screen *screen,
const uint level = surface->level;
const uint texWidth = ct->base.width[level];
const uint texHeight = ct->base.height[level];
- const void *map = pipe_buffer_map(screen, surface->buffer,
- PIPE_BUFFER_USAGE_CPU_READ);
+ const void *map = screen->surface_map(screen, surface, PIPE_BUFFER_USAGE_CPU_READ);
const uint *src = (const uint *) ((const ubyte *) map + surface->offset);
switch (ct->base.format) {
@@ -384,11 +382,12 @@ cell_untwiddle_texture(struct pipe_screen *screen,
default:
{
ct->untiled_data[level] = NULL;
- printf("Cell: untwiddle unsupported texture format %s\n", pf_name(ct->base.format));
+ printf("Cell: untwiddle unsupported texture format %s\n",
+ pf_name(ct->base.format));
}
}
- pipe_buffer_unmap(screen, surface->buffer);
+ screen->surface_unmap(screen, surface);
}
@@ -398,15 +397,13 @@ cell_get_tex_surface(struct pipe_screen *screen,
unsigned face, unsigned level, unsigned zslice,
unsigned usage)
{
- struct pipe_winsys *ws = screen->winsys;
struct cell_texture *ct = cell_texture(pt);
struct pipe_surface *ps;
- ps = ws->surface_alloc(ws);
+ ps = CALLOC_STRUCT(pipe_surface);
if (ps) {
- assert(ps->refcount);
- assert(ps->winsys);
- pipe_buffer_reference(screen, &ps->buffer, ct->buffer);
+ ps->refcount = 1;
+ pipe_texture_reference(&ps->texture, pt);
ps->format = pt->format;
ps->block = pt->block;
ps->width = pt->width[level];
@@ -425,9 +422,9 @@ cell_get_tex_surface(struct pipe_screen *screen,
ps->zslice = zslice;
if (pt->target == PIPE_TEXTURE_CUBE || pt->target == PIPE_TEXTURE_3D) {
- ps->offset += ((pt->target == PIPE_TEXTURE_CUBE) ? face : zslice) *
- ps->nblocksy *
- ps->stride;
+ ps->offset += ((pt->target == PIPE_TEXTURE_CUBE) ? face : zslice) *
+ ps->nblocksy *
+ ps->stride;
}
else {
assert(face == 0);
@@ -449,18 +446,27 @@ cell_tex_surface_release(struct pipe_screen *screen,
{
struct cell_texture *ct = cell_texture((*s)->texture);
const uint level = (*s)->level;
+ struct pipe_surface *surf = *s;
- if (((*s)->usage & PIPE_BUFFER_USAGE_CPU_READ) && (ct->untiled_data[level]))
+ if ((surf->usage & PIPE_BUFFER_USAGE_CPU_READ) && (ct->untiled_data[level]))
{
align_free(ct->untiled_data[level]);
ct->untiled_data[level] = NULL;
}
- /* XXX if done rendering to teximage, re-tile */
+ if ((ct->base.tex_usage & PIPE_TEXTURE_USAGE_SAMPLER) &&
+ (surf->usage & PIPE_BUFFER_USAGE_CPU_WRITE)) {
+ /* convert from linear to tiled layout */
+ cell_twiddle_texture(screen, surf);
+ }
- pipe_texture_reference(&(*s)->texture, NULL);
+ /* XXX if done rendering to teximage, re-tile */
- screen->winsys->surface_release(screen->winsys, s);
+ if (--surf->refcount == 0) {
+ pipe_texture_reference(&surf->texture, NULL);
+ FREE(surf);
+ }
+ *s = NULL;
}
@@ -475,17 +481,20 @@ cell_surface_map(struct pipe_screen *screen,
assert(ct);
+#if 0
if (flags & ~surface->usage) {
assert(0);
return NULL;
}
+#endif
- map = pipe_buffer_map( screen, surface->buffer, flags );
- if (map == NULL)
+ map = pipe_buffer_map( screen, ct->buffer, flags );
+ if (map == NULL) {
return NULL;
- else
- {
- if ((surface->usage & PIPE_BUFFER_USAGE_CPU_READ) && (ct->untiled_data[level])) {
+ }
+ else {
+ if ((surface->usage & PIPE_BUFFER_USAGE_CPU_READ) &&
+ (ct->untiled_data[level])) {
return (void *) ((ubyte *) ct->untiled_data[level] + surface->offset);
}
else {
@@ -503,13 +512,7 @@ cell_surface_unmap(struct pipe_screen *screen,
assert(ct);
- if ((ct->base.tex_usage & PIPE_TEXTURE_USAGE_SAMPLER) &&
- (surface->usage & PIPE_BUFFER_USAGE_CPU_WRITE)) {
- /* convert from linear to tiled layout */
- cell_twiddle_texture(screen, surface);
- }
-
- pipe_buffer_unmap( screen, surface->buffer );
+ pipe_buffer_unmap( screen, ct->buffer );
}
diff --git a/src/gallium/drivers/cell/spu/Makefile b/src/gallium/drivers/cell/spu/Makefile
index 116453b79c..3cc52301da 100644
--- a/src/gallium/drivers/cell/spu/Makefile
+++ b/src/gallium/drivers/cell/spu/Makefile
@@ -33,9 +33,10 @@ OLD_SOURCES = \
spu_vertex_shader.c
-SPU_OBJECTS = $(SOURCES:.c=.o) \
+SPU_OBJECTS = $(SOURCES:.c=.o)
+
+SPU_ASM_OUT = $(SOURCES:.c=.s)
-SPU_ASM_OUT = $(SOURCES:.c=.s) \
INCLUDE_DIRS = \
-I$(TOP)/src/mesa \
diff --git a/src/gallium/drivers/cell/spu/spu_per_fragment_op.c b/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
index 683664e8a4..eba9f95cf1 100644
--- a/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
+++ b/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
@@ -85,7 +85,7 @@ spu_fallback_fragment_ops(uint x, uint y,
* Do alpha test
*/
if (spu.depth_stencil_alpha.alpha.enabled) {
- vector float ref = spu_splats(spu.depth_stencil_alpha.alpha.ref);
+ vector float ref = spu_splats(spu.depth_stencil_alpha.alpha.ref_value);
vector unsigned int amask;
switch (spu.depth_stencil_alpha.alpha.func) {
diff --git a/src/gallium/drivers/cell/spu/spu_tri.c b/src/gallium/drivers/cell/spu/spu_tri.c
index 0d9fcb9997..d727268475 100644
--- a/src/gallium/drivers/cell/spu/spu_tri.c
+++ b/src/gallium/drivers/cell/spu/spu_tri.c
@@ -29,7 +29,6 @@
* Triangle rendering within a tile.
*/
-#include <transpose_matrix4x4.h>
#include "pipe/p_compiler.h"
#include "pipe/p_format.h"
#include "util/u_math.h"
@@ -71,6 +70,12 @@ struct vertex_header {
#define MASK_ALL 0xf
+#define CHAN0 0
+#define CHAN1 1
+#define CHAN2 2
+#define CHAN3 3
+
+
#define DEBUG_VERTS 0
/**
@@ -144,99 +149,97 @@ struct setup_stage {
static struct setup_stage setup;
-/**
- * Evaluate attribute coefficients (plane equations) to compute
- * attribute values for the four fragments in a quad.
- * Eg: four colors will be computed (in AoS format).
- */
-static INLINE void
-eval_coeff(uint slot, float x, float y, vector float w, vector float result[4])
+static INLINE vector float
+splatx(vector float v)
{
- switch (spu.vertex_info.attrib[slot].interp_mode) {
- case INTERP_CONSTANT:
- result[QUAD_TOP_LEFT] =
- result[QUAD_TOP_RIGHT] =
- result[QUAD_BOTTOM_LEFT] =
- result[QUAD_BOTTOM_RIGHT] = setup.coef[slot].a0;
- break;
- case INTERP_LINEAR:
- {
- vector float dadx = setup.coef[slot].dadx;
- vector float dady = setup.coef[slot].dady;
- vector float topLeft =
- spu_add(setup.coef[slot].a0,
- spu_add(spu_mul(spu_splats(x), dadx),
- spu_mul(spu_splats(y), dady)));
-
- result[QUAD_TOP_LEFT] = topLeft;
- result[QUAD_TOP_RIGHT] = spu_add(topLeft, dadx);
- result[QUAD_BOTTOM_LEFT] = spu_add(topLeft, dady);
- result[QUAD_BOTTOM_RIGHT] = spu_add(spu_add(topLeft, dadx), dady);
- }
- break;
- case INTERP_PERSPECTIVE:
- {
- vector float dadx = setup.coef[slot].dadx;
- vector float dady = setup.coef[slot].dady;
- vector float topLeft =
- spu_add(setup.coef[slot].a0,
- spu_add(spu_mul(spu_splats(x), dadx),
- spu_mul(spu_splats(y), dady)));
-
- vector float wInv = spu_re(w); /* 1.0 / w */
-
- result[QUAD_TOP_LEFT] = spu_mul(topLeft, wInv);
- result[QUAD_TOP_RIGHT] = spu_mul(spu_add(topLeft, dadx), wInv);
- result[QUAD_BOTTOM_LEFT] = spu_mul(spu_add(topLeft, dady), wInv);
- result[QUAD_BOTTOM_RIGHT] = spu_mul(spu_add(spu_add(topLeft, dadx), dady), wInv);
- }
- break;
- case INTERP_POS:
- case INTERP_NONE:
- break;
- default:
- ASSERT(0);
- }
+ return spu_splats(spu_extract(v, CHAN0));
}
-
-/**
- * As above, but return 4 vectors in SOA format.
- * XXX this will all be re-written someday.
- */
-static INLINE void
-eval_coeff_soa(uint slot, float x, float y, vector float w, vector float result[4])
+static INLINE vector float
+splaty(vector float v)
{
- eval_coeff(slot, x, y, w, result);
- _transpose_matrix4x4(result, result);
+ return spu_splats(spu_extract(v, CHAN1));
}
+static INLINE vector float
+splatz(vector float v)
+{
+ return spu_splats(spu_extract(v, CHAN2));
+}
-/** Evalute coefficients to get Z for four pixels in a quad */
static INLINE vector float
-eval_z(float x, float y)
+splatw(vector float v)
{
- const uint slot = 0;
- const float dzdx = spu_extract(setup.coef[slot].dadx, 2);
- const float dzdy = spu_extract(setup.coef[slot].dady, 2);
- const float topLeft = spu_extract(setup.coef[slot].a0, 2) + x * dzdx + y * dzdy;
- const vector float topLeftv = spu_splats(topLeft);
- const vector float derivs = (vector float) { 0.0, dzdx, dzdy, dzdx + dzdy };
- return spu_add(topLeftv, derivs);
+ return spu_splats(spu_extract(v, CHAN3));
}
-/** Evalute coefficients to get W for four pixels in a quad */
-static INLINE vector float
-eval_w(float x, float y)
+/**
+ * Setup fragment shader inputs by evaluating triangle's vertex
+ * attribute coefficient info.
+ * \param x quad x pos
+ * \param y quad y pos
+ * \param fragZ returns quad Z values
+ * \param fragInputs returns fragment program inputs
+ * Note: this code could be incorporated into the fragment program
+ * itself to avoid the loop and switch.
+ */
+static void
+eval_inputs(float x, float y, vector float *fragZ, vector float fragInputs[])
{
- const uint slot = 0;
- const float dwdx = spu_extract(setup.coef[slot].dadx, 3);
- const float dwdy = spu_extract(setup.coef[slot].dady, 3);
- const float topLeft = spu_extract(setup.coef[slot].a0, 3) + x * dwdx + y * dwdy;
- const vector float topLeftv = spu_splats(topLeft);
- const vector float derivs = (vector float) { 0.0, dwdx, dwdy, dwdx + dwdy };
- return spu_add(topLeftv, derivs);
+ static const vector float deltaX = (const vector float) {0, 1, 0, 1};
+ static const vector float deltaY = (const vector float) {0, 0, 1, 1};
+
+ const uint posSlot = 0;
+ const vector float pos = setup.coef[posSlot].a0;
+ const vector float dposdx = setup.coef[posSlot].dadx;
+ const vector float dposdy = setup.coef[posSlot].dady;
+ const vector float fragX = spu_splats(x) + deltaX;
+ const vector float fragY = spu_splats(y) + deltaY;
+ vector float fragW, wInv;
+ uint i;
+
+ *fragZ = splatz(pos) + fragX * splatz(dposdx) + fragY * splatz(dposdy);
+ fragW = splatw(pos) + fragX * splatw(dposdx) + fragY * splatw(dposdy);
+ wInv = spu_re(fragW); /* 1 / w */
+
+ /* loop over fragment program inputs */
+ for (i = 0; i < spu.vertex_info.num_attribs; i++) {
+ uint attr = i + 1;
+ enum interp_mode interp = spu.vertex_info.attrib[attr].interp_mode;
+
+ /* constant term */
+ vector float a0 = setup.coef[attr].a0;
+ vector float r0 = splatx(a0);
+ vector float r1 = splaty(a0);
+ vector float r2 = splatz(a0);
+ vector float r3 = splatw(a0);
+
+ if (interp == INTERP_LINEAR || interp == INTERP_PERSPECTIVE) {
+ /* linear term */
+ vector float dadx = setup.coef[attr].dadx;
+ vector float dady = setup.coef[attr].dady;
+ /* Use SPU intrinsics here to get slightly better code.
+ * originally: r0 += fragX * splatx(dadx) + fragY * splatx(dady);
+ */
+ r0 = spu_madd(fragX, splatx(dadx), spu_madd(fragY, splatx(dady), r0));
+ r1 = spu_madd(fragX, splaty(dadx), spu_madd(fragY, splaty(dady), r1));
+ r2 = spu_madd(fragX, splatz(dadx), spu_madd(fragY, splatz(dady), r2));
+ r3 = spu_madd(fragX, splatw(dadx), spu_madd(fragY, splatw(dady), r3));
+ if (interp == INTERP_PERSPECTIVE) {
+ /* perspective term */
+ r0 *= wInv;
+ r1 *= wInv;
+ r2 *= wInv;
+ r3 *= wInv;
+ }
+ }
+ fragInputs[CHAN0] = r0;
+ fragInputs[CHAN1] = r1;
+ fragInputs[CHAN2] = r2;
+ fragInputs[CHAN3] = r3;
+ fragInputs += 4;
+ }
}
@@ -262,19 +265,11 @@ emit_quad( int x, int y, mask_t mask)
* Run fragment shader, execute per-fragment ops, update fb/tile.
*/
vector float inputs[4*4], outputs[2*4];
- vector float fragZ = eval_z((float) x, (float) y);
- vector float fragW = eval_w((float) x, (float) y);
vector unsigned int kill_mask;
+ vector float fragZ;
+
+ eval_inputs((float) x, (float) y, &fragZ, inputs);
- /* setup inputs */
-#if 0
- eval_coeff_soa(1, (float) x, (float) y, fragW, inputs);
-#else
- uint i;
- for (i = 0; i < spu.vertex_info.num_attribs; i++) {
- eval_coeff_soa(i+1, (float) x, (float) y, fragW, inputs + i * 4);
- }
-#endif
ASSERT(spu.fragment_program);
ASSERT(spu.fragment_ops);
diff --git a/src/gallium/drivers/i915simple/i915_fpc_translate.c b/src/gallium/drivers/i915simple/i915_fpc_translate.c
index 43d62c5176..d92bdc1bc6 100644
--- a/src/gallium/drivers/i915simple/i915_fpc_translate.c
+++ b/src/gallium/drivers/i915simple/i915_fpc_translate.c
@@ -964,7 +964,7 @@ i915_translate_instructions(struct i915_fp_compile *p,
= &parse.FullToken.FullImmediate;
const uint pos = p->num_immediates++;
uint j;
- for (j = 0; j < imm->Immediate.Size; j++) {
+ for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
p->immediates[pos][j] = imm->u.ImmediateFloat32[j].Float;
}
}
diff --git a/src/gallium/drivers/i965simple/brw_vs_emit.c b/src/gallium/drivers/i965simple/brw_vs_emit.c
index 34dbc0624d..e03d653482 100644
--- a/src/gallium/drivers/i965simple/brw_vs_emit.c
+++ b/src/gallium/drivers/i965simple/brw_vs_emit.c
@@ -1293,7 +1293,7 @@ void brw_vs_emit(struct brw_vs_compile *c)
break;
case TGSI_TOKEN_TYPE_IMMEDIATE: {
struct tgsi_full_immediate *imm = &parse.FullToken.FullImmediate;
- /*assert(imm->Immediate.Size == 4);*/
+ assert(imm->Immediate.NrTokens == 4 + 1);
c->prog_data.imm_buf[c->prog_data.num_imm][0] = imm->u.ImmediateFloat32[0].Float;
c->prog_data.imm_buf[c->prog_data.num_imm][1] = imm->u.ImmediateFloat32[1].Float;
c->prog_data.imm_buf[c->prog_data.num_imm][2] = imm->u.ImmediateFloat32[2].Float;
diff --git a/src/gallium/drivers/nouveau/nouveau_bo.h b/src/gallium/drivers/nouveau/nouveau_bo.h
deleted file mode 100644
index 65b138283c..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_bo.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_BO_H__
-#define __NOUVEAU_BO_H__
-
-/* Relocation/Buffer type flags */
-#define NOUVEAU_BO_VRAM (1 << 0)
-#define NOUVEAU_BO_GART (1 << 1)
-#define NOUVEAU_BO_RD (1 << 2)
-#define NOUVEAU_BO_WR (1 << 3)
-#define NOUVEAU_BO_RDWR (NOUVEAU_BO_RD | NOUVEAU_BO_WR)
-#define NOUVEAU_BO_MAP (1 << 4)
-#define NOUVEAU_BO_PIN (1 << 5)
-#define NOUVEAU_BO_LOW (1 << 6)
-#define NOUVEAU_BO_HIGH (1 << 7)
-#define NOUVEAU_BO_OR (1 << 8)
-#define NOUVEAU_BO_LOCAL (1 << 9)
-#define NOUVEAU_BO_TILED (1 << 10)
-#define NOUVEAU_BO_ZTILE (1 << 11)
-#define NOUVEAU_BO_DUMMY (1 << 31)
-
-struct nouveau_bo {
- struct nouveau_device *device;
- uint64_t handle;
-
- uint64_t size;
- void *map;
-
- uint32_t flags;
- uint64_t offset;
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_channel.h b/src/gallium/drivers/nouveau/nouveau_channel.h
deleted file mode 100644
index cd99a676bd..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_channel.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_CHANNEL_H__
-#define __NOUVEAU_CHANNEL_H__
-
-struct nouveau_channel {
- struct nouveau_device *device;
- int id;
-
- struct nouveau_pushbuf *pushbuf;
-
- struct nouveau_grobj *nullobj;
- struct nouveau_grobj *vram;
- struct nouveau_grobj *gart;
-
- void *user_private;
- void (*hang_notify)(struct nouveau_channel *);
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_class.h b/src/gallium/drivers/nouveau/nouveau_class.h
deleted file mode 100644
index 3df3d7b2b8..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_class.h
+++ /dev/null
@@ -1,8006 +0,0 @@
-/*************************************************************************
-
- Autogenerated file, do not edit !
-
-**************************************************************************
-
- Copyright (C) 2006-2008 :
- Dmitry Baryshkov,
- Laurent Carlier,
- Matthieu Castet,
- Dawid Gajownik,
- Jeremy Kolb,
- Stephane Loeuillet,
- Patrice Mandin,
- Stephane Marchesin,
- Serge Martin,
- Sylvain Munaut,
- Simon Raffeiner,
- Ben Skeggs,
- Erik Waling,
- koala_br,
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*************************************************************************/
-
-
-#ifndef NOUVEAU_REG_H
-#define NOUVEAU_REG_H 1
-
-
-#define NV01_ROOT 0x00000001
-
-
-
-#define NV01_CONTEXT_DMA 0x00000002
-
-
-
-#define NV01_DEVICE 0x00000003
-
-
-
-#define NV01_TIMER 0x00000004
-
-#define NV01_TIMER_SYNCHRONIZE 0x00000100
-#define NV01_TIMER_STOP_ALARM 0x00000104
-#define NV01_TIMER_DMA_NOTIFY 0x00000180
-#define NV01_TIMER_TIME(x) (0x00000300+((x)*4))
-#define NV01_TIMER_TIME__SIZE 0x00000002
-#define NV01_TIMER_ALARM_NOTIFY 0x00000308
-
-
-#define NV_IMAGE_STENCIL 0x00000010
-
-#define NV_IMAGE_STENCIL_NOTIFY 0x00000104
-#define NV_IMAGE_STENCIL_DMA_NOTIFY 0x00000180
-#define NV_IMAGE_STENCIL_IMAGE_OUTPUT 0x00000200
-#define NV_IMAGE_STENCIL_IMAGE_INPUT(x) (0x00000204+((x)*4))
-#define NV_IMAGE_STENCIL_IMAGE_INPUT__SIZE 0x00000002
-
-
-#define NV_IMAGE_BLEND_AND 0x00000011
-
-#define NV_IMAGE_BLEND_AND_NOP 0x00000100
-#define NV_IMAGE_BLEND_AND_NOTIFY 0x00000104
-#define NV_IMAGE_BLEND_AND_DMA_NOTIFY 0x00000180
-#define NV_IMAGE_BLEND_AND_IMAGE_OUTPUT 0x00000200
-#define NV_IMAGE_BLEND_AND_BETA_INPUT 0x00000204
-#define NV_IMAGE_BLEND_AND_IMAGE_INPUT 0x00000208
-
-
-#define NV01_CONTEXT_BETA1 0x00000012
-
-#define NV01_CONTEXT_BETA1_NOP 0x00000100
-#define NV01_CONTEXT_BETA1_NOTIFY 0x00000104
-#define NV01_CONTEXT_BETA1_DMA_NOTIFY 0x00000180
-#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300
-
-
-#define NV_IMAGE_ROP_AND 0x00000013
-
-#define NV_IMAGE_ROP_AND_NOTIFY 0x00000104
-#define NV_IMAGE_ROP_AND_DMA_NOTIFY 0x00000180
-#define NV_IMAGE_ROP_AND_IMAGE_OUTPUT 0x00000200
-#define NV_IMAGE_ROP_AND_ROP_INPUT 0x00000204
-#define NV_IMAGE_ROP_AND_IMAGE_INPUT(x) (0x00000208+((x)*4))
-#define NV_IMAGE_ROP_AND_IMAGE_INPUT__SIZE 0x00000002
-
-
-#define NV_IMAGE_COLOR_KEY 0x00000015
-
-
-
-#define NV01_CONTEXT_COLOR_KEY 0x00000017
-
-#define NV01_CONTEXT_COLOR_KEY_NOP 0x00000100
-#define NV01_CONTEXT_COLOR_KEY_NOTIFY 0x00000104
-#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY 0x00000180
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT 0x00000300
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A8Y8 0x00000001
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X24Y8 0x00000002
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5 0x00000003
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X17R5G5B5 0x00000004
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8 0x00000005
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X8R8G8B8 0x00000006
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16Y16 0x00000007
-#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16Y16 0x00000008
-#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304
-
-
-#define NV01_CONTEXT_PATTERN 0x00000018
-
-#define NV01_CONTEXT_PATTERN_NOP 0x00000100
-#define NV01_CONTEXT_PATTERN_NOTIFY 0x00000104
-#define NV01_CONTEXT_PATTERN_DMA_NOTIFY 0x00000180
-#define NV01_CONTEXT_PATTERN_COLOR_FORMAT 0x00000300
-#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT 0x00000304
-#define NV01_CONTEXT_PATTERN_SHAPE 0x00000308
-#define NV01_CONTEXT_PATTERN_COLOR(x) (0x00000310+((x)*4))
-#define NV01_CONTEXT_PATTERN_COLOR__SIZE 0x00000002
-#define NV01_CONTEXT_PATTERN_PATTERN(x) (0x00000318+((x)*4))
-#define NV01_CONTEXT_PATTERN_PATTERN__SIZE 0x00000002
-
-
-#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019
-
-#define NV01_CONTEXT_CLIP_RECTANGLE_NOP 0x00000100
-#define NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY 0x00000104
-#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180
-#define NV01_CONTEXT_CLIP_RECTANGLE_POINT 0x00000300
-#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_SHIFT 0
-#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_MASK 0x0000ffff
-#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_SHIFT 16
-#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_MASK 0xffff0000
-#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE 0x00000304
-#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_SHIFT 0
-#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_MASK 0x0000ffff
-#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_SHIFT 16
-#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_MASK 0xffff0000
-
-
-#define NV01_RENDER_SOLID_LINE 0x0000001c
-
-#define NV01_RENDER_SOLID_LINE_NOP 0x00000100
-#define NV01_RENDER_SOLID_LINE_NOTIFY 0x00000104
-#define NV01_RENDER_SOLID_LINE_PATCH 0x0000010c
-#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY 0x00000180
-#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE 0x00000184
-#define NV01_RENDER_SOLID_LINE_PATTERN 0x00000188
-#define NV01_RENDER_SOLID_LINE_ROP 0x0000018c
-#define NV01_RENDER_SOLID_LINE_BETA1 0x00000190
-#define NV01_RENDER_SOLID_LINE_SURFACE 0x00000194
-#define NV01_RENDER_SOLID_LINE_OPERATION 0x000002fc
-#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND 0x00000000
-#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND 0x00000001
-#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND 0x00000002
-#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY 0x00000003
-#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT 0x00000005
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT 0x00000300
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A8Y8 0x00000001
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X24Y8 0x00000002
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5 0x00000003
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X17R5G5B5 0x00000004
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8 0x00000005
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X8R8G8B8 0x00000006
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16Y16 0x00000007
-#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16Y16 0x00000008
-#define NV01_RENDER_SOLID_LINE_COLOR 0x00000304
-#define NV01_RENDER_SOLID_LINE_LINE_POINT0(x) (0x00000400+((x)*8))
-#define NV01_RENDER_SOLID_LINE_LINE_POINT0__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X_SHIFT 0
-#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_SHIFT 16
-#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_LINE_LINE_POINT1(x) (0x00000404+((x)*8))
-#define NV01_RENDER_SOLID_LINE_LINE_POINT1__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X_SHIFT 0
-#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_SHIFT 16
-#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(x) (0x00000480+((x)*16))
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(x) (0x00000484+((x)*16))
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(x) (0x00000488+((x)*16))
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(x) (0x0000048c+((x)*16))
-#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_POLYLINE(x) (0x00000500+((x)*4))
-#define NV01_RENDER_SOLID_LINE_POLYLINE__SIZE 0x00000020
-#define NV01_RENDER_SOLID_LINE_POLYLINE_X_SHIFT 0
-#define NV01_RENDER_SOLID_LINE_POLYLINE_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_LINE_POLYLINE_Y_SHIFT 16
-#define NV01_RENDER_SOLID_LINE_POLYLINE_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(x) (0x00000580+((x)*8))
-#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(x) (0x00000584+((x)*8))
-#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(x) (0x00000600+((x)*8))
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(x) (0x00000604+((x)*8))
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__SIZE 0x00000010
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_SHIFT 0
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_SHIFT 16
-#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_MASK 0xffff0000
-
-
-#define NV01_RENDER_SOLID_TRIANGLE 0x0000001d
-
-#define NV01_RENDER_SOLID_TRIANGLE_NOP 0x00000100
-#define NV01_RENDER_SOLID_TRIANGLE_NOTIFY 0x00000104
-#define NV01_RENDER_SOLID_TRIANGLE_PATCH 0x0000010c
-#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY 0x00000180
-#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE 0x00000184
-#define NV01_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188
-#define NV01_RENDER_SOLID_TRIANGLE_ROP 0x0000018c
-#define NV01_RENDER_SOLID_TRIANGLE_BETA1 0x00000190
-#define NV01_RENDER_SOLID_TRIANGLE_SURFACE 0x00000194
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION 0x000002fc
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND 0x00000000
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND 0x00000001
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND 0x00000002
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY 0x00000003
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT 0x00000005
-#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT 0x00000300
-#define NV01_RENDER_SOLID_TRIANGLE_COLOR 0x00000304
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0 0x00000310
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1 0x00000314
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2 0x00000318
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X 0x00000320
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y 0x00000324
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X 0x00000328
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y 0x0000032c
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X 0x00000330
-#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y 0x00000334
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(x) (0x00000400+((x)*4))
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__SIZE 0x00000020
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(x) (0x00000480+((x)*8))
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__SIZE 0x00000010
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(x) (0x00000484+((x)*8))
-#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__SIZE 0x00000010
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(x) (0x00000500+((x)*16))
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__SIZE 0x00000008
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(x) (0x00000504+((x)*16))
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__SIZE 0x00000008
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(x) (0x00000508+((x)*16))
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__SIZE 0x00000008
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(x) (0x0000050c+((x)*16))
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__SIZE 0x00000008
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(x) (0x00000580+((x)*8))
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__SIZE 0x00000010
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(x) (0x00000584+((x)*8))
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__SIZE 0x00000010
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_SHIFT 0
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_SHIFT 16
-#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_MASK 0xffff0000
-
-
-#define NV01_RENDER_SOLID_RECTANGLE 0x0000001e
-
-#define NV01_RENDER_SOLID_RECTANGLE_NOP 0x00000100
-#define NV01_RENDER_SOLID_RECTANGLE_NOTIFY 0x00000104
-#define NV01_RENDER_SOLID_RECTANGLE_PATCH 0x0000010c
-#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY 0x00000180
-#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE 0x00000184
-#define NV01_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188
-#define NV01_RENDER_SOLID_RECTANGLE_ROP 0x0000018c
-#define NV01_RENDER_SOLID_RECTANGLE_BETA1 0x00000190
-#define NV01_RENDER_SOLID_RECTANGLE_SURFACE 0x00000194
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION 0x000002fc
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND 0x00000000
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND 0x00000001
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND 0x00000002
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY 0x00000003
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT 0x00000005
-#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT 0x00000300
-#define NV01_RENDER_SOLID_RECTANGLE_COLOR 0x00000304
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(x) (0x00000400+((x)*8))
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__SIZE 0x00000010
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_SHIFT 0
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_SHIFT 16
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_MASK 0xffff0000
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(x) (0x00000404+((x)*8))
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__SIZE 0x00000010
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_SHIFT 0
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_MASK 0x0000ffff
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_SHIFT 16
-#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_MASK 0xffff0000
-
-
-#define NV01_IMAGE_BLIT 0x0000001f
-
-#define NV01_IMAGE_BLIT_NOP 0x00000100
-#define NV01_IMAGE_BLIT_NOTIFY 0x00000104
-#define NV01_IMAGE_BLIT_PATCH 0x0000010c
-#define NV01_IMAGE_BLIT_DMA_NOTIFY 0x00000180
-#define NV01_IMAGE_BLIT_COLOR_KEY 0x00000184
-#define NV01_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188
-#define NV01_IMAGE_BLIT_PATTERN 0x0000018c
-#define NV01_IMAGE_BLIT_ROP 0x00000190
-#define NV01_IMAGE_BLIT_BETA1 0x00000194
-#define NV01_IMAGE_BLIT_SURFACE 0x0000019c
-#define NV01_IMAGE_BLIT_OPERATION 0x000002fc
-#define NV01_IMAGE_BLIT_IMAGE_INPUT 0x00000204
-#define NV01_IMAGE_BLIT_POINT_IN 0x00000300
-#define NV01_IMAGE_BLIT_POINT_IN_X_SHIFT 0
-#define NV01_IMAGE_BLIT_POINT_IN_X_MASK 0x0000ffff
-#define NV01_IMAGE_BLIT_POINT_IN_Y_SHIFT 16
-#define NV01_IMAGE_BLIT_POINT_IN_Y_MASK 0xffff0000
-#define NV01_IMAGE_BLIT_POINT_OUT 0x00000304
-#define NV01_IMAGE_BLIT_POINT_OUT_X_SHIFT 0
-#define NV01_IMAGE_BLIT_POINT_OUT_X_MASK 0x0000ffff
-#define NV01_IMAGE_BLIT_POINT_OUT_Y_SHIFT 16
-#define NV01_IMAGE_BLIT_POINT_OUT_Y_MASK 0xffff0000
-#define NV01_IMAGE_BLIT_SIZE 0x00000308
-#define NV01_IMAGE_BLIT_SIZE_W_SHIFT 0
-#define NV01_IMAGE_BLIT_SIZE_W_MASK 0x0000ffff
-#define NV01_IMAGE_BLIT_SIZE_H_SHIFT 16
-#define NV01_IMAGE_BLIT_SIZE_H_MASK 0xffff0000
-
-
-#define NV01_IMAGE_FROM_CPU 0x00000021
-
-#define NV01_IMAGE_FROM_CPU_NOP 0x00000100
-#define NV01_IMAGE_FROM_CPU_NOTIFY 0x00000104
-#define NV01_IMAGE_FROM_CPU_PATCH 0x0000010c
-#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
-#define NV01_IMAGE_FROM_CPU_COLOR_KEY 0x00000184
-#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188
-#define NV01_IMAGE_FROM_CPU_PATTERN 0x0000018c
-#define NV01_IMAGE_FROM_CPU_ROP 0x00000190
-#define NV01_IMAGE_FROM_CPU_BETA1 0x00000194
-#define NV01_IMAGE_FROM_CPU_SURFACE 0x00000198
-#define NV01_IMAGE_FROM_CPU_OPERATION 0x000002fc
-#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND 0x00000000
-#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND 0x00000001
-#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND 0x00000002
-#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY 0x00000003
-#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT 0x00000005
-#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300
-#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_Y8 0x00000001
-#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5 0x00000002
-#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5 0x00000003
-#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8 0x00000004
-#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8 0x00000005
-#define NV01_IMAGE_FROM_CPU_POINT 0x00000304
-#define NV01_IMAGE_FROM_CPU_POINT_X_SHIFT 0
-#define NV01_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff
-#define NV01_IMAGE_FROM_CPU_POINT_Y_SHIFT 16
-#define NV01_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000
-#define NV01_IMAGE_FROM_CPU_SIZE_OUT 0x00000308
-#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W_SHIFT 0
-#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W_MASK 0x0000ffff
-#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H_SHIFT 16
-#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H_MASK 0xffff0000
-#define NV01_IMAGE_FROM_CPU_SIZE_IN 0x0000030c
-#define NV01_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT 0
-#define NV01_IMAGE_FROM_CPU_SIZE_IN_W_MASK 0x0000ffff
-#define NV01_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT 16
-#define NV01_IMAGE_FROM_CPU_SIZE_IN_H_MASK 0xffff0000
-#define NV01_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4))
-#define NV01_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020
-
-
-#define NV01_NULL 0x00000030
-
-
-
-#define NV03_STRETCHED_IMAGE_FROM_CPU 0x00000036
-
-#define NV03_STRETCHED_IMAGE_FROM_CPU_NOP 0x00000100
-#define NV03_STRETCHED_IMAGE_FROM_CPU_NOTIFY 0x00000104
-#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH 0x0000010c
-#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
-#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184
-#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188
-#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP 0x0000018c
-#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1 0x00000190
-#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000194
-#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION 0x000002fc
-#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300
-#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN 0x00000304
-#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT 0
-#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_MASK 0x0000ffff
-#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT 16
-#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_MASK 0xffff0000
-#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU 0x00000308
-#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV 0x0000030c
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT 0x00000310
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_SHIFT 0
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_MASK 0x0000ffff
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_SHIFT 16
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_MASK 0xffff0000
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE 0x00000314
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_SHIFT 0
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_MASK 0x0000ffff
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_SHIFT 16
-#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_MASK 0xffff0000
-#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4 0x00000318
-#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_SHIFT 0
-#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_MASK 0x0000ffff
-#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_SHIFT 16
-#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_MASK 0xffff0000
-#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4))
-#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020
-
-
-#define NV03_SCALED_IMAGE_FROM_MEMORY 0x00000037
-
-#define NV03_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100
-#define NV03_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104
-#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180
-#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184
-#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188
-#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c
-#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190
-#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000194
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008
-#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK 0xffff0000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK 0xffff0000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT 0x00000310
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_X_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_X_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_Y_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_Y_MASK 0xffff0000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE 0x00000314
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_W_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_W_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_H_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_H_MASK 0xffff0000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_DELTA_DU_DX 0x00000318
-#define NV03_SCALED_IMAGE_FROM_MEMORY_DELTA_DV_DY 0x0000031c
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE 0x00000400
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_W_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_W_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_H_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_H_MASK 0xffff0000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT 0x00000404
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_PITCH_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_PITCH_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_MASK 0x00ff0000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_CENTER 0x00010000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_CORNER 0x00020000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_INTERPOLATOR_SHIFT 24
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_INTERPOLATOR_MASK 0xff000000
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_OFFSET 0x00000408
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT 0x0000040c
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_U_SHIFT 0
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_U_MASK 0x0000ffff
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_V_SHIFT 16
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_V_MASK 0xffff0000
-
-
-#define NV04_DVD_SUBPICTURE 0x00000038
-
-#define NV04_DVD_SUBPICTURE_NOP 0x00000100
-#define NV04_DVD_SUBPICTURE_NOTIFY 0x00000104
-#define NV04_DVD_SUBPICTURE_WAIT_FOR_IDLE 0x00000108
-#define NV04_DVD_SUBPICTURE_DMA_NOTIFY 0x00000180
-#define NV04_DVD_SUBPICTURE_DMA_OVERLAY 0x00000184
-#define NV04_DVD_SUBPICTURE_DMA_IMAGEIN 0x00000188
-#define NV04_DVD_SUBPICTURE_DMA_IMAGEOUT 0x0000018c
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT 0x00000300
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_SHIFT 0
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_SHIFT 16
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE 0x00000304
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_SHIFT 0
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_SHIFT 16
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT 0x00000308
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_SHIFT 0
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_SHIFT 16
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_IMAGEOUT_OFFSET 0x0000030c
-#define NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DU_DX 0x00000310
-#define NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DV_DY 0x00000314
-#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE 0x00000318
-#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_SHIFT 0
-#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_SHIFT 16
-#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT 0x0000031c
-#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_SHIFT 0
-#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_SHIFT 16
-#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_IMAGEIN_OFFSET 0x00000320
-#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT 0x00000324
-#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_SHIFT 0
-#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_SHIFT 16
-#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DU_DX 0x00000328
-#define NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DV_DY 0x0000032c
-#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE 0x00000330
-#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_SHIFT 0
-#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_SHIFT 16
-#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT 0x00000334
-#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_SHIFT 0
-#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_SHIFT 16
-#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_MASK 0xffff0000
-#define NV04_DVD_SUBPICTURE_OVERLAY_OFFSET 0x00000338
-#define NV04_DVD_SUBPICTURE_OVERLAY_POINT 0x0000033c
-#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_SHIFT 0
-#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_MASK 0x0000ffff
-#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_SHIFT 16
-#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_MASK 0xffff0000
-
-
-#define NV04_MEMORY_TO_MEMORY_FORMAT 0x00000039
-
-#define NV04_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
-#define NV04_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
-#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
-#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN 0x00000184
-#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT 0x00000188
-#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
-#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310
-#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314
-#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318
-#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c
-#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT 0
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK 0x0000000f
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT 8
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK 0x00000f00
-#define NV04_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328
-
-
-#define NV01_MEMORY_LOCAL_BANKED 0x0000003d
-
-
-
-#define NV01_MAPPING_SYSTEM 0x0000003e
-
-
-
-#define NV03_MEMORY_LOCAL_CURSOR 0x0000003f
-
-
-
-#define NV01_MEMORY_LOCAL_LINEAR 0x00000040
-
-
-
-#define NV01_MAPPING_LOCAL 0x00000041
-
-
-
-#define NV04_CONTEXT_SURFACES_2D 0x00000042
-
-#define NV04_CONTEXT_SURFACES_2D_NOP 0x00000100
-#define NV04_CONTEXT_SURFACES_2D_NOTIFY 0x00000104
-#define NV04_CONTEXT_SURFACES_2D_PM_TRIGGER 0x00000140
-#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180
-#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE 0x00000184
-#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN 0x00000188
-#define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8 0x00000001
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5 0x00000002
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5 0x00000003
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5 0x00000004
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16 0x00000005
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8 0x00000006
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8 0x00000007
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x00000008
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8 0x00000009
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8 0x0000000a
-#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32 0x0000000b
-#define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304
-#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT 0
-#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK 0x0000ffff
-#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT 16
-#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK 0xffff0000
-#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308
-#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c
-
-
-#define NV03_CONTEXT_ROP 0x00000043
-
-#define NV03_CONTEXT_ROP_NOP 0x00000100
-#define NV03_CONTEXT_ROP_NOTIFY 0x00000104
-#define NV03_CONTEXT_ROP_DMA_NOTIFY 0x00000180
-#define NV03_CONTEXT_ROP_ROP 0x00000300
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SHIFT 0
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_MASK 0x0000000f
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_CLEAR 0x00000000
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOR 0x00000001
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_INVERTED 0x00000002
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY_INVERTED 0x00000003
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_REVERSE 0x00000004
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_INVERT 0x00000005
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_XOR 0x00000006
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NAND 0x00000007
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND 0x00000008
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_EQUI 0x00000009
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOOP 0x0000000a
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_INVERTED 0x0000000b
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY 0x0000000c
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_REVERSE 0x0000000d
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR 0x0000000e
-#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SET 0x0000000f
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SHIFT 4
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_MASK 0x000000f0
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_CLEAR 0x00000000
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOR 0x00000010
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_INVERTED 0x00000020
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY_INVERTED 0x00000030
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_REVERSE 0x00000040
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_INVERT 0x00000050
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_XOR 0x00000060
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NAND 0x00000070
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND 0x00000080
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_EQUI 0x00000090
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOOP 0x000000a0
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_INVERTED 0x000000b0
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY 0x000000c0
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_REVERSE 0x000000d0
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR 0x000000e0
-#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SET 0x000000f0
-
-
-#define NV04_IMAGE_PATTERN 0x00000044
-
-#define NV04_IMAGE_PATTERN_NOP 0x00000100
-#define NV04_IMAGE_PATTERN_NOTIFY 0x00000104
-#define NV04_IMAGE_PATTERN_DMA_NOTIFY 0x00000180
-#define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300
-#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5 0x00000001
-#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5 0x00000002
-#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8 0x00000003
-#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT 0x00000304
-#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6 0x00000001
-#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE 0x00000002
-#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308
-#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8 0x00000000
-#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1 0x00000001
-#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64 0x00000002
-#define NV04_IMAGE_PATTERN_PATTERN_SELECT 0x0000030c
-#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO 0x00000001
-#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR 0x00000002
-#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310
-#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314
-#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318
-#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c
-#define NV04_IMAGE_PATTERN_PATTERN_Y8(x) (0x00000400+((x)*4))
-#define NV04_IMAGE_PATTERN_PATTERN_Y8__SIZE 0x00000010
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_SHIFT 0
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_MASK 0x000000ff
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_SHIFT 8
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_MASK 0x0000ff00
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_SHIFT 16
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_MASK 0x00ff0000
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_SHIFT 24
-#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_MASK 0xff000000
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(x) (0x00000500+((x)*4))
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__SIZE 0x00000020
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_SHIFT 0
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_MASK 0x0000001f
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_SHIFT 5
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_MASK 0x000007e0
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_SHIFT 11
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_MASK 0x0000f800
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_SHIFT 16
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_MASK 0x001f0000
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_SHIFT 21
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_MASK 0x07e00000
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_SHIFT 27
-#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_MASK 0xf8000000
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(x) (0x00000600+((x)*4))
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__SIZE 0x00000020
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_SHIFT 0
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_MASK 0x0000001f
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_SHIFT 5
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_MASK 0x000003e0
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_SHIFT 10
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_MASK 0x00007c00
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_SHIFT 16
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_MASK 0x001f0000
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_SHIFT 21
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_MASK 0x03e00000
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_SHIFT 26
-#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_MASK 0x7c000000
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(x) (0x00000700+((x)*4))
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__SIZE 0x00000040
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_SHIFT 0
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_MASK 0x000000ff
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_SHIFT 8
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_MASK 0x0000ff00
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_SHIFT 16
-#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_MASK 0x00ff0000
-
-
-#define NV03_VIDEO_LUT_CURSOR_DAC 0x00000046
-
-#define NV03_VIDEO_LUT_CURSOR_DAC_SYNCHRONIZE 0x00000100
-#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_IMAGE 0x00000104
-#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_CURSOR 0x00000108
-#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_DAC 0x0000010c
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_NOTIFY 0x00000180
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE(x) (0x00000184+((x)*4))
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT(x) (0x0000018c+((x)*4))
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR(x) (0x00000194+((x)*4))
-#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_GET 0x000002fc
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET(x) (0x00000300+((x)*8))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT(x) (0x00000304+((x)*8))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_MASK 0x0fff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_SHIFT 28
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_MASK 0xf0000000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET(x) (0x00000340+((x)*12))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT(x) (0x00000344+((x)*12))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_MASK 0xffff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT(x) (0x00000348+((x)*12))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A 0x00000358
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_MASK 0xffff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE(x) (0x00000380+((x)*16))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_MASK 0xffff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC(x) (0x00000384+((x)*16))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_MASK 0x0fff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_SHIFT 28
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_MASK 0xf0000000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC(x) (0x00000388+((x)*16))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_MASK 0x0fff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_SHIFT 28
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_MASK 0xf0000000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE(x) (0x0000038c+((x)*16))
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE__SIZE 0x00000002
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_SHIFT 0
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_MASK 0x0000ffff
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_SHIFT 16
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_MASK 0x0fff0000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_SHIFT 28
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_MASK 0xf0000000
-#define NV03_VIDEO_LUT_CURSOR_DAC_SET_PIXEL_CLOCK 0x000003a0
-
-
-#define NV03_DX3_TEXTURED_TRIANGLE 0x00000048
-
-#define NV03_DX3_TEXTURED_TRIANGLE_NOP 0x00000100
-#define NV03_DX3_TEXTURED_TRIANGLE_NOTIFY 0x00000104
-#define NV03_DX3_TEXTURED_TRIANGLE_PATCH 0x0000010c
-#define NV03_DX3_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
-#define NV03_DX3_TEXTURED_TRIANGLE_DMA_TEXTURE 0x00000184
-#define NV03_DX3_TEXTURED_TRIANGLE_CLIP_RECTANGLE 0x00000188
-#define NV03_DX3_TEXTURED_TRIANGLE_SURFACE 0x0000018c
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK 0x0000ffff
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT 16
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK 0x000f0000
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 20
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00f00000
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT 24
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK 0x0f000000
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT 28
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK 0xf0000000
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER 0x0000030c
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK 0x0000001f
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT 8
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK 0x00001f00
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT 16
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK 0x00ff0000
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR 0x00000310
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK 0x000000ff
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT 8
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK 0x0000ff00
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT 16
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK 0x00ff0000
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT 0x00000314
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK 0x0000000f
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT 4
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK 0x00000030
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT 6
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK 0x000000c0
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT 8
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK 0x00000f00
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT 12
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK 0x00007000
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE (1 << 15)
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT 16
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK 0x000f0000
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT 20
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK 0x00f00000
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT 24
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK 0x07000000
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT 27
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK 0x18000000
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_BETA (1 << 29)
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND (1 << 30)
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND (1 << 31)
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL 0x00000318
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK 0x000000ff
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT 8
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK 0xffffff00
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR(x) (0x00001000+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_MASK 0x0000000f
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_SHIFT 4
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_MASK 0x000000f0
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_SHIFT 8
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_MASK 0x00000f00
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_SHIFT 12
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_MASK 0x0000f000
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I4_SHIFT 16
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I4_MASK 0x000f0000
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I5_SHIFT 20
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I5_MASK 0x00f00000
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_FOG_SHIFT 24
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_FOG_MASK 0xff000000
-#define NV03_DX3_TEXTURED_TRIANGLE_COLOR(x) (0x00001004+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_COLOR__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_X(x) (0x00001008+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_X__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_Y(x) (0x0000100c+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_Y__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_Z(x) (0x00001010+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_Z__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_M(x) (0x00001014+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_M__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_U(x) (0x00001018+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_U__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_V(x) (0x0000101c+((x)*32))
-#define NV03_DX3_TEXTURED_TRIANGLE_V__SIZE 0x00000040
-
-
-#define NV04_GDI_RECTANGLE_TEXT 0x0000004a
-
-#define NV04_GDI_RECTANGLE_TEXT_NOP 0x00000100
-#define NV04_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104
-#define NV04_GDI_RECTANGLE_TEXT_PATCH 0x0000010c
-#define NV04_GDI_RECTANGLE_TEXT_PM_TRIGGER 0x00000140
-#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180
-#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS 0x00000184
-#define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188
-#define NV04_GDI_RECTANGLE_TEXT_ROP 0x0000018c
-#define NV04_GDI_RECTANGLE_TEXT_BETA1 0x00000190
-#define NV04_GDI_RECTANGLE_TEXT_BETA4 0x00000194
-#define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND 0x00000000
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND 0x00000001
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND 0x00000002
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY 0x00000003
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT 0x00000005
-#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300
-#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5 0x00000001
-#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5 0x00000002
-#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8 0x00000003
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6 0x00000001
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE 0x00000002
-#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(x) (0x00000400+((x)*8))
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__SIZE 0x00000020
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(x) (0x00000404+((x)*8))
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__SIZE 0x00000020
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0 0x000005f4
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1 0x000005f8
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B 0x000005fc
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(x) (0x00000600+((x)*8))
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__SIZE 0x00000020
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(x) (0x00000604+((x)*8))
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__SIZE 0x00000020
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x000007ec
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x000007f0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C 0x000007f4
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_C 0x000007f8
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_POINT_C 0x000007fc
-#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x) (0x00000800+((x)*4))
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE 0x00000080
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x00000be4
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x00000be8
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E 0x00000bec
-#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E 0x00000bf0
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x00000bf4
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x00000bf8
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_POINT_E 0x00000bfc
-#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x) (0x00000c00+((x)*4))
-#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE 0x00000080
-#define NV04_GDI_RECTANGLE_TEXT_FONT_F 0x00000ff0
-#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_MASK 0x0fffffff
-#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_SHIFT 28
-#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_MASK 0xf0000000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0 0x00000ff4
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1 0x00000ff8
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F 0x00000ffc
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(x) (0x00001000+((x)*4))
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__SIZE 0x00000100
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_MASK 0x000000ff
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_SHIFT 8
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_MASK 0x000fff00
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_SHIFT 20
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_MASK 0xfff00000
-#define NV04_GDI_RECTANGLE_TEXT_FONT_G 0x000017f0
-#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_MASK 0x0fffffff
-#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_SHIFT 28
-#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_MASK 0xf0000000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0 0x000017f4
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1 0x000017f8
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G 0x000017fc
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(x) (0x00001800+((x)*8))
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__SIZE 0x00000100
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_SHIFT 0
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_MASK 0x0000ffff
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_SHIFT 16
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_MASK 0xffff0000
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(x) (0x00001804+((x)*8))
-#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__SIZE 0x00000100
-
-
-#define NV03_GDI_RECTANGLE_TEXT 0x0000004b
-
-#define NV03_GDI_RECTANGLE_TEXT_NOP 0x00000100
-#define NV03_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104
-#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180
-#define NV03_GDI_RECTANGLE_TEXT_PATTERN 0x00000184
-#define NV03_GDI_RECTANGLE_TEXT_ROP 0x00000188
-#define NV03_GDI_RECTANGLE_TEXT_BETA1 0x0000018c
-#define NV03_GDI_RECTANGLE_TEXT_SURFACE 0x00000190
-#define NV03_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc
-#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304
-#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT 0x00000400
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE 0x00000404
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B 0x000007f4
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B 0x000007f8
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B 0x000007fc
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0 0x00000800
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1 0x00000804
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x00000bec
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x00000bf0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C 0x00000bf4
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_C 0x00000bf8
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_POINT_C 0x00000bfc
-#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x) (0x00000c00+((x)*4))
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE 0x00000020
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0 0x00000fe8
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1 0x00000fec
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D 0x00000ff0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D 0x00000ff4
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D 0x00000ff8
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_POINT_D 0x00000ffc
-#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(x) (0x00001000+((x)*4))
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__SIZE 0x00000020
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x000013e4
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x000013e8
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E 0x000013ec
-#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E 0x000013f0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x000013f4
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x000013f8
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_POINT_E 0x000013fc
-#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT 0
-#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X_MASK 0x0000ffff
-#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT 16
-#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK 0xffff0000
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x) (0x00001400+((x)*4))
-#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE 0x00000020
-
-
-#define NV04_SWIZZLED_SURFACE 0x00000052
-
-#define NV04_SWIZZLED_SURFACE_NOP 0x00000100
-#define NV04_SWIZZLED_SURFACE_NOTIFY 0x00000104
-#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180
-#define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184
-#define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_SHIFT 0
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x000000ff
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8 0x00000001
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000002
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000003
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5 0x00000004
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16 0x00000005
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000006
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000007
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000008
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000009
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8 0x0000000a
-#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32 0x0000000b
-#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT 16
-#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_MASK 0x00ff0000
-#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT 24
-#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_MASK 0xff000000
-#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304
-
-
-#define NV04_CONTEXT_SURFACES_3D 0x00000053
-
-#define NV04_CONTEXT_SURFACES_3D_NOP 0x00000100
-#define NV04_CONTEXT_SURFACES_3D_NOTIFY 0x00000104
-#define NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180
-#define NV04_CONTEXT_SURFACES_3D_DMA_COLOR 0x00000184
-#define NV04_CONTEXT_SURFACES_3D_DMA_ZETA 0x00000188
-#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL 0x000002f8
-#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_SHIFT 0
-#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK 0x0000ffff
-#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_SHIFT 16
-#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_MASK 0xffff0000
-#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL 0x000002fc
-#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_SHIFT 0
-#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK 0x0000ffff
-#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_SHIFT 16
-#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_MASK 0xffff0000
-#define NV04_CONTEXT_SURFACES_3D_FORMAT 0x00000300
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_SHIFT 0
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK 0x000000ff
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000001
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000002
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5 0x00000003
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000004
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000005
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000006
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000007
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8 0x00000008
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT 8
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK 0x0000ff00
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_PITCH 0x00000100
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SWIZZLE 0x00000200
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_SHIFT 16
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_MASK 0x00ff0000
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_SHIFT 24
-#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_MASK 0xff000000
-#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE 0x00000304
-#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_SHIFT 0
-#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_MASK 0x0000ffff
-#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_SHIFT 16
-#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_MASK 0xffff0000
-#define NV04_CONTEXT_SURFACES_3D_PITCH 0x00000308
-#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_SHIFT 0
-#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK 0x0000ffff
-#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT 16
-#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK 0xffff0000
-#define NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x0000030c
-#define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000310
-
-
-#define NV04_DX5_TEXTURED_TRIANGLE 0x00000054
-
-#define NV04_DX5_TEXTURED_TRIANGLE_NOP 0x00000100
-#define NV04_DX5_TEXTURED_TRIANGLE_NOTIFY 0x00000104
-#define NV04_DX5_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
-#define NV04_DX5_TEXTURED_TRIANGLE_DMA_A 0x00000184
-#define NV04_DX5_TEXTURED_TRIANGLE_DMA_B 0x00000188
-#define NV04_DX5_TEXTURED_TRIANGLE_SURFACE 0x0000018c
-#define NV04_DX5_TEXTURED_TRIANGLE_COLORKEY 0x00000300
-#define NV04_DX5_TEXTURED_TRIANGLE_OFFSET 0x00000304
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT 0x00000308
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_DMA_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_DMA_MASK 0x00000003
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT 2
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK 0x0000000c
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER 0x00000020
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER 0x00000040
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER 0x00000080
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8 0x00000100
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5 0x00000200
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5 0x00000300
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4 0x00000400
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5 0x00000500
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8 0x00000600
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8 0x00000700
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT 0x01000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT 0x02000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE 0x03000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER 0x04000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP 0x05000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_WRAPU (1 << 27)
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT 0x10000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT 0x20000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE 0x30000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER 0x40000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP 0x50000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_WRAPV (1 << 31)
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER 0x0000030c
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15)
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK 0x07000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST 0x01000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR 0x02000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27)
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT 28
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST 0x10000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR 0x20000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31)
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND 0x00000310
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK 0x0000000f
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT 4
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_MASK 0x00000f00
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT 12
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK 0x0000f000
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE_MASK 0x000f0000
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_ALPHA_ENABLE_SHIFT 20
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_ALPHA_ENABLE_MASK 0x00f00000
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL 0x00000314
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK 0x000000ff
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK 0x00000f00
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_TEST_ENABLE (1 << 12)
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ORIGIN (1 << 13)
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_SHIFT 14
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_MASK 0x0000c000
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK 0x000f0000
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT 20
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK 0x00300000
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE (1 << 22)
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE (1 << 23)
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_MASK 0x3f000000
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT 30
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK 0xc0000000
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR 0x00000318
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK 0xff000000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00000400+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x00000404+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00000408+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x0000040c+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00000410+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK 0x000000ff
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK 0x0000ff00
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK 0x00ff0000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK 0xff000000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00000414+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK 0x000000ff
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK 0x0000ff00
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK 0x00ff0000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00000418+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000041c+((x)*32))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000010
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE(x) (0x00000600+((x)*4))
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE__SIZE 0x00000040
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I0_SHIFT 0
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I0_MASK 0x0000000f
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I1_SHIFT 4
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I1_MASK 0x000000f0
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I2_SHIFT 8
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I2_MASK 0x00000f00
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I3_SHIFT 12
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I3_MASK 0x0000f000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I4_SHIFT 16
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I4_MASK 0x000f0000
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I5_SHIFT 20
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I5_MASK 0x00f00000
-
-
-#define NV04_DX6_MULTITEX_TRIANGLE 0x00000055
-
-#define NV04_DX6_MULTITEX_TRIANGLE_NOP 0x00000100
-#define NV04_DX6_MULTITEX_TRIANGLE_NOTIFY 0x00000104
-#define NV04_DX6_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180
-#define NV04_DX6_MULTITEX_TRIANGLE_DMA_A 0x00000184
-#define NV04_DX6_MULTITEX_TRIANGLE_DMA_B 0x00000188
-#define NV04_DX6_MULTITEX_TRIANGLE_SURFACE 0x0000018c
-#define NV04_DX6_MULTITEX_TRIANGLE_OFFSET(x) (0x00000308+((x)*4))
-#define NV04_DX6_MULTITEX_TRIANGLE_OFFSET__SIZE 0x00000002
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT(x) (0x00000310+((x)*4))
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT__SIZE 0x00000002
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_DMA_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_DMA_MASK 0x0000000f
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_WRAPU (1 << 27)
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_WRAPV (1 << 31)
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER(x) (0x00000318+((x)*4))
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER__SIZE 0x00000002
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15)
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK 0x07000000
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27)
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT 28
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA 0x00000320
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE0 (1 << 0)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA0 (1 << 1)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT0_SHIFT 2
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT0_MASK 0x000000fc
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE1 (1 << 8)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA1 (1 << 9)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT1_SHIFT 10
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT1_MASK 0x0000fc00
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE2 (1 << 16)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA2 (1 << 17)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT2_SHIFT 18
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT2_MASK 0x00fc0000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE3 (1 << 24)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA3 (1 << 25)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT3_SHIFT 26
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT3_MASK 0x1c000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_OPERATION_SHIFT 29
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_OPERATION_MASK 0xe0000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR 0x00000324
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE0 (1 << 0)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA0 (1 << 1)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT0_SHIFT 2
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT0_MASK 0x000000fc
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE1 (1 << 8)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA1 (1 << 9)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT1_SHIFT 10
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT1_MASK 0x0000fc00
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE2 (1 << 16)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA2 (1 << 17)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT2_SHIFT 18
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT2_MASK 0x00fc0000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE3 (1 << 24)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA3 (1 << 25)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT3_SHIFT 26
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT3_MASK 0x1c000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_OPERATION_SHIFT 29
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_OPERATION_MASK 0xe0000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA 0x0000032c
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE0 (1 << 0)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA0 (1 << 1)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT0_SHIFT 2
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT0_MASK 0x000000fc
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE1 (1 << 8)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA1 (1 << 9)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT1_SHIFT 10
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT1_MASK 0x0000fc00
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE2 (1 << 16)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA2 (1 << 17)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT2_SHIFT 18
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT2_MASK 0x00fc0000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE3 (1 << 24)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA3 (1 << 25)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT3_SHIFT 26
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT3_MASK 0x1c000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_OPERATION_SHIFT 29
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_OPERATION_MASK 0xe0000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR 0x00000330
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE0 (1 << 0)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA0 (1 << 1)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT0_SHIFT 2
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT0_MASK 0x000000fc
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE1 (1 << 8)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA1 (1 << 9)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT1_SHIFT 10
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT1_MASK 0x0000fc00
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE2 (1 << 16)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA2 (1 << 17)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT2_SHIFT 18
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT2_MASK 0x00fc0000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE3 (1 << 24)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA3 (1 << 25)
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT3_SHIFT 26
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT3_MASK 0x1c000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_OPERATION_SHIFT 29
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_OPERATION_MASK 0xe0000000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK 0x000000ff
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK 0x0000ff00
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK 0x00ff0000
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK 0xff000000
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND 0x00000338
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT 4
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_MASK 0x00000f00
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT 12
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK 0x0000f000
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE_MASK 0x000f0000
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_ALPHA_ENABLE_SHIFT 20
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_ALPHA_ENABLE_MASK 0x00f00000
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0 0x0000033c
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK 0x000000ff
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK 0x00000f00
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_TEST_ENABLE (1 << 12)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ORIGIN (1 << 13)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE_SHIFT 14
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE_MASK 0x0000c000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK 0x000f0000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT 20
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK 0x00300000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE (1 << 22)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 23)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE_ENABLE (1 << 24)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_ENABLE (1 << 25)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_ENABLE (1 << 26)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_ENABLE (1 << 27)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_ENABLE (1 << 28)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_ENABLE (1 << 29)
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT 30
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK 0xc0000000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1 0x00000340
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_TEST_ENABLE_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_TEST_ENABLE_MASK 0x0000000f
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT 4
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK 0x000000f0
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK 0x0000ff00
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2 0x00000344
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK 0x0000000f
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT 4
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK 0x000000f0
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK 0x00000f00
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR 0x00000348
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK 0xff000000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x) (0x00000400+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x) (0x00000404+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x) (0x00000408+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x) (0x0000040c+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x) (0x00000410+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK 0x000000ff
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK 0x0000ff00
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK 0x00ff0000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK 0xff000000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x) (0x00000414+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK 0x000000ff
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK 0x0000ff00
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK 0x00ff0000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT 24
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK 0xff000000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x) (0x00000418+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x) (0x0000041c+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x) (0x00000420+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x) (0x00000424+((x)*40))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE 0x00000008
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE(x) (0x00000540+((x)*4))
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE__SIZE 0x00000030
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I0_SHIFT 0
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I0_MASK 0x0000000f
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I1_SHIFT 4
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I1_MASK 0x000000f0
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I2_SHIFT 8
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I2_MASK 0x00000f00
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I3_SHIFT 12
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I3_MASK 0x0000f000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I4_SHIFT 16
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I4_MASK 0x000f0000
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I5_SHIFT 20
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I5_MASK 0x00f00000
-
-
-#define NV10_DX5_TEXTURED_TRIANGLE 0x00000094
-
-
-
-#define NV10TCL 0x00000056
-
-#define NV10TCL_NOP 0x00000100
-#define NV10TCL_NOTIFY 0x00000104
-#define NV10TCL_DMA_NOTIFY 0x00000180
-#define NV10TCL_DMA_IN_MEMORY0 0x00000184
-#define NV10TCL_DMA_IN_MEMORY1 0x00000188
-#define NV10TCL_DMA_VTXBUF0 0x0000018c
-#define NV10TCL_DMA_IN_MEMORY2 0x00000194
-#define NV10TCL_DMA_IN_MEMORY3 0x00000198
-#define NV10TCL_RT_HORIZ 0x00000200
-#define NV10TCL_RT_HORIZ_X_SHIFT 0
-#define NV10TCL_RT_HORIZ_X_MASK 0x0000ffff
-#define NV10TCL_RT_HORIZ_W_SHIFT 16
-#define NV10TCL_RT_HORIZ_W_MASK 0xffff0000
-#define NV10TCL_RT_VERT 0x00000204
-#define NV10TCL_RT_VERT_Y_SHIFT 0
-#define NV10TCL_RT_VERT_Y_MASK 0x0000ffff
-#define NV10TCL_RT_VERT_H_SHIFT 16
-#define NV10TCL_RT_VERT_H_MASK 0xffff0000
-#define NV10TCL_RT_FORMAT 0x00000208
-#define NV10TCL_RT_FORMAT_TYPE_SHIFT 8
-#define NV10TCL_RT_FORMAT_TYPE_MASK 0x00000f00
-#define NV10TCL_RT_FORMAT_TYPE_LINEAR 0x00000100
-#define NV10TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200
-#define NV10TCL_RT_FORMAT_COLOR_SHIFT 0
-#define NV10TCL_RT_FORMAT_COLOR_MASK 0x0000001f
-#define NV10TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003
-#define NV10TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005
-#define NV10TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008
-#define NV10TCL_RT_FORMAT_COLOR_B8 0x00000009
-#define NV10TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d
-#define NV10TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f
-#define NV10TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010
-#define NV10TCL_RT_PITCH 0x0000020c
-#define NV10TCL_RT_PITCH_COLOR_PITCH_SHIFT 0
-#define NV10TCL_RT_PITCH_COLOR_PITCH_MASK 0x0000ffff
-#define NV10TCL_RT_PITCH_ZETA_PITCH_SHIFT 16
-#define NV10TCL_RT_PITCH_ZETA_PITCH_MASK 0xffff0000
-#define NV10TCL_COLOR_OFFSET 0x00000210
-#define NV10TCL_ZETA_OFFSET 0x00000214
-#define NV10TCL_TX_OFFSET(x) (0x00000218+((x)*4))
-#define NV10TCL_TX_OFFSET__SIZE 0x00000002
-#define NV10TCL_TX_FORMAT(x) (0x00000220+((x)*4))
-#define NV10TCL_TX_FORMAT__SIZE 0x00000002
-#define NV10TCL_TX_FORMAT_DMA0 (1 << 0)
-#define NV10TCL_TX_FORMAT_DMA1 (1 << 1)
-#define NV10TCL_TX_FORMAT_CUBE_MAP (1 << 2)
-#define NV10TCL_TX_FORMAT_FORMAT_SHIFT 7
-#define NV10TCL_TX_FORMAT_FORMAT_MASK 0x00000780
-#define NV10TCL_TX_FORMAT_FORMAT_L8 0x00000000
-#define NV10TCL_TX_FORMAT_FORMAT_A8 0x00000080
-#define NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000100
-#define NV10TCL_TX_FORMAT_FORMAT_A8_RECT 0x00000180
-#define NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000200
-#define NV10TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000280
-#define NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000300
-#define NV10TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000380
-#define NV10TCL_TX_FORMAT_FORMAT_INDEX8 0x00000580
-#define NV10TCL_TX_FORMAT_FORMAT_DXT1 0x00000600
-#define NV10TCL_TX_FORMAT_FORMAT_DXT3 0x00000700
-#define NV10TCL_TX_FORMAT_FORMAT_DXT5 0x00000780
-#define NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00000800
-#define NV10TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00000880
-#define NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00000900
-#define NV10TCL_TX_FORMAT_FORMAT_L8_RECT 0x00000980
-#define NV10TCL_TX_FORMAT_FORMAT_A8L8 0x00000d00
-#define NV10TCL_TX_FORMAT_FORMAT_A8_RECT2 0x00000d80
-#define NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00000e80
-#define NV10TCL_TX_FORMAT_FORMAT_R8G8B8_RECT 0x00000f00
-#define NV10TCL_TX_FORMAT_FORMAT_L8A8_RECT 0x00001000
-#define NV10TCL_TX_FORMAT_FORMAT_DSDT 0x00001400
-#define NV10TCL_TX_FORMAT_FORMAT_A16 0x00001900
-#define NV10TCL_TX_FORMAT_FORMAT_HILO16 0x00001980
-#define NV10TCL_TX_FORMAT_FORMAT_A16_RECT 0x00001a80
-#define NV10TCL_TX_FORMAT_FORMAT_HILO16_RECT 0x00001b00
-#define NV10TCL_TX_FORMAT_FORMAT_HILO8 0x00002200
-#define NV10TCL_TX_FORMAT_FORMAT_SIGNED_HILO8 0x00002280
-#define NV10TCL_TX_FORMAT_FORMAT_HILO8_RECT 0x00002300
-#define NV10TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00002380
-#define NV10TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00002500
-#define NV10TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00002580
-#define NV10TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV 0x00002600
-#define NV10TCL_TX_FORMAT_NPOT (1 << 11)
-#define NV10TCL_TX_FORMAT_MIPMAP (1 << 15)
-#define NV10TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 16
-#define NV10TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x000f0000
-#define NV10TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 20
-#define NV10TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x00f00000
-#define NV10TCL_TX_FORMAT_WRAP_S_SHIFT 24
-#define NV10TCL_TX_FORMAT_WRAP_S_MASK 0x0f000000
-#define NV10TCL_TX_FORMAT_WRAP_S_REPEAT 0x01000000
-#define NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT 0x02000000
-#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE 0x03000000
-#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER 0x04000000
-#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP 0x05000000
-#define NV10TCL_TX_FORMAT_WRAP_T_SHIFT 28
-#define NV10TCL_TX_FORMAT_WRAP_T_MASK 0xf0000000
-#define NV10TCL_TX_FORMAT_WRAP_T_REPEAT 0x10000000
-#define NV10TCL_TX_FORMAT_WRAP_T_MIRRORED_REPEAT 0x20000000
-#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE 0x30000000
-#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER 0x40000000
-#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP 0x50000000
-#define NV10TCL_TX_ENABLE(x) (0x00000228+((x)*4))
-#define NV10TCL_TX_ENABLE__SIZE 0x00000002
-#define NV10TCL_TX_ENABLE_ANISOTROPY_SHIFT 4
-#define NV10TCL_TX_ENABLE_ANISOTROPY_MASK 0x00000030
-#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14
-#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000
-#define NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26
-#define NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000
-#define NV10TCL_TX_ENABLE_ENABLE (1 << 30)
-#define NV10TCL_TX_NPOT_PITCH(x) (0x00000230+((x)*4))
-#define NV10TCL_TX_NPOT_PITCH__SIZE 0x00000002
-#define NV10TCL_TX_NPOT_PITCH_PITCH_SHIFT 16
-#define NV10TCL_TX_NPOT_PITCH_PITCH_MASK 0xffff0000
-#define NV10TCL_TX_NPOT_SIZE(x) (0x00000240+((x)*4))
-#define NV10TCL_TX_NPOT_SIZE__SIZE 0x00000002
-#define NV10TCL_TX_NPOT_SIZE_H_SHIFT 0
-#define NV10TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff
-#define NV10TCL_TX_NPOT_SIZE_W_SHIFT 16
-#define NV10TCL_TX_NPOT_SIZE_W_MASK 0xffff0000
-#define NV10TCL_TX_FILTER(x) (0x00000248+((x)*4))
-#define NV10TCL_TX_FILTER__SIZE 0x00000002
-#define NV10TCL_TX_FILTER_LOD_BIAS_SHIFT 8
-#define NV10TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00
-#define NV10TCL_TX_FILTER_MINIFY_SHIFT 24
-#define NV10TCL_TX_FILTER_MINIFY_MASK 0x0f000000
-#define NV10TCL_TX_FILTER_MINIFY_NEAREST 0x01000000
-#define NV10TCL_TX_FILTER_MINIFY_LINEAR 0x02000000
-#define NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000
-#define NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000
-#define NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000
-#define NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000
-#define NV10TCL_TX_FILTER_MAGNIFY_SHIFT 28
-#define NV10TCL_TX_FILTER_MAGNIFY_MASK 0xf0000000
-#define NV10TCL_TX_FILTER_MAGNIFY_NEAREST 0x10000000
-#define NV10TCL_TX_FILTER_MAGNIFY_LINEAR 0x20000000
-#define NV10TCL_TX_PALETTE_OFFSET(x) (0x00000250+((x)*4))
-#define NV10TCL_TX_PALETTE_OFFSET__SIZE 0x00000002
-#define NV10TCL_RC_IN_ALPHA(x) (0x00000260+((x)*4))
-#define NV10TCL_RC_IN_ALPHA__SIZE 0x00000002
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_NV 0x0000000c
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE1_NV 0x0000000d
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4)
-#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
-#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_NV 0x00000c00
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE1_NV 0x00000d00
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12)
-#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
-#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_NV 0x000c0000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE1_NV 0x000d0000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20)
-#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
-#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_NV 0x0c000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE1_NV 0x0d000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28)
-#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
-#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV10TCL_RC_IN_RGB(x) (0x00000268+((x)*4))
-#define NV10TCL_RC_IN_RGB__SIZE 0x00000002
-#define NV10TCL_RC_IN_RGB_D_INPUT_SHIFT 0
-#define NV10TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f
-#define NV10TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV10TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003
-#define NV10TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV10TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_NV 0x0000000c
-#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE1_NV 0x0000000d
-#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV10TCL_RC_IN_RGB_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4)
-#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV10TCL_RC_IN_RGB_D_MAPPING_SHIFT 5
-#define NV10TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0
-#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV10TCL_RC_IN_RGB_C_INPUT_SHIFT 8
-#define NV10TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00
-#define NV10TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV10TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300
-#define NV10TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV10TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_NV 0x00000c00
-#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE1_NV 0x00000d00
-#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV10TCL_RC_IN_RGB_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12)
-#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_SHIFT 13
-#define NV10TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV10TCL_RC_IN_RGB_B_INPUT_SHIFT 16
-#define NV10TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000
-#define NV10TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV10TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000
-#define NV10TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV10TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_NV 0x000c0000
-#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE1_NV 0x000d0000
-#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV10TCL_RC_IN_RGB_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20)
-#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_SHIFT 21
-#define NV10TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV10TCL_RC_IN_RGB_A_INPUT_SHIFT 24
-#define NV10TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_NV 0x0c000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE1_NV 0x0d000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV10TCL_RC_IN_RGB_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28)
-#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_SHIFT 29
-#define NV10TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV10TCL_RC_COLOR(x) (0x00000270+((x)*4))
-#define NV10TCL_RC_COLOR__SIZE 0x00000002
-#define NV10TCL_RC_COLOR_B_SHIFT 0
-#define NV10TCL_RC_COLOR_B_MASK 0x000000ff
-#define NV10TCL_RC_COLOR_G_SHIFT 8
-#define NV10TCL_RC_COLOR_G_MASK 0x0000ff00
-#define NV10TCL_RC_COLOR_R_SHIFT 16
-#define NV10TCL_RC_COLOR_R_MASK 0x00ff0000
-#define NV10TCL_RC_COLOR_A_SHIFT 24
-#define NV10TCL_RC_COLOR_A_MASK 0xff000000
-#define NV10TCL_RC_OUT_ALPHA(x) (0x00000278+((x)*4))
-#define NV10TCL_RC_OUT_ALPHA__SIZE 0x00000002
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB 0x00000008
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB 0x00000009
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV 0x0000000c
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV 0x0000000d
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x00000080
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x00000090
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000000c0
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000000d0
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x00000c00
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x00000d00
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
-#define NV10TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
-#define NV10TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
-#define NV10TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14)
-#define NV10TCL_RC_OUT_ALPHA_BIAS (1 << 15)
-#define NV10TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000
-#define NV10TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SHIFT 17
-#define NV10TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000
-#define NV10TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x00020000
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x00040000
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
-#define NV10TCL_RC_OUT_RGB(x) (0x00000280+((x)*4))
-#define NV10TCL_RC_OUT_RGB__SIZE 0x00000002
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB 0x00000008
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB 0x00000009
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV 0x0000000c
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV 0x0000000d
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x00000080
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x00000090
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000000c0
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000000d0
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x00000c00
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x00000d00
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
-#define NV10TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
-#define NV10TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
-#define NV10TCL_RC_OUT_RGB_MUX_SUM (1 << 14)
-#define NV10TCL_RC_OUT_RGB_BIAS (1 << 15)
-#define NV10TCL_RC_OUT_RGB_BIAS_NONE 0x00000000
-#define NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
-#define NV10TCL_RC_OUT_RGB_SCALE_SHIFT 17
-#define NV10TCL_RC_OUT_RGB_SCALE_MASK 0x00000000
-#define NV10TCL_RC_OUT_RGB_SCALE_NONE 0x00000000
-#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x00020000
-#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x00040000
-#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
-#define NV10TCL_RC_OUT_RGB_OPERATION_SHIFT 27
-#define NV10TCL_RC_OUT_RGB_OPERATION_MASK 0x38000000
-#define NV10TCL_RC_FINAL0 0x00000288
-#define NV10TCL_RC_FINAL0_D_INPUT_SHIFT 0
-#define NV10TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f
-#define NV10TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV10TCL_RC_FINAL0_D_INPUT_FOG 0x00000003
-#define NV10TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV10TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_NV 0x0000000c
-#define NV10TCL_RC_FINAL0_D_INPUT_SPARE1_NV 0x0000000d
-#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV10TCL_RC_FINAL0_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4)
-#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV10TCL_RC_FINAL0_D_MAPPING_SHIFT 5
-#define NV10TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0
-#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV10TCL_RC_FINAL0_C_INPUT_SHIFT 8
-#define NV10TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00
-#define NV10TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV10TCL_RC_FINAL0_C_INPUT_FOG 0x00000300
-#define NV10TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV10TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_NV 0x00000c00
-#define NV10TCL_RC_FINAL0_C_INPUT_SPARE1_NV 0x00000d00
-#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV10TCL_RC_FINAL0_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12)
-#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV10TCL_RC_FINAL0_C_MAPPING_SHIFT 13
-#define NV10TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000
-#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV10TCL_RC_FINAL0_B_INPUT_SHIFT 16
-#define NV10TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000
-#define NV10TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV10TCL_RC_FINAL0_B_INPUT_FOG 0x00030000
-#define NV10TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV10TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_NV 0x000c0000
-#define NV10TCL_RC_FINAL0_B_INPUT_SPARE1_NV 0x000d0000
-#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV10TCL_RC_FINAL0_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20)
-#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV10TCL_RC_FINAL0_B_MAPPING_SHIFT 21
-#define NV10TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000
-#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV10TCL_RC_FINAL0_A_INPUT_SHIFT 24
-#define NV10TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000
-#define NV10TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV10TCL_RC_FINAL0_A_INPUT_FOG 0x03000000
-#define NV10TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV10TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_NV 0x0c000000
-#define NV10TCL_RC_FINAL0_A_INPUT_SPARE1_NV 0x0d000000
-#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV10TCL_RC_FINAL0_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28)
-#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_SHIFT 29
-#define NV10TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV10TCL_RC_FINAL1 0x0000028c
-#define NV10TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
-#define NV10TCL_RC_FINAL1_G_INPUT_SHIFT 8
-#define NV10TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00
-#define NV10TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV10TCL_RC_FINAL1_G_INPUT_FOG 0x00000300
-#define NV10TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV10TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE0_ARB 0x00000800
-#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE1_ARB 0x00000900
-#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_NV 0x00000c00
-#define NV10TCL_RC_FINAL1_G_INPUT_SPARE1_NV 0x00000d00
-#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV10TCL_RC_FINAL1_G_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12)
-#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV10TCL_RC_FINAL1_G_MAPPING_SHIFT 13
-#define NV10TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000
-#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV10TCL_RC_FINAL1_F_INPUT_SHIFT 16
-#define NV10TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000
-#define NV10TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV10TCL_RC_FINAL1_F_INPUT_FOG 0x00030000
-#define NV10TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV10TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE0_ARB 0x00080000
-#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE1_ARB 0x00090000
-#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_NV 0x000c0000
-#define NV10TCL_RC_FINAL1_F_INPUT_SPARE1_NV 0x000d0000
-#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV10TCL_RC_FINAL1_F_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20)
-#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV10TCL_RC_FINAL1_F_MAPPING_SHIFT 21
-#define NV10TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000
-#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV10TCL_RC_FINAL1_E_INPUT_SHIFT 24
-#define NV10TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000
-#define NV10TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000
-#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV10TCL_RC_FINAL1_E_INPUT_FOG 0x03000000
-#define NV10TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV10TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE0_ARB 0x08000000
-#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE1_ARB 0x09000000
-#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_NV 0x0c000000
-#define NV10TCL_RC_FINAL1_E_INPUT_SPARE1_NV 0x0d000000
-#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV10TCL_RC_FINAL1_E_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28)
-#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
-#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_SHIFT 29
-#define NV10TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV10TCL_LIGHT_MODEL 0x00000294
-#define NV10TCL_LIGHT_MODEL_COLOR_CONTROL (1 << 1)
-#define NV10TCL_LIGHT_MODEL_LOCAL_VIEWER (1 << 16)
-#define NV10TCL_COLOR_MATERIAL_ENABLE 0x00000298
-#define NV10TCL_COLOR_MATERIAL_ENABLE_SPECULAR (1 << 0)
-#define NV10TCL_COLOR_MATERIAL_ENABLE_DIFFUSE (1 << 1)
-#define NV10TCL_COLOR_MATERIAL_ENABLE_AMBIENT (1 << 2)
-#define NV10TCL_COLOR_MATERIAL_ENABLE_EMISSION (1 << 3)
-#define NV10TCL_FOG_MODE 0x0000029c
-#define NV10TCL_FOG_MODE_EXP 0x00000800
-#define NV10TCL_FOG_MODE_EXP_2 0x00000802
-#define NV10TCL_FOG_MODE_EXP2 0x00000803
-#define NV10TCL_FOG_MODE_LINEAR 0x00000804
-#define NV10TCL_FOG_MODE_LINEAR_2 0x00002601
-#define NV10TCL_FOG_COORD_DIST 0x000002a0
-#define NV10TCL_FOG_COORD_DIST_COORD_FALSE 0x00000000
-#define NV10TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_RADIAL_NV 0x00000001
-#define NV10TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_PLANE_ABSOLUTE_NV 0x00000002
-#define NV10TCL_FOG_COORD_DIST_COORD_FOG 0x00000003
-#define NV10TCL_FOG_ENABLE 0x000002a4
-#define NV10TCL_FOG_COLOR 0x000002a8
-#define NV10TCL_FOG_COLOR_R_SHIFT 0
-#define NV10TCL_FOG_COLOR_R_MASK 0x000000ff
-#define NV10TCL_FOG_COLOR_G_SHIFT 8
-#define NV10TCL_FOG_COLOR_G_MASK 0x0000ff00
-#define NV10TCL_FOG_COLOR_B_SHIFT 16
-#define NV10TCL_FOG_COLOR_B_MASK 0x00ff0000
-#define NV10TCL_FOG_COLOR_A_SHIFT 24
-#define NV10TCL_FOG_COLOR_A_MASK 0xff000000
-#define NV10TCL_VIEWPORT_CLIP_MODE 0x000002b4
-#define NV10TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*4))
-#define NV10TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008
-#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_SHIFT 0
-#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_MASK 0x000007ff
-#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_LEFT_ENABLE (1 << 11)
-#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_SHIFT 16
-#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_MASK 0x07ff0000
-#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_RIGHT_ENABLE (1 << 27)
-#define NV10TCL_VIEWPORT_CLIP_VERT(x) (0x000002e0+((x)*4))
-#define NV10TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008
-#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_SHIFT 0
-#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_MASK 0x000007ff
-#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_TOP_ENABLE (1 << 11)
-#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_SHIFT 16
-#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_MASK 0x07ff0000
-#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_BOTTOM_ENABLE (1 << 27)
-#define NV10TCL_ALPHA_FUNC_ENABLE 0x00000300
-#define NV10TCL_BLEND_FUNC_ENABLE 0x00000304
-#define NV10TCL_CULL_FACE_ENABLE 0x00000308
-#define NV10TCL_DEPTH_TEST_ENABLE 0x0000030c
-#define NV10TCL_DITHER_ENABLE 0x00000310
-#define NV10TCL_LIGHTING_ENABLE 0x00000314
-#define NV10TCL_POINT_PARAMETERS_ENABLE 0x00000318
-#define NV10TCL_POINT_SMOOTH_ENABLE 0x0000031c
-#define NV10TCL_LINE_SMOOTH_ENABLE 0x00000320
-#define NV10TCL_POLYGON_SMOOTH_ENABLE 0x00000324
-#define NV10TCL_VERTEX_WEIGHT_ENABLE 0x00000328
-#define NV10TCL_STENCIL_ENABLE 0x0000032c
-#define NV10TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000330
-#define NV10TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000334
-#define NV10TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000338
-#define NV10TCL_ALPHA_FUNC_FUNC 0x0000033c
-#define NV10TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200
-#define NV10TCL_ALPHA_FUNC_FUNC_LESS 0x00000201
-#define NV10TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202
-#define NV10TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
-#define NV10TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
-#define NV10TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
-#define NV10TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV10TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
-#define NV10TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
-#define NV10TCL_ALPHA_FUNC_REF 0x00000340
-#define NV10TCL_BLEND_FUNC_SRC 0x00000344
-#define NV10TCL_BLEND_FUNC_SRC_ZERO 0x00000000
-#define NV10TCL_BLEND_FUNC_SRC_ONE 0x00000001
-#define NV10TCL_BLEND_FUNC_SRC_SRC_COLOR 0x00000300
-#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA 0x00000302
-#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV10TCL_BLEND_FUNC_SRC_DST_ALPHA 0x00000304
-#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV10TCL_BLEND_FUNC_SRC_DST_COLOR 0x00000306
-#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR 0x00000307
-#define NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE 0x00000308
-#define NV10TCL_BLEND_FUNC_SRC_CONSTANT_COLOR 0x00008001
-#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV10TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA 0x00008003
-#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV10TCL_BLEND_FUNC_DST 0x00000348
-#define NV10TCL_BLEND_FUNC_DST_ZERO 0x00000000
-#define NV10TCL_BLEND_FUNC_DST_ONE 0x00000001
-#define NV10TCL_BLEND_FUNC_DST_SRC_COLOR 0x00000300
-#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV10TCL_BLEND_FUNC_DST_SRC_ALPHA 0x00000302
-#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV10TCL_BLEND_FUNC_DST_DST_ALPHA 0x00000304
-#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV10TCL_BLEND_FUNC_DST_DST_COLOR 0x00000306
-#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR 0x00000307
-#define NV10TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE 0x00000308
-#define NV10TCL_BLEND_FUNC_DST_CONSTANT_COLOR 0x00008001
-#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV10TCL_BLEND_FUNC_DST_CONSTANT_ALPHA 0x00008003
-#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV10TCL_BLEND_COLOR 0x0000034c
-#define NV10TCL_BLEND_COLOR_B_SHIFT 0
-#define NV10TCL_BLEND_COLOR_B_MASK 0x000000ff
-#define NV10TCL_BLEND_COLOR_G_SHIFT 8
-#define NV10TCL_BLEND_COLOR_G_MASK 0x0000ff00
-#define NV10TCL_BLEND_COLOR_R_SHIFT 16
-#define NV10TCL_BLEND_COLOR_R_MASK 0x00ff0000
-#define NV10TCL_BLEND_COLOR_A_SHIFT 24
-#define NV10TCL_BLEND_COLOR_A_MASK 0xff000000
-#define NV10TCL_BLEND_EQUATION 0x00000350
-#define NV10TCL_BLEND_EQUATION_FUNC_ADD 0x00008006
-#define NV10TCL_BLEND_EQUATION_MIN 0x00008007
-#define NV10TCL_BLEND_EQUATION_MAX 0x00008008
-#define NV10TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a
-#define NV10TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b
-#define NV10TCL_DEPTH_FUNC 0x00000354
-#define NV10TCL_DEPTH_FUNC_NEVER 0x00000200
-#define NV10TCL_DEPTH_FUNC_LESS 0x00000201
-#define NV10TCL_DEPTH_FUNC_EQUAL 0x00000202
-#define NV10TCL_DEPTH_FUNC_LEQUAL 0x00000203
-#define NV10TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV10TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV10TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
-#define NV10TCL_DEPTH_FUNC_GEQUAL 0x00000206
-#define NV10TCL_DEPTH_FUNC_ALWAYS 0x00000207
-#define NV10TCL_COLOR_MASK 0x00000358
-#define NV10TCL_COLOR_MASK_B (1 << 0)
-#define NV10TCL_COLOR_MASK_G (1 << 8)
-#define NV10TCL_COLOR_MASK_R (1 << 16)
-#define NV10TCL_COLOR_MASK_A (1 << 24)
-#define NV10TCL_DEPTH_WRITE_ENABLE 0x0000035c
-#define NV10TCL_STENCIL_MASK 0x00000360
-#define NV10TCL_STENCIL_FUNC_FUNC 0x00000364
-#define NV10TCL_STENCIL_FUNC_FUNC_NEVER 0x00000200
-#define NV10TCL_STENCIL_FUNC_FUNC_LESS 0x00000201
-#define NV10TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202
-#define NV10TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203
-#define NV10TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
-#define NV10TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
-#define NV10TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV10TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206
-#define NV10TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207
-#define NV10TCL_STENCIL_FUNC_REF 0x00000368
-#define NV10TCL_STENCIL_FUNC_MASK 0x0000036c
-#define NV10TCL_STENCIL_OP_FAIL 0x00000370
-#define NV10TCL_STENCIL_OP_FAIL_ZERO 0x00000000
-#define NV10TCL_STENCIL_OP_FAIL_INVERT 0x0000150a
-#define NV10TCL_STENCIL_OP_FAIL_KEEP 0x00001e00
-#define NV10TCL_STENCIL_OP_FAIL_REPLACE 0x00001e01
-#define NV10TCL_STENCIL_OP_FAIL_INCR 0x00001e02
-#define NV10TCL_STENCIL_OP_FAIL_DECR 0x00001e03
-#define NV10TCL_STENCIL_OP_FAIL_INCR_WRAP 0x00008507
-#define NV10TCL_STENCIL_OP_FAIL_DECR_WRAP 0x00008508
-#define NV10TCL_STENCIL_OP_ZFAIL 0x00000374
-#define NV10TCL_STENCIL_OP_ZFAIL_ZERO 0x00000000
-#define NV10TCL_STENCIL_OP_ZFAIL_INVERT 0x0000150a
-#define NV10TCL_STENCIL_OP_ZFAIL_KEEP 0x00001e00
-#define NV10TCL_STENCIL_OP_ZFAIL_REPLACE 0x00001e01
-#define NV10TCL_STENCIL_OP_ZFAIL_INCR 0x00001e02
-#define NV10TCL_STENCIL_OP_ZFAIL_DECR 0x00001e03
-#define NV10TCL_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV10TCL_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV10TCL_STENCIL_OP_ZPASS 0x00000378
-#define NV10TCL_STENCIL_OP_ZPASS_ZERO 0x00000000
-#define NV10TCL_STENCIL_OP_ZPASS_INVERT 0x0000150a
-#define NV10TCL_STENCIL_OP_ZPASS_KEEP 0x00001e00
-#define NV10TCL_STENCIL_OP_ZPASS_REPLACE 0x00001e01
-#define NV10TCL_STENCIL_OP_ZPASS_INCR 0x00001e02
-#define NV10TCL_STENCIL_OP_ZPASS_DECR 0x00001e03
-#define NV10TCL_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV10TCL_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV10TCL_SHADE_MODEL 0x0000037c
-#define NV10TCL_SHADE_MODEL_FLAT 0x00001d00
-#define NV10TCL_SHADE_MODEL_SMOOTH 0x00001d01
-#define NV10TCL_LINE_WIDTH 0x00000380
-#define NV10TCL_POLYGON_OFFSET_FACTOR 0x00000384
-#define NV10TCL_POLYGON_OFFSET_UNITS 0x00000388
-#define NV10TCL_POLYGON_MODE_FRONT 0x0000038c
-#define NV10TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
-#define NV10TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
-#define NV10TCL_POLYGON_MODE_FRONT_FILL 0x00001b02
-#define NV10TCL_POLYGON_MODE_BACK 0x00000390
-#define NV10TCL_POLYGON_MODE_BACK_POINT 0x00001b00
-#define NV10TCL_POLYGON_MODE_BACK_LINE 0x00001b01
-#define NV10TCL_POLYGON_MODE_BACK_FILL 0x00001b02
-#define NV10TCL_DEPTH_RANGE_NEAR 0x00000394
-#define NV10TCL_DEPTH_RANGE_FAR 0x00000398
-#define NV10TCL_CULL_FACE 0x0000039c
-#define NV10TCL_CULL_FACE_FRONT 0x00000404
-#define NV10TCL_CULL_FACE_BACK 0x00000405
-#define NV10TCL_CULL_FACE_FRONT_AND_BACK 0x00000408
-#define NV10TCL_FRONT_FACE 0x000003a0
-#define NV10TCL_FRONT_FACE_CW 0x00000900
-#define NV10TCL_FRONT_FACE_CCW 0x00000901
-#define NV10TCL_NORMALIZE_ENABLE 0x000003a4
-#define NV10TCL_COLOR_MATERIAL_R 0x000003a8
-#define NV10TCL_COLOR_MATERIAL_G 0x000003ac
-#define NV10TCL_COLOR_MATERIAL_B 0x000003b0
-#define NV10TCL_COLOR_MATERIAL_A 0x000003b4
-#define NV10TCL_COLOR_CONTROL 0x000003b8
-#define NV10TCL_ENABLED_LIGHTS 0x000003bc
-#define NV10TCL_ENABLED_LIGHTS_LIGHT0 (1 << 0)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT1 (1 << 2)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT2 (1 << 4)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT3 (1 << 6)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT4 (1 << 8)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT5 (1 << 10)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT6 (1 << 12)
-#define NV10TCL_ENABLED_LIGHTS_LIGHT7 (1 << 14)
-#define NV10TCL_TX_GEN_S(x) (0x000003c0+((x)*16))
-#define NV10TCL_TX_GEN_S__SIZE 0x00000002
-#define NV10TCL_TX_GEN_S_FALSE 0x00000000
-#define NV10TCL_TX_GEN_S_EYE_LINEAR 0x00002400
-#define NV10TCL_TX_GEN_S_OBJECT_LINEAR 0x00002401
-#define NV10TCL_TX_GEN_S_SPHERE_MAP 0x00002402
-#define NV10TCL_TX_GEN_S_NORMAL_MAP 0x00008511
-#define NV10TCL_TX_GEN_S_REFLECTION_MAP 0x00008512
-#define NV10TCL_TX_GEN_T(x) (0x000003c4+((x)*16))
-#define NV10TCL_TX_GEN_T__SIZE 0x00000002
-#define NV10TCL_TX_GEN_T_FALSE 0x00000000
-#define NV10TCL_TX_GEN_T_EYE_LINEAR 0x00002400
-#define NV10TCL_TX_GEN_T_OBJECT_LINEAR 0x00002401
-#define NV10TCL_TX_GEN_T_SPHERE_MAP 0x00002402
-#define NV10TCL_TX_GEN_T_NORMAL_MAP 0x00008511
-#define NV10TCL_TX_GEN_T_REFLECTION_MAP 0x00008512
-#define NV10TCL_TX_GEN_R(x) (0x000003c8+((x)*16))
-#define NV10TCL_TX_GEN_R__SIZE 0x00000002
-#define NV10TCL_TX_GEN_R_FALSE 0x00000000
-#define NV10TCL_TX_GEN_R_EYE_LINEAR 0x00002400
-#define NV10TCL_TX_GEN_R_OBJECT_LINEAR 0x00002401
-#define NV10TCL_TX_GEN_R_SPHERE_MAP 0x00002402
-#define NV10TCL_TX_GEN_R_NORMAL_MAP 0x00008511
-#define NV10TCL_TX_GEN_R_REFLECTION_MAP 0x00008512
-#define NV10TCL_TX_GEN_Q(x) (0x000003cc+((x)*16))
-#define NV10TCL_TX_GEN_Q__SIZE 0x00000002
-#define NV10TCL_TX_GEN_Q_FALSE 0x00000000
-#define NV10TCL_TX_GEN_Q_EYE_LINEAR 0x00002400
-#define NV10TCL_TX_GEN_Q_OBJECT_LINEAR 0x00002401
-#define NV10TCL_TX_GEN_Q_SPHERE_MAP 0x00002402
-#define NV10TCL_TX_GEN_Q_NORMAL_MAP 0x00008511
-#define NV10TCL_TX_GEN_Q_REFLECTION_MAP 0x00008512
-#define NV10TCL_TX_MATRIX_ENABLE(x) (0x000003e0+((x)*4))
-#define NV10TCL_TX_MATRIX_ENABLE__SIZE 0x00000002
-#define NV10TCL_VIEW_MATRIX_ENABLE 0x000003e8
-#define NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW1 (1 << 0)
-#define NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW0 (1 << 1)
-#define NV10TCL_VIEW_MATRIX_ENABLE_PROJECTION (1 << 2)
-#define NV10TCL_POINT_SIZE 0x000003ec
-#define NV10TCL_MODELVIEW0_MATRIX(x) (0x00000400+((x)*4))
-#define NV10TCL_MODELVIEW0_MATRIX__SIZE 0x00000010
-#define NV10TCL_MODELVIEW1_MATRIX(x) (0x00000440+((x)*4))
-#define NV10TCL_MODELVIEW1_MATRIX__SIZE 0x00000010
-#define NV10TCL_INVERSE_MODELVIEW0_MATRIX(x) (0x00000480+((x)*4))
-#define NV10TCL_INVERSE_MODELVIEW0_MATRIX__SIZE 0x00000010
-#define NV10TCL_INVERSE_MODELVIEW1_MATRIX(x) (0x000004c0+((x)*4))
-#define NV10TCL_INVERSE_MODELVIEW1_MATRIX__SIZE 0x00000010
-#define NV10TCL_PROJECTION_MATRIX(x) (0x00000500+((x)*4))
-#define NV10TCL_PROJECTION_MATRIX__SIZE 0x00000010
-#define NV10TCL_TX0_MATRIX(x) (0x00000540+((x)*4))
-#define NV10TCL_TX0_MATRIX__SIZE 0x00000010
-#define NV10TCL_TX1_MATRIX(x) (0x00000580+((x)*4))
-#define NV10TCL_TX1_MATRIX__SIZE 0x00000010
-#define NV10TCL_CLIP_PLANE_A(x) (0x00000600+((x)*16))
-#define NV10TCL_CLIP_PLANE_A__SIZE 0x00000008
-#define NV10TCL_CLIP_PLANE_B(x) (0x00000604+((x)*16))
-#define NV10TCL_CLIP_PLANE_B__SIZE 0x00000008
-#define NV10TCL_CLIP_PLANE_C(x) (0x00000608+((x)*16))
-#define NV10TCL_CLIP_PLANE_C__SIZE 0x00000008
-#define NV10TCL_CLIP_PLANE_D(x) (0x0000060c+((x)*16))
-#define NV10TCL_CLIP_PLANE_D__SIZE 0x00000008
-#define NV10TCL_FOG_EQUATION_CONSTANT 0x00000680
-#define NV10TCL_FOG_EQUATION_LINEAR 0x00000684
-#define NV10TCL_FOG_EQUATION_QUADRATIC 0x00000688
-#define NV10TCL_FRONT_MATERIAL_SHININESS(x) (0x000006a0+((x)*4))
-#define NV10TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006
-#define NV10TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000006c4
-#define NV10TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000006c8
-#define NV10TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000006cc
-#define NV10TCL_VIEWPORT_SCALE_X 0x000006e8
-#define NV10TCL_VIEWPORT_SCALE_Y 0x000006ec
-#define NV10TCL_VIEWPORT_SCALE_Z 0x000006f0
-#define NV10TCL_VIEWPORT_SCALE_W 0x000006f4
-#define NV10TCL_POINT_PARAMETER(x) (0x000006f8+((x)*4))
-#define NV10TCL_POINT_PARAMETER__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x) (0x00000800+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x) (0x00000804+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x) (0x00000808+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x) (0x0000080c+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x) (0x00000810+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x) (0x00000814+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x) (0x00000818+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x) (0x0000081c+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE 0x00000008
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x) (0x00000820+((x)*128))
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE 0x00000008
-#define NV10TCL_LIGHT_HALF_VECTOR_X(x) (0x00000828+((x)*128))
-#define NV10TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008
-#define NV10TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000082c+((x)*128))
-#define NV10TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008
-#define NV10TCL_LIGHT_HALF_VECTOR_Z(x) (0x00000830+((x)*128))
-#define NV10TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008
-#define NV10TCL_LIGHT_DIRECTION_X(x) (0x00000834+((x)*128))
-#define NV10TCL_LIGHT_DIRECTION_X__SIZE 0x00000008
-#define NV10TCL_LIGHT_DIRECTION_Y(x) (0x00000838+((x)*128))
-#define NV10TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008
-#define NV10TCL_LIGHT_DIRECTION_Z(x) (0x0000083c+((x)*128))
-#define NV10TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00000840+((x)*128))
-#define NV10TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00000844+((x)*128))
-#define NV10TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00000848+((x)*128))
-#define NV10TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_DIR_X(x) (0x0000084c+((x)*128))
-#define NV10TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_DIR_Y(x) (0x00000850+((x)*128))
-#define NV10TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_DIR_Z(x) (0x00000854+((x)*128))
-#define NV10TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008
-#define NV10TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00000858+((x)*128))
-#define NV10TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008
-#define NV10TCL_LIGHT_POSITION_X(x) (0x0000085c+((x)*128))
-#define NV10TCL_LIGHT_POSITION_X__SIZE 0x00000008
-#define NV10TCL_LIGHT_POSITION_Y(x) (0x00000860+((x)*128))
-#define NV10TCL_LIGHT_POSITION_Y__SIZE 0x00000008
-#define NV10TCL_LIGHT_POSITION_Z(x) (0x00000864+((x)*128))
-#define NV10TCL_LIGHT_POSITION_Z__SIZE 0x00000008
-#define NV10TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00000868+((x)*128))
-#define NV10TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008
-#define NV10TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000086c+((x)*128))
-#define NV10TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008
-#define NV10TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00000870+((x)*128))
-#define NV10TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008
-#define NV10TCL_VERTEX_POS_3F_X 0x00000c00
-#define NV10TCL_VERTEX_POS_3F_Y 0x00000c04
-#define NV10TCL_VERTEX_POS_3F_Z 0x00000c08
-#define NV10TCL_VERTEX_POS_4F_X 0x00000c18
-#define NV10TCL_VERTEX_POS_4F_Y 0x00000c1c
-#define NV10TCL_VERTEX_POS_4F_Z 0x00000c20
-#define NV10TCL_VERTEX_POS_4F_W 0x00000c24
-#define NV10TCL_VERTEX_NOR_3F_X 0x00000c30
-#define NV10TCL_VERTEX_NOR_3F_Y 0x00000c34
-#define NV10TCL_VERTEX_NOR_3F_Z 0x00000c38
-#define NV10TCL_VERTEX_NOR_3I_XY 0x00000c40
-#define NV10TCL_VERTEX_NOR_3I_XY_X_SHIFT 0
-#define NV10TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
-#define NV10TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16
-#define NV10TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
-#define NV10TCL_VERTEX_NOR_3I_Z 0x00000c44
-#define NV10TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0
-#define NV10TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
-#define NV10TCL_VERTEX_COL_4F_R 0x00000c50
-#define NV10TCL_VERTEX_COL_4F_G 0x00000c54
-#define NV10TCL_VERTEX_COL_4F_B 0x00000c58
-#define NV10TCL_VERTEX_COL_4F_A 0x00000c5c
-#define NV10TCL_VERTEX_COL_3F_R 0x00000c60
-#define NV10TCL_VERTEX_COL_3F_G 0x00000c64
-#define NV10TCL_VERTEX_COL_3F_B 0x00000c68
-#define NV10TCL_VERTEX_COL_4I 0x00000c6c
-#define NV10TCL_VERTEX_COL_4I_R_SHIFT 0
-#define NV10TCL_VERTEX_COL_4I_R_MASK 0x000000ff
-#define NV10TCL_VERTEX_COL_4I_G_SHIFT 8
-#define NV10TCL_VERTEX_COL_4I_G_MASK 0x0000ff00
-#define NV10TCL_VERTEX_COL_4I_B_SHIFT 16
-#define NV10TCL_VERTEX_COL_4I_B_MASK 0x00ff0000
-#define NV10TCL_VERTEX_COL_4I_A_SHIFT 24
-#define NV10TCL_VERTEX_COL_4I_A_MASK 0xff000000
-#define NV10TCL_VERTEX_COL2_3F_R 0x00000c80
-#define NV10TCL_VERTEX_COL2_3F_G 0x00000c84
-#define NV10TCL_VERTEX_COL2_3F_B 0x00000c88
-#define NV10TCL_VERTEX_COL2_3I 0x00000c8c
-#define NV10TCL_VERTEX_COL2_3I_R_SHIFT 0
-#define NV10TCL_VERTEX_COL2_3I_R_MASK 0x000000ff
-#define NV10TCL_VERTEX_COL2_3I_G_SHIFT 8
-#define NV10TCL_VERTEX_COL2_3I_G_MASK 0x0000ff00
-#define NV10TCL_VERTEX_COL2_3I_B_SHIFT 16
-#define NV10TCL_VERTEX_COL2_3I_B_MASK 0x00ff0000
-#define NV10TCL_VERTEX_TX0_2F_S 0x00000c90
-#define NV10TCL_VERTEX_TX0_2F_T 0x00000c94
-#define NV10TCL_VERTEX_TX0_2I 0x00000c98
-#define NV10TCL_VERTEX_TX0_2I_S_SHIFT 0
-#define NV10TCL_VERTEX_TX0_2I_S_MASK 0x0000ffff
-#define NV10TCL_VERTEX_TX0_2I_T_SHIFT 16
-#define NV10TCL_VERTEX_TX0_2I_T_MASK 0xffff0000
-#define NV10TCL_VERTEX_TX0_4F_S 0x00000ca0
-#define NV10TCL_VERTEX_TX0_4F_T 0x00000ca4
-#define NV10TCL_VERTEX_TX0_4F_R 0x00000ca8
-#define NV10TCL_VERTEX_TX0_4F_Q 0x00000cac
-#define NV10TCL_VERTEX_TX0_4I_ST 0x00000cb0
-#define NV10TCL_VERTEX_TX0_4I_ST_S_SHIFT 0
-#define NV10TCL_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff
-#define NV10TCL_VERTEX_TX0_4I_ST_T_SHIFT 16
-#define NV10TCL_VERTEX_TX0_4I_ST_T_MASK 0xffff0000
-#define NV10TCL_VERTEX_TX0_4I_RQ 0x00000cb4
-#define NV10TCL_VERTEX_TX0_4I_RQ_R_SHIFT 0
-#define NV10TCL_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff
-#define NV10TCL_VERTEX_TX0_4I_RQ_Q_SHIFT 16
-#define NV10TCL_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000
-#define NV10TCL_VERTEX_TX1_2F_S 0x00000cb8
-#define NV10TCL_VERTEX_TX1_2F_T 0x00000cbc
-#define NV10TCL_VERTEX_TX1_2I 0x00000cc0
-#define NV10TCL_VERTEX_TX1_2I_S_SHIFT 0
-#define NV10TCL_VERTEX_TX1_2I_S_MASK 0x0000ffff
-#define NV10TCL_VERTEX_TX1_2I_T_SHIFT 16
-#define NV10TCL_VERTEX_TX1_2I_T_MASK 0xffff0000
-#define NV10TCL_VERTEX_TX1_4F_S 0x00000cc8
-#define NV10TCL_VERTEX_TX1_4F_T 0x00000ccc
-#define NV10TCL_VERTEX_TX1_4F_R 0x00000cd0
-#define NV10TCL_VERTEX_TX1_4F_Q 0x00000cd4
-#define NV10TCL_VERTEX_TX1_4I_ST 0x00000cd8
-#define NV10TCL_VERTEX_TX1_4I_ST_S_SHIFT 0
-#define NV10TCL_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff
-#define NV10TCL_VERTEX_TX1_4I_ST_T_SHIFT 16
-#define NV10TCL_VERTEX_TX1_4I_ST_T_MASK 0xffff0000
-#define NV10TCL_VERTEX_TX1_4I_RQ 0x00000cdc
-#define NV10TCL_VERTEX_TX1_4I_RQ_R_SHIFT 0
-#define NV10TCL_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff
-#define NV10TCL_VERTEX_TX1_4I_RQ_Q_SHIFT 16
-#define NV10TCL_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000
-#define NV10TCL_VERTEX_FOG_1F 0x00000ce0
-#define NV10TCL_VERTEX_WGH_1F 0x00000ce4
-#define NV10TCL_EDGEFLAG_ENABLE 0x00000cec
-#define NV10TCL_VERTEX_ARRAY_VALIDATE 0x00000cf0
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_OFFSET(x) (0x00000d00+((x)*8))
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_OFFSET__SIZE 0x00000008
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT(x) (0x00000d04+((x)*8))
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT__SIZE 0x00000008
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_POS 0x00000d00
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS 0x00000d04
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_COL 0x00000d08
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL 0x00000d0c
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_COL2 0x00000d10
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2 0x00000d14
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_COL2_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_TX0 0x00000d18
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0 0x00000d1c
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX0_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_TX1 0x00000d20
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1 0x00000d24
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_TX1_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_NOR 0x00000d28
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR 0x00000d2c
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_NOR_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_WGH 0x00000d30
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH 0x00000d34
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_WGH_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_ARRAY_OFFSET_FOG 0x00000d38
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG 0x00000d3c
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG_TYPE_SHIFT 0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG_TYPE_MASK 0x0000000f
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG_FIELDS_SHIFT 4
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG_FIELDS_MASK 0x000000f0
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG_STRIDE_SHIFT 8
-#define NV10TCL_VERTEX_ARRAY_FORMAT_FOG_STRIDE_MASK 0x0000ff00
-#define NV10TCL_VERTEX_BEGIN_END 0x00000dfc
-#define NV10TCL_VERTEX_BEGIN_END_STOP 0x00000000
-#define NV10TCL_VERTEX_BEGIN_END_POINTS 0x00000001
-#define NV10TCL_VERTEX_BEGIN_END_LINES 0x00000002
-#define NV10TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003
-#define NV10TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004
-#define NV10TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005
-#define NV10TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006
-#define NV10TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007
-#define NV10TCL_VERTEX_BEGIN_END_QUADS 0x00000008
-#define NV10TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009
-#define NV10TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a
-#define NV10TCL_VB_ELEMENT_U16 0x00000e00
-#define NV10TCL_VB_ELEMENT_U16_I0_SHIFT 0
-#define NV10TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff
-#define NV10TCL_VB_ELEMENT_U16_I1_SHIFT 16
-#define NV10TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000
-#define NV10TCL_VB_ELEMENT_U32 0x00001100
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END 0x000013fc
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_STOP 0x00000000
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_POINTS 0x00000001
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINES 0x00000002
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_LOOP 0x00000003
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_STRIP 0x00000004
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLES 0x00000005
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_STRIP 0x00000006
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_FAN 0x00000007
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_QUADS 0x00000008
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_QUAD_STRIP 0x00000009
-#define NV10TCL_VERTEX_BUFFER_BEGIN_END_POLYGON 0x0000000a
-#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS 0x00001400
-#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_SHIFT 0
-#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK 0x0000ffff
-#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_SHIFT 24
-#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_MASK 0xff000000
-#define NV10TCL_VERTEX_ARRAY_DATA 0x00001800
-
-
-#define NV04_CONTEXT_COLOR_KEY 0x00000057
-
-
-
-#define NV03_CONTEXT_SURFACES_2D 0x00000058
-
-#define NV03_CONTEXT_SURFACES_2D_SYNCHRONIZE 0x00000100
-#define NV03_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180
-#define NV03_CONTEXT_SURFACES_2D_DMA_SOURCE 0x00000184
-#define NV03_CONTEXT_SURFACES_2D_DMA_DESTIN 0x00000188
-#define NV03_CONTEXT_SURFACES_2D_COLOR_FORMAT 0x00000300
-#define NV03_CONTEXT_SURFACES_2D_PITCH 0x00000304
-#define NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT 0
-#define NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK 0x0000ffff
-#define NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT 16
-#define NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK 0xffff0000
-#define NV03_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308
-#define NV03_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c
-
-
-#define NV03_CONTEXT_SURFACES_3D 0x0000005a
-
-#define NV03_CONTEXT_SURFACES_3D_SYNCHRONIZE 0x00000100
-#define NV03_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180
-#define NV03_CONTEXT_SURFACES_3D_DMA_SURFACE 0x00000184
-#define NV03_CONTEXT_SURFACES_3D_PITCH 0x00000300
-#define NV03_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x00000304
-#define NV03_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000308
-
-
-#define NV04_RENDER_SOLID_LINE 0x0000005c
-
-#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198
-
-
-#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d
-
-
-
-#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e
-
-#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198
-
-
-#define NV04_IMAGE_BLIT 0x0000005f
-
-#define NV04_IMAGE_BLIT_NOP 0x00000100
-#define NV04_IMAGE_BLIT_NOTIFY 0x00000104
-#define NV04_IMAGE_BLIT_DMA_NOTIFY 0x00000180
-#define NV04_IMAGE_BLIT_COLOR_KEY 0x00000184
-#define NV04_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188
-#define NV04_IMAGE_BLIT_PATTERN 0x0000018c
-#define NV04_IMAGE_BLIT_ROP 0x00000190
-#define NV04_IMAGE_BLIT_BETA4 0x00000198
-#define NV04_IMAGE_BLIT_SURFACE 0x0000019c
-#define NV04_IMAGE_BLIT_OPERATION 0x000002fc
-#define NV04_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000
-#define NV04_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001
-#define NV04_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002
-#define NV04_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003
-#define NV04_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV04_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005
-
-
-#define NV04_INDEXED_IMAGE_FROM_CPU 0x00000060
-
-#define NV04_INDEXED_IMAGE_FROM_CPU_NOP 0x00000100
-#define NV04_INDEXED_IMAGE_FROM_CPU_NOTIFY 0x00000104
-#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c
-#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
-#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184
-#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8
-#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec
-#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0
-#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4
-#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8
-#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc
-#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR 0x00000400
-
-
-#define NV04_IMAGE_FROM_CPU 0x00000061
-
-#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198
-#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c
-
-
-#define NV10_CONTEXT_SURFACES_2D 0x00000062
-
-
-
-#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063
-
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002
-
-
-#define NV01_IMAGE_SRCCOPY_AND 0x00000064
-
-#define NV01_IMAGE_SRCCOPY_AND_NOTIFY 0x00000104
-#define NV01_IMAGE_SRCCOPY_AND_DMA_NOTIFY 0x00000180
-#define NV01_IMAGE_SRCCOPY_AND_IMAGE_OUTPUT 0x00000200
-#define NV01_IMAGE_SRCCOPY_AND_IMAGE_INPUT 0x00000204
-
-
-#define NV05_INDEXED_IMAGE_FROM_CPU 0x00000064
-
-#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188
-#define NV05_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c
-#define NV05_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190
-#define NV05_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194
-#define NV05_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198
-#define NV05_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c
-#define NV05_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0
-#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0
-#define NV05_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4
-#define NV05_INDEXED_IMAGE_FROM_CPU_INDICES 0x00000400
-
-
-#define NV05_IMAGE_FROM_CPU 0x00000065
-
-#define NV05_IMAGE_FROM_CPU_BETA4 0x00000198
-#define NV05_IMAGE_FROM_CPU_SURFACE 0x0000019c
-
-
-#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066
-
-#define NV05_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194
-#define NV05_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198
-#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
-
-
-#define NV04_IMAGE_BLEND_PREMULT 0x00000067
-
-#define NV04_IMAGE_BLEND_PREMULT_NOP 0x00000100
-#define NV04_IMAGE_BLEND_PREMULT_NOTIFY 0x00000104
-#define NV04_IMAGE_BLEND_PREMULT_DMA_NOTIFY 0x00000180
-#define NV04_IMAGE_BLEND_PREMULT_IMAGE_OUTPUT 0x00000200
-#define NV04_IMAGE_BLEND_PREMULT_BETA_INPUT 0x00000204
-#define NV04_IMAGE_BLEND_PREMULT_IMAGE_INPUT 0x00000208
-
-
-#define NV03_CHANNEL_PIO 0x0000006a
-
-
-
-#define NV03_CHANNEL_DMA 0x0000006b
-
-
-
-#define NV04_BETA_SOLID 0x00000072
-
-#define NV04_BETA_SOLID_NOP 0x00000100
-#define NV04_BETA_SOLID_NOTIFY 0x00000104
-#define NV04_BETA_SOLID_DMA_NOTIFY 0x00000180
-#define NV04_BETA_SOLID_BETA_OUTPUT 0x00000200
-#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300
-
-
-#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076
-
-
-
-#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077
-
-#define NV04_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100
-#define NV04_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184
-#define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188
-#define NV04_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c
-#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190
-#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK 0xffff0000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK 0xffff0000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_MASK 0xffff0000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_MASK 0xffff0000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_W_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_W_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_MASK 0xffff0000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000
-#define NV04_SCALED_IMAGE_FROM_MEMORY_ADDRESS 0x00000408
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_X_SHIFT 0
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_X_MASK 0x0000ffff
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_Y_SHIFT 16
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_Y_MASK 0xffff0000
-
-
-#define NV10_TEXTURE_FROM_CPU 0x0000007b
-
-#define NV10_TEXTURE_FROM_CPU_NOP 0x00000100
-#define NV10_TEXTURE_FROM_CPU_NOTIFY 0x00000104
-#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE 0x00000108
-#define NV10_TEXTURE_FROM_CPU_PM_TRIGGER 0x00000140
-#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY 0x00000180
-#define NV10_TEXTURE_FROM_CPU_SURFACE 0x00000184
-#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT 0x00000300
-#define NV10_TEXTURE_FROM_CPU_POINT 0x00000304
-#define NV10_TEXTURE_FROM_CPU_POINT_X_SHIFT 0
-#define NV10_TEXTURE_FROM_CPU_POINT_X_MASK 0x0000ffff
-#define NV10_TEXTURE_FROM_CPU_POINT_Y_SHIFT 16
-#define NV10_TEXTURE_FROM_CPU_POINT_Y_MASK 0xffff0000
-#define NV10_TEXTURE_FROM_CPU_SIZE 0x00000308
-#define NV10_TEXTURE_FROM_CPU_SIZE_W_SHIFT 0
-#define NV10_TEXTURE_FROM_CPU_SIZE_W_MASK 0x0000ffff
-#define NV10_TEXTURE_FROM_CPU_SIZE_H_SHIFT 16
-#define NV10_TEXTURE_FROM_CPU_SIZE_H_MASK 0xffff0000
-#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL 0x0000030c
-#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_SHIFT 0
-#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_MASK 0x0000ffff
-#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_SHIFT 16
-#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_MASK 0xffff0000
-#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL 0x00000310
-#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_SHIFT 0
-#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_MASK 0x0000ffff
-#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_SHIFT 16
-#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_MASK 0xffff0000
-#define NV10_TEXTURE_FROM_CPU_COLOR(x) (0x00000400+((x)*4))
-#define NV10_TEXTURE_FROM_CPU_COLOR__SIZE 0x00000700
-
-
-#define NV10_VIDEO_DISPLAY 0x0000007c
-
-
-
-#define NV10_DVD_SUBPICTURE 0x00000088
-
-
-
-#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089
-
-#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108
-
-
-#define NV10_IMAGE_FROM_CPU 0x0000008a
-
-#define NV10_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
-
-
-#define NV10_CONTEXT_SURFACES_3D 0x00000093
-
-
-
-#define NV10_DX5_TEXTURE_TRIANGLE 0x00000094
-
-
-
-#define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000095
-
-
-
-#define NV11TCL 0x00000096
-
-#define NV11TCL_COLOR_LOGIC_OP_ENABLE 0x00000d40
-#define NV11TCL_COLOR_LOGIC_OP_OP 0x00000d44
-#define NV11TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
-#define NV11TCL_COLOR_LOGIC_OP_OP_AND 0x00001501
-#define NV11TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502
-#define NV11TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503
-#define NV11TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504
-#define NV11TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505
-#define NV11TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506
-#define NV11TCL_COLOR_LOGIC_OP_OP_OR 0x00001507
-#define NV11TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508
-#define NV11TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509
-#define NV11TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a
-#define NV11TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b
-#define NV11TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c
-#define NV11TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d
-#define NV11TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e
-#define NV11TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f
-
-
-#define NV20TCL 0x00000097
-
-#define NV20TCL_NOP 0x00000100
-#define NV20TCL_NOTIFY 0x00000104
-#define NV20TCL_DMA_NOTIFY 0x00000180
-#define NV20TCL_DMA_TEXTURE0 0x00000184
-#define NV20TCL_DMA_TEXTURE1 0x00000188
-#define NV20TCL_DMA_COLOR 0x00000194
-#define NV20TCL_DMA_ZETA 0x00000198
-#define NV20TCL_DMA_VTXBUF0 0x0000019c
-#define NV20TCL_DMA_VTXBUF1 0x000001a0
-#define NV20TCL_DMA_FENCE 0x000001a4
-#define NV20TCL_DMA_QUERY 0x000001a8
-#define NV20TCL_RT_HORIZ 0x00000200
-#define NV20TCL_RT_HORIZ_X_SHIFT 0
-#define NV20TCL_RT_HORIZ_X_MASK 0x0000ffff
-#define NV20TCL_RT_HORIZ_W_SHIFT 16
-#define NV20TCL_RT_HORIZ_W_MASK 0xffff0000
-#define NV20TCL_RT_VERT 0x00000204
-#define NV20TCL_RT_VERT_Y_SHIFT 0
-#define NV20TCL_RT_VERT_Y_MASK 0x0000ffff
-#define NV20TCL_RT_VERT_H_SHIFT 16
-#define NV20TCL_RT_VERT_H_MASK 0xffff0000
-#define NV20TCL_RT_FORMAT 0x00000208
-#define NV20TCL_RT_FORMAT_TYPE_SHIFT 8
-#define NV20TCL_RT_FORMAT_TYPE_MASK 0x00000f00
-#define NV20TCL_RT_FORMAT_TYPE_LINEAR 0x00000100
-#define NV20TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200
-#define NV20TCL_RT_FORMAT_COLOR_SHIFT 0
-#define NV20TCL_RT_FORMAT_COLOR_MASK 0x0000001f
-#define NV20TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003
-#define NV20TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005
-#define NV20TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008
-#define NV20TCL_RT_FORMAT_COLOR_B8 0x00000009
-#define NV20TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d
-#define NV20TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f
-#define NV20TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010
-#define NV20TCL_RT_PITCH 0x0000020c
-#define NV20TCL_RT_PITCH_COLOR_PITCH_SHIFT 0
-#define NV20TCL_RT_PITCH_COLOR_PITCH_MASK 0x0000ffff
-#define NV20TCL_RT_PITCH_ZETA_PITCH_SHIFT 16
-#define NV20TCL_RT_PITCH_ZETA_PITCH_MASK 0xffff0000
-#define NV20TCL_COLOR_OFFSET 0x00000210
-#define NV20TCL_ZETA_OFFSET 0x00000214
-#define NV20TCL_RC_IN_ALPHA(x) (0x00000260+((x)*4))
-#define NV20TCL_RC_IN_ALPHA__SIZE 0x00000008
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_NV 0x0000000c
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE1_NV 0x0000000d
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4)
-#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
-#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_NV 0x00000c00
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE1_NV 0x00000d00
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12)
-#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
-#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_NV 0x000c0000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE1_NV 0x000d0000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20)
-#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
-#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_NV 0x0c000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE1_NV 0x0d000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28)
-#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
-#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV20TCL_RC_FINAL0 0x00000288
-#define NV20TCL_RC_FINAL0_D_INPUT_SHIFT 0
-#define NV20TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f
-#define NV20TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV20TCL_RC_FINAL0_D_INPUT_FOG 0x00000003
-#define NV20TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV20TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_NV 0x0000000c
-#define NV20TCL_RC_FINAL0_D_INPUT_SPARE1_NV 0x0000000d
-#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV20TCL_RC_FINAL0_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4)
-#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV20TCL_RC_FINAL0_D_MAPPING_SHIFT 5
-#define NV20TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0
-#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV20TCL_RC_FINAL0_C_INPUT_SHIFT 8
-#define NV20TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00
-#define NV20TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV20TCL_RC_FINAL0_C_INPUT_FOG 0x00000300
-#define NV20TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV20TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_NV 0x00000c00
-#define NV20TCL_RC_FINAL0_C_INPUT_SPARE1_NV 0x00000d00
-#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV20TCL_RC_FINAL0_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12)
-#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV20TCL_RC_FINAL0_C_MAPPING_SHIFT 13
-#define NV20TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000
-#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV20TCL_RC_FINAL0_B_INPUT_SHIFT 16
-#define NV20TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000
-#define NV20TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV20TCL_RC_FINAL0_B_INPUT_FOG 0x00030000
-#define NV20TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV20TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_NV 0x000c0000
-#define NV20TCL_RC_FINAL0_B_INPUT_SPARE1_NV 0x000d0000
-#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV20TCL_RC_FINAL0_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20)
-#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV20TCL_RC_FINAL0_B_MAPPING_SHIFT 21
-#define NV20TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000
-#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV20TCL_RC_FINAL0_A_INPUT_SHIFT 24
-#define NV20TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000
-#define NV20TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV20TCL_RC_FINAL0_A_INPUT_FOG 0x03000000
-#define NV20TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV20TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_NV 0x0c000000
-#define NV20TCL_RC_FINAL0_A_INPUT_SPARE1_NV 0x0d000000
-#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV20TCL_RC_FINAL0_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28)
-#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_SHIFT 29
-#define NV20TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV20TCL_RC_FINAL1 0x0000028c
-#define NV20TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
-#define NV20TCL_RC_FINAL1_G_INPUT_SHIFT 8
-#define NV20TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00
-#define NV20TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV20TCL_RC_FINAL1_G_INPUT_FOG 0x00000300
-#define NV20TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV20TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE0_ARB 0x00000800
-#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE1_ARB 0x00000900
-#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_NV 0x00000c00
-#define NV20TCL_RC_FINAL1_G_INPUT_SPARE1_NV 0x00000d00
-#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV20TCL_RC_FINAL1_G_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12)
-#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV20TCL_RC_FINAL1_G_MAPPING_SHIFT 13
-#define NV20TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000
-#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV20TCL_RC_FINAL1_F_INPUT_SHIFT 16
-#define NV20TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000
-#define NV20TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV20TCL_RC_FINAL1_F_INPUT_FOG 0x00030000
-#define NV20TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV20TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE0_ARB 0x00080000
-#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE1_ARB 0x00090000
-#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_NV 0x000c0000
-#define NV20TCL_RC_FINAL1_F_INPUT_SPARE1_NV 0x000d0000
-#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV20TCL_RC_FINAL1_F_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20)
-#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV20TCL_RC_FINAL1_F_MAPPING_SHIFT 21
-#define NV20TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000
-#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV20TCL_RC_FINAL1_E_INPUT_SHIFT 24
-#define NV20TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000
-#define NV20TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV20TCL_RC_FINAL1_E_INPUT_FOG 0x03000000
-#define NV20TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV20TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE0_ARB 0x08000000
-#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE1_ARB 0x09000000
-#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_NV 0x0c000000
-#define NV20TCL_RC_FINAL1_E_INPUT_SPARE1_NV 0x0d000000
-#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV20TCL_RC_FINAL1_E_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28)
-#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_SHIFT 29
-#define NV20TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV20TCL_LIGHT_CONTROL 0x00000294
-#define NV20TCL_FOG_MODE 0x0000029c
-#define NV20TCL_FOG_MODE_EXP 0x00000800
-#define NV20TCL_FOG_MODE_EXP_2 0x00000802
-#define NV20TCL_FOG_MODE_EXP2 0x00000803
-#define NV20TCL_FOG_MODE_LINEAR 0x00000804
-#define NV20TCL_FOG_MODE_LINEAR_2 0x00002601
-#define NV20TCL_FOG_COORD_DIST 0x000002a0
-#define NV20TCL_FOG_COORD_DIST_COORD_FALSE 0x00000000
-#define NV20TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_RADIAL_NV 0x00000001
-#define NV20TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_PLANE_ABSOLUTE_NV 0x00000002
-#define NV20TCL_FOG_COORD_DIST_COORD_FOG 0x00000003
-#define NV20TCL_FOG_ENABLE 0x000002a4
-#define NV20TCL_FOG_COLOR 0x000002a8
-#define NV20TCL_FOG_COLOR_R_SHIFT 0
-#define NV20TCL_FOG_COLOR_R_MASK 0x000000ff
-#define NV20TCL_FOG_COLOR_G_SHIFT 8
-#define NV20TCL_FOG_COLOR_G_MASK 0x0000ff00
-#define NV20TCL_FOG_COLOR_B_SHIFT 16
-#define NV20TCL_FOG_COLOR_B_MASK 0x00ff0000
-#define NV20TCL_FOG_COLOR_A_SHIFT 24
-#define NV20TCL_FOG_COLOR_A_MASK 0xff000000
-#define NV20TCL_VIEWPORT_CLIP_MODE 0x000002b4
-#define NV20TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*4))
-#define NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008
-#define NV20TCL_VIEWPORT_CLIP_VERT(x) (0x000002e0+((x)*4))
-#define NV20TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008
-#define NV20TCL_ALPHA_FUNC_ENABLE 0x00000300
-#define NV20TCL_BLEND_FUNC_ENABLE 0x00000304
-#define NV20TCL_CULL_FACE_ENABLE 0x00000308
-#define NV20TCL_DEPTH_TEST_ENABLE 0x0000030c
-#define NV20TCL_DITHER_ENABLE 0x00000310
-#define NV20TCL_LIGHTING_ENABLE 0x00000314
-#define NV20TCL_POINT_PARAMETERS_ENABLE 0x00000318
-#define NV20TCL_POINT_SMOOTH_ENABLE 0x0000031c
-#define NV20TCL_LINE_SMOOTH_ENABLE 0x00000320
-#define NV20TCL_POLYGON_SMOOTH_ENABLE 0x00000324
-#define NV20TCL_STENCIL_ENABLE 0x0000032c
-#define NV20TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000330
-#define NV20TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000334
-#define NV20TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000338
-#define NV20TCL_ALPHA_FUNC_FUNC 0x0000033c
-#define NV20TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200
-#define NV20TCL_ALPHA_FUNC_FUNC_LESS 0x00000201
-#define NV20TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202
-#define NV20TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
-#define NV20TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
-#define NV20TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
-#define NV20TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV20TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
-#define NV20TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
-#define NV20TCL_ALPHA_FUNC_REF 0x00000340
-#define NV20TCL_BLEND_FUNC_SRC 0x00000344
-#define NV20TCL_BLEND_FUNC_SRC_ZERO 0x00000000
-#define NV20TCL_BLEND_FUNC_SRC_ONE 0x00000001
-#define NV20TCL_BLEND_FUNC_SRC_SRC_COLOR 0x00000300
-#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA 0x00000302
-#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV20TCL_BLEND_FUNC_SRC_DST_ALPHA 0x00000304
-#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV20TCL_BLEND_FUNC_SRC_DST_COLOR 0x00000306
-#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR 0x00000307
-#define NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE 0x00000308
-#define NV20TCL_BLEND_FUNC_SRC_CONSTANT_COLOR 0x00008001
-#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV20TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA 0x00008003
-#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV20TCL_BLEND_FUNC_DST 0x00000348
-#define NV20TCL_BLEND_FUNC_DST_ZERO 0x00000000
-#define NV20TCL_BLEND_FUNC_DST_ONE 0x00000001
-#define NV20TCL_BLEND_FUNC_DST_SRC_COLOR 0x00000300
-#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV20TCL_BLEND_FUNC_DST_SRC_ALPHA 0x00000302
-#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV20TCL_BLEND_FUNC_DST_DST_ALPHA 0x00000304
-#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV20TCL_BLEND_FUNC_DST_DST_COLOR 0x00000306
-#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR 0x00000307
-#define NV20TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE 0x00000308
-#define NV20TCL_BLEND_FUNC_DST_CONSTANT_COLOR 0x00008001
-#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV20TCL_BLEND_FUNC_DST_CONSTANT_ALPHA 0x00008003
-#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV20TCL_BLEND_COLOR 0x0000034c
-#define NV20TCL_BLEND_COLOR_B_SHIFT 0
-#define NV20TCL_BLEND_COLOR_B_MASK 0x000000ff
-#define NV20TCL_BLEND_COLOR_G_SHIFT 8
-#define NV20TCL_BLEND_COLOR_G_MASK 0x0000ff00
-#define NV20TCL_BLEND_COLOR_R_SHIFT 16
-#define NV20TCL_BLEND_COLOR_R_MASK 0x00ff0000
-#define NV20TCL_BLEND_COLOR_A_SHIFT 24
-#define NV20TCL_BLEND_COLOR_A_MASK 0xff000000
-#define NV20TCL_BLEND_EQUATION 0x00000350
-#define NV20TCL_BLEND_EQUATION_FUNC_ADD 0x00008006
-#define NV20TCL_BLEND_EQUATION_MIN 0x00008007
-#define NV20TCL_BLEND_EQUATION_MAX 0x00008008
-#define NV20TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a
-#define NV20TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b
-#define NV20TCL_DEPTH_FUNC 0x00000354
-#define NV20TCL_DEPTH_FUNC_NEVER 0x00000200
-#define NV20TCL_DEPTH_FUNC_LESS 0x00000201
-#define NV20TCL_DEPTH_FUNC_EQUAL 0x00000202
-#define NV20TCL_DEPTH_FUNC_LEQUAL 0x00000203
-#define NV20TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV20TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV20TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
-#define NV20TCL_DEPTH_FUNC_GEQUAL 0x00000206
-#define NV20TCL_DEPTH_FUNC_ALWAYS 0x00000207
-#define NV20TCL_COLOR_MASK 0x00000358
-#define NV20TCL_COLOR_MASK_B (1 << 0)
-#define NV20TCL_COLOR_MASK_G (1 << 8)
-#define NV20TCL_COLOR_MASK_R (1 << 16)
-#define NV20TCL_COLOR_MASK_A (1 << 24)
-#define NV20TCL_DEPTH_WRITE_ENABLE 0x0000035c
-#define NV20TCL_STENCIL_MASK 0x00000360
-#define NV20TCL_STENCIL_FUNC_FUNC 0x00000364
-#define NV20TCL_STENCIL_FUNC_FUNC_NEVER 0x00000200
-#define NV20TCL_STENCIL_FUNC_FUNC_LESS 0x00000201
-#define NV20TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202
-#define NV20TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203
-#define NV20TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
-#define NV20TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
-#define NV20TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV20TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206
-#define NV20TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207
-#define NV20TCL_STENCIL_FUNC_REF 0x00000368
-#define NV20TCL_STENCIL_FUNC_MASK 0x0000036c
-#define NV20TCL_STENCIL_OP_FAIL 0x00000370
-#define NV20TCL_STENCIL_OP_FAIL_ZERO 0x00000000
-#define NV20TCL_STENCIL_OP_FAIL_INVERT 0x0000150a
-#define NV20TCL_STENCIL_OP_FAIL_KEEP 0x00001e00
-#define NV20TCL_STENCIL_OP_FAIL_REPLACE 0x00001e01
-#define NV20TCL_STENCIL_OP_FAIL_INCR 0x00001e02
-#define NV20TCL_STENCIL_OP_FAIL_DECR 0x00001e03
-#define NV20TCL_STENCIL_OP_FAIL_INCR_WRAP 0x00008507
-#define NV20TCL_STENCIL_OP_FAIL_DECR_WRAP 0x00008508
-#define NV20TCL_STENCIL_OP_ZFAIL 0x00000374
-#define NV20TCL_STENCIL_OP_ZFAIL_ZERO 0x00000000
-#define NV20TCL_STENCIL_OP_ZFAIL_INVERT 0x0000150a
-#define NV20TCL_STENCIL_OP_ZFAIL_KEEP 0x00001e00
-#define NV20TCL_STENCIL_OP_ZFAIL_REPLACE 0x00001e01
-#define NV20TCL_STENCIL_OP_ZFAIL_INCR 0x00001e02
-#define NV20TCL_STENCIL_OP_ZFAIL_DECR 0x00001e03
-#define NV20TCL_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV20TCL_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV20TCL_STENCIL_OP_ZPASS 0x00000378
-#define NV20TCL_STENCIL_OP_ZPASS_ZERO 0x00000000
-#define NV20TCL_STENCIL_OP_ZPASS_INVERT 0x0000150a
-#define NV20TCL_STENCIL_OP_ZPASS_KEEP 0x00001e00
-#define NV20TCL_STENCIL_OP_ZPASS_REPLACE 0x00001e01
-#define NV20TCL_STENCIL_OP_ZPASS_INCR 0x00001e02
-#define NV20TCL_STENCIL_OP_ZPASS_DECR 0x00001e03
-#define NV20TCL_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV20TCL_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV20TCL_SHADE_MODEL 0x0000037c
-#define NV20TCL_SHADE_MODEL_FLAT 0x00001d00
-#define NV20TCL_SHADE_MODEL_SMOOTH 0x00001d01
-#define NV20TCL_LINE_WIDTH 0x00000380
-#define NV20TCL_POLYGON_OFFSET_FACTOR 0x00000384
-#define NV20TCL_POLYGON_OFFSET_UNITS 0x00000388
-#define NV20TCL_POLYGON_MODE_FRONT 0x0000038c
-#define NV20TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
-#define NV20TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
-#define NV20TCL_POLYGON_MODE_FRONT_FILL 0x00001b02
-#define NV20TCL_POLYGON_MODE_BACK 0x00000390
-#define NV20TCL_POLYGON_MODE_BACK_POINT 0x00001b00
-#define NV20TCL_POLYGON_MODE_BACK_LINE 0x00001b01
-#define NV20TCL_POLYGON_MODE_BACK_FILL 0x00001b02
-#define NV20TCL_DEPTH_RANGE_NEAR 0x00000394
-#define NV20TCL_DEPTH_RANGE_FAR 0x00000398
-#define NV20TCL_CULL_FACE 0x0000039c
-#define NV20TCL_CULL_FACE_FRONT 0x00000404
-#define NV20TCL_CULL_FACE_BACK 0x00000405
-#define NV20TCL_CULL_FACE_FRONT_AND_BACK 0x00000408
-#define NV20TCL_FRONT_FACE 0x000003a0
-#define NV20TCL_FRONT_FACE_CW 0x00000900
-#define NV20TCL_FRONT_FACE_CCW 0x00000901
-#define NV20TCL_NORMALIZE_ENABLE 0x000003a4
-#define NV20TCL_COLOR_MATERIAL_FRONT_R 0x000003a8
-#define NV20TCL_COLOR_MATERIAL_FRONT_G 0x000003ac
-#define NV20TCL_COLOR_MATERIAL_FRONT_B 0x000003b0
-#define NV20TCL_COLOR_MATERIAL_FRONT_A 0x000003b4
-#define NV20TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8
-#define NV20TCL_ENABLED_LIGHTS 0x000003bc
-#define NV20TCL_TX_GEN_S(x) (0x000003c0+((x)*16))
-#define NV20TCL_TX_GEN_S__SIZE 0x00000004
-#define NV20TCL_TX_GEN_S_FALSE 0x00000000
-#define NV20TCL_TX_GEN_S_EYE_LINEAR 0x00002400
-#define NV20TCL_TX_GEN_S_OBJECT_LINEAR 0x00002401
-#define NV20TCL_TX_GEN_S_SPHERE_MAP 0x00002402
-#define NV20TCL_TX_GEN_S_NORMAL_MAP 0x00008511
-#define NV20TCL_TX_GEN_S_REFLECTION_MAP 0x00008512
-#define NV20TCL_TX_GEN_T(x) (0x000003c4+((x)*16))
-#define NV20TCL_TX_GEN_T__SIZE 0x00000004
-#define NV20TCL_TX_GEN_T_FALSE 0x00000000
-#define NV20TCL_TX_GEN_T_EYE_LINEAR 0x00002400
-#define NV20TCL_TX_GEN_T_OBJECT_LINEAR 0x00002401
-#define NV20TCL_TX_GEN_T_SPHERE_MAP 0x00002402
-#define NV20TCL_TX_GEN_T_NORMAL_MAP 0x00008511
-#define NV20TCL_TX_GEN_T_REFLECTION_MAP 0x00008512
-#define NV20TCL_TX_GEN_R(x) (0x000003c8+((x)*16))
-#define NV20TCL_TX_GEN_R__SIZE 0x00000004
-#define NV20TCL_TX_GEN_R_FALSE 0x00000000
-#define NV20TCL_TX_GEN_R_EYE_LINEAR 0x00002400
-#define NV20TCL_TX_GEN_R_OBJECT_LINEAR 0x00002401
-#define NV20TCL_TX_GEN_R_SPHERE_MAP 0x00002402
-#define NV20TCL_TX_GEN_R_NORMAL_MAP 0x00008511
-#define NV20TCL_TX_GEN_R_REFLECTION_MAP 0x00008512
-#define NV20TCL_TX_GEN_Q(x) (0x000003cc+((x)*16))
-#define NV20TCL_TX_GEN_Q__SIZE 0x00000004
-#define NV20TCL_TX_GEN_Q_FALSE 0x00000000
-#define NV20TCL_TX_GEN_Q_EYE_LINEAR 0x00002400
-#define NV20TCL_TX_GEN_Q_OBJECT_LINEAR 0x00002401
-#define NV20TCL_TX_GEN_Q_SPHERE_MAP 0x00002402
-#define NV20TCL_TX_GEN_Q_NORMAL_MAP 0x00008511
-#define NV20TCL_TX_GEN_Q_REFLECTION_MAP 0x00008512
-#define NV20TCL_TX_MATRIX_ENABLE(x) (0x00000420+((x)*4))
-#define NV20TCL_TX_MATRIX_ENABLE__SIZE 0x00000004
-#define NV20TCL_POINT_SIZE 0x0000043c
-#define NV20TCL_MODELVIEW0_MATRIX(x) (0x00000480+((x)*4))
-#define NV20TCL_MODELVIEW0_MATRIX__SIZE 0x00000010
-#define NV20TCL_MODELVIEW1_MATRIX(x) (0x000004c0+((x)*4))
-#define NV20TCL_MODELVIEW1_MATRIX__SIZE 0x00000010
-#define NV20TCL_MODELVIEW2_MATRIX(x) (0x00000500+((x)*4))
-#define NV20TCL_MODELVIEW2_MATRIX__SIZE 0x00000010
-#define NV20TCL_MODELVIEW3_MATRIX(x) (0x00000540+((x)*4))
-#define NV20TCL_MODELVIEW3_MATRIX__SIZE 0x00000010
-#define NV20TCL_INVERSE_MODELVIEW0_MATRIX(x) (0x00000580+((x)*4))
-#define NV20TCL_INVERSE_MODELVIEW0_MATRIX__SIZE 0x00000010
-#define NV20TCL_INVERSE_MODELVIEW1_MATRIX(x) (0x000005c0+((x)*4))
-#define NV20TCL_INVERSE_MODELVIEW1_MATRIX__SIZE 0x00000010
-#define NV20TCL_INVERSE_MODELVIEW2_MATRIX(x) (0x00000600+((x)*4))
-#define NV20TCL_INVERSE_MODELVIEW2_MATRIX__SIZE 0x00000010
-#define NV20TCL_INVERSE_MODELVIEW3_MATRIX(x) (0x00000640+((x)*4))
-#define NV20TCL_INVERSE_MODELVIEW3_MATRIX__SIZE 0x00000010
-#define NV20TCL_PROJECTION_MATRIX(x) (0x00000680+((x)*4))
-#define NV20TCL_PROJECTION_MATRIX__SIZE 0x00000010
-#define NV20TCL_TX0_MATRIX(x) (0x000006c0+((x)*4))
-#define NV20TCL_TX0_MATRIX__SIZE 0x00000010
-#define NV20TCL_TX1_MATRIX(x) (0x00000700+((x)*4))
-#define NV20TCL_TX1_MATRIX__SIZE 0x00000010
-#define NV20TCL_TX2_MATRIX(x) (0x00000740+((x)*4))
-#define NV20TCL_TX2_MATRIX__SIZE 0x00000010
-#define NV20TCL_TX3_MATRIX(x) (0x00000780+((x)*4))
-#define NV20TCL_TX3_MATRIX__SIZE 0x00000010
-#define NV20TCL_TX0_CLIP_PLANE_A(x) (0x00000840+((x)*16))
-#define NV20TCL_TX0_CLIP_PLANE_A__SIZE 0x00000004
-#define NV20TCL_TX0_CLIP_PLANE_B(x) (0x00000844+((x)*16))
-#define NV20TCL_TX0_CLIP_PLANE_B__SIZE 0x00000004
-#define NV20TCL_TX0_CLIP_PLANE_C(x) (0x00000848+((x)*16))
-#define NV20TCL_TX0_CLIP_PLANE_C__SIZE 0x00000004
-#define NV20TCL_TX0_CLIP_PLANE_D(x) (0x0000084c+((x)*16))
-#define NV20TCL_TX0_CLIP_PLANE_D__SIZE 0x00000004
-#define NV20TCL_TX1_CLIP_PLANE_A(x) (0x00000880+((x)*16))
-#define NV20TCL_TX1_CLIP_PLANE_A__SIZE 0x00000004
-#define NV20TCL_TX1_CLIP_PLANE_B(x) (0x00000884+((x)*16))
-#define NV20TCL_TX1_CLIP_PLANE_B__SIZE 0x00000004
-#define NV20TCL_TX1_CLIP_PLANE_C(x) (0x00000888+((x)*16))
-#define NV20TCL_TX1_CLIP_PLANE_C__SIZE 0x00000004
-#define NV20TCL_TX1_CLIP_PLANE_D(x) (0x0000088c+((x)*16))
-#define NV20TCL_TX1_CLIP_PLANE_D__SIZE 0x00000004
-#define NV20TCL_TX2_CLIP_PLANE_A(x) (0x000008c0+((x)*16))
-#define NV20TCL_TX2_CLIP_PLANE_A__SIZE 0x00000004
-#define NV20TCL_TX2_CLIP_PLANE_B(x) (0x000008c4+((x)*16))
-#define NV20TCL_TX2_CLIP_PLANE_B__SIZE 0x00000004
-#define NV20TCL_TX2_CLIP_PLANE_C(x) (0x000008c8+((x)*16))
-#define NV20TCL_TX2_CLIP_PLANE_C__SIZE 0x00000004
-#define NV20TCL_TX2_CLIP_PLANE_D(x) (0x000008cc+((x)*16))
-#define NV20TCL_TX2_CLIP_PLANE_D__SIZE 0x00000004
-#define NV20TCL_TX3_CLIP_PLANE_A(x) (0x00000900+((x)*16))
-#define NV20TCL_TX3_CLIP_PLANE_A__SIZE 0x00000004
-#define NV20TCL_TX3_CLIP_PLANE_B(x) (0x00000904+((x)*16))
-#define NV20TCL_TX3_CLIP_PLANE_B__SIZE 0x00000004
-#define NV20TCL_TX3_CLIP_PLANE_C(x) (0x00000908+((x)*16))
-#define NV20TCL_TX3_CLIP_PLANE_C__SIZE 0x00000004
-#define NV20TCL_TX3_CLIP_PLANE_D(x) (0x0000090c+((x)*16))
-#define NV20TCL_TX3_CLIP_PLANE_D__SIZE 0x00000004
-#define NV20TCL_FOG_EQUATION_CONSTANT 0x000009c0
-#define NV20TCL_FOG_EQUATION_LINEAR 0x000009c4
-#define NV20TCL_FOG_EQUATION_QUADRATIC 0x000009c8
-#define NV20TCL_FRONT_MATERIAL_SHININESS(x) (0x000009e0+((x)*4))
-#define NV20TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006
-#define NV20TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10
-#define NV20TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14
-#define NV20TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18
-#define NV20TCL_VIEWPORT_SCALE0_X 0x00000a20
-#define NV20TCL_VIEWPORT_SCALE0_Y 0x00000a24
-#define NV20TCL_VIEWPORT_SCALE0_Z 0x00000a28
-#define NV20TCL_VIEWPORT_SCALE0_W 0x00000a2c
-#define NV20TCL_POINT_PARAMETER(x) (0x00000a30+((x)*4))
-#define NV20TCL_POINT_PARAMETER__SIZE 0x00000008
-#define NV20TCL_RC_CONSTANT_COLOR0(x) (0x00000a60+((x)*4))
-#define NV20TCL_RC_CONSTANT_COLOR0__SIZE 0x00000008
-#define NV20TCL_RC_CONSTANT_COLOR0_B_SHIFT 0
-#define NV20TCL_RC_CONSTANT_COLOR0_B_MASK 0x000000ff
-#define NV20TCL_RC_CONSTANT_COLOR0_G_SHIFT 8
-#define NV20TCL_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00
-#define NV20TCL_RC_CONSTANT_COLOR0_R_SHIFT 16
-#define NV20TCL_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000
-#define NV20TCL_RC_CONSTANT_COLOR0_A_SHIFT 24
-#define NV20TCL_RC_CONSTANT_COLOR0_A_MASK 0xff000000
-#define NV20TCL_RC_CONSTANT_COLOR1(x) (0x00000a80+((x)*4))
-#define NV20TCL_RC_CONSTANT_COLOR1__SIZE 0x00000008
-#define NV20TCL_RC_CONSTANT_COLOR1_B_SHIFT 0
-#define NV20TCL_RC_CONSTANT_COLOR1_B_MASK 0x000000ff
-#define NV20TCL_RC_CONSTANT_COLOR1_G_SHIFT 8
-#define NV20TCL_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00
-#define NV20TCL_RC_CONSTANT_COLOR1_R_SHIFT 16
-#define NV20TCL_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000
-#define NV20TCL_RC_CONSTANT_COLOR1_A_SHIFT 24
-#define NV20TCL_RC_CONSTANT_COLOR1_A_MASK 0xff000000
-#define NV20TCL_RC_OUT_ALPHA(x) (0x00000aa0+((x)*4))
-#define NV20TCL_RC_OUT_ALPHA__SIZE 0x00000008
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB 0x00000008
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB 0x00000009
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV 0x0000000c
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV 0x0000000d
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x00000080
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x00000090
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000000c0
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000000d0
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x00000c00
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x00000d00
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
-#define NV20TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
-#define NV20TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
-#define NV20TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14)
-#define NV20TCL_RC_OUT_ALPHA_BIAS (1 << 15)
-#define NV20TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000
-#define NV20TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SHIFT 17
-#define NV20TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000
-#define NV20TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x00020000
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x00040000
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
-#define NV20TCL_RC_IN_RGB(x) (0x00000ac0+((x)*4))
-#define NV20TCL_RC_IN_RGB__SIZE 0x00000008
-#define NV20TCL_RC_IN_RGB_D_INPUT_SHIFT 0
-#define NV20TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f
-#define NV20TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV20TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003
-#define NV20TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV20TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_NV 0x0000000c
-#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE1_NV 0x0000000d
-#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV20TCL_RC_IN_RGB_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4)
-#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV20TCL_RC_IN_RGB_D_MAPPING_SHIFT 5
-#define NV20TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0
-#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV20TCL_RC_IN_RGB_C_INPUT_SHIFT 8
-#define NV20TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00
-#define NV20TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV20TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300
-#define NV20TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV20TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_NV 0x00000c00
-#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE1_NV 0x00000d00
-#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV20TCL_RC_IN_RGB_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12)
-#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_SHIFT 13
-#define NV20TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV20TCL_RC_IN_RGB_B_INPUT_SHIFT 16
-#define NV20TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000
-#define NV20TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV20TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000
-#define NV20TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV20TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_NV 0x000c0000
-#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE1_NV 0x000d0000
-#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV20TCL_RC_IN_RGB_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20)
-#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_SHIFT 21
-#define NV20TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV20TCL_RC_IN_RGB_A_INPUT_SHIFT 24
-#define NV20TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_NV 0x0c000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE1_NV 0x0d000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV20TCL_RC_IN_RGB_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28)
-#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
-#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_SHIFT 29
-#define NV20TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV20TCL_VIEWPORT_SCALE1_X 0x00000af0
-#define NV20TCL_VIEWPORT_SCALE1_Y 0x00000af4
-#define NV20TCL_VIEWPORT_SCALE1_Z 0x00000af8
-#define NV20TCL_VIEWPORT_SCALE1_W 0x00000afc
-#define NV20TCL_VP_UPLOAD_INST(x) (0x00000b00+((x)*4))
-#define NV20TCL_VP_UPLOAD_INST__SIZE 0x00000004
-#define NV20TCL_VP_UPLOAD_CONST(x) (0x00000b80+((x)*4))
-#define NV20TCL_VP_UPLOAD_CONST__SIZE 0x00000004
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_R(x) (0x00000c00+((x)*64))
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_G(x) (0x00000c04+((x)*64))
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_B(x) (0x00000c08+((x)*64))
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x) (0x00001000+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x) (0x00001004+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x) (0x00001008+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x) (0x0000100c+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x) (0x00001010+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x) (0x00001014+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x) (0x00001018+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x) (0x0000101c+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE 0x00000008
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x) (0x00001020+((x)*128))
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE 0x00000008
-#define NV20TCL_LIGHT_HALF_VECTOR_X(x) (0x00001028+((x)*128))
-#define NV20TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008
-#define NV20TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000102c+((x)*128))
-#define NV20TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008
-#define NV20TCL_LIGHT_HALF_VECTOR_Z(x) (0x00001030+((x)*128))
-#define NV20TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008
-#define NV20TCL_LIGHT_DIRECTION_X(x) (0x00001034+((x)*128))
-#define NV20TCL_LIGHT_DIRECTION_X__SIZE 0x00000008
-#define NV20TCL_LIGHT_DIRECTION_Y(x) (0x00001038+((x)*128))
-#define NV20TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008
-#define NV20TCL_LIGHT_DIRECTION_Z(x) (0x0000103c+((x)*128))
-#define NV20TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008
-#define NV20TCL_LIGHT_POSITION_X(x) (0x0000105c+((x)*128))
-#define NV20TCL_LIGHT_POSITION_X__SIZE 0x00000008
-#define NV20TCL_LIGHT_POSITION_Y(x) (0x00001060+((x)*128))
-#define NV20TCL_LIGHT_POSITION_Y__SIZE 0x00000008
-#define NV20TCL_LIGHT_POSITION_Z(x) (0x00001064+((x)*128))
-#define NV20TCL_LIGHT_POSITION_Z__SIZE 0x00000008
-#define NV20TCL_LIGHT_CONSTANT_ATTENUATION(x) (0x00001068+((x)*128))
-#define NV20TCL_LIGHT_CONSTANT_ATTENUATION__SIZE 0x00000008
-#define NV20TCL_LIGHT_LINEAR_ATTENUATION(x) (0x0000106c+((x)*128))
-#define NV20TCL_LIGHT_LINEAR_ATTENUATION__SIZE 0x00000008
-#define NV20TCL_LIGHT_QUADRATIC_ATTENUATION(x) (0x00001070+((x)*128))
-#define NV20TCL_LIGHT_QUADRATIC_ATTENUATION__SIZE 0x00000008
-#define NV20TCL_POLYGON_STIPPLE_ENABLE 0x0000147c
-#define NV20TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4))
-#define NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020
-#define NV20TCL_VERTEX_POS_3F_X 0x00001500
-#define NV20TCL_VERTEX_POS_3F_Y 0x00001504
-#define NV20TCL_VERTEX_POS_3F_Z 0x00001508
-#define NV20TCL_VERTEX_POS_4F_X 0x00001518
-#define NV20TCL_VERTEX_POS_4F_Y 0x0000151c
-#define NV20TCL_VERTEX_POS_4F_Z 0x00001520
-#define NV20TCL_VERTEX_POS_3I_XY 0x00001528
-#define NV20TCL_VERTEX_POS_3I_XY_X_SHIFT 0
-#define NV20TCL_VERTEX_POS_3I_XY_X_MASK 0x0000ffff
-#define NV20TCL_VERTEX_POS_3I_XY_Y_SHIFT 16
-#define NV20TCL_VERTEX_POS_3I_XY_Y_MASK 0xffff0000
-#define NV20TCL_VERTEX_POS_3I_Z 0x0000152c
-#define NV20TCL_VERTEX_POS_3I_Z_Z_SHIFT 0
-#define NV20TCL_VERTEX_POS_3I_Z_Z_MASK 0x0000ffff
-#define NV20TCL_VERTEX_NOR_3F_X 0x00001530
-#define NV20TCL_VERTEX_NOR_3F_Y 0x00001534
-#define NV20TCL_VERTEX_NOR_3F_Z 0x00001538
-#define NV20TCL_VERTEX_NOR_3I_XY 0x00001540
-#define NV20TCL_VERTEX_NOR_3I_XY_X_SHIFT 0
-#define NV20TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
-#define NV20TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16
-#define NV20TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
-#define NV20TCL_VERTEX_NOR_3I_Z 0x00001544
-#define NV20TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0
-#define NV20TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
-#define NV20TCL_VERTEX_COL_4F_X 0x00001550
-#define NV20TCL_VERTEX_COL_4F_Y 0x00001554
-#define NV20TCL_VERTEX_COL_4F_Z 0x00001558
-#define NV20TCL_VERTEX_COL_4F_W 0x0000155c
-#define NV20TCL_VERTEX_COL_3F_X 0x00001560
-#define NV20TCL_VERTEX_COL_3F_Y 0x00001564
-#define NV20TCL_VERTEX_COL_3F_Z 0x00001568
-#define NV20TCL_VERTEX_COL_4I 0x0000156c
-#define NV20TCL_VERTEX_COL_4I_R_SHIFT 0
-#define NV20TCL_VERTEX_COL_4I_R_MASK 0x000000ff
-#define NV20TCL_VERTEX_COL_4I_G_SHIFT 8
-#define NV20TCL_VERTEX_COL_4I_G_MASK 0x0000ff00
-#define NV20TCL_VERTEX_COL_4I_B_SHIFT 16
-#define NV20TCL_VERTEX_COL_4I_B_MASK 0x00ff0000
-#define NV20TCL_VERTEX_COL_4I_A_SHIFT 24
-#define NV20TCL_VERTEX_COL_4I_A_MASK 0xff000000
-#define NV20TCL_VERTEX_COL2_3F_X 0x00001580
-#define NV20TCL_VERTEX_COL2_3F_Y 0x00001584
-#define NV20TCL_VERTEX_COL2_3F_Z 0x00001588
-#define NV20TCL_VERTEX_COL2_4I 0x0000158c
-#define NV20TCL_VERTEX_COL2_4I_R_SHIFT 0
-#define NV20TCL_VERTEX_COL2_4I_R_MASK 0x000000ff
-#define NV20TCL_VERTEX_COL2_4I_G_SHIFT 8
-#define NV20TCL_VERTEX_COL2_4I_G_MASK 0x0000ff00
-#define NV20TCL_VERTEX_COL2_4I_B_SHIFT 16
-#define NV20TCL_VERTEX_COL2_4I_B_MASK 0x00ff0000
-#define NV20TCL_VERTEX_COL2_4I_A_SHIFT 24
-#define NV20TCL_VERTEX_COL2_4I_A_MASK 0xff000000
-#define NV20TCL_VERTEX_TX0_2F_S 0x00001590
-#define NV20TCL_VERTEX_TX0_2F_T 0x00001594
-#define NV20TCL_VERTEX_TX0_2I 0x00001598
-#define NV20TCL_VERTEX_TX0_2I_S_SHIFT 0
-#define NV20TCL_VERTEX_TX0_2I_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX0_2I_T_SHIFT 16
-#define NV20TCL_VERTEX_TX0_2I_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX0_4F_S 0x000015a0
-#define NV20TCL_VERTEX_TX0_4F_T 0x000015a4
-#define NV20TCL_VERTEX_TX0_4F_R 0x000015a8
-#define NV20TCL_VERTEX_TX0_4F_Q 0x000015ac
-#define NV20TCL_VERTEX_TX0_4I_ST 0x000015b0
-#define NV20TCL_VERTEX_TX0_4I_ST_S_SHIFT 0
-#define NV20TCL_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX0_4I_ST_T_SHIFT 16
-#define NV20TCL_VERTEX_TX0_4I_ST_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX0_4I_RQ 0x000015b4
-#define NV20TCL_VERTEX_TX0_4I_RQ_R_SHIFT 0
-#define NV20TCL_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX0_4I_RQ_Q_SHIFT 16
-#define NV20TCL_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX1_2F_S 0x000015b8
-#define NV20TCL_VERTEX_TX1_2F_T 0x000015bc
-#define NV20TCL_VERTEX_TX1_2I 0x000015c0
-#define NV20TCL_VERTEX_TX1_2I_S_SHIFT 0
-#define NV20TCL_VERTEX_TX1_2I_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX1_2I_T_SHIFT 16
-#define NV20TCL_VERTEX_TX1_2I_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX1_4F_S 0x000015c8
-#define NV20TCL_VERTEX_TX1_4F_T 0x000015cc
-#define NV20TCL_VERTEX_TX1_4F_R 0x000015d0
-#define NV20TCL_VERTEX_TX1_4F_Q 0x000015d4
-#define NV20TCL_VERTEX_TX1_4I_ST 0x000015d8
-#define NV20TCL_VERTEX_TX1_4I_ST_S_SHIFT 0
-#define NV20TCL_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX1_4I_ST_T_SHIFT 16
-#define NV20TCL_VERTEX_TX1_4I_ST_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX1_4I_RQ 0x000015dc
-#define NV20TCL_VERTEX_TX1_4I_RQ_R_SHIFT 0
-#define NV20TCL_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX1_4I_RQ_Q_SHIFT 16
-#define NV20TCL_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX2_2F_S 0x000015e0
-#define NV20TCL_VERTEX_TX2_2F_T 0x000015e4
-#define NV20TCL_VERTEX_TX2_2I 0x000015e8
-#define NV20TCL_VERTEX_TX2_2I_S_SHIFT 0
-#define NV20TCL_VERTEX_TX2_2I_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX2_2I_T_SHIFT 16
-#define NV20TCL_VERTEX_TX2_2I_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX2_4F_S 0x000015f0
-#define NV20TCL_VERTEX_TX2_4F_T 0x000015f4
-#define NV20TCL_VERTEX_TX2_4F_R 0x000015f8
-#define NV20TCL_VERTEX_TX2_4F_Q 0x000015fc
-#define NV20TCL_VERTEX_TX2_4I_ST 0x00001600
-#define NV20TCL_VERTEX_TX2_4I_ST_S_SHIFT 0
-#define NV20TCL_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX2_4I_ST_T_SHIFT 16
-#define NV20TCL_VERTEX_TX2_4I_ST_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX2_4I_RQ 0x00001604
-#define NV20TCL_VERTEX_TX2_4I_RQ_R_SHIFT 0
-#define NV20TCL_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX2_4I_RQ_Q_SHIFT 16
-#define NV20TCL_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX3_2F_S 0x00001608
-#define NV20TCL_VERTEX_TX3_2F_T 0x0000160c
-#define NV20TCL_VERTEX_TX3_2I 0x00001610
-#define NV20TCL_VERTEX_TX3_2I_S_SHIFT 0
-#define NV20TCL_VERTEX_TX3_2I_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX3_2I_T_SHIFT 16
-#define NV20TCL_VERTEX_TX3_2I_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX3_4F_S 0x00001620
-#define NV20TCL_VERTEX_TX3_4F_T 0x00001624
-#define NV20TCL_VERTEX_TX3_4F_R 0x00001628
-#define NV20TCL_VERTEX_TX3_4F_Q 0x0000162c
-#define NV20TCL_VERTEX_TX3_4I_ST 0x00001630
-#define NV20TCL_VERTEX_TX3_4I_ST_S_SHIFT 0
-#define NV20TCL_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX3_4I_ST_T_SHIFT 16
-#define NV20TCL_VERTEX_TX3_4I_ST_T_MASK 0xffff0000
-#define NV20TCL_VERTEX_TX3_4I_RQ 0x00001634
-#define NV20TCL_VERTEX_TX3_4I_RQ_R_SHIFT 0
-#define NV20TCL_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff
-#define NV20TCL_VERTEX_TX3_4I_RQ_Q_SHIFT 16
-#define NV20TCL_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000
-#define NV20TCL_VERTEX_FOG_1F 0x00001698
-#define NV20TCL_EDGEFLAG_ENABLE 0x000016bc
-#define NV20TCL_VTXBUF_ADDRESS(x) (0x00001720+((x)*4))
-#define NV20TCL_VTXBUF_ADDRESS__SIZE 0x00000010
-#define NV20TCL_VTXBUF_ADDRESS_DMA1 (1 << 31)
-#define NV20TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0
-#define NV20TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff
-#define NV20TCL_VTXFMT(x) (0x00001760+((x)*4))
-#define NV20TCL_VTXFMT__SIZE 0x00000010
-#define NV20TCL_VTXFMT_TYPE_SHIFT 0
-#define NV20TCL_VTXFMT_TYPE_MASK 0x0000000f
-#define NV20TCL_VTXFMT_TYPE_FLOAT 0x00000002
-#define NV20TCL_VTXFMT_TYPE_UBYTE 0x00000004
-#define NV20TCL_VTXFMT_TYPE_USHORT 0x00000005
-#define NV20TCL_VTXFMT_SIZE_SHIFT 4
-#define NV20TCL_VTXFMT_SIZE_MASK 0x000000f0
-#define NV20TCL_VTXFMT_STRIDE_SHIFT 8
-#define NV20TCL_VTXFMT_STRIDE_MASK 0x0000ff00
-#define NV20TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0
-#define NV20TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4
-#define NV20TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8
-#define NV20TCL_COLOR_MATERIAL_BACK_A 0x000017ac
-#define NV20TCL_COLOR_MATERIAL_BACK_R 0x000017b0
-#define NV20TCL_COLOR_MATERIAL_BACK_G 0x000017b4
-#define NV20TCL_COLOR_MATERIAL_BACK_B 0x000017b8
-#define NV20TCL_COLOR_LOGIC_OP_ENABLE 0x000017bc
-#define NV20TCL_COLOR_LOGIC_OP_OP 0x000017c0
-#define NV20TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
-#define NV20TCL_COLOR_LOGIC_OP_OP_AND 0x00001501
-#define NV20TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502
-#define NV20TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503
-#define NV20TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504
-#define NV20TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505
-#define NV20TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506
-#define NV20TCL_COLOR_LOGIC_OP_OP_OR 0x00001507
-#define NV20TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508
-#define NV20TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509
-#define NV20TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a
-#define NV20TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b
-#define NV20TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c
-#define NV20TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d
-#define NV20TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e
-#define NV20TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f
-#define NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE 0x000017c4
-#define NV20TCL_TX_SHADER_CULL_MODE 0x000017f8
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S (1 << 0)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S_LESS 0x00000001
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T (1 << 1)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T_LESS 0x00000002
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R (1 << 2)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R_LESS 0x00000004
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q (1 << 3)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_LESS 0x00000008
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S (1 << 4)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S_LESS 0x00000010
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T (1 << 5)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T_LESS 0x00000020
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R (1 << 6)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R_LESS 0x00000040
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q (1 << 7)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_LESS 0x00000080
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S (1 << 8)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S_LESS 0x00000100
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T (1 << 9)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T_LESS 0x00000200
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R (1 << 10)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R_LESS 0x00000400
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q (1 << 11)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_LESS 0x00000800
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S (1 << 12)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S_LESS 0x00001000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T (1 << 13)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T_LESS 0x00002000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R (1 << 14)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R_LESS 0x00004000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q (1 << 15)
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_GEQUAL 0x00000000
-#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_LESS 0x00008000
-#define NV20TCL_VERTEX_BEGIN_END 0x000017fc
-#define NV20TCL_VERTEX_BEGIN_END_STOP 0x00000000
-#define NV20TCL_VERTEX_BEGIN_END_POINTS 0x00000001
-#define NV20TCL_VERTEX_BEGIN_END_LINES 0x00000002
-#define NV20TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003
-#define NV20TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004
-#define NV20TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005
-#define NV20TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006
-#define NV20TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007
-#define NV20TCL_VERTEX_BEGIN_END_QUADS 0x00000008
-#define NV20TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009
-#define NV20TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a
-#define NV20TCL_VB_ELEMENT_U16 0x00001800
-#define NV20TCL_VB_ELEMENT_U16_I0_SHIFT 0
-#define NV20TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff
-#define NV20TCL_VB_ELEMENT_U16_I1_SHIFT 16
-#define NV20TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000
-#define NV20TCL_VB_VERTEX_BATCH 0x00001810
-#define NV20TCL_VB_VERTEX_BATCH_OFFSET_SHIFT 0
-#define NV20TCL_VB_VERTEX_BATCH_OFFSET_MASK 0x00ffffff
-#define NV20TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24
-#define NV20TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000
-#define NV20TCL_VERTEX_DATA 0x00001818
-#define NV20TCL_TX_SHADER_CONST_EYE_X 0x0000181c
-#define NV20TCL_TX_SHADER_CONST_EYE_Y 0x00001820
-#define NV20TCL_TX_SHADER_CONST_EYE_Z 0x00001824
-#define NV20TCL_VTX_ATTR_4F_X(x) (0x00001a00+((x)*16))
-#define NV20TCL_VTX_ATTR_4F_X__SIZE 0x00000010
-#define NV20TCL_VTX_ATTR_4F_Y(x) (0x00001a04+((x)*16))
-#define NV20TCL_VTX_ATTR_4F_Y__SIZE 0x00000010
-#define NV20TCL_VTX_ATTR_4F_Z(x) (0x00001a08+((x)*16))
-#define NV20TCL_VTX_ATTR_4F_Z__SIZE 0x00000010
-#define NV20TCL_VTX_ATTR_4F_W(x) (0x00001a0c+((x)*16))
-#define NV20TCL_VTX_ATTR_4F_W__SIZE 0x00000010
-#define NV20TCL_TX_OFFSET(x) (0x00001b00+((x)*64))
-#define NV20TCL_TX_OFFSET__SIZE 0x00000004
-#define NV20TCL_TX_FORMAT(x) (0x00001b04+((x)*64))
-#define NV20TCL_TX_FORMAT__SIZE 0x00000004
-#define NV20TCL_TX_FORMAT_DMA0 (1 << 0)
-#define NV20TCL_TX_FORMAT_DMA1 (1 << 1)
-#define NV20TCL_TX_FORMAT_CUBIC (1 << 2)
-#define NV20TCL_TX_FORMAT_NO_BORDER (1 << 3)
-#define NV20TCL_TX_FORMAT_DIMS_SHIFT 4
-#define NV20TCL_TX_FORMAT_DIMS_MASK 0x000000f0
-#define NV20TCL_TX_FORMAT_DIMS_1D 0x00000010
-#define NV20TCL_TX_FORMAT_DIMS_2D 0x00000020
-#define NV20TCL_TX_FORMAT_DIMS_3D 0x00000030
-#define NV20TCL_TX_FORMAT_FORMAT_SHIFT 8
-#define NV20TCL_TX_FORMAT_FORMAT_MASK 0x0000ff00
-#define NV20TCL_TX_FORMAT_FORMAT_L8 0x00000000
-#define NV20TCL_TX_FORMAT_FORMAT_A8 0x00000100
-#define NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000200
-#define NV20TCL_TX_FORMAT_FORMAT_A8_RECT 0x00000300
-#define NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000400
-#define NV20TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000500
-#define NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000600
-#define NV20TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000700
-#define NV20TCL_TX_FORMAT_FORMAT_INDEX8 0x00000b00
-#define NV20TCL_TX_FORMAT_FORMAT_DXT1 0x00000c00
-#define NV20TCL_TX_FORMAT_FORMAT_DXT3 0x00000e00
-#define NV20TCL_TX_FORMAT_FORMAT_DXT5 0x00000f00
-#define NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000
-#define NV20TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100
-#define NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200
-#define NV20TCL_TX_FORMAT_FORMAT_L8_RECT 0x00001300
-#define NV20TCL_TX_FORMAT_FORMAT_A8L8 0x00001a00
-#define NV20TCL_TX_FORMAT_FORMAT_A8_RECT2 0x00001b00
-#define NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00
-#define NV20TCL_TX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00
-#define NV20TCL_TX_FORMAT_FORMAT_L8A8_RECT 0x00002000
-#define NV20TCL_TX_FORMAT_FORMAT_DSDT 0x00002800
-#define NV20TCL_TX_FORMAT_FORMAT_A16 0x00003200
-#define NV20TCL_TX_FORMAT_FORMAT_HILO16 0x00003300
-#define NV20TCL_TX_FORMAT_FORMAT_A16_RECT 0x00003500
-#define NV20TCL_TX_FORMAT_FORMAT_HILO16_RECT 0x00003600
-#define NV20TCL_TX_FORMAT_FORMAT_HILO8 0x00004400
-#define NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500
-#define NV20TCL_TX_FORMAT_FORMAT_HILO8_RECT 0x00004600
-#define NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700
-#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00
-#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00
-#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00
-#define NV20TCL_TX_FORMAT_MIPMAP (1 << 19)
-#define NV20TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 20
-#define NV20TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x00f00000
-#define NV20TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 24
-#define NV20TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x0f000000
-#define NV20TCL_TX_FORMAT_BASE_SIZE_W_SHIFT 28
-#define NV20TCL_TX_FORMAT_BASE_SIZE_W_MASK 0xf0000000
-#define NV20TCL_TX_WRAP(x) (0x00001b08+((x)*64))
-#define NV20TCL_TX_WRAP__SIZE 0x00000004
-#define NV20TCL_TX_WRAP_S_SHIFT 0
-#define NV20TCL_TX_WRAP_S_MASK 0x000000ff
-#define NV20TCL_TX_WRAP_S_REPEAT 0x00000001
-#define NV20TCL_TX_WRAP_S_MIRRORED_REPEAT 0x00000002
-#define NV20TCL_TX_WRAP_S_CLAMP_TO_EDGE 0x00000003
-#define NV20TCL_TX_WRAP_S_CLAMP_TO_BORDER 0x00000004
-#define NV20TCL_TX_WRAP_S_CLAMP 0x00000005
-#define NV20TCL_TX_WRAP_T_SHIFT 8
-#define NV20TCL_TX_WRAP_T_MASK 0x00000f00
-#define NV20TCL_TX_WRAP_T_REPEAT 0x00000100
-#define NV20TCL_TX_WRAP_T_MIRRORED_REPEAT 0x00000200
-#define NV20TCL_TX_WRAP_T_CLAMP_TO_EDGE 0x00000300
-#define NV20TCL_TX_WRAP_T_CLAMP_TO_BORDER 0x00000400
-#define NV20TCL_TX_WRAP_T_CLAMP 0x00000500
-#define NV20TCL_TX_WRAP_R_SHIFT 16
-#define NV20TCL_TX_WRAP_R_MASK 0x000f0000
-#define NV20TCL_TX_WRAP_R_REPEAT 0x00010000
-#define NV20TCL_TX_WRAP_R_MIRRORED_REPEAT 0x00020000
-#define NV20TCL_TX_WRAP_R_CLAMP_TO_EDGE 0x00030000
-#define NV20TCL_TX_WRAP_R_CLAMP_TO_BORDER 0x00040000
-#define NV20TCL_TX_WRAP_R_CLAMP 0x00050000
-#define NV20TCL_TX_ENABLE(x) (0x00001b0c+((x)*64))
-#define NV20TCL_TX_ENABLE__SIZE 0x00000004
-#define NV20TCL_TX_ENABLE_ANISO_SHIFT 4
-#define NV20TCL_TX_ENABLE_ANISO_MASK 0x00000030
-#define NV20TCL_TX_ENABLE_ANISO_NONE 0x00000000
-#define NV20TCL_TX_ENABLE_ANISO_2X 0x00000010
-#define NV20TCL_TX_ENABLE_ANISO_4X 0x00000020
-#define NV20TCL_TX_ENABLE_ANISO_8X 0x00000030
-#define NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14
-#define NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000
-#define NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26
-#define NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000
-#define NV20TCL_TX_ENABLE_ENABLE (1 << 30)
-#define NV20TCL_TX_SWIZZLE(x) (0x00001b10+((x)*64))
-#define NV20TCL_TX_SWIZZLE__SIZE 0x00000004
-#define NV20TCL_TX_SWIZZLE_RECT_PITCH_SHIFT 16
-#define NV20TCL_TX_SWIZZLE_RECT_PITCH_MASK 0xffff0000
-#define NV20TCL_TX_FILTER(x) (0x00001b14+((x)*64))
-#define NV20TCL_TX_FILTER__SIZE 0x00000004
-#define NV20TCL_TX_FILTER_LOD_BIAS_SHIFT 8
-#define NV20TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00
-#define NV20TCL_TX_FILTER_MINIFY_SHIFT 16
-#define NV20TCL_TX_FILTER_MINIFY_MASK 0x000f0000
-#define NV20TCL_TX_FILTER_MINIFY_NEAREST 0x00010000
-#define NV20TCL_TX_FILTER_MINIFY_LINEAR 0x00020000
-#define NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x00030000
-#define NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x00040000
-#define NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x00050000
-#define NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x00060000
-#define NV20TCL_TX_FILTER_MAGNIFY_SHIFT 24
-#define NV20TCL_TX_FILTER_MAGNIFY_MASK 0x0f000000
-#define NV20TCL_TX_FILTER_MAGNIFY_NEAREST 0x01000000
-#define NV20TCL_TX_FILTER_MAGNIFY_LINEAR 0x02000000
-#define NV20TCL_TX_NPOT_SIZE(x) (0x00001b1c+((x)*64))
-#define NV20TCL_TX_NPOT_SIZE__SIZE 0x00000004
-#define NV20TCL_TX_NPOT_SIZE_H_SHIFT 0
-#define NV20TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff
-#define NV20TCL_TX_NPOT_SIZE_W_SHIFT 16
-#define NV20TCL_TX_NPOT_SIZE_W_MASK 0xffff0000
-#define NV20TCL_TX_PALETTE_OFFSET(x) (0x00001b20+((x)*64))
-#define NV20TCL_TX_PALETTE_OFFSET__SIZE 0x00000004
-#define NV20TCL_TX_BORDER_COLOR(x) (0x00001b24+((x)*64))
-#define NV20TCL_TX_BORDER_COLOR__SIZE 0x00000004
-#define NV20TCL_TX_BORDER_COLOR_B_SHIFT 0
-#define NV20TCL_TX_BORDER_COLOR_B_MASK 0x000000ff
-#define NV20TCL_TX_BORDER_COLOR_G_SHIFT 8
-#define NV20TCL_TX_BORDER_COLOR_G_MASK 0x0000ff00
-#define NV20TCL_TX_BORDER_COLOR_R_SHIFT 16
-#define NV20TCL_TX_BORDER_COLOR_R_MASK 0x00ff0000
-#define NV20TCL_TX_BORDER_COLOR_A_SHIFT 24
-#define NV20TCL_TX_BORDER_COLOR_A_MASK 0xff000000
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX00(x) (0x00001b28+((x)*64))
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX00__SIZE 0x00000004
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX01(x) (0x00001b2c+((x)*64))
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX01__SIZE 0x00000004
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX11(x) (0x00001b30+((x)*64))
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX11__SIZE 0x00000004
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX10(x) (0x00001b34+((x)*64))
-#define NV20TCL_TX_SHADER_OFFSET_MATRIX10__SIZE 0x00000004
-#define NV20TCL_DEPTH_UNK17D8 0x00001d78
-#define NV20TCL_DEPTH_UNK17D8_CLAMP_SHIFT 4
-#define NV20TCL_DEPTH_UNK17D8_CLAMP_MASK 0x000000f0
-#define NV20TCL_MULTISAMPLE_CONTROL 0x00001d7c
-#define NV20TCL_CLEAR_DEPTH_VALUE 0x00001d8c
-#define NV20TCL_CLEAR_VALUE 0x00001d90
-#define NV20TCL_CLEAR_BUFFERS 0x00001d94
-#define NV20TCL_CLEAR_BUFFERS_COLOR_A (1 << 7)
-#define NV20TCL_CLEAR_BUFFERS_COLOR_B (1 << 6)
-#define NV20TCL_CLEAR_BUFFERS_COLOR_G (1 << 5)
-#define NV20TCL_CLEAR_BUFFERS_COLOR_R (1 << 4)
-#define NV20TCL_CLEAR_BUFFERS_STENCIL (1 << 1)
-#define NV20TCL_CLEAR_BUFFERS_DEPTH (1 << 0)
-#define NV20TCL_RC_COLOR0 0x00001e20
-#define NV20TCL_RC_COLOR0_B_SHIFT 0
-#define NV20TCL_RC_COLOR0_B_MASK 0x000000ff
-#define NV20TCL_RC_COLOR0_G_SHIFT 8
-#define NV20TCL_RC_COLOR0_G_MASK 0x0000ff00
-#define NV20TCL_RC_COLOR0_R_SHIFT 16
-#define NV20TCL_RC_COLOR0_R_MASK 0x00ff0000
-#define NV20TCL_RC_COLOR0_A_SHIFT 24
-#define NV20TCL_RC_COLOR0_A_MASK 0xff000000
-#define NV20TCL_RC_COLOR1 0x00001e24
-#define NV20TCL_RC_COLOR1_B_SHIFT 0
-#define NV20TCL_RC_COLOR1_B_MASK 0x000000ff
-#define NV20TCL_RC_COLOR1_G_SHIFT 8
-#define NV20TCL_RC_COLOR1_G_MASK 0x0000ff00
-#define NV20TCL_RC_COLOR1_R_SHIFT 16
-#define NV20TCL_RC_COLOR1_R_MASK 0x00ff0000
-#define NV20TCL_RC_COLOR1_A_SHIFT 24
-#define NV20TCL_RC_COLOR1_A_MASK 0xff000000
-#define NV20TCL_BACK_MATERIAL_SHININESS(x) (0x00001e28+((x)*4))
-#define NV20TCL_BACK_MATERIAL_SHININESS__SIZE 0x00000006
-#define NV20TCL_RC_OUT_RGB(x) (0x00001e40+((x)*4))
-#define NV20TCL_RC_OUT_RGB__SIZE 0x00000008
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB 0x00000008
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB 0x00000009
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV 0x0000000c
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV 0x0000000d
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x00000080
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x00000090
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000000c0
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000000d0
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x00000c00
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x00000d00
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
-#define NV20TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
-#define NV20TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
-#define NV20TCL_RC_OUT_RGB_MUX_SUM (1 << 14)
-#define NV20TCL_RC_OUT_RGB_BIAS (1 << 15)
-#define NV20TCL_RC_OUT_RGB_BIAS_NONE 0x00000000
-#define NV20TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
-#define NV20TCL_RC_OUT_RGB_SCALE_SHIFT 17
-#define NV20TCL_RC_OUT_RGB_SCALE_MASK 0x00000000
-#define NV20TCL_RC_OUT_RGB_SCALE_NONE 0x00000000
-#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x00020000
-#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x00040000
-#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
-#define NV20TCL_RC_ENABLE 0x00001e60
-#define NV20TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0
-#define NV20TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f
-#define NV20TCL_TX_RCOMP 0x00001e6c
-#define NV20TCL_TX_RCOMP_NEVER 0x00000000
-#define NV20TCL_TX_RCOMP_GREATER 0x00000001
-#define NV20TCL_TX_RCOMP_EQUAL 0x00000002
-#define NV20TCL_TX_RCOMP_GEQUAL 0x00000003
-#define NV20TCL_TX_RCOMP_LESS 0x00000004
-#define NV20TCL_TX_RCOMP_NOTEQUAL 0x00000005
-#define NV20TCL_TX_RCOMP_LEQUAL 0x00000006
-#define NV20TCL_TX_RCOMP_ALWAYS 0x00000007
-#define NV20TCL_TX_SHADER_OP 0x00001e70
-#define NV20TCL_TX_SHADER_OP_TX0_SHIFT 0
-#define NV20TCL_TX_SHADER_OP_TX0_MASK 0x0000001f
-#define NV20TCL_TX_SHADER_OP_TX0_NONE 0x00000000
-#define NV20TCL_TX_SHADER_OP_TX0_TEXTURE_2D 0x00000001
-#define NV20TCL_TX_SHADER_OP_TX0_PASS_THROUGH 0x00000004
-#define NV20TCL_TX_SHADER_OP_TX0_CULL_FRAGMENT 0x00000005
-#define NV20TCL_TX_SHADER_OP_TX0_OFFSET_TEXTURE_2D 0x00000006
-#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_TEXTURE_2D 0x00000009
-#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_DEPTH_REPLACE 0x0000000a
-#define NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_AR_TEXTURE_2D 0x0000000f
-#define NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_GB_TEXTURE_2D 0x00000010
-#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT 0x00000011
-#define NV20TCL_TX_SHADER_OP_TX1_SHIFT 5
-#define NV20TCL_TX_SHADER_OP_TX1_MASK 0x000003e0
-#define NV20TCL_TX_SHADER_OP_TX1_NONE 0x00000000
-#define NV20TCL_TX_SHADER_OP_TX1_TEXTURE_2D 0x00000020
-#define NV20TCL_TX_SHADER_OP_TX1_PASS_THROUGH 0x00000080
-#define NV20TCL_TX_SHADER_OP_TX1_CULL_FRAGMENT 0x000000a0
-#define NV20TCL_TX_SHADER_OP_TX1_OFFSET_TEXTURE_2D 0x000000c0
-#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_TEXTURE_2D 0x00000120
-#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_DEPTH_REPLACE 0x00000140
-#define NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_AR_TEXTURE_2D 0x000001e0
-#define NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_GB_TEXTURE_2D 0x00000200
-#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT 0x00000220
-#define NV20TCL_TX_SHADER_OP_TX2_SHIFT 10
-#define NV20TCL_TX_SHADER_OP_TX2_MASK 0x00007c00
-#define NV20TCL_TX_SHADER_OP_TX2_NONE 0x00000000
-#define NV20TCL_TX_SHADER_OP_TX2_TEXTURE_2D 0x00000400
-#define NV20TCL_TX_SHADER_OP_TX2_PASS_THROUGH 0x00001000
-#define NV20TCL_TX_SHADER_OP_TX2_CULL_FRAGMENT 0x00001400
-#define NV20TCL_TX_SHADER_OP_TX2_OFFSET_TEXTURE_2D 0x00001800
-#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_TEXTURE_2D 0x00002400
-#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_DEPTH_REPLACE 0x00002800
-#define NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_AR_TEXTURE_2D 0x00003c00
-#define NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_GB_TEXTURE_2D 0x00004000
-#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT 0x00004400
-#define NV20TCL_TX_SHADER_OP_TX3_SHIFT 15
-#define NV20TCL_TX_SHADER_OP_TX3_MASK 0x000f8000
-#define NV20TCL_TX_SHADER_OP_TX3_NONE 0x00000000
-#define NV20TCL_TX_SHADER_OP_TX3_TEXTURE_2D 0x00008000
-#define NV20TCL_TX_SHADER_OP_TX3_PASS_THROUGH 0x00020000
-#define NV20TCL_TX_SHADER_OP_TX3_CULL_FRAGMENT 0x00028000
-#define NV20TCL_TX_SHADER_OP_TX3_OFFSET_TEXTURE_2D 0x00030000
-#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_TEXTURE_2D 0x00048000
-#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_DEPTH_REPLACE 0x00050000
-#define NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_AR_TEXTURE_2D 0x00078000
-#define NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_GB_TEXTURE_2D 0x00080000
-#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT 0x00088000
-#define NV20TCL_TX_SHADER_DOTMAPPING 0x00001e74
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX0_SHIFT 0
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX0_MASK 0x0000000f
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX1_SHIFT 4
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX1_MASK 0x000000f0
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX2_SHIFT 8
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX2_MASK 0x00000f00
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX3_SHIFT 12
-#define NV20TCL_TX_SHADER_DOTMAPPING_TX3_MASK 0x0000f000
-#define NV20TCL_TX_SHADER_PREVIOUS 0x00001e78
-#define NV20TCL_TX_SHADER_PREVIOUS_TX0_SHIFT 8
-#define NV20TCL_TX_SHADER_PREVIOUS_TX0_MASK 0x00000f00
-#define NV20TCL_TX_SHADER_PREVIOUS_TX1_SHIFT 12
-#define NV20TCL_TX_SHADER_PREVIOUS_TX1_MASK 0x0000f000
-#define NV20TCL_TX_SHADER_PREVIOUS_TX2_SHIFT 16
-#define NV20TCL_TX_SHADER_PREVIOUS_TX2_MASK 0x00030000
-#define NV20TCL_TX_SHADER_PREVIOUS_TX3_SHIFT 20
-#define NV20TCL_TX_SHADER_PREVIOUS_TX3_MASK 0x00300000
-#define NV20TCL_ENGINE 0x00001e94
-#define NV20TCL_ENGINE_VP (1 << 1)
-#define NV20TCL_ENGINE_FIXED (1 << 2)
-#define NV20TCL_VP_UPLOAD_FROM_ID 0x00001e9c
-#define NV20TCL_VP_START_FROM_ID 0x00001ea0
-#define NV20TCL_VP_UPLOAD_CONST_ID 0x00001ea4
-#define NV20TCL_VIEWPORT_TRANSLATE_X 0x00001f00
-#define NV20TCL_VIEWPORT_TRANSLATE_Y 0x00001f04
-#define NV20TCL_VIEWPORT_TRANSLATE_Z 0x00001f08
-#define NV20TCL_VIEWPORT_TRANSLATE_W 0x00001f0c
-
-
-#define NV17TCL 0x00000099
-
-#define NV17TCL_DMA_IN_MEMORY4 0x000001ac
-#define NV17TCL_DMA_IN_MEMORY5 0x000001b0
-#define NV17TCL_COLOR_MASK_ENABLE 0x000002bc
-#define NV17TCL_LMA_DEPTH_BUFFER_PITCH 0x00000d5c
-#define NV17TCL_LMA_DEPTH_BUFFER_OFFSET 0x00000d60
-#define NV17TCL_LMA_DEPTH_FILL_VALUE 0x00000d68
-#define NV17TCL_LMA_DEPTH_BUFFER_CLEAR 0x00000d6c
-#define NV17TCL_LMA_DEPTH_ENABLE 0x00001658
-
-
-#define NV20_SWIZZLED_SURFACE 0x0000009e
-
-
-
-#define NV12_IMAGE_BLIT 0x0000009f
-
-
-
-#define NV30_CONTEXT_SURFACES_2D 0x00000362
-
-
-
-#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366
-
-
-
-#define NV30_TEXTURE_FROM_CPU 0x0000037b
-
-
-
-#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389
-
-
-
-#define NV30_IMAGE_FROM_CPU 0x0000038a
-
-
-
-#define NV30TCL 0x00000397
-
-
-
-#define NV30_SWIZZLED_SURFACE 0x0000039e
-
-
-
-#define NV35TCL 0x00000497
-
-
-
-#define NV25TCL 0x00000597
-
-#define NV25TCL_DMA_IN_MEMORY4 0x0000019c
-#define NV25TCL_DMA_IN_MEMORY5 0x000001a0
-#define NV25TCL_DMA_IN_MEMORY8 0x000001ac
-#define NV25TCL_DMA_IN_MEMORY9 0x000001b0
-
-
-#define NV34TCL 0x00000697
-
-#define NV34TCL_NOP 0x00000100
-#define NV34TCL_NOTIFY 0x00000104
-#define NV34TCL_DMA_NOTIFY 0x00000180
-#define NV34TCL_DMA_TEXTURE0 0x00000184
-#define NV34TCL_DMA_TEXTURE1 0x00000188
-#define NV34TCL_DMA_COLOR1 0x0000018c
-#define NV34TCL_DMA_COLOR0 0x00000194
-#define NV34TCL_DMA_ZETA 0x00000198
-#define NV34TCL_DMA_VTXBUF0 0x0000019c
-#define NV34TCL_DMA_VTXBUF1 0x000001a0
-#define NV34TCL_DMA_FENCE 0x000001a4
-#define NV34TCL_DMA_QUERY 0x000001a8
-#define NV34TCL_DMA_IN_MEMORY7 0x000001ac
-#define NV34TCL_DMA_IN_MEMORY8 0x000001b0
-#define NV34TCL_RT_HORIZ 0x00000200
-#define NV34TCL_RT_HORIZ_X_SHIFT 0
-#define NV34TCL_RT_HORIZ_X_MASK 0x0000ffff
-#define NV34TCL_RT_HORIZ_W_SHIFT 16
-#define NV34TCL_RT_HORIZ_W_MASK 0xffff0000
-#define NV34TCL_RT_VERT 0x00000204
-#define NV34TCL_RT_VERT_Y_SHIFT 0
-#define NV34TCL_RT_VERT_Y_MASK 0x0000ffff
-#define NV34TCL_RT_VERT_H_SHIFT 16
-#define NV34TCL_RT_VERT_H_MASK 0xffff0000
-#define NV34TCL_RT_FORMAT 0x00000208
-#define NV34TCL_RT_FORMAT_TYPE_SHIFT 8
-#define NV34TCL_RT_FORMAT_TYPE_MASK 0x00000f00
-#define NV34TCL_RT_FORMAT_TYPE_LINEAR 0x00000100
-#define NV34TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200
-#define NV34TCL_RT_FORMAT_ZETA_SHIFT 5
-#define NV34TCL_RT_FORMAT_ZETA_MASK 0x000000e0
-#define NV34TCL_RT_FORMAT_ZETA_Z16 0x00000020
-#define NV34TCL_RT_FORMAT_ZETA_Z24S8 0x00000040
-#define NV34TCL_RT_FORMAT_COLOR_SHIFT 0
-#define NV34TCL_RT_FORMAT_COLOR_MASK 0x0000001f
-#define NV34TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003
-#define NV34TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005
-#define NV34TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008
-#define NV34TCL_RT_FORMAT_COLOR_B8 0x00000009
-#define NV34TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d
-#define NV34TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f
-#define NV34TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010
-#define NV34TCL_COLOR0_PITCH 0x0000020c
-#define NV34TCL_COLOR0_PITCH_COLOR0_SHIFT 0
-#define NV34TCL_COLOR0_PITCH_COLOR0_MASK 0x0000ffff
-#define NV34TCL_COLOR0_PITCH_ZETA_SHIFT 16
-#define NV34TCL_COLOR0_PITCH_ZETA_MASK 0xffff0000
-#define NV34TCL_COLOR0_OFFSET 0x00000210
-#define NV34TCL_ZETA_OFFSET 0x00000214
-#define NV34TCL_COLOR1_OFFSET 0x00000218
-#define NV34TCL_COLOR1_PITCH 0x0000021c
-#define NV34TCL_RT_ENABLE 0x00000220
-#define NV34TCL_RT_ENABLE_MRT (1 << 4)
-#define NV34TCL_RT_ENABLE_COLOR1 (1 << 1)
-#define NV34TCL_RT_ENABLE_COLOR0 (1 << 0)
-#define NV34TCL_LMA_DEPTH_PITCH 0x0000022c
-#define NV34TCL_LMA_DEPTH_OFFSET 0x00000230
-#define NV34TCL_TX_UNITS_ENABLE 0x0000023c
-#define NV34TCL_TX_UNITS_ENABLE_TX0 (1 << 0)
-#define NV34TCL_TX_UNITS_ENABLE_TX1 (1 << 1)
-#define NV34TCL_TX_UNITS_ENABLE_TX2 (1 << 2)
-#define NV34TCL_TX_UNITS_ENABLE_TX3 (1 << 3)
-#define NV34TCL_TX_UNITS_ENABLE_TX4 (1 << 4)
-#define NV34TCL_TX_UNITS_ENABLE_TX5 (1 << 5)
-#define NV34TCL_TX_UNITS_ENABLE_TX6 (1 << 6)
-#define NV34TCL_TX_UNITS_ENABLE_TX7 (1 << 7)
-#define NV34TCL_TX_MATRIX_ENABLE(x) (0x00000240+((x)*4))
-#define NV34TCL_TX_MATRIX_ENABLE__SIZE 0x00000008
-#define NV34TCL_VIEWPORT_TX_ORIGIN 0x000002b8
-#define NV34TCL_VIEWPORT_TX_ORIGIN_X_SHIFT 0
-#define NV34TCL_VIEWPORT_TX_ORIGIN_X_MASK 0x0000ffff
-#define NV34TCL_VIEWPORT_TX_ORIGIN_Y_SHIFT 16
-#define NV34TCL_VIEWPORT_TX_ORIGIN_Y_MASK 0xffff0000
-#define NV34TCL_VIEWPORT_CLIP_MODE 0x000002bc
-#define NV34TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*8))
-#define NV34TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008
-#define NV34TCL_VIEWPORT_CLIP_HORIZ_L_SHIFT 0
-#define NV34TCL_VIEWPORT_CLIP_HORIZ_L_MASK 0x0000ffff
-#define NV34TCL_VIEWPORT_CLIP_HORIZ_R_SHIFT 16
-#define NV34TCL_VIEWPORT_CLIP_HORIZ_R_MASK 0xffff0000
-#define NV34TCL_VIEWPORT_CLIP_VERT(x) (0x000002c4+((x)*8))
-#define NV34TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008
-#define NV34TCL_VIEWPORT_CLIP_VERT_T_SHIFT 0
-#define NV34TCL_VIEWPORT_CLIP_VERT_T_MASK 0x0000ffff
-#define NV34TCL_VIEWPORT_CLIP_VERT_D_SHIFT 16
-#define NV34TCL_VIEWPORT_CLIP_VERT_D_MASK 0xffff0000
-#define NV34TCL_DITHER_ENABLE 0x00000300
-#define NV34TCL_ALPHA_FUNC_ENABLE 0x00000304
-#define NV34TCL_ALPHA_FUNC_FUNC 0x00000308
-#define NV34TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200
-#define NV34TCL_ALPHA_FUNC_FUNC_LESS 0x00000201
-#define NV34TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202
-#define NV34TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
-#define NV34TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
-#define NV34TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
-#define NV34TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV34TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
-#define NV34TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
-#define NV34TCL_ALPHA_FUNC_REF 0x0000030c
-#define NV34TCL_BLEND_FUNC_ENABLE 0x00000310
-#define NV34TCL_BLEND_FUNC_SRC 0x00000314
-#define NV34TCL_BLEND_FUNC_SRC_RGB_SHIFT 0
-#define NV34TCL_BLEND_FUNC_SRC_RGB_MASK 0x0000ffff
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00000000
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE 0x00000001
-#define NV34TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV34TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV34TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV34TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307
-#define NV34TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308
-#define NV34TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV34TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003
-#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SHIFT 16
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_MASK 0xffff0000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000
-#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
-#define NV34TCL_BLEND_FUNC_DST 0x00000318
-#define NV34TCL_BLEND_FUNC_DST_RGB_SHIFT 0
-#define NV34TCL_BLEND_FUNC_DST_RGB_MASK 0x0000ffff
-#define NV34TCL_BLEND_FUNC_DST_RGB_ZERO 0x00000000
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE 0x00000001
-#define NV34TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV34TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV34TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV34TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307
-#define NV34TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308
-#define NV34TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV34TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003
-#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_SHIFT 16
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_MASK 0xffff0000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00010000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000
-#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
-#define NV34TCL_BLEND_COLOR 0x0000031c
-#define NV34TCL_BLEND_COLOR_B_SHIFT 0
-#define NV34TCL_BLEND_COLOR_B_MASK 0x000000ff
-#define NV34TCL_BLEND_COLOR_G_SHIFT 8
-#define NV34TCL_BLEND_COLOR_G_MASK 0x0000ff00
-#define NV34TCL_BLEND_COLOR_R_SHIFT 16
-#define NV34TCL_BLEND_COLOR_R_MASK 0x00ff0000
-#define NV34TCL_BLEND_COLOR_A_SHIFT 24
-#define NV34TCL_BLEND_COLOR_A_MASK 0xff000000
-#define NV34TCL_BLEND_EQUATION 0x00000320
-#define NV34TCL_BLEND_EQUATION_FUNC_ADD 0x00008006
-#define NV34TCL_BLEND_EQUATION_MIN 0x00008007
-#define NV34TCL_BLEND_EQUATION_MAX 0x00008008
-#define NV34TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a
-#define NV34TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b
-#define NV34TCL_COLOR_MASK 0x00000324
-#define NV34TCL_COLOR_MASK_B_SHIFT 0
-#define NV34TCL_COLOR_MASK_B_MASK 0x000000ff
-#define NV34TCL_COLOR_MASK_G_SHIFT 8
-#define NV34TCL_COLOR_MASK_G_MASK 0x0000ff00
-#define NV34TCL_COLOR_MASK_R_SHIFT 16
-#define NV34TCL_COLOR_MASK_R_MASK 0x00ff0000
-#define NV34TCL_COLOR_MASK_A_SHIFT 24
-#define NV34TCL_COLOR_MASK_A_MASK 0xff000000
-#define NV34TCL_STENCIL_BACK_ENABLE 0x00000328
-#define NV34TCL_STENCIL_BACK_MASK 0x0000032c
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC 0x00000330
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
-#define NV34TCL_STENCIL_BACK_FUNC_REF 0x00000334
-#define NV34TCL_STENCIL_BACK_FUNC_MASK 0x00000338
-#define NV34TCL_STENCIL_BACK_OP_FAIL 0x0000033c
-#define NV34TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000
-#define NV34TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a
-#define NV34TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00
-#define NV34TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01
-#define NV34TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02
-#define NV34TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03
-#define NV34TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507
-#define NV34TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL 0x00000340
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV34TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV34TCL_STENCIL_BACK_OP_ZPASS 0x00000344
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV34TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV34TCL_STENCIL_FRONT_ENABLE 0x00000348
-#define NV34TCL_STENCIL_FRONT_MASK 0x0000034c
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC 0x00000350
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
-#define NV34TCL_STENCIL_FRONT_FUNC_REF 0x00000354
-#define NV34TCL_STENCIL_FRONT_FUNC_MASK 0x00000358
-#define NV34TCL_STENCIL_FRONT_OP_FAIL 0x0000035c
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507
-#define NV34TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL 0x00000360
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS 0x00000364
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV34TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV34TCL_SHADE_MODEL 0x00000368
-#define NV34TCL_SHADE_MODEL_FLAT 0x00001d00
-#define NV34TCL_SHADE_MODEL_SMOOTH 0x00001d01
-#define NV34TCL_FOG_ENABLE 0x0000036c
-#define NV34TCL_FOG_COLOR 0x00000370
-#define NV34TCL_FOG_COLOR_R_SHIFT 0
-#define NV34TCL_FOG_COLOR_R_MASK 0x000000ff
-#define NV34TCL_FOG_COLOR_G_SHIFT 8
-#define NV34TCL_FOG_COLOR_G_MASK 0x0000ff00
-#define NV34TCL_FOG_COLOR_B_SHIFT 16
-#define NV34TCL_FOG_COLOR_B_MASK 0x00ff0000
-#define NV34TCL_FOG_COLOR_A_SHIFT 24
-#define NV34TCL_FOG_COLOR_A_MASK 0xff000000
-#define NV34TCL_COLOR_LOGIC_OP_ENABLE 0x00000374
-#define NV34TCL_COLOR_LOGIC_OP_OP 0x00000378
-#define NV34TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
-#define NV34TCL_COLOR_LOGIC_OP_OP_AND 0x00001501
-#define NV34TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502
-#define NV34TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503
-#define NV34TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504
-#define NV34TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505
-#define NV34TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506
-#define NV34TCL_COLOR_LOGIC_OP_OP_OR 0x00001507
-#define NV34TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508
-#define NV34TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509
-#define NV34TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a
-#define NV34TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b
-#define NV34TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c
-#define NV34TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d
-#define NV34TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e
-#define NV34TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f
-#define NV34TCL_NORMALIZE_ENABLE 0x0000037c
-#define NV34TCL_COLOR_MATERIAL 0x00000390
-#define NV34TCL_COLOR_MATERIAL_FRONT_EMISSION_ENABLE (1 << 0)
-#define NV34TCL_COLOR_MATERIAL_FRONT_AMBIENT_ENABLE (1 << 2)
-#define NV34TCL_COLOR_MATERIAL_FRONT_DIFFUSE_ENABLE (1 << 4)
-#define NV34TCL_COLOR_MATERIAL_FRONT_SPECULAR_ENABLE (1 << 6)
-#define NV34TCL_COLOR_MATERIAL_BACK_EMISSION_ENABLE (1 << 8)
-#define NV34TCL_COLOR_MATERIAL_BACK_AMBIENT_ENABLE (1 << 10)
-#define NV34TCL_COLOR_MATERIAL_BACK_DIFFUSE_ENABLE (1 << 12)
-#define NV34TCL_COLOR_MATERIAL_BACK_SPECULAR_ENABLE (1 << 14)
-#define NV34TCL_DEPTH_RANGE_NEAR 0x00000394
-#define NV34TCL_DEPTH_RANGE_FAR 0x00000398
-#define NV34TCL_COLOR_MATERIAL_FRONT_R 0x000003a0
-#define NV34TCL_COLOR_MATERIAL_FRONT_G 0x000003a4
-#define NV34TCL_COLOR_MATERIAL_FRONT_B 0x000003a8
-#define NV34TCL_COLOR_MATERIAL_FRONT_A 0x000003b4
-#define NV34TCL_LINE_WIDTH 0x000003b8
-#define NV34TCL_LINE_SMOOTH_ENABLE 0x000003bc
-#define NV34TCL_TX_GEN_S(x) (0x00000400+((x)*16))
-#define NV34TCL_TX_GEN_S__SIZE 0x00000008
-#define NV34TCL_TX_GEN_S_FALSE 0x00000000
-#define NV34TCL_TX_GEN_S_EYE_LINEAR 0x00002400
-#define NV34TCL_TX_GEN_S_OBJECT_LINEAR 0x00002401
-#define NV34TCL_TX_GEN_S_SPHERE_MAP 0x00002402
-#define NV34TCL_TX_GEN_S_NORMAL_MAP 0x00008511
-#define NV34TCL_TX_GEN_S_REFLECTION_MAP 0x00008512
-#define NV34TCL_TX_GEN_T(x) (0x00000404+((x)*16))
-#define NV34TCL_TX_GEN_T__SIZE 0x00000008
-#define NV34TCL_TX_GEN_T_FALSE 0x00000000
-#define NV34TCL_TX_GEN_T_EYE_LINEAR 0x00002400
-#define NV34TCL_TX_GEN_T_OBJECT_LINEAR 0x00002401
-#define NV34TCL_TX_GEN_T_SPHERE_MAP 0x00002402
-#define NV34TCL_TX_GEN_T_NORMAL_MAP 0x00008511
-#define NV34TCL_TX_GEN_T_REFLECTION_MAP 0x00008512
-#define NV34TCL_TX_GEN_R(x) (0x00000408+((x)*16))
-#define NV34TCL_TX_GEN_R__SIZE 0x00000008
-#define NV34TCL_TX_GEN_R_FALSE 0x00000000
-#define NV34TCL_TX_GEN_R_EYE_LINEAR 0x00002400
-#define NV34TCL_TX_GEN_R_OBJECT_LINEAR 0x00002401
-#define NV34TCL_TX_GEN_R_SPHERE_MAP 0x00002402
-#define NV34TCL_TX_GEN_R_NORMAL_MAP 0x00008511
-#define NV34TCL_TX_GEN_R_REFLECTION_MAP 0x00008512
-#define NV34TCL_TX_GEN_Q(x) (0x0000040c+((x)*16))
-#define NV34TCL_TX_GEN_Q__SIZE 0x00000008
-#define NV34TCL_TX_GEN_Q_FALSE 0x00000000
-#define NV34TCL_TX_GEN_Q_EYE_LINEAR 0x00002400
-#define NV34TCL_TX_GEN_Q_OBJECT_LINEAR 0x00002401
-#define NV34TCL_TX_GEN_Q_SPHERE_MAP 0x00002402
-#define NV34TCL_TX_GEN_Q_NORMAL_MAP 0x00008511
-#define NV34TCL_TX_GEN_Q_REFLECTION_MAP 0x00008512
-#define NV34TCL_MODELVIEW_MATRIX(x) (0x00000480+((x)*4))
-#define NV34TCL_MODELVIEW_MATRIX__SIZE 0x00000010
-#define NV34TCL_INVERSE_MODELVIEW_MATRIX(x) (0x00000580+((x)*4))
-#define NV34TCL_INVERSE_MODELVIEW_MATRIX__SIZE 0x0000000c
-#define NV34TCL_PROJECTION_MATRIX(x) (0x00000680+((x)*4))
-#define NV34TCL_PROJECTION_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX0_MATRIX(x) (0x000006c0+((x)*4))
-#define NV34TCL_TX0_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX1_MATRIX(x) (0x00000700+((x)*4))
-#define NV34TCL_TX1_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX2_MATRIX(x) (0x00000740+((x)*4))
-#define NV34TCL_TX2_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX3_MATRIX(x) (0x00000780+((x)*4))
-#define NV34TCL_TX3_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX4_MATRIX(x) (0x000007c0+((x)*4))
-#define NV34TCL_TX4_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX5_MATRIX(x) (0x00000800+((x)*4))
-#define NV34TCL_TX5_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX6_MATRIX(x) (0x00000840+((x)*4))
-#define NV34TCL_TX6_MATRIX__SIZE 0x00000010
-#define NV34TCL_TX7_MATRIX(x) (0x00000880+((x)*4))
-#define NV34TCL_TX7_MATRIX__SIZE 0x00000010
-#define NV34TCL_SCISSOR_HORIZ 0x000008c0
-#define NV34TCL_SCISSOR_HORIZ_X_SHIFT 0
-#define NV34TCL_SCISSOR_HORIZ_X_MASK 0x0000ffff
-#define NV34TCL_SCISSOR_HORIZ_W_SHIFT 16
-#define NV34TCL_SCISSOR_HORIZ_W_MASK 0xffff0000
-#define NV34TCL_SCISSOR_VERT 0x000008c4
-#define NV34TCL_SCISSOR_VERT_Y_SHIFT 0
-#define NV34TCL_SCISSOR_VERT_Y_MASK 0x0000ffff
-#define NV34TCL_SCISSOR_VERT_H_SHIFT 16
-#define NV34TCL_SCISSOR_VERT_H_MASK 0xffff0000
-#define NV34TCL_FOG_COORD_DIST 0x000008c8
-#define NV34TCL_FOG_COORD_DIST_COORD_FALSE 0x00000000
-#define NV34TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_RADIAL_NV 0x00000001
-#define NV34TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_PLANE_ABSOLUTE_NV 0x00000002
-#define NV34TCL_FOG_COORD_DIST_COORD_FOG 0x00000003
-#define NV34TCL_FOG_MODE 0x000008cc
-#define NV34TCL_FOG_MODE_EXP 0x00000800
-#define NV34TCL_FOG_MODE_EXP_2 0x00000802
-#define NV34TCL_FOG_MODE_EXP2 0x00000803
-#define NV34TCL_FOG_MODE_LINEAR 0x00000804
-#define NV34TCL_FOG_MODE_LINEAR_2 0x00002601
-#define NV34TCL_FOG_EQUATION_CONSTANT 0x000008d0
-#define NV34TCL_FOG_EQUATION_LINEAR 0x000008d4
-#define NV34TCL_FOG_EQUATION_QUADRATIC 0x000008d8
-#define NV34TCL_FP_ACTIVE_PROGRAM 0x000008e4
-#define NV34TCL_FP_ACTIVE_PROGRAM_DMA0 (1 << 0)
-#define NV34TCL_FP_ACTIVE_PROGRAM_DMA1 (1 << 1)
-#define NV34TCL_FP_ACTIVE_PROGRAM_OFFSET_SHIFT 2
-#define NV34TCL_FP_ACTIVE_PROGRAM_OFFSET_MASK 0xfffffffc
-#define NV34TCL_RC_COLOR0 0x000008ec
-#define NV34TCL_RC_COLOR0_B_SHIFT 0
-#define NV34TCL_RC_COLOR0_B_MASK 0x000000ff
-#define NV34TCL_RC_COLOR0_G_SHIFT 8
-#define NV34TCL_RC_COLOR0_G_MASK 0x0000ff00
-#define NV34TCL_RC_COLOR0_R_SHIFT 16
-#define NV34TCL_RC_COLOR0_R_MASK 0x00ff0000
-#define NV34TCL_RC_COLOR0_A_SHIFT 24
-#define NV34TCL_RC_COLOR0_A_MASK 0xff000000
-#define NV34TCL_RC_COLOR1 0x000008f0
-#define NV34TCL_RC_COLOR1_B_SHIFT 0
-#define NV34TCL_RC_COLOR1_B_MASK 0x000000ff
-#define NV34TCL_RC_COLOR1_G_SHIFT 8
-#define NV34TCL_RC_COLOR1_G_MASK 0x0000ff00
-#define NV34TCL_RC_COLOR1_R_SHIFT 16
-#define NV34TCL_RC_COLOR1_R_MASK 0x00ff0000
-#define NV34TCL_RC_COLOR1_A_SHIFT 24
-#define NV34TCL_RC_COLOR1_A_MASK 0xff000000
-#define NV34TCL_RC_FINAL0 0x000008f4
-#define NV34TCL_RC_FINAL0_D_INPUT_SHIFT 0
-#define NV34TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f
-#define NV34TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV34TCL_RC_FINAL0_D_INPUT_FOG 0x00000003
-#define NV34TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV34TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0_NV 0x0000000c
-#define NV34TCL_RC_FINAL0_D_INPUT_SPARE1_NV 0x0000000d
-#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV34TCL_RC_FINAL0_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4)
-#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV34TCL_RC_FINAL0_D_MAPPING_SHIFT 5
-#define NV34TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0
-#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV34TCL_RC_FINAL0_C_INPUT_SHIFT 8
-#define NV34TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00
-#define NV34TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV34TCL_RC_FINAL0_C_INPUT_FOG 0x00000300
-#define NV34TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV34TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0_NV 0x00000c00
-#define NV34TCL_RC_FINAL0_C_INPUT_SPARE1_NV 0x00000d00
-#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV34TCL_RC_FINAL0_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12)
-#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV34TCL_RC_FINAL0_C_MAPPING_SHIFT 13
-#define NV34TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000
-#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV34TCL_RC_FINAL0_B_INPUT_SHIFT 16
-#define NV34TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000
-#define NV34TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV34TCL_RC_FINAL0_B_INPUT_FOG 0x00030000
-#define NV34TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV34TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0_NV 0x000c0000
-#define NV34TCL_RC_FINAL0_B_INPUT_SPARE1_NV 0x000d0000
-#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV34TCL_RC_FINAL0_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20)
-#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV34TCL_RC_FINAL0_B_MAPPING_SHIFT 21
-#define NV34TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000
-#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV34TCL_RC_FINAL0_A_INPUT_SHIFT 24
-#define NV34TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000
-#define NV34TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV34TCL_RC_FINAL0_A_INPUT_FOG 0x03000000
-#define NV34TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV34TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0_NV 0x0c000000
-#define NV34TCL_RC_FINAL0_A_INPUT_SPARE1_NV 0x0d000000
-#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV34TCL_RC_FINAL0_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28)
-#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_SHIFT 29
-#define NV34TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV34TCL_RC_FINAL1 0x000008f8
-#define NV34TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
-#define NV34TCL_RC_FINAL1_G_INPUT_SHIFT 8
-#define NV34TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00
-#define NV34TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV34TCL_RC_FINAL1_G_INPUT_FOG 0x00000300
-#define NV34TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV34TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE0_ARB 0x00000800
-#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE1_ARB 0x00000900
-#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0_NV 0x00000c00
-#define NV34TCL_RC_FINAL1_G_INPUT_SPARE1_NV 0x00000d00
-#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV34TCL_RC_FINAL1_G_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12)
-#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV34TCL_RC_FINAL1_G_MAPPING_SHIFT 13
-#define NV34TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000
-#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV34TCL_RC_FINAL1_F_INPUT_SHIFT 16
-#define NV34TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000
-#define NV34TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV34TCL_RC_FINAL1_F_INPUT_FOG 0x00030000
-#define NV34TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV34TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE0_ARB 0x00080000
-#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE1_ARB 0x00090000
-#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0_NV 0x000c0000
-#define NV34TCL_RC_FINAL1_F_INPUT_SPARE1_NV 0x000d0000
-#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV34TCL_RC_FINAL1_F_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20)
-#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV34TCL_RC_FINAL1_F_MAPPING_SHIFT 21
-#define NV34TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000
-#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV34TCL_RC_FINAL1_E_INPUT_SHIFT 24
-#define NV34TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000
-#define NV34TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV34TCL_RC_FINAL1_E_INPUT_FOG 0x03000000
-#define NV34TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV34TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE0_ARB 0x08000000
-#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE1_ARB 0x09000000
-#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0_NV 0x0c000000
-#define NV34TCL_RC_FINAL1_E_INPUT_SPARE1_NV 0x0d000000
-#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV34TCL_RC_FINAL1_E_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28)
-#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_SHIFT 29
-#define NV34TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV34TCL_RC_ENABLE 0x000008fc
-#define NV34TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0
-#define NV34TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f
-#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR0_SHIFT 12
-#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR0_MASK 0x0000f000
-#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR1_SHIFT 16
-#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR1_MASK 0x000f0000
-#define NV34TCL_RC_IN_ALPHA(x) (0x00000900+((x)*32))
-#define NV34TCL_RC_IN_ALPHA__SIZE 0x00000008
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0_NV 0x0000000c
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE1_NV 0x0000000d
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4)
-#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
-#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0_NV 0x00000c00
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE1_NV 0x00000d00
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12)
-#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
-#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0_NV 0x000c0000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE1_NV 0x000d0000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20)
-#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
-#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0_NV 0x0c000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE1_NV 0x0d000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28)
-#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
-#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV34TCL_RC_IN_RGB(x) (0x00000904+((x)*32))
-#define NV34TCL_RC_IN_RGB__SIZE 0x00000008
-#define NV34TCL_RC_IN_RGB_D_INPUT_SHIFT 0
-#define NV34TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f
-#define NV34TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV34TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003
-#define NV34TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV34TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE0_ARB 0x00000008
-#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE1_ARB 0x00000009
-#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0_NV 0x0000000c
-#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE1_NV 0x0000000d
-#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV34TCL_RC_IN_RGB_D_INPUT_E_TIMES_F_NV 0x0000000f
-#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4)
-#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
-#define NV34TCL_RC_IN_RGB_D_MAPPING_SHIFT 5
-#define NV34TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0
-#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
-#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
-#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
-#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
-#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
-#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
-#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
-#define NV34TCL_RC_IN_RGB_C_INPUT_SHIFT 8
-#define NV34TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00
-#define NV34TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV34TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300
-#define NV34TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV34TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE0_ARB 0x00000800
-#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE1_ARB 0x00000900
-#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0_NV 0x00000c00
-#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE1_NV 0x00000d00
-#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV34TCL_RC_IN_RGB_C_INPUT_E_TIMES_F_NV 0x00000f00
-#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12)
-#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_SHIFT 13
-#define NV34TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
-#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
-#define NV34TCL_RC_IN_RGB_B_INPUT_SHIFT 16
-#define NV34TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000
-#define NV34TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
-#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
-#define NV34TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000
-#define NV34TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV 0x00040000
-#define NV34TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV 0x00050000
-#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE0_ARB 0x00080000
-#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE1_ARB 0x00090000
-#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0_NV 0x000c0000
-#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE1_NV 0x000d0000
-#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
-#define NV34TCL_RC_IN_RGB_B_INPUT_E_TIMES_F_NV 0x000f0000
-#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20)
-#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_SHIFT 21
-#define NV34TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
-#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
-#define NV34TCL_RC_IN_RGB_A_INPUT_SHIFT 24
-#define NV34TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV 0x04000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV 0x05000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE0_ARB 0x08000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE1_ARB 0x09000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0_NV 0x0c000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE1_NV 0x0d000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
-#define NV34TCL_RC_IN_RGB_A_INPUT_E_TIMES_F_NV 0x0f000000
-#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28)
-#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
-#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_SHIFT 29
-#define NV34TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
-#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
-#define NV34TCL_RC_CONSTANT_COLOR0(x) (0x00000908+((x)*32))
-#define NV34TCL_RC_CONSTANT_COLOR0__SIZE 0x00000008
-#define NV34TCL_RC_CONSTANT_COLOR0_B_SHIFT 0
-#define NV34TCL_RC_CONSTANT_COLOR0_B_MASK 0x000000ff
-#define NV34TCL_RC_CONSTANT_COLOR0_G_SHIFT 8
-#define NV34TCL_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00
-#define NV34TCL_RC_CONSTANT_COLOR0_R_SHIFT 16
-#define NV34TCL_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000
-#define NV34TCL_RC_CONSTANT_COLOR0_A_SHIFT 24
-#define NV34TCL_RC_CONSTANT_COLOR0_A_MASK 0xff000000
-#define NV34TCL_RC_CONSTANT_COLOR1(x) (0x0000090c+((x)*32))
-#define NV34TCL_RC_CONSTANT_COLOR1__SIZE 0x00000008
-#define NV34TCL_RC_CONSTANT_COLOR1_B_SHIFT 0
-#define NV34TCL_RC_CONSTANT_COLOR1_B_MASK 0x000000ff
-#define NV34TCL_RC_CONSTANT_COLOR1_G_SHIFT 8
-#define NV34TCL_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00
-#define NV34TCL_RC_CONSTANT_COLOR1_R_SHIFT 16
-#define NV34TCL_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000
-#define NV34TCL_RC_CONSTANT_COLOR1_A_SHIFT 24
-#define NV34TCL_RC_CONSTANT_COLOR1_A_MASK 0xff000000
-#define NV34TCL_RC_OUT_ALPHA(x) (0x00000910+((x)*32))
-#define NV34TCL_RC_OUT_ALPHA__SIZE 0x00000008
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB 0x00000008
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB 0x00000009
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV 0x0000000c
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV 0x0000000d
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x00000080
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x00000090
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000000c0
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000000d0
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x00000c00
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x00000d00
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
-#define NV34TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
-#define NV34TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
-#define NV34TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14)
-#define NV34TCL_RC_OUT_ALPHA_BIAS (1 << 15)
-#define NV34TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000
-#define NV34TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SHIFT 17
-#define NV34TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000
-#define NV34TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x00020000
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x00040000
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
-#define NV34TCL_RC_OUT_RGB(x) (0x00000914+((x)*32))
-#define NV34TCL_RC_OUT_RGB__SIZE 0x00000008
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB 0x00000008
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB 0x00000009
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV 0x0000000c
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV 0x0000000d
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x00000080
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x00000090
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000000c0
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000000d0
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x00000c00
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x00000d00
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
-#define NV34TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
-#define NV34TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
-#define NV34TCL_RC_OUT_RGB_MUX_SUM (1 << 14)
-#define NV34TCL_RC_OUT_RGB_BIAS (1 << 15)
-#define NV34TCL_RC_OUT_RGB_BIAS_NONE 0x00000000
-#define NV34TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
-#define NV34TCL_RC_OUT_RGB_SCALE_SHIFT 17
-#define NV34TCL_RC_OUT_RGB_SCALE_MASK 0x00000000
-#define NV34TCL_RC_OUT_RGB_SCALE_NONE 0x00000000
-#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x00020000
-#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x00040000
-#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
-#define NV34TCL_VIEWPORT_HORIZ 0x00000a00
-#define NV34TCL_VIEWPORT_HORIZ_X_SHIFT 0
-#define NV34TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff
-#define NV34TCL_VIEWPORT_HORIZ_W_SHIFT 16
-#define NV34TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000
-#define NV34TCL_VIEWPORT_VERT 0x00000a04
-#define NV34TCL_VIEWPORT_VERT_Y_SHIFT 0
-#define NV34TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff
-#define NV34TCL_VIEWPORT_VERT_H_SHIFT 16
-#define NV34TCL_VIEWPORT_VERT_H_MASK 0xffff0000
-#define NV34TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10
-#define NV34TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14
-#define NV34TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18
-#define NV34TCL_VIEWPORT_TRANSLATE_X 0x00000a20
-#define NV34TCL_VIEWPORT_TRANSLATE_Y 0x00000a24
-#define NV34TCL_VIEWPORT_TRANSLATE_Z 0x00000a28
-#define NV34TCL_VIEWPORT_TRANSLATE_W 0x00000a2c
-#define NV34TCL_VIEWPORT_SCALE_X 0x00000a30
-#define NV34TCL_VIEWPORT_SCALE_Y 0x00000a34
-#define NV34TCL_VIEWPORT_SCALE_Z 0x00000a38
-#define NV34TCL_VIEWPORT_SCALE_W 0x00000a3c
-#define NV34TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000a60
-#define NV34TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000a64
-#define NV34TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000a68
-#define NV34TCL_DEPTH_FUNC 0x00000a6c
-#define NV34TCL_DEPTH_FUNC_NEVER 0x00000200
-#define NV34TCL_DEPTH_FUNC_LESS 0x00000201
-#define NV34TCL_DEPTH_FUNC_EQUAL 0x00000202
-#define NV34TCL_DEPTH_FUNC_LEQUAL 0x00000203
-#define NV34TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV34TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV34TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
-#define NV34TCL_DEPTH_FUNC_GEQUAL 0x00000206
-#define NV34TCL_DEPTH_FUNC_ALWAYS 0x00000207
-#define NV34TCL_DEPTH_WRITE_ENABLE 0x00000a70
-#define NV34TCL_DEPTH_TEST_ENABLE 0x00000a74
-#define NV34TCL_POLYGON_OFFSET_FACTOR 0x00000a78
-#define NV34TCL_POLYGON_OFFSET_UNITS 0x00000a7c
-#define NV34TCL_VTX_ATTR_3I_XY(x) (0x00000a80+((x)*8))
-#define NV34TCL_VTX_ATTR_3I_XY__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_3I_XY_X_SHIFT 0
-#define NV34TCL_VTX_ATTR_3I_XY_X_MASK 0x0000ffff
-#define NV34TCL_VTX_ATTR_3I_XY_Y_SHIFT 16
-#define NV34TCL_VTX_ATTR_3I_XY_Y_MASK 0xffff0000
-#define NV34TCL_VTX_ATTR_3I_Z(x) (0x00000a84+((x)*8))
-#define NV34TCL_VTX_ATTR_3I_Z__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_3I_Z_Z_SHIFT 0
-#define NV34TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff
-#define NV34TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4))
-#define NV34TCL_VP_UPLOAD_INST__SIZE 0x00000004
-#define NV34TCL_TX0_CLIP_PLANE_A(x) (0x00000e00+((x)*16))
-#define NV34TCL_TX0_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX0_CLIP_PLANE_B(x) (0x00000e04+((x)*16))
-#define NV34TCL_TX0_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX0_CLIP_PLANE_C(x) (0x00000e08+((x)*16))
-#define NV34TCL_TX0_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX0_CLIP_PLANE_D(x) (0x00000e0c+((x)*16))
-#define NV34TCL_TX0_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX1_CLIP_PLANE_A(x) (0x00000e40+((x)*16))
-#define NV34TCL_TX1_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX1_CLIP_PLANE_B(x) (0x00000e44+((x)*16))
-#define NV34TCL_TX1_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX1_CLIP_PLANE_C(x) (0x00000e48+((x)*16))
-#define NV34TCL_TX1_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX1_CLIP_PLANE_D(x) (0x00000e4c+((x)*16))
-#define NV34TCL_TX1_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX2_CLIP_PLANE_A(x) (0x00000e80+((x)*16))
-#define NV34TCL_TX2_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX2_CLIP_PLANE_B(x) (0x00000e84+((x)*16))
-#define NV34TCL_TX2_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX2_CLIP_PLANE_C(x) (0x00000e88+((x)*16))
-#define NV34TCL_TX2_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX2_CLIP_PLANE_D(x) (0x00000e8c+((x)*16))
-#define NV34TCL_TX2_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX3_CLIP_PLANE_A(x) (0x00000ec0+((x)*16))
-#define NV34TCL_TX3_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX3_CLIP_PLANE_B(x) (0x00000ec4+((x)*16))
-#define NV34TCL_TX3_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX3_CLIP_PLANE_C(x) (0x00000ec8+((x)*16))
-#define NV34TCL_TX3_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX3_CLIP_PLANE_D(x) (0x00000ecc+((x)*16))
-#define NV34TCL_TX3_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX4_CLIP_PLANE_A(x) (0x00000f00+((x)*16))
-#define NV34TCL_TX4_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX4_CLIP_PLANE_B(x) (0x00000f04+((x)*16))
-#define NV34TCL_TX4_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX4_CLIP_PLANE_C(x) (0x00000f08+((x)*16))
-#define NV34TCL_TX4_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX4_CLIP_PLANE_D(x) (0x00000f0c+((x)*16))
-#define NV34TCL_TX4_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX5_CLIP_PLANE_A(x) (0x00000f40+((x)*16))
-#define NV34TCL_TX5_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX5_CLIP_PLANE_B(x) (0x00000f44+((x)*16))
-#define NV34TCL_TX5_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX5_CLIP_PLANE_C(x) (0x00000f48+((x)*16))
-#define NV34TCL_TX5_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX5_CLIP_PLANE_D(x) (0x00000f4c+((x)*16))
-#define NV34TCL_TX5_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX6_CLIP_PLANE_A(x) (0x00000f80+((x)*16))
-#define NV34TCL_TX6_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX6_CLIP_PLANE_B(x) (0x00000f84+((x)*16))
-#define NV34TCL_TX6_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX6_CLIP_PLANE_C(x) (0x00000f88+((x)*16))
-#define NV34TCL_TX6_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX6_CLIP_PLANE_D(x) (0x00000f8c+((x)*16))
-#define NV34TCL_TX6_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_TX7_CLIP_PLANE_A(x) (0x00000fc0+((x)*16))
-#define NV34TCL_TX7_CLIP_PLANE_A__SIZE 0x00000004
-#define NV34TCL_TX7_CLIP_PLANE_B(x) (0x00000fc4+((x)*16))
-#define NV34TCL_TX7_CLIP_PLANE_B__SIZE 0x00000004
-#define NV34TCL_TX7_CLIP_PLANE_C(x) (0x00000fc8+((x)*16))
-#define NV34TCL_TX7_CLIP_PLANE_C__SIZE 0x00000004
-#define NV34TCL_TX7_CLIP_PLANE_D(x) (0x00000fcc+((x)*16))
-#define NV34TCL_TX7_CLIP_PLANE_D__SIZE 0x00000004
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x) (0x00001000+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x) (0x00001004+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x) (0x00001008+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x) (0x0000100c+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x) (0x00001010+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x) (0x00001014+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x) (0x00001018+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x) (0x0000101c+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE 0x00000008
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x) (0x00001020+((x)*64))
-#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE 0x00000008
-#define NV34TCL_LIGHT_HALF_VECTOR_X(x) (0x00001028+((x)*64))
-#define NV34TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008
-#define NV34TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000102c+((x)*64))
-#define NV34TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008
-#define NV34TCL_LIGHT_HALF_VECTOR_Z(x) (0x00001030+((x)*64))
-#define NV34TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008
-#define NV34TCL_LIGHT_DIRECTION_X(x) (0x00001034+((x)*64))
-#define NV34TCL_LIGHT_DIRECTION_X__SIZE 0x00000008
-#define NV34TCL_LIGHT_DIRECTION_Y(x) (0x00001038+((x)*64))
-#define NV34TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008
-#define NV34TCL_LIGHT_DIRECTION_Z(x) (0x0000103c+((x)*64))
-#define NV34TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00001200+((x)*64))
-#define NV34TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00001204+((x)*64))
-#define NV34TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00001208+((x)*64))
-#define NV34TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_DIR_X(x) (0x0000120c+((x)*64))
-#define NV34TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_DIR_Y(x) (0x00001210+((x)*64))
-#define NV34TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_DIR_Z(x) (0x00001214+((x)*64))
-#define NV34TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008
-#define NV34TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00001218+((x)*64))
-#define NV34TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008
-#define NV34TCL_LIGHT_POSITION_X(x) (0x0000121c+((x)*64))
-#define NV34TCL_LIGHT_POSITION_X__SIZE 0x00000008
-#define NV34TCL_LIGHT_POSITION_Y(x) (0x00001220+((x)*64))
-#define NV34TCL_LIGHT_POSITION_Y__SIZE 0x00000008
-#define NV34TCL_LIGHT_POSITION_Z(x) (0x00001224+((x)*64))
-#define NV34TCL_LIGHT_POSITION_Z__SIZE 0x00000008
-#define NV34TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00001228+((x)*64))
-#define NV34TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008
-#define NV34TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000122c+((x)*64))
-#define NV34TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008
-#define NV34TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00001230+((x)*64))
-#define NV34TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008
-#define NV34TCL_FRONT_MATERIAL_SHININESS(x) (0x00001400+((x)*4))
-#define NV34TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006
-#define NV34TCL_ENABLED_LIGHTS 0x00001420
-#define NV34TCL_FP_REG_CONTROL 0x00001450
-#define NV34TCL_FP_REG_CONTROL_UNK1_SHIFT 16
-#define NV34TCL_FP_REG_CONTROL_UNK1_MASK 0xffff0000
-#define NV34TCL_FP_REG_CONTROL_UNK0_SHIFT 0
-#define NV34TCL_FP_REG_CONTROL_UNK0_MASK 0x0000ffff
-#define NV34TCL_VP_CLIP_PLANES_ENABLE 0x00001478
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 (1 << 1)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 (1 << 5)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 (1 << 9)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 (1 << 13)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4 (1 << 17)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5 (1 << 21)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE6 (1 << 25)
-#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE7 (1 << 29)
-#define NV34TCL_POLYGON_STIPPLE_ENABLE 0x0000147c
-#define NV34TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4))
-#define NV34TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020
-#define NV34TCL_VTX_ATTR_3F_X(x) (0x00001500+((x)*16))
-#define NV34TCL_VTX_ATTR_3F_X__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_3F_Y(x) (0x00001504+((x)*16))
-#define NV34TCL_VTX_ATTR_3F_Y__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_3F_Z(x) (0x00001508+((x)*16))
-#define NV34TCL_VTX_ATTR_3F_Z__SIZE 0x00000010
-#define NV34TCL_VP_CLIP_PLANE_A(x) (0x00001600+((x)*16))
-#define NV34TCL_VP_CLIP_PLANE_A__SIZE 0x00000006
-#define NV34TCL_VP_CLIP_PLANE_B(x) (0x00001604+((x)*16))
-#define NV34TCL_VP_CLIP_PLANE_B__SIZE 0x00000006
-#define NV34TCL_VP_CLIP_PLANE_C(x) (0x00001608+((x)*16))
-#define NV34TCL_VP_CLIP_PLANE_C__SIZE 0x00000006
-#define NV34TCL_VP_CLIP_PLANE_D(x) (0x0000160c+((x)*16))
-#define NV34TCL_VP_CLIP_PLANE_D__SIZE 0x00000006
-#define NV34TCL_VTXBUF_ADDRESS(x) (0x00001680+((x)*4))
-#define NV34TCL_VTXBUF_ADDRESS__SIZE 0x00000010
-#define NV34TCL_VTXBUF_ADDRESS_DMA1 (1 << 31)
-#define NV34TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0
-#define NV34TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff
-#define NV34TCL_VTXFMT(x) (0x00001740+((x)*4))
-#define NV34TCL_VTXFMT__SIZE 0x00000010
-#define NV34TCL_VTXFMT_TYPE_SHIFT 0
-#define NV34TCL_VTXFMT_TYPE_MASK 0x0000000f
-#define NV34TCL_VTXFMT_TYPE_FLOAT 0x00000002
-#define NV34TCL_VTXFMT_TYPE_UBYTE 0x00000004
-#define NV34TCL_VTXFMT_TYPE_USHORT 0x00000005
-#define NV34TCL_VTXFMT_SIZE_SHIFT 4
-#define NV34TCL_VTXFMT_SIZE_MASK 0x000000f0
-#define NV34TCL_VTXFMT_STRIDE_SHIFT 8
-#define NV34TCL_VTXFMT_STRIDE_MASK 0x0000ff00
-#define NV34TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0
-#define NV34TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4
-#define NV34TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8
-#define NV34TCL_COLOR_MATERIAL_BACK_R 0x000017b0
-#define NV34TCL_COLOR_MATERIAL_BACK_G 0x000017b4
-#define NV34TCL_COLOR_MATERIAL_BACK_B 0x000017b8
-#define NV34TCL_COLOR_MATERIAL_BACK_A 0x000017c0
-#define NV34TCL_QUERY_RESET 0x000017c8
-#define NV34TCL_QUERY_UNK17CC 0x000017cc
-#define NV34TCL_QUERY_GET 0x00001800
-#define NV34TCL_QUERY_GET_UNK24_SHIFT 24
-#define NV34TCL_QUERY_GET_UNK24_MASK 0xff000000
-#define NV34TCL_QUERY_GET_OFFSET_SHIFT 0
-#define NV34TCL_QUERY_GET_OFFSET_MASK 0x00ffffff
-#define NV34TCL_VERTEX_BEGIN_END 0x00001808
-#define NV34TCL_VERTEX_BEGIN_END_STOP 0x00000000
-#define NV34TCL_VERTEX_BEGIN_END_POINTS 0x00000001
-#define NV34TCL_VERTEX_BEGIN_END_LINES 0x00000002
-#define NV34TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003
-#define NV34TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004
-#define NV34TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005
-#define NV34TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006
-#define NV34TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007
-#define NV34TCL_VERTEX_BEGIN_END_QUADS 0x00000008
-#define NV34TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009
-#define NV34TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a
-#define NV34TCL_VB_ELEMENT_U16 0x0000180c
-#define NV34TCL_VB_ELEMENT_U16_I0_SHIFT 0
-#define NV34TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff
-#define NV34TCL_VB_ELEMENT_U16_I1_SHIFT 16
-#define NV34TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000
-#define NV34TCL_VB_ELEMENT_U32 0x00001810
-#define NV34TCL_VB_VERTEX_BATCH 0x00001814
-#define NV34TCL_VB_VERTEX_BATCH_OFFSET_SHIFT 0
-#define NV34TCL_VB_VERTEX_BATCH_OFFSET_MASK 0x00ffffff
-#define NV34TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24
-#define NV34TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000
-#define NV34TCL_VERTEX_DATA 0x00001818
-#define NV34TCL_IDXBUF_ADDRESS 0x0000181c
-#define NV34TCL_IDXBUF_FORMAT 0x00001820
-#define NV34TCL_IDXBUF_FORMAT_TYPE_SHIFT 4
-#define NV34TCL_IDXBUF_FORMAT_TYPE_MASK 0x000000f0
-#define NV34TCL_IDXBUF_FORMAT_TYPE_U32 0x00000000
-#define NV34TCL_IDXBUF_FORMAT_TYPE_U16 0x00000010
-#define NV34TCL_IDXBUF_FORMAT_DMA1 (1 << 0)
-#define NV34TCL_VB_INDEX_BATCH 0x00001824
-#define NV34TCL_VB_INDEX_BATCH_COUNT_SHIFT 24
-#define NV34TCL_VB_INDEX_BATCH_COUNT_MASK 0xff000000
-#define NV34TCL_VB_INDEX_BATCH_START_SHIFT 0
-#define NV34TCL_VB_INDEX_BATCH_START_MASK 0x00ffffff
-#define NV34TCL_POLYGON_MODE_FRONT 0x00001828
-#define NV34TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
-#define NV34TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
-#define NV34TCL_POLYGON_MODE_FRONT_FILL 0x00001b02
-#define NV34TCL_POLYGON_MODE_BACK 0x0000182c
-#define NV34TCL_POLYGON_MODE_BACK_POINT 0x00001b00
-#define NV34TCL_POLYGON_MODE_BACK_LINE 0x00001b01
-#define NV34TCL_POLYGON_MODE_BACK_FILL 0x00001b02
-#define NV34TCL_CULL_FACE 0x00001830
-#define NV34TCL_CULL_FACE_FRONT 0x00000404
-#define NV34TCL_CULL_FACE_BACK 0x00000405
-#define NV34TCL_CULL_FACE_FRONT_AND_BACK 0x00000408
-#define NV34TCL_FRONT_FACE 0x00001834
-#define NV34TCL_FRONT_FACE_CW 0x00000900
-#define NV34TCL_FRONT_FACE_CCW 0x00000901
-#define NV34TCL_POLYGON_SMOOTH_ENABLE 0x00001838
-#define NV34TCL_CULL_FACE_ENABLE 0x0000183c
-#define NV34TCL_TX_PALETTE_OFFSET(x) (0x00001840+((x)*4))
-#define NV34TCL_TX_PALETTE_OFFSET__SIZE 0x00000004
-#define NV34TCL_VTX_ATTR_2F_X(x) (0x00001880+((x)*8))
-#define NV34TCL_VTX_ATTR_2F_X__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_2F_Y(x) (0x00001884+((x)*8))
-#define NV34TCL_VTX_ATTR_2F_Y__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_2I(x) (0x00001900+((x)*4))
-#define NV34TCL_VTX_ATTR_2I__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_2I_X_SHIFT 0
-#define NV34TCL_VTX_ATTR_2I_X_MASK 0x0000ffff
-#define NV34TCL_VTX_ATTR_2I_Y_SHIFT 16
-#define NV34TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
-#define NV34TCL_VTX_ATTR_4UB(x) (0x00001940+((x)*4))
-#define NV34TCL_VTX_ATTR_4UB__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_4UB_X_SHIFT 0
-#define NV34TCL_VTX_ATTR_4UB_X_MASK 0x000000ff
-#define NV34TCL_VTX_ATTR_4UB_Y_SHIFT 8
-#define NV34TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00
-#define NV34TCL_VTX_ATTR_4UB_Z_SHIFT 16
-#define NV34TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000
-#define NV34TCL_VTX_ATTR_4UB_W_SHIFT 24
-#define NV34TCL_VTX_ATTR_4UB_W_MASK 0xff000000
-#define NV34TCL_VTX_ATTR_4I_XY(x) (0x00001980+((x)*8))
-#define NV34TCL_VTX_ATTR_4I_XY__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_4I_XY_X_SHIFT 0
-#define NV34TCL_VTX_ATTR_4I_XY_X_MASK 0x0000ffff
-#define NV34TCL_VTX_ATTR_4I_XY_Y_SHIFT 16
-#define NV34TCL_VTX_ATTR_4I_XY_Y_MASK 0xffff0000
-#define NV34TCL_VTX_ATTR_4I_ZW(x) (0x00001984+((x)*8))
-#define NV34TCL_VTX_ATTR_4I_ZW__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_4I_ZW_Z_SHIFT 0
-#define NV34TCL_VTX_ATTR_4I_ZW_Z_MASK 0x0000ffff
-#define NV34TCL_VTX_ATTR_4I_ZW_W_SHIFT 16
-#define NV34TCL_VTX_ATTR_4I_ZW_W_MASK 0xffff0000
-#define NV34TCL_TX_OFFSET(x) (0x00001a00+((x)*32))
-#define NV34TCL_TX_OFFSET__SIZE 0x00000004
-#define NV34TCL_TX_FORMAT(x) (0x00001a04+((x)*32))
-#define NV34TCL_TX_FORMAT__SIZE 0x00000004
-#define NV34TCL_TX_FORMAT_DMA0 (1 << 0)
-#define NV34TCL_TX_FORMAT_DMA1 (1 << 1)
-#define NV34TCL_TX_FORMAT_CUBIC (1 << 2)
-#define NV34TCL_TX_FORMAT_NO_BORDER (1 << 3)
-#define NV34TCL_TX_FORMAT_DIMS_SHIFT 4
-#define NV34TCL_TX_FORMAT_DIMS_MASK 0x000000f0
-#define NV34TCL_TX_FORMAT_DIMS_1D 0x00000010
-#define NV34TCL_TX_FORMAT_DIMS_2D 0x00000020
-#define NV34TCL_TX_FORMAT_DIMS_3D 0x00000030
-#define NV34TCL_TX_FORMAT_FORMAT_SHIFT 8
-#define NV34TCL_TX_FORMAT_FORMAT_MASK 0x0000ff00
-#define NV34TCL_TX_FORMAT_FORMAT_L8 0x00000000
-#define NV34TCL_TX_FORMAT_FORMAT_A8 0x00000100
-#define NV34TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000200
-#define NV34TCL_TX_FORMAT_FORMAT_A8_RECT 0x00000300
-#define NV34TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000400
-#define NV34TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000500
-#define NV34TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000600
-#define NV34TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000700
-#define NV34TCL_TX_FORMAT_FORMAT_INDEX8 0x00000b00
-#define NV34TCL_TX_FORMAT_FORMAT_DXT1 0x00000c00
-#define NV34TCL_TX_FORMAT_FORMAT_DXT3 0x00000e00
-#define NV34TCL_TX_FORMAT_FORMAT_DXT5 0x00000f00
-#define NV34TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000
-#define NV34TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100
-#define NV34TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200
-#define NV34TCL_TX_FORMAT_FORMAT_L8_RECT 0x00001300
-#define NV34TCL_TX_FORMAT_FORMAT_A8L8 0x00001a00
-#define NV34TCL_TX_FORMAT_FORMAT_A8_RECT2 0x00001b00
-#define NV34TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00
-#define NV34TCL_TX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00
-#define NV34TCL_TX_FORMAT_FORMAT_L8A8_RECT 0x00002000
-#define NV34TCL_TX_FORMAT_FORMAT_DSDT 0x00002800
-#define NV34TCL_TX_FORMAT_FORMAT_A16 0x00003200
-#define NV34TCL_TX_FORMAT_FORMAT_HILO16 0x00003300
-#define NV34TCL_TX_FORMAT_FORMAT_A16_RECT 0x00003500
-#define NV34TCL_TX_FORMAT_FORMAT_HILO16_RECT 0x00003600
-#define NV34TCL_TX_FORMAT_FORMAT_HILO8 0x00004400
-#define NV34TCL_TX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500
-#define NV34TCL_TX_FORMAT_FORMAT_HILO8_RECT 0x00004600
-#define NV34TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700
-#define NV34TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00
-#define NV34TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00
-#define NV34TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00
-#define NV34TCL_TX_FORMAT_MIPMAP (1 << 19)
-#define NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 20
-#define NV34TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x00f00000
-#define NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 24
-#define NV34TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x0f000000
-#define NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT 28
-#define NV34TCL_TX_FORMAT_BASE_SIZE_W_MASK 0xf0000000
-#define NV34TCL_TX_WRAP(x) (0x00001a08+((x)*32))
-#define NV34TCL_TX_WRAP__SIZE 0x00000004
-#define NV34TCL_TX_WRAP_S_SHIFT 0
-#define NV34TCL_TX_WRAP_S_MASK 0x000000ff
-#define NV34TCL_TX_WRAP_S_REPEAT 0x00000001
-#define NV34TCL_TX_WRAP_S_MIRRORED_REPEAT 0x00000002
-#define NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE 0x00000003
-#define NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER 0x00000004
-#define NV34TCL_TX_WRAP_S_CLAMP 0x00000005
-#define NV34TCL_TX_WRAP_T_SHIFT 8
-#define NV34TCL_TX_WRAP_T_MASK 0x00000f00
-#define NV34TCL_TX_WRAP_T_REPEAT 0x00000100
-#define NV34TCL_TX_WRAP_T_MIRRORED_REPEAT 0x00000200
-#define NV34TCL_TX_WRAP_T_CLAMP_TO_EDGE 0x00000300
-#define NV34TCL_TX_WRAP_T_CLAMP_TO_BORDER 0x00000400
-#define NV34TCL_TX_WRAP_T_CLAMP 0x00000500
-#define NV34TCL_TX_WRAP_EXPAND_NORMAL_SHIFT 12
-#define NV34TCL_TX_WRAP_EXPAND_NORMAL_MASK 0x0000f000
-#define NV34TCL_TX_WRAP_R_SHIFT 16
-#define NV34TCL_TX_WRAP_R_MASK 0x000f0000
-#define NV34TCL_TX_WRAP_R_REPEAT 0x00010000
-#define NV34TCL_TX_WRAP_R_MIRRORED_REPEAT 0x00020000
-#define NV34TCL_TX_WRAP_R_CLAMP_TO_EDGE 0x00030000
-#define NV34TCL_TX_WRAP_R_CLAMP_TO_BORDER 0x00040000
-#define NV34TCL_TX_WRAP_R_CLAMP 0x00050000
-#define NV34TCL_TX_WRAP_RCOMP_SHIFT 28
-#define NV34TCL_TX_WRAP_RCOMP_MASK 0xf0000000
-#define NV34TCL_TX_WRAP_RCOMP_NEVER 0x00000000
-#define NV34TCL_TX_WRAP_RCOMP_GREATER 0x10000000
-#define NV34TCL_TX_WRAP_RCOMP_EQUAL 0x20000000
-#define NV34TCL_TX_WRAP_RCOMP_GEQUAL 0x30000000
-#define NV34TCL_TX_WRAP_RCOMP_LESS 0x40000000
-#define NV34TCL_TX_WRAP_RCOMP_NOTEQUAL 0x50000000
-#define NV34TCL_TX_WRAP_RCOMP_LEQUAL 0x60000000
-#define NV34TCL_TX_WRAP_RCOMP_ALWAYS 0x70000000
-#define NV34TCL_TX_ENABLE(x) (0x00001a0c+((x)*32))
-#define NV34TCL_TX_ENABLE__SIZE 0x00000004
-#define NV34TCL_TX_ENABLE_ANISO_SHIFT 4
-#define NV34TCL_TX_ENABLE_ANISO_MASK 0x00000030
-#define NV34TCL_TX_ENABLE_ANISO_NONE 0x00000000
-#define NV34TCL_TX_ENABLE_ANISO_2X 0x00000010
-#define NV34TCL_TX_ENABLE_ANISO_4X 0x00000020
-#define NV34TCL_TX_ENABLE_ANISO_8X 0x00000030
-#define NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14
-#define NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000
-#define NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26
-#define NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000
-#define NV34TCL_TX_ENABLE_ENABLE (1 << 30)
-#define NV34TCL_TX_SWIZZLE(x) (0x00001a10+((x)*32))
-#define NV34TCL_TX_SWIZZLE__SIZE 0x00000004
-#define NV34TCL_TX_SWIZZLE_S0_X_SHIFT 14
-#define NV34TCL_TX_SWIZZLE_S0_X_MASK 0x0000c000
-#define NV34TCL_TX_SWIZZLE_S0_X_ZERO 0x00000000
-#define NV34TCL_TX_SWIZZLE_S0_X_ONE 0x00004000
-#define NV34TCL_TX_SWIZZLE_S0_X_S1 0x00008000
-#define NV34TCL_TX_SWIZZLE_S0_Y_SHIFT 12
-#define NV34TCL_TX_SWIZZLE_S0_Y_MASK 0x00003000
-#define NV34TCL_TX_SWIZZLE_S0_Y_ZERO 0x00000000
-#define NV34TCL_TX_SWIZZLE_S0_Y_ONE 0x00001000
-#define NV34TCL_TX_SWIZZLE_S0_Y_S1 0x00002000
-#define NV34TCL_TX_SWIZZLE_S0_Z_SHIFT 10
-#define NV34TCL_TX_SWIZZLE_S0_Z_MASK 0x00000c00
-#define NV34TCL_TX_SWIZZLE_S0_Z_ZERO 0x00000000
-#define NV34TCL_TX_SWIZZLE_S0_Z_ONE 0x00000400
-#define NV34TCL_TX_SWIZZLE_S0_Z_S1 0x00000800
-#define NV34TCL_TX_SWIZZLE_S0_W_SHIFT 8
-#define NV34TCL_TX_SWIZZLE_S0_W_MASK 0x00000300
-#define NV34TCL_TX_SWIZZLE_S0_W_ZERO 0x00000000
-#define NV34TCL_TX_SWIZZLE_S0_W_ONE 0x00000100
-#define NV34TCL_TX_SWIZZLE_S0_W_S1 0x00000200
-#define NV34TCL_TX_SWIZZLE_S1_X_SHIFT 6
-#define NV34TCL_TX_SWIZZLE_S1_X_MASK 0x000000c0
-#define NV34TCL_TX_SWIZZLE_S1_X_W 0x00000000
-#define NV34TCL_TX_SWIZZLE_S1_X_Z 0x00000040
-#define NV34TCL_TX_SWIZZLE_S1_X_Y 0x00000080
-#define NV34TCL_TX_SWIZZLE_S1_X_X 0x000000c0
-#define NV34TCL_TX_SWIZZLE_S1_Y_SHIFT 4
-#define NV34TCL_TX_SWIZZLE_S1_Y_MASK 0x00000030
-#define NV34TCL_TX_SWIZZLE_S1_Y_W 0x00000000
-#define NV34TCL_TX_SWIZZLE_S1_Y_Z 0x00000010
-#define NV34TCL_TX_SWIZZLE_S1_Y_Y 0x00000020
-#define NV34TCL_TX_SWIZZLE_S1_Y_X 0x00000030
-#define NV34TCL_TX_SWIZZLE_S1_Z_SHIFT 2
-#define NV34TCL_TX_SWIZZLE_S1_Z_MASK 0x0000000c
-#define NV34TCL_TX_SWIZZLE_S1_Z_W 0x00000000
-#define NV34TCL_TX_SWIZZLE_S1_Z_Z 0x00000004
-#define NV34TCL_TX_SWIZZLE_S1_Z_Y 0x00000008
-#define NV34TCL_TX_SWIZZLE_S1_Z_X 0x0000000c
-#define NV34TCL_TX_SWIZZLE_S1_W_SHIFT 0
-#define NV34TCL_TX_SWIZZLE_S1_W_MASK 0x00000003
-#define NV34TCL_TX_SWIZZLE_S1_W_W 0x00000000
-#define NV34TCL_TX_SWIZZLE_S1_W_Z 0x00000001
-#define NV34TCL_TX_SWIZZLE_S1_W_Y 0x00000002
-#define NV34TCL_TX_SWIZZLE_S1_W_X 0x00000003
-#define NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT 16
-#define NV34TCL_TX_SWIZZLE_RECT_PITCH_MASK 0xffff0000
-#define NV34TCL_TX_FILTER(x) (0x00001a14+((x)*32))
-#define NV34TCL_TX_FILTER__SIZE 0x00000004
-#define NV34TCL_TX_FILTER_LOD_BIAS_SHIFT 8
-#define NV34TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00
-#define NV34TCL_TX_FILTER_MINIFY_SHIFT 16
-#define NV34TCL_TX_FILTER_MINIFY_MASK 0x000f0000
-#define NV34TCL_TX_FILTER_MINIFY_NEAREST 0x00010000
-#define NV34TCL_TX_FILTER_MINIFY_LINEAR 0x00020000
-#define NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x00030000
-#define NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x00040000
-#define NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x00050000
-#define NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x00060000
-#define NV34TCL_TX_FILTER_MAGNIFY_SHIFT 24
-#define NV34TCL_TX_FILTER_MAGNIFY_MASK 0x0f000000
-#define NV34TCL_TX_FILTER_MAGNIFY_NEAREST 0x01000000
-#define NV34TCL_TX_FILTER_MAGNIFY_LINEAR 0x02000000
-#define NV34TCL_TX_FILTER_SIGNED_BLUE (1 << 28)
-#define NV34TCL_TX_FILTER_SIGNED_GREEN (1 << 29)
-#define NV34TCL_TX_FILTER_SIGNED_RED (1 << 30)
-#define NV34TCL_TX_FILTER_SIGNED_ALPHA (1 << 31)
-#define NV34TCL_TX_NPOT_SIZE(x) (0x00001a18+((x)*32))
-#define NV34TCL_TX_NPOT_SIZE__SIZE 0x00000004
-#define NV34TCL_TX_NPOT_SIZE_H_SHIFT 0
-#define NV34TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff
-#define NV34TCL_TX_NPOT_SIZE_W_SHIFT 16
-#define NV34TCL_TX_NPOT_SIZE_W_MASK 0xffff0000
-#define NV34TCL_TX_BORDER_COLOR(x) (0x00001a1c+((x)*32))
-#define NV34TCL_TX_BORDER_COLOR__SIZE 0x00000004
-#define NV34TCL_TX_BORDER_COLOR_B_SHIFT 0
-#define NV34TCL_TX_BORDER_COLOR_B_MASK 0x000000ff
-#define NV34TCL_TX_BORDER_COLOR_G_SHIFT 8
-#define NV34TCL_TX_BORDER_COLOR_G_MASK 0x0000ff00
-#define NV34TCL_TX_BORDER_COLOR_R_SHIFT 16
-#define NV34TCL_TX_BORDER_COLOR_R_MASK 0x00ff0000
-#define NV34TCL_TX_BORDER_COLOR_A_SHIFT 24
-#define NV34TCL_TX_BORDER_COLOR_A_MASK 0xff000000
-#define NV34TCL_VTX_ATTR_4F_X(x) (0x00001c00+((x)*16))
-#define NV34TCL_VTX_ATTR_4F_X__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_4F_Y(x) (0x00001c04+((x)*16))
-#define NV34TCL_VTX_ATTR_4F_Y__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_4F_Z(x) (0x00001c08+((x)*16))
-#define NV34TCL_VTX_ATTR_4F_Z__SIZE 0x00000010
-#define NV34TCL_VTX_ATTR_4F_W(x) (0x00001c0c+((x)*16))
-#define NV34TCL_VTX_ATTR_4F_W__SIZE 0x00000010
-#define NV34TCL_FP_CONTROL 0x00001d60
-#define NV34TCL_FP_CONTROL_USES_KIL (1 << 7)
-#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_SHIFT 0
-#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_MASK 0x0000000f
-#define NV34TCL_DEPTH_UNK17D8 0x00001d78
-#define NV34TCL_DEPTH_UNK17D8_CLAMP_SHIFT 4
-#define NV34TCL_DEPTH_UNK17D8_CLAMP_MASK 0x000000f0
-#define NV34TCL_MULTISAMPLE_CONTROL 0x00001d7c
-#define NV34TCL_MULTISAMPLE_CONTROL_ENABLE (1 << 0)
-#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_COVERAGE (1 << 4)
-#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_ONE (1 << 8)
-#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE_SHIFT 16
-#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE_MASK 0xffff0000
-#define NV34TCL_CLEAR_DEPTH_VALUE 0x00001d8c
-#define NV34TCL_CLEAR_COLOR_VALUE 0x00001d90
-#define NV34TCL_CLEAR_COLOR_VALUE_B_SHIFT 0
-#define NV34TCL_CLEAR_COLOR_VALUE_B_MASK 0x000000ff
-#define NV34TCL_CLEAR_COLOR_VALUE_G_SHIFT 8
-#define NV34TCL_CLEAR_COLOR_VALUE_G_MASK 0x0000ff00
-#define NV34TCL_CLEAR_COLOR_VALUE_R_SHIFT 16
-#define NV34TCL_CLEAR_COLOR_VALUE_R_MASK 0x00ff0000
-#define NV34TCL_CLEAR_COLOR_VALUE_A_SHIFT 24
-#define NV34TCL_CLEAR_COLOR_VALUE_A_MASK 0xff000000
-#define NV34TCL_CLEAR_BUFFERS 0x00001d94
-#define NV34TCL_CLEAR_BUFFERS_COLOR_A (1 << 7)
-#define NV34TCL_CLEAR_BUFFERS_COLOR_B (1 << 6)
-#define NV34TCL_CLEAR_BUFFERS_COLOR_G (1 << 5)
-#define NV34TCL_CLEAR_BUFFERS_COLOR_R (1 << 4)
-#define NV34TCL_CLEAR_BUFFERS_STENCIL (1 << 1)
-#define NV34TCL_CLEAR_BUFFERS_DEPTH (1 << 0)
-#define NV34TCL_DO_VERTICES 0x00001dac
-#define NV34TCL_LINE_STIPPLE_ENABLE 0x00001db4
-#define NV34TCL_LINE_STIPPLE_PATTERN 0x00001db8
-#define NV34TCL_LINE_STIPPLE_PATTERN_FACTOR_SHIFT 0
-#define NV34TCL_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff
-#define NV34TCL_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16
-#define NV34TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000
-#define NV34TCL_BACK_MATERIAL_SHININESS(x) (0x00001e20+((x)*4))
-#define NV34TCL_BACK_MATERIAL_SHININESS__SIZE 0x00000006
-#define NV34TCL_VTX_ATTR_1F(x) (0x00001e40+((x)*4))
-#define NV34TCL_VTX_ATTR_1F__SIZE 0x00000010
-#define NV34TCL_ENGINE 0x00001e94
-#define NV34TCL_ENGINE_FP (1 << 0)
-#define NV34TCL_ENGINE_VP (1 << 1)
-#define NV34TCL_ENGINE_FIXED (1 << 2)
-#define NV34TCL_VP_UPLOAD_FROM_ID 0x00001e9c
-#define NV34TCL_VP_START_FROM_ID 0x00001ea0
-#define NV34TCL_POINT_PARAMETERS(x) (0x00001ec0+((x)*4))
-#define NV34TCL_POINT_PARAMETERS__SIZE 0x00000008
-#define NV34TCL_POINT_SIZE 0x00001ee0
-#define NV34TCL_POINT_PARAMETERS_ENABLE 0x00001ee4
-#define NV34TCL_POINT_SPRITE 0x00001ee8
-#define NV34TCL_POINT_SPRITE_ENABLE (1 << 0)
-#define NV34TCL_POINT_SPRITE_R_MODE_SHIFT 1
-#define NV34TCL_POINT_SPRITE_R_MODE_MASK 0x00000006
-#define NV34TCL_POINT_SPRITE_R_MODE_ZERO 0x00000000
-#define NV34TCL_POINT_SPRITE_R_MODE_R 0x00000002
-#define NV34TCL_POINT_SPRITE_R_MODE_S 0x00000004
-#define NV34TCL_POINT_SPRITE_COORD_REPLACE (1 << 11)
-#define NV34TCL_VP_UPLOAD_CONST_ID 0x00001efc
-#define NV34TCL_VP_UPLOAD_CONST_X(x) (0x00001f00+((x)*16))
-#define NV34TCL_VP_UPLOAD_CONST_X__SIZE 0x00000004
-#define NV34TCL_VP_UPLOAD_CONST_Y(x) (0x00001f04+((x)*16))
-#define NV34TCL_VP_UPLOAD_CONST_Y__SIZE 0x00000004
-#define NV34TCL_VP_UPLOAD_CONST_Z(x) (0x00001f08+((x)*16))
-#define NV34TCL_VP_UPLOAD_CONST_Z__SIZE 0x00000004
-#define NV34TCL_VP_UPLOAD_CONST_W(x) (0x00001f0c+((x)*16))
-#define NV34TCL_VP_UPLOAD_CONST_W__SIZE 0x00000004
-#define NV34TCL_UNK1f80(x) (0x00001f80+((x)*4))
-#define NV34TCL_UNK1f80__SIZE 0x00000010
-
-
-#define NV40_CONTEXT_SURFACES_2D 0x00003062
-
-
-
-#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066
-
-
-
-#define NV40_TEXTURE_FROM_CPU 0x0000307b
-
-
-
-#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089
-
-
-
-#define NV40_IMAGE_FROM_CPU 0x0000308a
-
-
-
-#define NV40_SWIZZLED_SURFACE 0x0000309e
-
-
-
-#define NV40TCL 0x00004097
-
-#define NV40TCL_REF_CNT 0x00000050
-#define NV40TCL_NOP 0x00000100
-#define NV40TCL_NOTIFY 0x00000104
-#define NV40TCL_DMA_NOTIFY 0x00000180
-#define NV40TCL_DMA_TEXTURE0 0x00000184
-#define NV40TCL_DMA_TEXTURE1 0x00000188
-#define NV40TCL_DMA_COLOR1 0x0000018c
-#define NV40TCL_DMA_COLOR0 0x00000194
-#define NV40TCL_DMA_ZETA 0x00000198
-#define NV40TCL_DMA_VTXBUF0 0x0000019c
-#define NV40TCL_DMA_VTXBUF1 0x000001a0
-#define NV40TCL_DMA_FENCE 0x000001a4
-#define NV40TCL_DMA_QUERY 0x000001a8
-#define NV40TCL_DMA_UNK01AC 0x000001ac
-#define NV40TCL_DMA_UNK01B0 0x000001b0
-#define NV40TCL_DMA_COLOR2 0x000001b4
-#define NV40TCL_DMA_COLOR3 0x000001b8
-#define NV40TCL_RT_HORIZ 0x00000200
-#define NV40TCL_RT_HORIZ_W_SHIFT 16
-#define NV40TCL_RT_HORIZ_W_MASK 0xffff0000
-#define NV40TCL_RT_HORIZ_X_SHIFT 0
-#define NV40TCL_RT_HORIZ_X_MASK 0x0000ffff
-#define NV40TCL_RT_VERT 0x00000204
-#define NV40TCL_RT_VERT_H_SHIFT 16
-#define NV40TCL_RT_VERT_H_MASK 0xffff0000
-#define NV40TCL_RT_VERT_Y_SHIFT 0
-#define NV40TCL_RT_VERT_Y_MASK 0x0000ffff
-#define NV40TCL_RT_FORMAT 0x00000208
-#define NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT 24
-#define NV40TCL_RT_FORMAT_LOG2_HEIGHT_MASK 0xff000000
-#define NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT 16
-#define NV40TCL_RT_FORMAT_LOG2_WIDTH_MASK 0x00ff0000
-#define NV40TCL_RT_FORMAT_TYPE_SHIFT 8
-#define NV40TCL_RT_FORMAT_TYPE_MASK 0x00000f00
-#define NV40TCL_RT_FORMAT_TYPE_LINEAR 0x00000100
-#define NV40TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200
-#define NV40TCL_RT_FORMAT_ZETA_SHIFT 5
-#define NV40TCL_RT_FORMAT_ZETA_MASK 0x000000e0
-#define NV40TCL_RT_FORMAT_ZETA_Z16 0x00000020
-#define NV40TCL_RT_FORMAT_ZETA_Z24S8 0x00000040
-#define NV40TCL_RT_FORMAT_COLOR_SHIFT 0
-#define NV40TCL_RT_FORMAT_COLOR_MASK 0x0000001f
-#define NV40TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003
-#define NV40TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005
-#define NV40TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008
-#define NV40TCL_RT_FORMAT_COLOR_B8 0x00000009
-#define NV40TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d
-#define NV40TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f
-#define NV40TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010
-#define NV40TCL_COLOR0_PITCH 0x0000020c
-#define NV40TCL_COLOR0_OFFSET 0x00000210
-#define NV40TCL_ZETA_OFFSET 0x00000214
-#define NV40TCL_COLOR1_OFFSET 0x00000218
-#define NV40TCL_COLOR1_PITCH 0x0000021c
-#define NV40TCL_RT_ENABLE 0x00000220
-#define NV40TCL_RT_ENABLE_MRT (1 << 4)
-#define NV40TCL_RT_ENABLE_COLOR3 (1 << 3)
-#define NV40TCL_RT_ENABLE_COLOR2 (1 << 2)
-#define NV40TCL_RT_ENABLE_COLOR1 (1 << 1)
-#define NV40TCL_RT_ENABLE_COLOR0 (1 << 0)
-#define NV40TCL_ZETA_PITCH 0x0000022c
-#define NV40TCL_COLOR2_PITCH 0x00000280
-#define NV40TCL_COLOR3_PITCH 0x00000284
-#define NV40TCL_COLOR2_OFFSET 0x00000288
-#define NV40TCL_COLOR3_OFFSET 0x0000028c
-#define NV40TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*8))
-#define NV40TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008
-#define NV40TCL_VIEWPORT_CLIP_VERT(x) (0x000002c4+((x)*8))
-#define NV40TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008
-#define NV40TCL_DITHER_ENABLE 0x00000300
-#define NV40TCL_ALPHA_TEST_ENABLE 0x00000304
-#define NV40TCL_ALPHA_TEST_FUNC 0x00000308
-#define NV40TCL_ALPHA_TEST_FUNC_NEVER 0x00000200
-#define NV40TCL_ALPHA_TEST_FUNC_LESS 0x00000201
-#define NV40TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202
-#define NV40TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203
-#define NV40TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
-#define NV40TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
-#define NV40TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205
-#define NV40TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206
-#define NV40TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207
-#define NV40TCL_ALPHA_TEST_REF 0x0000030c
-#define NV40TCL_BLEND_ENABLE 0x00000310
-#define NV40TCL_BLEND_FUNC_SRC 0x00000314
-#define NV40TCL_BLEND_FUNC_SRC_RGB_SHIFT 0
-#define NV40TCL_BLEND_FUNC_SRC_RGB_MASK 0x0000ffff
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00000000
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE 0x00000001
-#define NV40TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV40TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV40TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV40TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307
-#define NV40TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308
-#define NV40TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV40TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003
-#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SHIFT 16
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_MASK 0xffff0000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000
-#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
-#define NV40TCL_BLEND_FUNC_DST 0x00000318
-#define NV40TCL_BLEND_FUNC_DST_RGB_SHIFT 0
-#define NV40TCL_BLEND_FUNC_DST_RGB_MASK 0x0000ffff
-#define NV40TCL_BLEND_FUNC_DST_RGB_ZERO 0x00000000
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE 0x00000001
-#define NV40TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV40TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV40TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV40TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307
-#define NV40TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308
-#define NV40TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV40TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003
-#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_SHIFT 16
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_MASK 0xffff0000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00010000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000
-#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
-#define NV40TCL_BLEND_COLOR 0x0000031c
-#define NV40TCL_BLEND_EQUATION 0x00000320
-#define NV40TCL_BLEND_EQUATION_RGB_SHIFT 0
-#define NV40TCL_BLEND_EQUATION_RGB_MASK 0x0000ffff
-#define NV40TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006
-#define NV40TCL_BLEND_EQUATION_RGB_MIN 0x00008007
-#define NV40TCL_BLEND_EQUATION_RGB_MAX 0x00008008
-#define NV40TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a
-#define NV40TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b
-#define NV40TCL_BLEND_EQUATION_ALPHA_SHIFT 16
-#define NV40TCL_BLEND_EQUATION_ALPHA_MASK 0xffff0000
-#define NV40TCL_BLEND_EQUATION_ALPHA_FUNC_ADD 0x80060000
-#define NV40TCL_BLEND_EQUATION_ALPHA_MIN 0x80070000
-#define NV40TCL_BLEND_EQUATION_ALPHA_MAX 0x80080000
-#define NV40TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x800a0000
-#define NV40TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x800b0000
-#define NV40TCL_COLOR_MASK 0x00000324
-#define NV40TCL_COLOR_MASK_BUFFER0_B_SHIFT 0
-#define NV40TCL_COLOR_MASK_BUFFER0_B_MASK 0x000000ff
-#define NV40TCL_COLOR_MASK_BUFFER0_G_SHIFT 8
-#define NV40TCL_COLOR_MASK_BUFFER0_G_MASK 0x0000ff00
-#define NV40TCL_COLOR_MASK_BUFFER0_R_SHIFT 16
-#define NV40TCL_COLOR_MASK_BUFFER0_R_MASK 0x00ff0000
-#define NV40TCL_COLOR_MASK_BUFFER0_A_SHIFT 24
-#define NV40TCL_COLOR_MASK_BUFFER0_A_MASK 0xff000000
-#define NV40TCL_STENCIL_FRONT_ENABLE 0x00000328
-#define NV40TCL_STENCIL_FRONT_MASK 0x0000032c
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC 0x00000330
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
-#define NV40TCL_STENCIL_FRONT_FUNC_REF 0x00000334
-#define NV40TCL_STENCIL_FRONT_FUNC_MASK 0x00000338
-#define NV40TCL_STENCIL_FRONT_OP_FAIL 0x0000033c
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507
-#define NV40TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL 0x00000340
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS 0x00000344
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV40TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV40TCL_STENCIL_BACK_ENABLE 0x00000348
-#define NV40TCL_STENCIL_BACK_MASK 0x0000034c
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC 0x00000350
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
-#define NV40TCL_STENCIL_BACK_FUNC_REF 0x00000354
-#define NV40TCL_STENCIL_BACK_FUNC_MASK 0x00000358
-#define NV40TCL_STENCIL_BACK_OP_FAIL 0x0000035c
-#define NV40TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000
-#define NV40TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a
-#define NV40TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00
-#define NV40TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01
-#define NV40TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02
-#define NV40TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03
-#define NV40TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507
-#define NV40TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL 0x00000360
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV40TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV40TCL_STENCIL_BACK_OP_ZPASS 0x00000364
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV40TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV40TCL_SHADE_MODEL 0x00000368
-#define NV40TCL_SHADE_MODEL_FLAT 0x00001d00
-#define NV40TCL_SHADE_MODEL_SMOOTH 0x00001d01
-#define NV40TCL_MRT_COLOR_MASK 0x00000370
-#define NV40TCL_MRT_COLOR_MASK_BUFFER1_A (1 << 4)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER1_R (1 << 5)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER1_G (1 << 6)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER1_B (1 << 7)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER2_A (1 << 8)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER2_R (1 << 9)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER2_G (1 << 10)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER2_B (1 << 11)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER3_A (1 << 12)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER3_R (1 << 13)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER3_G (1 << 14)
-#define NV40TCL_MRT_COLOR_MASK_BUFFER3_B (1 << 15)
-#define NV40TCL_COLOR_LOGIC_OP_ENABLE 0x00000374
-#define NV40TCL_COLOR_LOGIC_OP 0x00000378
-#define NV40TCL_COLOR_LOGIC_OP_CLEAR 0x00001500
-#define NV40TCL_COLOR_LOGIC_OP_AND 0x00001501
-#define NV40TCL_COLOR_LOGIC_OP_AND_REVERSE 0x00001502
-#define NV40TCL_COLOR_LOGIC_OP_COPY 0x00001503
-#define NV40TCL_COLOR_LOGIC_OP_AND_INVERTED 0x00001504
-#define NV40TCL_COLOR_LOGIC_OP_NOOP 0x00001505
-#define NV40TCL_COLOR_LOGIC_OP_XOR 0x00001506
-#define NV40TCL_COLOR_LOGIC_OP_OR 0x00001507
-#define NV40TCL_COLOR_LOGIC_OP_NOR 0x00001508
-#define NV40TCL_COLOR_LOGIC_OP_EQUIV 0x00001509
-#define NV40TCL_COLOR_LOGIC_OP_INVERT 0x0000150a
-#define NV40TCL_COLOR_LOGIC_OP_OR_REVERSE 0x0000150b
-#define NV40TCL_COLOR_LOGIC_OP_COPY_INVERTED 0x0000150c
-#define NV40TCL_COLOR_LOGIC_OP_OR_INVERTED 0x0000150d
-#define NV40TCL_COLOR_LOGIC_OP_NAND 0x0000150e
-#define NV40TCL_COLOR_LOGIC_OP_SET 0x0000150f
-#define NV40TCL_DEPTH_RANGE_NEAR 0x00000394
-#define NV40TCL_DEPTH_RANGE_FAR 0x00000398
-#define NV40TCL_LINE_WIDTH 0x000003b8
-#define NV40TCL_LINE_SMOOTH_ENABLE 0x000003bc
-#define NV40TCL_UNK03C0(x) (0x000003c0+((x)*4))
-#define NV40TCL_UNK03C0__SIZE 0x00000010
-#define NV40TCL_UNK0400(x) (0x00000400+((x)*4))
-#define NV40TCL_UNK0400__SIZE 0x00000010
-#define NV40TCL_UNK0440(x) (0x00000440+((x)*4))
-#define NV40TCL_UNK0440__SIZE 0x00000020
-#define NV40TCL_SCISSOR_HORIZ 0x000008c0
-#define NV40TCL_SCISSOR_HORIZ_X_SHIFT 0
-#define NV40TCL_SCISSOR_HORIZ_X_MASK 0x0000ffff
-#define NV40TCL_SCISSOR_HORIZ_W_SHIFT 16
-#define NV40TCL_SCISSOR_HORIZ_W_MASK 0xffff0000
-#define NV40TCL_SCISSOR_VERT 0x000008c4
-#define NV40TCL_SCISSOR_VERT_Y_SHIFT 0
-#define NV40TCL_SCISSOR_VERT_Y_MASK 0x0000ffff
-#define NV40TCL_SCISSOR_VERT_H_SHIFT 16
-#define NV40TCL_SCISSOR_VERT_H_MASK 0xffff0000
-#define NV40TCL_FOG_MODE 0x000008cc
-#define NV40TCL_FOG_EQUATION_CONSTANT 0x000008d0
-#define NV40TCL_FOG_EQUATION_LINEAR 0x000008d4
-#define NV40TCL_FOG_EQUATION_QUADRATIC 0x000008d8
-#define NV40TCL_FP_ADDRESS 0x000008e4
-#define NV40TCL_FP_ADDRESS_OFFSET_SHIFT 8
-#define NV40TCL_FP_ADDRESS_OFFSET_MASK 0xffffff00
-#define NV40TCL_FP_ADDRESS_DMA1 (1 << 1)
-#define NV40TCL_FP_ADDRESS_DMA0 (1 << 0)
-#define NV40TCL_VIEWPORT_HORIZ 0x00000a00
-#define NV40TCL_VIEWPORT_HORIZ_W_SHIFT 16
-#define NV40TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000
-#define NV40TCL_VIEWPORT_HORIZ_X_SHIFT 0
-#define NV40TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff
-#define NV40TCL_VIEWPORT_VERT 0x00000a04
-#define NV40TCL_VIEWPORT_VERT_H_SHIFT 16
-#define NV40TCL_VIEWPORT_VERT_H_MASK 0xffff0000
-#define NV40TCL_VIEWPORT_VERT_Y_SHIFT 0
-#define NV40TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff
-#define NV40TCL_VIEWPORT_TRANSLATE_X 0x00000a20
-#define NV40TCL_VIEWPORT_TRANSLATE_Y 0x00000a24
-#define NV40TCL_VIEWPORT_TRANSLATE_Z 0x00000a28
-#define NV40TCL_VIEWPORT_TRANSLATE_W 0x00000a2c
-#define NV40TCL_VIEWPORT_SCALE_X 0x00000a30
-#define NV40TCL_VIEWPORT_SCALE_Y 0x00000a34
-#define NV40TCL_VIEWPORT_SCALE_Z 0x00000a38
-#define NV40TCL_VIEWPORT_SCALE_W 0x00000a3c
-#define NV40TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000a60
-#define NV40TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000a64
-#define NV40TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000a68
-#define NV40TCL_DEPTH_FUNC 0x00000a6c
-#define NV40TCL_DEPTH_FUNC_NEVER 0x00000200
-#define NV40TCL_DEPTH_FUNC_LESS 0x00000201
-#define NV40TCL_DEPTH_FUNC_EQUAL 0x00000202
-#define NV40TCL_DEPTH_FUNC_LEQUAL 0x00000203
-#define NV40TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV40TCL_DEPTH_FUNC_GREATER 0x00000204
-#define NV40TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
-#define NV40TCL_DEPTH_FUNC_GEQUAL 0x00000206
-#define NV40TCL_DEPTH_FUNC_ALWAYS 0x00000207
-#define NV40TCL_DEPTH_WRITE_ENABLE 0x00000a70
-#define NV40TCL_DEPTH_TEST_ENABLE 0x00000a74
-#define NV40TCL_POLYGON_OFFSET_FACTOR 0x00000a78
-#define NV40TCL_POLYGON_OFFSET_UNITS 0x00000a7c
-#define NV40TCL_VTX_ATTR_3I_XY(x) (0x00000a80+((x)*8))
-#define NV40TCL_VTX_ATTR_3I_XY__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_3I_XY_X_SHIFT 0
-#define NV40TCL_VTX_ATTR_3I_XY_X_MASK 0x0000ffff
-#define NV40TCL_VTX_ATTR_3I_XY_Y_SHIFT 16
-#define NV40TCL_VTX_ATTR_3I_XY_Y_MASK 0xffff0000
-#define NV40TCL_VTX_ATTR_3I_Z(x) (0x00000a84+((x)*8))
-#define NV40TCL_VTX_ATTR_3I_Z__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_3I_Z_Z_SHIFT 0
-#define NV40TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff
-#define NV40TCL_UNK0B40(x) (0x00000b40+((x)*4))
-#define NV40TCL_UNK0B40__SIZE 0x00000008
-#define NV40TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4))
-#define NV40TCL_VP_UPLOAD_INST__SIZE 0x00000004
-#define NV40TCL_CLIP_PLANE_ENABLE 0x00001478
-#define NV40TCL_CLIP_PLANE_ENABLE_PLANE0 (1 << 1)
-#define NV40TCL_CLIP_PLANE_ENABLE_PLANE1 (1 << 5)
-#define NV40TCL_CLIP_PLANE_ENABLE_PLANE2 (1 << 9)
-#define NV40TCL_CLIP_PLANE_ENABLE_PLANE3 (1 << 13)
-#define NV40TCL_CLIP_PLANE_ENABLE_PLANE4 (1 << 17)
-#define NV40TCL_CLIP_PLANE_ENABLE_PLANE5 (1 << 21)
-#define NV40TCL_POLYGON_STIPPLE_ENABLE 0x0000147c
-#define NV40TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4))
-#define NV40TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020
-#define NV40TCL_VTX_ATTR_3F_X(x) (0x00001500+((x)*16))
-#define NV40TCL_VTX_ATTR_3F_X__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_3F_Y(x) (0x00001504+((x)*16))
-#define NV40TCL_VTX_ATTR_3F_Y__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_3F_Z(x) (0x00001508+((x)*16))
-#define NV40TCL_VTX_ATTR_3F_Z__SIZE 0x00000010
-#define NV40TCL_VTXBUF_ADDRESS(x) (0x00001680+((x)*4))
-#define NV40TCL_VTXBUF_ADDRESS__SIZE 0x00000010
-#define NV40TCL_VTXBUF_ADDRESS_DMA1 (1 << 31)
-#define NV40TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0
-#define NV40TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff
-#define NV40TCL_VTX_CACHE_INVALIDATE 0x00001714
-#define NV40TCL_VTXFMT(x) (0x00001740+((x)*4))
-#define NV40TCL_VTXFMT__SIZE 0x00000010
-#define NV40TCL_VTXFMT_TYPE_SHIFT 0
-#define NV40TCL_VTXFMT_TYPE_MASK 0x0000000f
-#define NV40TCL_VTXFMT_TYPE_FLOAT 0x00000002
-#define NV40TCL_VTXFMT_TYPE_UBYTE 0x00000004
-#define NV40TCL_VTXFMT_TYPE_USHORT 0x00000005
-#define NV40TCL_VTXFMT_SIZE_SHIFT 4
-#define NV40TCL_VTXFMT_SIZE_MASK 0x000000f0
-#define NV40TCL_VTXFMT_STRIDE_SHIFT 8
-#define NV40TCL_VTXFMT_STRIDE_MASK 0x0000ff00
-#define NV40TCL_QUERY_RESET 0x000017c8
-#define NV40TCL_QUERY_UNK17CC 0x000017cc
-#define NV40TCL_QUERY_GET 0x00001800
-#define NV40TCL_QUERY_GET_UNK24_SHIFT 24
-#define NV40TCL_QUERY_GET_UNK24_MASK 0xff000000
-#define NV40TCL_QUERY_GET_OFFSET_SHIFT 0
-#define NV40TCL_QUERY_GET_OFFSET_MASK 0x00ffffff
-#define NV40TCL_BEGIN_END 0x00001808
-#define NV40TCL_BEGIN_END_STOP 0x00000000
-#define NV40TCL_BEGIN_END_POINTS 0x00000001
-#define NV40TCL_BEGIN_END_LINES 0x00000002
-#define NV40TCL_BEGIN_END_LINE_LOOP 0x00000003
-#define NV40TCL_BEGIN_END_LINE_STRIP 0x00000004
-#define NV40TCL_BEGIN_END_TRIANGLES 0x00000005
-#define NV40TCL_BEGIN_END_TRIANGLE_STRIP 0x00000006
-#define NV40TCL_BEGIN_END_TRIANGLE_FAN 0x00000007
-#define NV40TCL_BEGIN_END_QUADS 0x00000008
-#define NV40TCL_BEGIN_END_QUAD_STRIP 0x00000009
-#define NV40TCL_BEGIN_END_POLYGON 0x0000000a
-#define NV40TCL_VB_ELEMENT_U16 0x0000180c
-#define NV40TCL_VB_ELEMENT_U16_1_SHIFT 16
-#define NV40TCL_VB_ELEMENT_U16_1_MASK 0xffff0000
-#define NV40TCL_VB_ELEMENT_U16_0_SHIFT 0
-#define NV40TCL_VB_ELEMENT_U16_0_MASK 0x0000ffff
-#define NV40TCL_VB_ELEMENT_U32 0x00001810
-#define NV40TCL_VB_VERTEX_BATCH 0x00001814
-#define NV40TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24
-#define NV40TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000
-#define NV40TCL_VB_VERTEX_BATCH_START_SHIFT 0
-#define NV40TCL_VB_VERTEX_BATCH_START_MASK 0x00ffffff
-#define NV40TCL_VERTEX_DATA 0x00001818
-#define NV40TCL_IDXBUF_ADDRESS 0x0000181c
-#define NV40TCL_IDXBUF_FORMAT 0x00001820
-#define NV40TCL_IDXBUF_FORMAT_TYPE_SHIFT 4
-#define NV40TCL_IDXBUF_FORMAT_TYPE_MASK 0x000000f0
-#define NV40TCL_IDXBUF_FORMAT_TYPE_U32 0x00000000
-#define NV40TCL_IDXBUF_FORMAT_TYPE_U16 0x00000010
-#define NV40TCL_IDXBUF_FORMAT_DMA1 (1 << 0)
-#define NV40TCL_VB_INDEX_BATCH 0x00001824
-#define NV40TCL_VB_INDEX_BATCH_COUNT_SHIFT 24
-#define NV40TCL_VB_INDEX_BATCH_COUNT_MASK 0xff000000
-#define NV40TCL_VB_INDEX_BATCH_START_SHIFT 0
-#define NV40TCL_VB_INDEX_BATCH_START_MASK 0x00ffffff
-#define NV40TCL_POLYGON_MODE_FRONT 0x00001828
-#define NV40TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
-#define NV40TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
-#define NV40TCL_POLYGON_MODE_FRONT_FILL 0x00001b02
-#define NV40TCL_POLYGON_MODE_BACK 0x0000182c
-#define NV40TCL_POLYGON_MODE_BACK_POINT 0x00001b00
-#define NV40TCL_POLYGON_MODE_BACK_LINE 0x00001b01
-#define NV40TCL_POLYGON_MODE_BACK_FILL 0x00001b02
-#define NV40TCL_CULL_FACE 0x00001830
-#define NV40TCL_CULL_FACE_FRONT 0x00000404
-#define NV40TCL_CULL_FACE_BACK 0x00000405
-#define NV40TCL_CULL_FACE_FRONT_AND_BACK 0x00000408
-#define NV40TCL_FRONT_FACE 0x00001834
-#define NV40TCL_FRONT_FACE_CW 0x00000900
-#define NV40TCL_FRONT_FACE_CCW 0x00000901
-#define NV40TCL_POLYGON_SMOOTH_ENABLE 0x00001838
-#define NV40TCL_CULL_FACE_ENABLE 0x0000183c
-#define NV40TCL_TEX_SIZE1(x) (0x00001840+((x)*4))
-#define NV40TCL_TEX_SIZE1__SIZE 0x00000008
-#define NV40TCL_TEX_SIZE1_DEPTH_SHIFT 20
-#define NV40TCL_TEX_SIZE1_DEPTH_MASK 0xfff00000
-#define NV40TCL_TEX_SIZE1_PITCH_SHIFT 0
-#define NV40TCL_TEX_SIZE1_PITCH_MASK 0x0000ffff
-#define NV40TCL_VTX_ATTR_2F_X(x) (0x00001880+((x)*8))
-#define NV40TCL_VTX_ATTR_2F_X__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_2F_Y(x) (0x00001884+((x)*8))
-#define NV40TCL_VTX_ATTR_2F_Y__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_2I(x) (0x00001900+((x)*4))
-#define NV40TCL_VTX_ATTR_2I__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_2I_X_SHIFT 0
-#define NV40TCL_VTX_ATTR_2I_X_MASK 0x0000ffff
-#define NV40TCL_VTX_ATTR_2I_Y_SHIFT 16
-#define NV40TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
-#define NV40TCL_VTX_ATTR_4UB(x) (0x00001940+((x)*4))
-#define NV40TCL_VTX_ATTR_4UB__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_4UB_X_SHIFT 0
-#define NV40TCL_VTX_ATTR_4UB_X_MASK 0x000000ff
-#define NV40TCL_VTX_ATTR_4UB_Y_SHIFT 8
-#define NV40TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00
-#define NV40TCL_VTX_ATTR_4UB_Z_SHIFT 16
-#define NV40TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000
-#define NV40TCL_VTX_ATTR_4UB_W_SHIFT 24
-#define NV40TCL_VTX_ATTR_4UB_W_MASK 0xff000000
-#define NV40TCL_VTX_ATTR_4I_XY(x) (0x00001980+((x)*8))
-#define NV40TCL_VTX_ATTR_4I_XY__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_4I_XY_X_SHIFT 0
-#define NV40TCL_VTX_ATTR_4I_XY_X_MASK 0x0000ffff
-#define NV40TCL_VTX_ATTR_4I_XY_Y_SHIFT 16
-#define NV40TCL_VTX_ATTR_4I_XY_Y_MASK 0xffff0000
-#define NV40TCL_VTX_ATTR_4I_ZW(x) (0x00001984+((x)*8))
-#define NV40TCL_VTX_ATTR_4I_ZW__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_4I_ZW_Z_SHIFT 0
-#define NV40TCL_VTX_ATTR_4I_ZW_Z_MASK 0x0000ffff
-#define NV40TCL_VTX_ATTR_4I_ZW_W_SHIFT 16
-#define NV40TCL_VTX_ATTR_4I_ZW_W_MASK 0xffff0000
-#define NV40TCL_TEX_OFFSET(x) (0x00001a00+((x)*32))
-#define NV40TCL_TEX_OFFSET__SIZE 0x00000010
-#define NV40TCL_TEX_FORMAT(x) (0x00001a04+((x)*32))
-#define NV40TCL_TEX_FORMAT__SIZE 0x00000010
-#define NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT 16
-#define NV40TCL_TEX_FORMAT_MIPMAP_COUNT_MASK 0x000f0000
-#define NV40TCL_TEX_FORMAT_RECT (1 << 14)
-#define NV40TCL_TEX_FORMAT_LINEAR (1 << 13)
-#define NV40TCL_TEX_FORMAT_FORMAT_SHIFT 8
-#define NV40TCL_TEX_FORMAT_FORMAT_MASK 0x00001f00
-#define NV40TCL_TEX_FORMAT_FORMAT_L8 0x00000100
-#define NV40TCL_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200
-#define NV40TCL_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000300
-#define NV40TCL_TEX_FORMAT_FORMAT_R5G6B5 0x00000400
-#define NV40TCL_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000500
-#define NV40TCL_TEX_FORMAT_FORMAT_DXT1 0x00000600
-#define NV40TCL_TEX_FORMAT_FORMAT_DXT3 0x00000700
-#define NV40TCL_TEX_FORMAT_FORMAT_DXT5 0x00000800
-#define NV40TCL_TEX_FORMAT_FORMAT_A8L8 0x00000b00
-#define NV40TCL_TEX_FORMAT_FORMAT_Z24 0x00001000
-#define NV40TCL_TEX_FORMAT_FORMAT_Z16 0x00001200
-#define NV40TCL_TEX_FORMAT_FORMAT_A16 0x00001400
-#define NV40TCL_TEX_FORMAT_FORMAT_A16L16 0x00001500
-#define NV40TCL_TEX_FORMAT_FORMAT_HILO8 0x00001800
-#define NV40TCL_TEX_FORMAT_FORMAT_RGBA16F 0x00001a00
-#define NV40TCL_TEX_FORMAT_FORMAT_RGBA32F 0x00001b00
-#define NV40TCL_TEX_FORMAT_DIMS_SHIFT 4
-#define NV40TCL_TEX_FORMAT_DIMS_MASK 0x000000f0
-#define NV40TCL_TEX_FORMAT_DIMS_1D 0x00000010
-#define NV40TCL_TEX_FORMAT_DIMS_2D 0x00000020
-#define NV40TCL_TEX_FORMAT_DIMS_3D 0x00000030
-#define NV40TCL_TEX_FORMAT_NO_BORDER (1 << 3)
-#define NV40TCL_TEX_FORMAT_CUBIC (1 << 2)
-#define NV40TCL_TEX_FORMAT_DMA1 (1 << 1)
-#define NV40TCL_TEX_FORMAT_DMA0 (1 << 0)
-#define NV40TCL_TEX_WRAP(x) (0x00001a08+((x)*32))
-#define NV40TCL_TEX_WRAP__SIZE 0x00000010
-#define NV40TCL_TEX_WRAP_S_SHIFT 0
-#define NV40TCL_TEX_WRAP_S_MASK 0x000000ff
-#define NV40TCL_TEX_WRAP_S_REPEAT 0x00000001
-#define NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002
-#define NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003
-#define NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER 0x00000004
-#define NV40TCL_TEX_WRAP_S_CLAMP 0x00000005
-#define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006
-#define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007
-#define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP 0x00000008
-#define NV40TCL_TEX_WRAP_T_SHIFT 8
-#define NV40TCL_TEX_WRAP_T_MASK 0x00000f00
-#define NV40TCL_TEX_WRAP_T_REPEAT 0x00000100
-#define NV40TCL_TEX_WRAP_T_MIRRORED_REPEAT 0x00000200
-#define NV40TCL_TEX_WRAP_T_CLAMP_TO_EDGE 0x00000300
-#define NV40TCL_TEX_WRAP_T_CLAMP_TO_BORDER 0x00000400
-#define NV40TCL_TEX_WRAP_T_CLAMP 0x00000500
-#define NV40TCL_TEX_WRAP_T_MIRROR_CLAMP_TO_EDGE 0x00000600
-#define NV40TCL_TEX_WRAP_T_MIRROR_CLAMP_TO_BORDER 0x00000700
-#define NV40TCL_TEX_WRAP_T_MIRROR_CLAMP 0x00000800
-#define NV40TCL_TEX_WRAP_EXPAND_NORMAL_SHIFT 12
-#define NV40TCL_TEX_WRAP_EXPAND_NORMAL_MASK 0x0000f000
-#define NV40TCL_TEX_WRAP_R_SHIFT 16
-#define NV40TCL_TEX_WRAP_R_MASK 0x00ff0000
-#define NV40TCL_TEX_WRAP_R_REPEAT 0x00010000
-#define NV40TCL_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000
-#define NV40TCL_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000
-#define NV40TCL_TEX_WRAP_R_CLAMP_TO_BORDER 0x00040000
-#define NV40TCL_TEX_WRAP_R_CLAMP 0x00050000
-#define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000
-#define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000
-#define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP 0x00080000
-#define NV40TCL_TEX_WRAP_RCOMP_SHIFT 28
-#define NV40TCL_TEX_WRAP_RCOMP_MASK 0xf0000000
-#define NV40TCL_TEX_WRAP_RCOMP_NEVER 0x00000000
-#define NV40TCL_TEX_WRAP_RCOMP_GREATER 0x10000000
-#define NV40TCL_TEX_WRAP_RCOMP_EQUAL 0x20000000
-#define NV40TCL_TEX_WRAP_RCOMP_GEQUAL 0x30000000
-#define NV40TCL_TEX_WRAP_RCOMP_LESS 0x40000000
-#define NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL 0x50000000
-#define NV40TCL_TEX_WRAP_RCOMP_LEQUAL 0x60000000
-#define NV40TCL_TEX_WRAP_RCOMP_ALWAYS 0x70000000
-#define NV40TCL_TEX_ENABLE(x) (0x00001a0c+((x)*32))
-#define NV40TCL_TEX_ENABLE__SIZE 0x00000010
-#define NV40TCL_TEX_ENABLE_ENABLE (1 << 31)
-#define NV40TCL_TEX_ENABLE_MIPMAP_MIN_LOD_SHIFT 27
-#define NV40TCL_TEX_ENABLE_MIPMAP_MIN_LOD_MASK 0x38000000
-#define NV40TCL_TEX_ENABLE_MIPMAP_MAX_LOD_SHIFT 15
-#define NV40TCL_TEX_ENABLE_MIPMAP_MAX_LOD_MASK 0x00038000
-#define NV40TCL_TEX_ENABLE_ANISO_SHIFT 4
-#define NV40TCL_TEX_ENABLE_ANISO_MASK 0x000000f0
-#define NV40TCL_TEX_ENABLE_ANISO_NONE 0x00000000
-#define NV40TCL_TEX_ENABLE_ANISO_2X 0x00000010
-#define NV40TCL_TEX_ENABLE_ANISO_4X 0x00000020
-#define NV40TCL_TEX_ENABLE_ANISO_6X 0x00000030
-#define NV40TCL_TEX_ENABLE_ANISO_8X 0x00000040
-#define NV40TCL_TEX_ENABLE_ANISO_10X 0x00000050
-#define NV40TCL_TEX_ENABLE_ANISO_12X 0x00000060
-#define NV40TCL_TEX_ENABLE_ANISO_16X 0x00000070
-#define NV40TCL_TEX_SWIZZLE(x) (0x00001a10+((x)*32))
-#define NV40TCL_TEX_SWIZZLE__SIZE 0x00000010
-#define NV40TCL_TEX_SWIZZLE_S0_X_SHIFT 14
-#define NV40TCL_TEX_SWIZZLE_S0_X_MASK 0x0000c000
-#define NV40TCL_TEX_SWIZZLE_S0_X_ZERO 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S0_X_ONE 0x00004000
-#define NV40TCL_TEX_SWIZZLE_S0_X_S1 0x00008000
-#define NV40TCL_TEX_SWIZZLE_S0_Y_SHIFT 12
-#define NV40TCL_TEX_SWIZZLE_S0_Y_MASK 0x00003000
-#define NV40TCL_TEX_SWIZZLE_S0_Y_ZERO 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S0_Y_ONE 0x00001000
-#define NV40TCL_TEX_SWIZZLE_S0_Y_S1 0x00002000
-#define NV40TCL_TEX_SWIZZLE_S0_Z_SHIFT 10
-#define NV40TCL_TEX_SWIZZLE_S0_Z_MASK 0x00000c00
-#define NV40TCL_TEX_SWIZZLE_S0_Z_ZERO 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S0_Z_ONE 0x00000400
-#define NV40TCL_TEX_SWIZZLE_S0_Z_S1 0x00000800
-#define NV40TCL_TEX_SWIZZLE_S0_W_SHIFT 8
-#define NV40TCL_TEX_SWIZZLE_S0_W_MASK 0x00000300
-#define NV40TCL_TEX_SWIZZLE_S0_W_ZERO 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S0_W_ONE 0x00000100
-#define NV40TCL_TEX_SWIZZLE_S0_W_S1 0x00000200
-#define NV40TCL_TEX_SWIZZLE_S1_X_SHIFT 6
-#define NV40TCL_TEX_SWIZZLE_S1_X_MASK 0x000000c0
-#define NV40TCL_TEX_SWIZZLE_S1_X_W 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S1_X_Z 0x00000040
-#define NV40TCL_TEX_SWIZZLE_S1_X_Y 0x00000080
-#define NV40TCL_TEX_SWIZZLE_S1_X_X 0x000000c0
-#define NV40TCL_TEX_SWIZZLE_S1_Y_SHIFT 4
-#define NV40TCL_TEX_SWIZZLE_S1_Y_MASK 0x00000030
-#define NV40TCL_TEX_SWIZZLE_S1_Y_W 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S1_Y_Z 0x00000010
-#define NV40TCL_TEX_SWIZZLE_S1_Y_Y 0x00000020
-#define NV40TCL_TEX_SWIZZLE_S1_Y_X 0x00000030
-#define NV40TCL_TEX_SWIZZLE_S1_Z_SHIFT 2
-#define NV40TCL_TEX_SWIZZLE_S1_Z_MASK 0x0000000c
-#define NV40TCL_TEX_SWIZZLE_S1_Z_W 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S1_Z_Z 0x00000004
-#define NV40TCL_TEX_SWIZZLE_S1_Z_Y 0x00000008
-#define NV40TCL_TEX_SWIZZLE_S1_Z_X 0x0000000c
-#define NV40TCL_TEX_SWIZZLE_S1_W_SHIFT 0
-#define NV40TCL_TEX_SWIZZLE_S1_W_MASK 0x00000003
-#define NV40TCL_TEX_SWIZZLE_S1_W_W 0x00000000
-#define NV40TCL_TEX_SWIZZLE_S1_W_Z 0x00000001
-#define NV40TCL_TEX_SWIZZLE_S1_W_Y 0x00000002
-#define NV40TCL_TEX_SWIZZLE_S1_W_X 0x00000003
-#define NV40TCL_TEX_FILTER(x) (0x00001a14+((x)*32))
-#define NV40TCL_TEX_FILTER__SIZE 0x00000010
-#define NV40TCL_TEX_FILTER_SIGNED_ALPHA (1 << 31)
-#define NV40TCL_TEX_FILTER_SIGNED_RED (1 << 30)
-#define NV40TCL_TEX_FILTER_SIGNED_GREEN (1 << 29)
-#define NV40TCL_TEX_FILTER_SIGNED_BLUE (1 << 28)
-#define NV40TCL_TEX_FILTER_MIN_SHIFT 16
-#define NV40TCL_TEX_FILTER_MIN_MASK 0x000f0000
-#define NV40TCL_TEX_FILTER_MIN_NEAREST 0x00010000
-#define NV40TCL_TEX_FILTER_MIN_LINEAR 0x00020000
-#define NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x00030000
-#define NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x00040000
-#define NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x00050000
-#define NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x00060000
-#define NV40TCL_TEX_FILTER_MAG_SHIFT 24
-#define NV40TCL_TEX_FILTER_MAG_MASK 0x0f000000
-#define NV40TCL_TEX_FILTER_MAG_NEAREST 0x01000000
-#define NV40TCL_TEX_FILTER_MAG_LINEAR 0x02000000
-#define NV40TCL_TEX_SIZE0(x) (0x00001a18+((x)*32))
-#define NV40TCL_TEX_SIZE0__SIZE 0x00000010
-#define NV40TCL_TEX_SIZE0_H_SHIFT 0
-#define NV40TCL_TEX_SIZE0_H_MASK 0x0000ffff
-#define NV40TCL_TEX_SIZE0_W_SHIFT 16
-#define NV40TCL_TEX_SIZE0_W_MASK 0xffff0000
-#define NV40TCL_TEX_BORDER_COLOR(x) (0x00001a1c+((x)*32))
-#define NV40TCL_TEX_BORDER_COLOR__SIZE 0x00000010
-#define NV40TCL_TEX_BORDER_COLOR_B_SHIFT 0
-#define NV40TCL_TEX_BORDER_COLOR_B_MASK 0x000000ff
-#define NV40TCL_TEX_BORDER_COLOR_G_SHIFT 8
-#define NV40TCL_TEX_BORDER_COLOR_G_MASK 0x0000ff00
-#define NV40TCL_TEX_BORDER_COLOR_R_SHIFT 16
-#define NV40TCL_TEX_BORDER_COLOR_R_MASK 0x00ff0000
-#define NV40TCL_TEX_BORDER_COLOR_A_SHIFT 24
-#define NV40TCL_TEX_BORDER_COLOR_A_MASK 0xff000000
-#define NV40TCL_VTX_ATTR_4F_X(x) (0x00001c00+((x)*16))
-#define NV40TCL_VTX_ATTR_4F_X__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_4F_Y(x) (0x00001c04+((x)*16))
-#define NV40TCL_VTX_ATTR_4F_Y__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_4F_Z(x) (0x00001c08+((x)*16))
-#define NV40TCL_VTX_ATTR_4F_Z__SIZE 0x00000010
-#define NV40TCL_VTX_ATTR_4F_W(x) (0x00001c0c+((x)*16))
-#define NV40TCL_VTX_ATTR_4F_W__SIZE 0x00000010
-#define NV40TCL_FP_CONTROL 0x00001d60
-#define NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT 24
-#define NV40TCL_FP_CONTROL_TEMP_COUNT_MASK 0xff000000
-#define NV40TCL_FP_CONTROL_KIL (1 << 7)
-#define NV40TCL_MULTISAMPLE_CONTROL 0x00001d7c
-#define NV40TCL_CLEAR_VALUE_DEPTH 0x00001d8c
-#define NV40TCL_CLEAR_VALUE_COLOR 0x00001d90
-#define NV40TCL_CLEAR_BUFFERS 0x00001d94
-#define NV40TCL_CLEAR_BUFFERS_COLOR_A (1 << 7)
-#define NV40TCL_CLEAR_BUFFERS_COLOR_B (1 << 6)
-#define NV40TCL_CLEAR_BUFFERS_COLOR_G (1 << 5)
-#define NV40TCL_CLEAR_BUFFERS_COLOR_R (1 << 4)
-#define NV40TCL_CLEAR_BUFFERS_STENCIL (1 << 1)
-#define NV40TCL_CLEAR_BUFFERS_DEPTH (1 << 0)
-#define NV40TCL_LINE_STIPPLE_ENABLE 0x00001db4
-#define NV40TCL_LINE_STIPPLE_PATTERN 0x00001db8
-#define NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_SHIFT 0
-#define NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff
-#define NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16
-#define NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000
-#define NV40TCL_VTX_ATTR_1F(x) (0x00001e40+((x)*4))
-#define NV40TCL_VTX_ATTR_1F__SIZE 0x00000010
-#define NV40TCL_VP_UPLOAD_FROM_ID 0x00001e9c
-#define NV40TCL_VP_START_FROM_ID 0x00001ea0
-#define NV40TCL_POINT_SIZE 0x00001ee0
-#define NV40TCL_POINT_SPRITE 0x00001ee8
-#define NV40TCL_VP_UPLOAD_CONST_ID 0x00001efc
-#define NV40TCL_VP_UPLOAD_CONST_X(x) (0x00001f00+((x)*16))
-#define NV40TCL_VP_UPLOAD_CONST_X__SIZE 0x00000004
-#define NV40TCL_VP_UPLOAD_CONST_Y(x) (0x00001f04+((x)*16))
-#define NV40TCL_VP_UPLOAD_CONST_Y__SIZE 0x00000004
-#define NV40TCL_VP_UPLOAD_CONST_Z(x) (0x00001f08+((x)*16))
-#define NV40TCL_VP_UPLOAD_CONST_Z__SIZE 0x00000004
-#define NV40TCL_VP_UPLOAD_CONST_W(x) (0x00001f0c+((x)*16))
-#define NV40TCL_VP_UPLOAD_CONST_W__SIZE 0x00000004
-#define NV40TCL_TEX_CACHE_CTL 0x00001fd8
-#define NV40TCL_VP_ATTRIB_EN 0x00001ff0
-#define NV40TCL_VP_RESULT_EN 0x00001ff4
-
-
-#define NV44TCL 0x00004497
-
-
-
-#define NV50_2D 0x0000502d
-
-#define NV50_2D_NOP 0x00000100
-#define NV50_2D_NOTIFY 0x00000104
-#define NV50_2D_DMA_NOTIFY 0x00000180
-#define NV50_2D_DMA_IN_MEMORY0 0x00000184
-#define NV50_2D_DMA_IN_MEMORY1 0x00000188
-#define NV50_2D_DMA_IN_MEMORY2 0x0000018c
-#define NV50_2D_DST_FORMAT 0x00000200
-#define NV50_2D_DST_FORMAT_32BPP 0x000000cf
-#define NV50_2D_DST_FORMAT_24BPP 0x000000e6
-#define NV50_2D_DST_FORMAT_16BPP 0x000000e8
-#define NV50_2D_DST_FORMAT_8BPP 0x000000f3
-#define NV50_2D_DST_FORMAT_15BPP 0x000000f8
-#define NV50_2D_DST_PITCH 0x00000214
-#define NV50_2D_DST_WIDTH 0x00000218
-#define NV50_2D_DST_HEIGHT 0x0000021c
-#define NV50_2D_DST_ADDRESS_HIGH 0x00000220
-#define NV50_2D_DST_ADDRESS_LOW 0x00000224
-#define NV50_2D_SRC_FORMAT 0x00000230
-#define NV50_2D_SRC_FORMAT_32BPP 0x000000cf
-#define NV50_2D_SRC_FORMAT_24BPP 0x000000e6
-#define NV50_2D_SRC_FORMAT_16BPP 0x000000e8
-#define NV50_2D_SRC_FORMAT_8BPP 0x000000f3
-#define NV50_2D_SRC_FORMAT_15BPP 0x000000f8
-#define NV50_2D_SRC_PITCH 0x00000244
-#define NV50_2D_SRC_WIDTH 0x00000248
-#define NV50_2D_SRC_HEIGHT 0x0000024c
-#define NV50_2D_SRC_ADDRESS_HIGH 0x00000250
-#define NV50_2D_SRC_ADDRESS_LOW 0x00000254
-#define NV50_2D_CLIP_X 0x00000280
-#define NV50_2D_CLIP_Y 0x00000284
-#define NV50_2D_CLIP_Z 0x00000288
-#define NV50_2D_CLIP_W 0x0000028c
-#define NV50_2D_ROP 0x000002a0
-#define NV50_2D_OPERATION 0x000002ac
-#define NV50_2D_OPERATION_SRCCOPY_AND 0x00000000
-#define NV50_2D_OPERATION_ROP_AND 0x00000001
-#define NV50_2D_OPERATION_BLEND_AND 0x00000002
-#define NV50_2D_OPERATION_SRCCOPY 0x00000003
-#define NV50_2D_OPERATION_SRCCOPY_PREMULT 0x00000004
-#define NV50_2D_OPERATION_BLEND_PREMULT 0x00000005
-#define NV50_2D_PATTERN_FORMAT 0x000002e8
-#define NV50_2D_PATTERN_FORMAT_16BPP 0x00000000
-#define NV50_2D_PATTERN_FORMAT_15BPP 0x00000001
-#define NV50_2D_PATTERN_FORMAT_32BPP 0x00000002
-#define NV50_2D_PATTERN_FORMAT_8BPP 0x00000003
-#define NV50_2D_PATTERN_COLOR(x) (0x000002f0+((x)*4))
-#define NV50_2D_PATTERN_COLOR__SIZE 0x00000002
-#define NV50_2D_PATTERN_BITMAP(x) (0x000002f8+((x)*4))
-#define NV50_2D_PATTERN_BITMAP__SIZE 0x00000002
-#define NV50_2D_RECT_FORMAT 0x00000584
-#define NV50_2D_RECT_FORMAT_32BPP 0x000000cf
-#define NV50_2D_RECT_FORMAT_24BPP 0x000000e6
-#define NV50_2D_RECT_FORMAT_16BPP 0x000000e8
-#define NV50_2D_RECT_FORMAT_8BPP 0x000000f3
-#define NV50_2D_RECT_FORMAT_15BPP 0x000000f8
-#define NV50_2D_RECT_COLOR 0x00000588
-#define NV50_2D_RECT_X1 0x00000600
-#define NV50_2D_RECT_Y1 0x00000604
-#define NV50_2D_RECT_X2 0x00000608
-#define NV50_2D_RECT_Y2 0x0000060c
-#define NV50_2D_SIFC_UNK0800 0x00000800
-#define NV50_2D_SIFC_FORMAT 0x00000804
-#define NV50_2D_SIFC_FORMAT_32BPP 0x000000cf
-#define NV50_2D_SIFC_FORMAT_24BPP 0x000000e6
-#define NV50_2D_SIFC_FORMAT_16BPP 0x000000e8
-#define NV50_2D_SIFC_FORMAT_8BPP 0x000000f3
-#define NV50_2D_SIFC_FORMAT_15BPP 0x000000f8
-#define NV50_2D_SIFC_WIDTH 0x00000838
-#define NV50_2D_SIFC_HEIGHT 0x0000083c
-#define NV50_2D_SIFC_SCALE_UNK0840 0x00000840
-#define NV50_2D_SIFC_SCALE_UNK0844 0x00000844
-#define NV50_2D_SIFC_SCALE_UNK0848 0x00000848
-#define NV50_2D_SIFC_SCALE_UNK084C 0x0000084c
-#define NV50_2D_SIFC_UNK0850 0x00000850
-#define NV50_2D_SIFC_DST_X 0x00000854
-#define NV50_2D_SIFC_UNK0858 0x00000858
-#define NV50_2D_SIFC_DST_Y 0x0000085c
-#define NV50_2D_SIFC_DATA 0x00000860
-#define NV50_2D_BLIT_DST_X 0x000008b0
-#define NV50_2D_BLIT_DST_Y 0x000008b4
-#define NV50_2D_BLIT_DST_W 0x000008b8
-#define NV50_2D_BLIT_DST_H 0x000008bc
-#define NV50_2D_BLIT_SRC_X 0x000008d4
-#define NV50_2D_BLIT_SRC_Y 0x000008dc
-
-
-#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
-
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
-
-
-#define NV50TCL 0x00005097
-
-#define NV50TCL_NOP 0x00000100
-#define NV50TCL_NOTIFY 0x00000104
-#define NV50TCL_DMA_NOTIFY 0x00000180
-#define NV50TCL_DMA_UNK0(x) (0x00000184+((x)*4))
-#define NV50TCL_DMA_UNK0__SIZE 0x0000000b
-#define NV50TCL_DMA_UNK1(x) (0x000001c0+((x)*4))
-#define NV50TCL_DMA_UNK1__SIZE 0x00000008
-#define NV50TCL_RT_ADDRESS_HIGH(x) (0x00000200+((x)*32))
-#define NV50TCL_RT_ADDRESS_HIGH__SIZE 0x00000008
-#define NV50TCL_RT_ADDRESS_LOW(x) (0x00000204+((x)*32))
-#define NV50TCL_RT_ADDRESS_LOW__SIZE 0x00000008
-#define NV50TCL_RT_FORMAT(x) (0x00000208+((x)*32))
-#define NV50TCL_RT_FORMAT__SIZE 0x00000008
-#define NV50TCL_RT_FORMAT_32BPP 0x000000cf
-#define NV50TCL_RT_FORMAT_24BPP 0x000000e6
-#define NV50TCL_RT_FORMAT_16BPP 0x000000e8
-#define NV50TCL_RT_FORMAT_8BPP 0x000000f3
-#define NV50TCL_RT_FORMAT_15BPP 0x000000f8
-#define NV50TCL_RT_TILE_UNK(x) (0x0000020c+((x)*32))
-#define NV50TCL_RT_TILE_UNK__SIZE 0x00000008
-#define NV50TCL_RT_UNK4(x) (0x00000210+((x)*32))
-#define NV50TCL_RT_UNK4__SIZE 0x00000008
-#define NV50TCL_VTX_ATTR_1F(x) (0x00000300+((x)*4))
-#define NV50TCL_VTX_ATTR_1F__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_2F_X(x) (0x00000380+((x)*8))
-#define NV50TCL_VTX_ATTR_2F_X__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_2F_Y(x) (0x00000384+((x)*8))
-#define NV50TCL_VTX_ATTR_2F_Y__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_3F_X(x) (0x00000400+((x)*16))
-#define NV50TCL_VTX_ATTR_3F_X__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_3F_Y(x) (0x00000404+((x)*16))
-#define NV50TCL_VTX_ATTR_3F_Y__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_3F_Z(x) (0x00000408+((x)*16))
-#define NV50TCL_VTX_ATTR_3F_Z__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_3F_W(x) (0x0000040c+((x)*16))
-#define NV50TCL_VTX_ATTR_3F_W__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4F_X(x) (0x00000500+((x)*16))
-#define NV50TCL_VTX_ATTR_4F_X__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4F_Y(x) (0x00000504+((x)*16))
-#define NV50TCL_VTX_ATTR_4F_Y__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4F_Z(x) (0x00000508+((x)*16))
-#define NV50TCL_VTX_ATTR_4F_Z__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4F_W(x) (0x0000050c+((x)*16))
-#define NV50TCL_VTX_ATTR_4F_W__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_2I(x) (0x00000680+((x)*4))
-#define NV50TCL_VTX_ATTR_2I__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_2I_X_SHIFT 0
-#define NV50TCL_VTX_ATTR_2I_X_MASK 0x0000ffff
-#define NV50TCL_VTX_ATTR_2I_Y_SHIFT 16
-#define NV50TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
-#define NV50TCL_VTX_ATTR_4I_0(x) (0x00000700+((x)*8))
-#define NV50TCL_VTX_ATTR_4I_0__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4I_0_X_SHIFT 0
-#define NV50TCL_VTX_ATTR_4I_0_X_MASK 0x0000ffff
-#define NV50TCL_VTX_ATTR_4I_0_Y_SHIFT 16
-#define NV50TCL_VTX_ATTR_4I_0_Y_MASK 0xffff0000
-#define NV50TCL_VTX_ATTR_4I_1(x) (0x00000704+((x)*8))
-#define NV50TCL_VTX_ATTR_4I_1__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4I_1_Z_SHIFT 0
-#define NV50TCL_VTX_ATTR_4I_1_Z_MASK 0x0000ffff
-#define NV50TCL_VTX_ATTR_4I_1_W_SHIFT 16
-#define NV50TCL_VTX_ATTR_4I_1_W_MASK 0xffff0000
-#define NV50TCL_VTX_ATTR_4NI_0(x) (0x00000780+((x)*8))
-#define NV50TCL_VTX_ATTR_4NI_0__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4NI_0_X_SHIFT 0
-#define NV50TCL_VTX_ATTR_4NI_0_X_MASK 0x0000ffff
-#define NV50TCL_VTX_ATTR_4NI_0_Y_SHIFT 16
-#define NV50TCL_VTX_ATTR_4NI_0_Y_MASK 0xffff0000
-#define NV50TCL_VTX_ATTR_4NI_1(x) (0x00000784+((x)*8))
-#define NV50TCL_VTX_ATTR_4NI_1__SIZE 0x00000010
-#define NV50TCL_VTX_ATTR_4NI_1_Z_SHIFT 0
-#define NV50TCL_VTX_ATTR_4NI_1_Z_MASK 0x0000ffff
-#define NV50TCL_VTX_ATTR_4NI_1_W_SHIFT 16
-#define NV50TCL_VTX_ATTR_4NI_1_W_MASK 0xffff0000
-#define NV50TCL_VERTEX_ARRAY_FORMAT(x) (0x00000900+((x)*16))
-#define NV50TCL_VERTEX_ARRAY_FORMAT__SIZE 0x00000010
-#define NV50TCL_VIEWPORT_UNK0(x) (0x00000a00+((x)*4))
-#define NV50TCL_VIEWPORT_UNK0__SIZE 0x00000003
-#define NV50TCL_VIEWPORT_UNK1(x) (0x00000a0c+((x)*4))
-#define NV50TCL_VIEWPORT_UNK1__SIZE 0x00000003
-#define NV50TCL_VIEWPORT_HORIZ 0x00000c00
-#define NV50TCL_VIEWPORT_HORIZ_X_SHIFT 0
-#define NV50TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff
-#define NV50TCL_VIEWPORT_HORIZ_W_SHIFT 16
-#define NV50TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000
-#define NV50TCL_VIEWPORT_VERT 0x00000c04
-#define NV50TCL_VIEWPORT_VERT_Y_SHIFT 0
-#define NV50TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff
-#define NV50TCL_VIEWPORT_VERT_H_SHIFT 16
-#define NV50TCL_VIEWPORT_VERT_H_MASK 0xffff0000
-#define NV50TCL_DEPTH_RANGE_NEAR 0x00000c08
-#define NV50TCL_DEPTH_RANGE_FAR 0x00000c0c
-#define NV50TCL_VIEWPORT_CLIP_HORIZ(x) (0x00000d00+((x)*8))
-#define NV50TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008
-#define NV50TCL_VIEWPORT_CLIP_VERT(x) (0x00000d04+((x)*8))
-#define NV50TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008
-#define NV50TCL_VERTEX_BUFFER_FIRST 0x00000d74
-#define NV50TCL_VERTEX_BUFFER_COUNT 0x00000d78
-#define NV50TCL_CLEAR_COLOR(x) (0x00000d80+((x)*4))
-#define NV50TCL_CLEAR_COLOR__SIZE 0x00000004
-#define NV50TCL_CLEAR_DEPTH 0x00000d90
-#define NV50TCL_CLEAR_STENCIL 0x00000da0
-#define NV50TCL_POLYGON_MODE_FRONT 0x00000dac
-#define NV50TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
-#define NV50TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
-#define NV50TCL_POLYGON_MODE_FRONT_FILL 0x00001b02
-#define NV50TCL_POLYGON_MODE_BACK 0x00000db0
-#define NV50TCL_POLYGON_MODE_BACK_POINT 0x00001b00
-#define NV50TCL_POLYGON_MODE_BACK_LINE 0x00001b01
-#define NV50TCL_POLYGON_MODE_BACK_FILL 0x00001b02
-#define NV50TCL_POLYGON_SMOOTH_ENABLE 0x00000db4
-#define NV50TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0
-#define NV50TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4
-#define NV50TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8
-#define NV50TCL_SCISSOR_HORIZ 0x00000e04
-#define NV50TCL_SCISSOR_HORIZ_L_SHIFT 0
-#define NV50TCL_SCISSOR_HORIZ_L_MASK 0x0000ffff
-#define NV50TCL_SCISSOR_HORIZ_R_SHIFT 16
-#define NV50TCL_SCISSOR_HORIZ_R_MASK 0xffff0000
-#define NV50TCL_SCISSOR_VERT 0x00000e08
-#define NV50TCL_SCISSOR_VERT_T_SHIFT 0
-#define NV50TCL_SCISSOR_VERT_T_MASK 0x0000ffff
-#define NV50TCL_SCISSOR_VERT_B_SHIFT 16
-#define NV50TCL_SCISSOR_VERT_B_MASK 0xffff0000
-#define NV50TCL_CB_ADDR 0x00000f00
-#define NV50TCL_CB_ADDR_ID_SHIFT 8
-#define NV50TCL_CB_ADDR_ID_MASK 0xffffff00
-#define NV50TCL_CB_ADDR_BUFFER_SHIFT 0
-#define NV50TCL_CB_ADDR_BUFFER_MASK 0x000000ff
-#define NV50TCL_CB_DATA(x) (0x00000f04+((x)*4))
-#define NV50TCL_CB_DATA__SIZE 0x00000010
-#define NV50TCL_STENCIL_FRONT_FUNC_REF 0x00000f54
-#define NV50TCL_STENCIL_FRONT_MASK 0x00000f58
-#define NV50TCL_STENCIL_FRONT_FUNC_MASK 0x00000f5c
-#define NV50TCL_GP_ADDRESS_HIGH 0x00000f70
-#define NV50TCL_GP_ADDRESS_LOW 0x00000f74
-#define NV50TCL_VP_ADDRESS_HIGH 0x00000f7c
-#define NV50TCL_VP_ADDRESS_LOW 0x00000f80
-#define NV50TCL_FP_ADDRESS_HIGH 0x00000fa4
-#define NV50TCL_FP_ADDRESS_LOW 0x00000fa8
-#define NV50TCL_ZETA_ADDRESS_HIGH 0x00000fe0
-#define NV50TCL_ZETA_ADDRESS_LOW 0x00000fe4
-#define NV50TCL_UNKFF4 0x00000ff4
-#define NV50TCL_UNKFF4_W_SHIFT 16
-#define NV50TCL_UNKFF4_W_MASK 0xffff0000
-#define NV50TCL_UNKFF8 0x00000ff8
-#define NV50TCL_UNKFF8_H_SHIFT 16
-#define NV50TCL_UNKFF8_H_MASK 0xffff0000
-#define NV50TCL_RT_HORIZ(x) (0x00001240+((x)*8))
-#define NV50TCL_RT_HORIZ__SIZE 0x00000008
-#define NV50TCL_RT_VERT(x) (0x00001244+((x)*8))
-#define NV50TCL_RT_VERT__SIZE 0x00000008
-#define NV50TCL_CB_DEF_ADDRESS_HIGH 0x00001280
-#define NV50TCL_CB_DEF_ADDRESS_LOW 0x00001284
-#define NV50TCL_CB_DEF_SET 0x00001288
-#define NV50TCL_CB_DEF_SET_SIZE_SHIFT 0
-#define NV50TCL_CB_DEF_SET_SIZE_MASK 0x0000ffff
-#define NV50TCL_CB_DEF_SET_BUFFER_SHIFT 16
-#define NV50TCL_CB_DEF_SET_BUFFER_MASK 0xffff0000
-#define NV50TCL_DEPTH_TEST_ENABLE 0x000012cc
-#define NV50TCL_SHADE_MODEL 0x000012d4
-#define NV50TCL_SHADE_MODEL_FLAT 0x00001d00
-#define NV50TCL_SHADE_MODEL_SMOOTH 0x00001d01
-#define NV50TCL_DEPTH_WRITE_ENABLE 0x000012e8
-#define NV50TCL_ALPHA_TEST_ENABLE 0x000012ec
-#define NV50TCL_DEPTH_TEST_FUNC 0x0000130c
-#define NV50TCL_DEPTH_TEST_FUNC_NEVER 0x00000200
-#define NV50TCL_DEPTH_TEST_FUNC_LESS 0x00000201
-#define NV50TCL_DEPTH_TEST_FUNC_EQUAL 0x00000202
-#define NV50TCL_DEPTH_TEST_FUNC_LEQUAL 0x00000203
-#define NV50TCL_DEPTH_TEST_FUNC_GREATER 0x00000204
-#define NV50TCL_DEPTH_TEST_FUNC_GREATER 0x00000204
-#define NV50TCL_DEPTH_TEST_FUNC_NOTEQUAL 0x00000205
-#define NV50TCL_DEPTH_TEST_FUNC_GEQUAL 0x00000206
-#define NV50TCL_DEPTH_TEST_FUNC_ALWAYS 0x00000207
-#define NV50TCL_ALPHA_TEST_REF 0x00001310
-#define NV50TCL_ALPHA_TEST_FUNC 0x00001314
-#define NV50TCL_ALPHA_TEST_FUNC_NEVER 0x00000200
-#define NV50TCL_ALPHA_TEST_FUNC_LESS 0x00000201
-#define NV50TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202
-#define NV50TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203
-#define NV50TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
-#define NV50TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
-#define NV50TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205
-#define NV50TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206
-#define NV50TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207
-#define NV50TCL_BLEND_COLOR(x) (0x0000131c+((x)*4))
-#define NV50TCL_BLEND_COLOR__SIZE 0x00000004
-#define NV50TCL_BLEND_EQUATION_RGB 0x00001340
-#define NV50TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006
-#define NV50TCL_BLEND_EQUATION_RGB_MIN 0x00008007
-#define NV50TCL_BLEND_EQUATION_RGB_MAX 0x00008008
-#define NV50TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a
-#define NV50TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b
-#define NV50TCL_BLEND_FUNC_SRC_RGB 0x00001344
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00000000
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE 0x00000001
-#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV50TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV50TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307
-#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308
-#define NV50TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV50TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003
-#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV50TCL_BLEND_FUNC_DST_RGB 0x00001348
-#define NV50TCL_BLEND_FUNC_DST_RGB_ZERO 0x00000000
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE 0x00000001
-#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV50TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV50TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307
-#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308
-#define NV50TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV50TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003
-#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV50TCL_BLEND_EQUATION_ALPHA 0x0000134c
-#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_ADD 0x00008006
-#define NV50TCL_BLEND_EQUATION_ALPHA_MIN 0x00008007
-#define NV50TCL_BLEND_EQUATION_ALPHA_MAX 0x00008008
-#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x0000800a
-#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x0000800b
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA 0x00001350
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00000001
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x00000300
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x00000302
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x00000304
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x00000306
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x00000307
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x00000308
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x00008001
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x00008003
-#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV50TCL_BLEND_FUNC_DST_ALPHA 0x00001358
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00000001
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x00000300
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x00000301
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x00000302
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x00000303
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x00000304
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x00000305
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x00000306
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x00000307
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x00000308
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x00008001
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x00008002
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x00008003
-#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x00008004
-#define NV50TCL_BLEND_ENABLE(x) (0x00001360+((x)*4))
-#define NV50TCL_BLEND_ENABLE__SIZE 0x00000008
-#define NV50TCL_STENCIL_BACK_ENABLE 0x00001380
-#define NV50TCL_STENCIL_BACK_OP_FAIL 0x00001384
-#define NV50TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000
-#define NV50TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a
-#define NV50TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00
-#define NV50TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01
-#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02
-#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03
-#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507
-#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL 0x00001388
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV50TCL_STENCIL_BACK_OP_ZPASS 0x0000138c
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC 0x00001390
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
-#define NV50TCL_STENCIL_BACK_FUNC_REF 0x00001394
-#define NV50TCL_STENCIL_BACK_MASK 0x00001398
-#define NV50TCL_STENCIL_BACK_FUNC_MASK 0x0000139c
-#define NV50TCL_LINE_WIDTH 0x000013b0
-#define NV50TCL_VP_START_ID 0x0000140c
-#define NV50TCL_GP_START_ID 0x00001410
-#define NV50TCL_FP_START_ID 0x00001414
-#define NV50TCL_POINT_SIZE 0x00001518
-#define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c
-#define NV50TCL_TSC_ADDRESS_LOW 0x00001560
-#define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c
-#define NV50TCL_LINE_SMOOTH_ENABLE 0x00001570
-#define NV50TCL_TIC_ADDRESS_HIGH 0x00001574
-#define NV50TCL_TIC_ADDRESS_LOW 0x00001578
-#define NV50TCL_STENCIL_FRONT_ENABLE 0x00001594
-#define NV50TCL_STENCIL_FRONT_OP_FAIL 0x00001598
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507
-#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL 0x0000159c
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS 0x000015a0
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC 0x000015a4
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
-#define NV50TCL_POLYGON_OFFSET_UNITS 0x000015bc
-#define NV50TCL_VERTEX_BEGIN 0x000015dc
-#define NV50TCL_VERTEX_BEGIN_POINTS 0x00000000
-#define NV50TCL_VERTEX_BEGIN_LINES 0x00000001
-#define NV50TCL_VERTEX_BEGIN_LINE_LOOP 0x00000002
-#define NV50TCL_VERTEX_BEGIN_LINE_STRIP 0x00000003
-#define NV50TCL_VERTEX_BEGIN_TRIANGLES 0x00000004
-#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP 0x00000005
-#define NV50TCL_VERTEX_BEGIN_TRIANGLE_FAN 0x00000006
-#define NV50TCL_VERTEX_BEGIN_QUADS 0x00000007
-#define NV50TCL_VERTEX_BEGIN_QUAD_STRIP 0x00000008
-#define NV50TCL_VERTEX_BEGIN_POLYGON 0x00000009
-#define NV50TCL_VERTEX_END 0x000015e0
-#define NV50TCL_VERTEX_DATA 0x00001640
-#define NV50TCL_VP_ATTR_EN_0 0x00001650
-#define NV50TCL_VP_ATTR_EN_0_7_SHIFT 28
-#define NV50TCL_VP_ATTR_EN_0_7_MASK 0xf0000000
-#define NV50TCL_VP_ATTR_EN_0_7_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_7_XNNN 0x10000000
-#define NV50TCL_VP_ATTR_EN_0_7_NYNN 0x20000000
-#define NV50TCL_VP_ATTR_EN_0_7_XYNN 0x30000000
-#define NV50TCL_VP_ATTR_EN_0_7_NNZN 0x40000000
-#define NV50TCL_VP_ATTR_EN_0_7_XNZN 0x50000000
-#define NV50TCL_VP_ATTR_EN_0_7_NYZN 0x60000000
-#define NV50TCL_VP_ATTR_EN_0_7_XYZN 0x70000000
-#define NV50TCL_VP_ATTR_EN_0_7_NNNW 0x80000000
-#define NV50TCL_VP_ATTR_EN_0_7_XNNW 0x90000000
-#define NV50TCL_VP_ATTR_EN_0_7_NYNW 0xa0000000
-#define NV50TCL_VP_ATTR_EN_0_7_XYNW 0xb0000000
-#define NV50TCL_VP_ATTR_EN_0_7_NNZW 0xc0000000
-#define NV50TCL_VP_ATTR_EN_0_7_XNZW 0xd0000000
-#define NV50TCL_VP_ATTR_EN_0_7_NYZW 0xe0000000
-#define NV50TCL_VP_ATTR_EN_0_7_XYZW 0xf0000000
-#define NV50TCL_VP_ATTR_EN_0_6_SHIFT 24
-#define NV50TCL_VP_ATTR_EN_0_6_MASK 0x0f000000
-#define NV50TCL_VP_ATTR_EN_0_6_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_6_XNNN 0x01000000
-#define NV50TCL_VP_ATTR_EN_0_6_NYNN 0x02000000
-#define NV50TCL_VP_ATTR_EN_0_6_XYNN 0x03000000
-#define NV50TCL_VP_ATTR_EN_0_6_NNZN 0x04000000
-#define NV50TCL_VP_ATTR_EN_0_6_XNZN 0x05000000
-#define NV50TCL_VP_ATTR_EN_0_6_NYZN 0x06000000
-#define NV50TCL_VP_ATTR_EN_0_6_XYZN 0x07000000
-#define NV50TCL_VP_ATTR_EN_0_6_NNNW 0x08000000
-#define NV50TCL_VP_ATTR_EN_0_6_XNNW 0x09000000
-#define NV50TCL_VP_ATTR_EN_0_6_NYNW 0x0a000000
-#define NV50TCL_VP_ATTR_EN_0_6_XYNW 0x0b000000
-#define NV50TCL_VP_ATTR_EN_0_6_NNZW 0x0c000000
-#define NV50TCL_VP_ATTR_EN_0_6_XNZW 0x0d000000
-#define NV50TCL_VP_ATTR_EN_0_6_NYZW 0x0e000000
-#define NV50TCL_VP_ATTR_EN_0_6_XYZW 0x0f000000
-#define NV50TCL_VP_ATTR_EN_0_5_SHIFT 20
-#define NV50TCL_VP_ATTR_EN_0_5_MASK 0x00f00000
-#define NV50TCL_VP_ATTR_EN_0_5_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_5_XNNN 0x00100000
-#define NV50TCL_VP_ATTR_EN_0_5_NYNN 0x00200000
-#define NV50TCL_VP_ATTR_EN_0_5_XYNN 0x00300000
-#define NV50TCL_VP_ATTR_EN_0_5_NNZN 0x00400000
-#define NV50TCL_VP_ATTR_EN_0_5_XNZN 0x00500000
-#define NV50TCL_VP_ATTR_EN_0_5_NYZN 0x00600000
-#define NV50TCL_VP_ATTR_EN_0_5_XYZN 0x00700000
-#define NV50TCL_VP_ATTR_EN_0_5_NNNW 0x00800000
-#define NV50TCL_VP_ATTR_EN_0_5_XNNW 0x00900000
-#define NV50TCL_VP_ATTR_EN_0_5_NYNW 0x00a00000
-#define NV50TCL_VP_ATTR_EN_0_5_XYNW 0x00b00000
-#define NV50TCL_VP_ATTR_EN_0_5_NNZW 0x00c00000
-#define NV50TCL_VP_ATTR_EN_0_5_XNZW 0x00d00000
-#define NV50TCL_VP_ATTR_EN_0_5_NYZW 0x00e00000
-#define NV50TCL_VP_ATTR_EN_0_5_XYZW 0x00f00000
-#define NV50TCL_VP_ATTR_EN_0_4_SHIFT 16
-#define NV50TCL_VP_ATTR_EN_0_4_MASK 0x000f0000
-#define NV50TCL_VP_ATTR_EN_0_4_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_4_XNNN 0x00010000
-#define NV50TCL_VP_ATTR_EN_0_4_NYNN 0x00020000
-#define NV50TCL_VP_ATTR_EN_0_4_XYNN 0x00030000
-#define NV50TCL_VP_ATTR_EN_0_4_NNZN 0x00040000
-#define NV50TCL_VP_ATTR_EN_0_4_XNZN 0x00050000
-#define NV50TCL_VP_ATTR_EN_0_4_NYZN 0x00060000
-#define NV50TCL_VP_ATTR_EN_0_4_XYZN 0x00070000
-#define NV50TCL_VP_ATTR_EN_0_4_NNNW 0x00080000
-#define NV50TCL_VP_ATTR_EN_0_4_XNNW 0x00090000
-#define NV50TCL_VP_ATTR_EN_0_4_NYNW 0x000a0000
-#define NV50TCL_VP_ATTR_EN_0_4_XYNW 0x000b0000
-#define NV50TCL_VP_ATTR_EN_0_4_NNZW 0x000c0000
-#define NV50TCL_VP_ATTR_EN_0_4_XNZW 0x000d0000
-#define NV50TCL_VP_ATTR_EN_0_4_NYZW 0x000e0000
-#define NV50TCL_VP_ATTR_EN_0_4_XYZW 0x000f0000
-#define NV50TCL_VP_ATTR_EN_0_3_SHIFT 12
-#define NV50TCL_VP_ATTR_EN_0_3_MASK 0x0000f000
-#define NV50TCL_VP_ATTR_EN_0_3_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_3_XNNN 0x00001000
-#define NV50TCL_VP_ATTR_EN_0_3_NYNN 0x00002000
-#define NV50TCL_VP_ATTR_EN_0_3_XYNN 0x00003000
-#define NV50TCL_VP_ATTR_EN_0_3_NNZN 0x00004000
-#define NV50TCL_VP_ATTR_EN_0_3_XNZN 0x00005000
-#define NV50TCL_VP_ATTR_EN_0_3_NYZN 0x00006000
-#define NV50TCL_VP_ATTR_EN_0_3_XYZN 0x00007000
-#define NV50TCL_VP_ATTR_EN_0_3_NNNW 0x00008000
-#define NV50TCL_VP_ATTR_EN_0_3_XNNW 0x00009000
-#define NV50TCL_VP_ATTR_EN_0_3_NYNW 0x0000a000
-#define NV50TCL_VP_ATTR_EN_0_3_XYNW 0x0000b000
-#define NV50TCL_VP_ATTR_EN_0_3_NNZW 0x0000c000
-#define NV50TCL_VP_ATTR_EN_0_3_XNZW 0x0000d000
-#define NV50TCL_VP_ATTR_EN_0_3_NYZW 0x0000e000
-#define NV50TCL_VP_ATTR_EN_0_3_XYZW 0x0000f000
-#define NV50TCL_VP_ATTR_EN_0_2_SHIFT 8
-#define NV50TCL_VP_ATTR_EN_0_2_MASK 0x00000f00
-#define NV50TCL_VP_ATTR_EN_0_2_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_2_XNNN 0x00000100
-#define NV50TCL_VP_ATTR_EN_0_2_NYNN 0x00000200
-#define NV50TCL_VP_ATTR_EN_0_2_XYNN 0x00000300
-#define NV50TCL_VP_ATTR_EN_0_2_NNZN 0x00000400
-#define NV50TCL_VP_ATTR_EN_0_2_XNZN 0x00000500
-#define NV50TCL_VP_ATTR_EN_0_2_NYZN 0x00000600
-#define NV50TCL_VP_ATTR_EN_0_2_XYZN 0x00000700
-#define NV50TCL_VP_ATTR_EN_0_2_NNNW 0x00000800
-#define NV50TCL_VP_ATTR_EN_0_2_XNNW 0x00000900
-#define NV50TCL_VP_ATTR_EN_0_2_NYNW 0x00000a00
-#define NV50TCL_VP_ATTR_EN_0_2_XYNW 0x00000b00
-#define NV50TCL_VP_ATTR_EN_0_2_NNZW 0x00000c00
-#define NV50TCL_VP_ATTR_EN_0_2_XNZW 0x00000d00
-#define NV50TCL_VP_ATTR_EN_0_2_NYZW 0x00000e00
-#define NV50TCL_VP_ATTR_EN_0_2_XYZW 0x00000f00
-#define NV50TCL_VP_ATTR_EN_0_1_SHIFT 4
-#define NV50TCL_VP_ATTR_EN_0_1_MASK 0x000000f0
-#define NV50TCL_VP_ATTR_EN_0_1_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_1_XNNN 0x00000010
-#define NV50TCL_VP_ATTR_EN_0_1_NYNN 0x00000020
-#define NV50TCL_VP_ATTR_EN_0_1_XYNN 0x00000030
-#define NV50TCL_VP_ATTR_EN_0_1_NNZN 0x00000040
-#define NV50TCL_VP_ATTR_EN_0_1_XNZN 0x00000050
-#define NV50TCL_VP_ATTR_EN_0_1_NYZN 0x00000060
-#define NV50TCL_VP_ATTR_EN_0_1_XYZN 0x00000070
-#define NV50TCL_VP_ATTR_EN_0_1_NNNW 0x00000080
-#define NV50TCL_VP_ATTR_EN_0_1_XNNW 0x00000090
-#define NV50TCL_VP_ATTR_EN_0_1_NYNW 0x000000a0
-#define NV50TCL_VP_ATTR_EN_0_1_XYNW 0x000000b0
-#define NV50TCL_VP_ATTR_EN_0_1_NNZW 0x000000c0
-#define NV50TCL_VP_ATTR_EN_0_1_XNZW 0x000000d0
-#define NV50TCL_VP_ATTR_EN_0_1_NYZW 0x000000e0
-#define NV50TCL_VP_ATTR_EN_0_1_XYZW 0x000000f0
-#define NV50TCL_VP_ATTR_EN_0_0_SHIFT 0
-#define NV50TCL_VP_ATTR_EN_0_0_MASK 0x0000000f
-#define NV50TCL_VP_ATTR_EN_0_0_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_0_0_XNNN 0x00000001
-#define NV50TCL_VP_ATTR_EN_0_0_NYNN 0x00000002
-#define NV50TCL_VP_ATTR_EN_0_0_XYNN 0x00000003
-#define NV50TCL_VP_ATTR_EN_0_0_NNZN 0x00000004
-#define NV50TCL_VP_ATTR_EN_0_0_XNZN 0x00000005
-#define NV50TCL_VP_ATTR_EN_0_0_NYZN 0x00000006
-#define NV50TCL_VP_ATTR_EN_0_0_XYZN 0x00000007
-#define NV50TCL_VP_ATTR_EN_0_0_NNNW 0x00000008
-#define NV50TCL_VP_ATTR_EN_0_0_XNNW 0x00000009
-#define NV50TCL_VP_ATTR_EN_0_0_NYNW 0x0000000a
-#define NV50TCL_VP_ATTR_EN_0_0_XYNW 0x0000000b
-#define NV50TCL_VP_ATTR_EN_0_0_NNZW 0x0000000c
-#define NV50TCL_VP_ATTR_EN_0_0_XNZW 0x0000000d
-#define NV50TCL_VP_ATTR_EN_0_0_NYZW 0x0000000e
-#define NV50TCL_VP_ATTR_EN_0_0_XYZW 0x0000000f
-#define NV50TCL_VP_ATTR_EN_1 0x00001654
-#define NV50TCL_VP_ATTR_EN_1_15_SHIFT 28
-#define NV50TCL_VP_ATTR_EN_1_15_MASK 0xf0000000
-#define NV50TCL_VP_ATTR_EN_1_15_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_15_XNNN 0x10000000
-#define NV50TCL_VP_ATTR_EN_1_15_NYNN 0x20000000
-#define NV50TCL_VP_ATTR_EN_1_15_XYNN 0x30000000
-#define NV50TCL_VP_ATTR_EN_1_15_NNZN 0x40000000
-#define NV50TCL_VP_ATTR_EN_1_15_XNZN 0x50000000
-#define NV50TCL_VP_ATTR_EN_1_15_NYZN 0x60000000
-#define NV50TCL_VP_ATTR_EN_1_15_XYZN 0x70000000
-#define NV50TCL_VP_ATTR_EN_1_15_NNNW 0x80000000
-#define NV50TCL_VP_ATTR_EN_1_15_XNNW 0x90000000
-#define NV50TCL_VP_ATTR_EN_1_15_NYNW 0xa0000000
-#define NV50TCL_VP_ATTR_EN_1_15_XYNW 0xb0000000
-#define NV50TCL_VP_ATTR_EN_1_15_NNZW 0xc0000000
-#define NV50TCL_VP_ATTR_EN_1_15_XNZW 0xd0000000
-#define NV50TCL_VP_ATTR_EN_1_15_NYZW 0xe0000000
-#define NV50TCL_VP_ATTR_EN_1_15_XYZW 0xf0000000
-#define NV50TCL_VP_ATTR_EN_1_14_SHIFT 24
-#define NV50TCL_VP_ATTR_EN_1_14_MASK 0x0f000000
-#define NV50TCL_VP_ATTR_EN_1_14_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_14_XNNN 0x01000000
-#define NV50TCL_VP_ATTR_EN_1_14_NYNN 0x02000000
-#define NV50TCL_VP_ATTR_EN_1_14_XYNN 0x03000000
-#define NV50TCL_VP_ATTR_EN_1_14_NNZN 0x04000000
-#define NV50TCL_VP_ATTR_EN_1_14_XNZN 0x05000000
-#define NV50TCL_VP_ATTR_EN_1_14_NYZN 0x06000000
-#define NV50TCL_VP_ATTR_EN_1_14_XYZN 0x07000000
-#define NV50TCL_VP_ATTR_EN_1_14_NNNW 0x08000000
-#define NV50TCL_VP_ATTR_EN_1_14_XNNW 0x09000000
-#define NV50TCL_VP_ATTR_EN_1_14_NYNW 0x0a000000
-#define NV50TCL_VP_ATTR_EN_1_14_XYNW 0x0b000000
-#define NV50TCL_VP_ATTR_EN_1_14_NNZW 0x0c000000
-#define NV50TCL_VP_ATTR_EN_1_14_XNZW 0x0d000000
-#define NV50TCL_VP_ATTR_EN_1_14_NYZW 0x0e000000
-#define NV50TCL_VP_ATTR_EN_1_14_XYZW 0x0f000000
-#define NV50TCL_VP_ATTR_EN_1_13_SHIFT 20
-#define NV50TCL_VP_ATTR_EN_1_13_MASK 0x00f00000
-#define NV50TCL_VP_ATTR_EN_1_13_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_13_XNNN 0x00100000
-#define NV50TCL_VP_ATTR_EN_1_13_NYNN 0x00200000
-#define NV50TCL_VP_ATTR_EN_1_13_XYNN 0x00300000
-#define NV50TCL_VP_ATTR_EN_1_13_NNZN 0x00400000
-#define NV50TCL_VP_ATTR_EN_1_13_XNZN 0x00500000
-#define NV50TCL_VP_ATTR_EN_1_13_NYZN 0x00600000
-#define NV50TCL_VP_ATTR_EN_1_13_XYZN 0x00700000
-#define NV50TCL_VP_ATTR_EN_1_13_NNNW 0x00800000
-#define NV50TCL_VP_ATTR_EN_1_13_XNNW 0x00900000
-#define NV50TCL_VP_ATTR_EN_1_13_NYNW 0x00a00000
-#define NV50TCL_VP_ATTR_EN_1_13_XYNW 0x00b00000
-#define NV50TCL_VP_ATTR_EN_1_13_NNZW 0x00c00000
-#define NV50TCL_VP_ATTR_EN_1_13_XNZW 0x00d00000
-#define NV50TCL_VP_ATTR_EN_1_13_NYZW 0x00e00000
-#define NV50TCL_VP_ATTR_EN_1_13_XYZW 0x00f00000
-#define NV50TCL_VP_ATTR_EN_1_12_SHIFT 16
-#define NV50TCL_VP_ATTR_EN_1_12_MASK 0x000f0000
-#define NV50TCL_VP_ATTR_EN_1_12_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_12_XNNN 0x00010000
-#define NV50TCL_VP_ATTR_EN_1_12_NYNN 0x00020000
-#define NV50TCL_VP_ATTR_EN_1_12_XYNN 0x00030000
-#define NV50TCL_VP_ATTR_EN_1_12_NNZN 0x00040000
-#define NV50TCL_VP_ATTR_EN_1_12_XNZN 0x00050000
-#define NV50TCL_VP_ATTR_EN_1_12_NYZN 0x00060000
-#define NV50TCL_VP_ATTR_EN_1_12_XYZN 0x00070000
-#define NV50TCL_VP_ATTR_EN_1_12_NNNW 0x00080000
-#define NV50TCL_VP_ATTR_EN_1_12_XNNW 0x00090000
-#define NV50TCL_VP_ATTR_EN_1_12_NYNW 0x000a0000
-#define NV50TCL_VP_ATTR_EN_1_12_XYNW 0x000b0000
-#define NV50TCL_VP_ATTR_EN_1_12_NNZW 0x000c0000
-#define NV50TCL_VP_ATTR_EN_1_12_XNZW 0x000d0000
-#define NV50TCL_VP_ATTR_EN_1_12_NYZW 0x000e0000
-#define NV50TCL_VP_ATTR_EN_1_12_XYZW 0x000f0000
-#define NV50TCL_VP_ATTR_EN_1_11_SHIFT 12
-#define NV50TCL_VP_ATTR_EN_1_11_MASK 0x0000f000
-#define NV50TCL_VP_ATTR_EN_1_11_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_11_XNNN 0x00001000
-#define NV50TCL_VP_ATTR_EN_1_11_NYNN 0x00002000
-#define NV50TCL_VP_ATTR_EN_1_11_XYNN 0x00003000
-#define NV50TCL_VP_ATTR_EN_1_11_NNZN 0x00004000
-#define NV50TCL_VP_ATTR_EN_1_11_XNZN 0x00005000
-#define NV50TCL_VP_ATTR_EN_1_11_NYZN 0x00006000
-#define NV50TCL_VP_ATTR_EN_1_11_XYZN 0x00007000
-#define NV50TCL_VP_ATTR_EN_1_11_NNNW 0x00008000
-#define NV50TCL_VP_ATTR_EN_1_11_XNNW 0x00009000
-#define NV50TCL_VP_ATTR_EN_1_11_NYNW 0x0000a000
-#define NV50TCL_VP_ATTR_EN_1_11_XYNW 0x0000b000
-#define NV50TCL_VP_ATTR_EN_1_11_NNZW 0x0000c000
-#define NV50TCL_VP_ATTR_EN_1_11_XNZW 0x0000d000
-#define NV50TCL_VP_ATTR_EN_1_11_NYZW 0x0000e000
-#define NV50TCL_VP_ATTR_EN_1_11_XYZW 0x0000f000
-#define NV50TCL_VP_ATTR_EN_1_10_SHIFT 8
-#define NV50TCL_VP_ATTR_EN_1_10_MASK 0x00000f00
-#define NV50TCL_VP_ATTR_EN_1_10_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_10_XNNN 0x00000100
-#define NV50TCL_VP_ATTR_EN_1_10_NYNN 0x00000200
-#define NV50TCL_VP_ATTR_EN_1_10_XYNN 0x00000300
-#define NV50TCL_VP_ATTR_EN_1_10_NNZN 0x00000400
-#define NV50TCL_VP_ATTR_EN_1_10_XNZN 0x00000500
-#define NV50TCL_VP_ATTR_EN_1_10_NYZN 0x00000600
-#define NV50TCL_VP_ATTR_EN_1_10_XYZN 0x00000700
-#define NV50TCL_VP_ATTR_EN_1_10_NNNW 0x00000800
-#define NV50TCL_VP_ATTR_EN_1_10_XNNW 0x00000900
-#define NV50TCL_VP_ATTR_EN_1_10_NYNW 0x00000a00
-#define NV50TCL_VP_ATTR_EN_1_10_XYNW 0x00000b00
-#define NV50TCL_VP_ATTR_EN_1_10_NNZW 0x00000c00
-#define NV50TCL_VP_ATTR_EN_1_10_XNZW 0x00000d00
-#define NV50TCL_VP_ATTR_EN_1_10_NYZW 0x00000e00
-#define NV50TCL_VP_ATTR_EN_1_10_XYZW 0x00000f00
-#define NV50TCL_VP_ATTR_EN_1_9_SHIFT 4
-#define NV50TCL_VP_ATTR_EN_1_9_MASK 0x000000f0
-#define NV50TCL_VP_ATTR_EN_1_9_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_9_XNNN 0x00000010
-#define NV50TCL_VP_ATTR_EN_1_9_NYNN 0x00000020
-#define NV50TCL_VP_ATTR_EN_1_9_XYNN 0x00000030
-#define NV50TCL_VP_ATTR_EN_1_9_NNZN 0x00000040
-#define NV50TCL_VP_ATTR_EN_1_9_XNZN 0x00000050
-#define NV50TCL_VP_ATTR_EN_1_9_NYZN 0x00000060
-#define NV50TCL_VP_ATTR_EN_1_9_XYZN 0x00000070
-#define NV50TCL_VP_ATTR_EN_1_9_NNNW 0x00000080
-#define NV50TCL_VP_ATTR_EN_1_9_XNNW 0x00000090
-#define NV50TCL_VP_ATTR_EN_1_9_NYNW 0x000000a0
-#define NV50TCL_VP_ATTR_EN_1_9_XYNW 0x000000b0
-#define NV50TCL_VP_ATTR_EN_1_9_NNZW 0x000000c0
-#define NV50TCL_VP_ATTR_EN_1_9_XNZW 0x000000d0
-#define NV50TCL_VP_ATTR_EN_1_9_NYZW 0x000000e0
-#define NV50TCL_VP_ATTR_EN_1_9_XYZW 0x000000f0
-#define NV50TCL_VP_ATTR_EN_1_8_SHIFT 0
-#define NV50TCL_VP_ATTR_EN_1_8_MASK 0x0000000f
-#define NV50TCL_VP_ATTR_EN_1_8_NONE 0x00000000
-#define NV50TCL_VP_ATTR_EN_1_8_XNNN 0x00000001
-#define NV50TCL_VP_ATTR_EN_1_8_NYNN 0x00000002
-#define NV50TCL_VP_ATTR_EN_1_8_XYNN 0x00000003
-#define NV50TCL_VP_ATTR_EN_1_8_NNZN 0x00000004
-#define NV50TCL_VP_ATTR_EN_1_8_XNZN 0x00000005
-#define NV50TCL_VP_ATTR_EN_1_8_NYZN 0x00000006
-#define NV50TCL_VP_ATTR_EN_1_8_XYZN 0x00000007
-#define NV50TCL_VP_ATTR_EN_1_8_NNNW 0x00000008
-#define NV50TCL_VP_ATTR_EN_1_8_XNNW 0x00000009
-#define NV50TCL_VP_ATTR_EN_1_8_NYNW 0x0000000a
-#define NV50TCL_VP_ATTR_EN_1_8_XYNW 0x0000000b
-#define NV50TCL_VP_ATTR_EN_1_8_NNZW 0x0000000c
-#define NV50TCL_VP_ATTR_EN_1_8_XNZW 0x0000000d
-#define NV50TCL_VP_ATTR_EN_1_8_NYZW 0x0000000e
-#define NV50TCL_VP_ATTR_EN_1_8_XYZW 0x0000000f
-#define NV50TCL_LINE_STIPPLE_ENABLE 0x0000166c
-#define NV50TCL_LINE_STIPPLE_PATTERN 0x00001680
-#define NV50TCL_POLYGON_STIPPLE_ENABLE 0x0000168c
-#define NV50TCL_VP_REG_HPOS 0x000016bc
-#define NV50TCL_VP_REG_HPOS_X_SHIFT 0
-#define NV50TCL_VP_REG_HPOS_X_MASK 0x000000ff
-#define NV50TCL_VP_REG_HPOS_Y_SHIFT 8
-#define NV50TCL_VP_REG_HPOS_Y_MASK 0x0000ff00
-#define NV50TCL_VP_REG_HPOS_Z_SHIFT 16
-#define NV50TCL_VP_REG_HPOS_Z_MASK 0x00ff0000
-#define NV50TCL_VP_REG_HPOS_W_SHIFT 24
-#define NV50TCL_VP_REG_HPOS_W_MASK 0xff000000
-#define NV50TCL_VP_REG_COL0 0x000016c0
-#define NV50TCL_VP_REG_COL0_X_SHIFT 0
-#define NV50TCL_VP_REG_COL0_X_MASK 0x000000ff
-#define NV50TCL_VP_REG_COL0_Y_SHIFT 8
-#define NV50TCL_VP_REG_COL0_Y_MASK 0x0000ff00
-#define NV50TCL_VP_REG_COL0_Z_SHIFT 16
-#define NV50TCL_VP_REG_COL0_Z_MASK 0x00ff0000
-#define NV50TCL_VP_REG_COL0_W_SHIFT 24
-#define NV50TCL_VP_REG_COL0_W_MASK 0xff000000
-#define NV50TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001700+((x)*4))
-#define NV50TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020
-#define NV50TCL_CULL_FACE_ENABLE 0x00001918
-#define NV50TCL_FRONT_FACE 0x0000191c
-#define NV50TCL_FRONT_FACE_CW 0x00000900
-#define NV50TCL_FRONT_FACE_CCW 0x00000901
-#define NV50TCL_CULL_FACE 0x00001920
-#define NV50TCL_CULL_FACE_FRONT 0x00000404
-#define NV50TCL_CULL_FACE_BACK 0x00000405
-#define NV50TCL_CULL_FACE_FRONT_AND_BACK 0x00000408
-#define NV50TCL_LOGIC_OP_ENABLE 0x000019c4
-#define NV50TCL_LOGIC_OP 0x000019c8
-#define NV50TCL_LOGIC_OP_CLEAR 0x00001500
-#define NV50TCL_LOGIC_OP_AND 0x00001501
-#define NV50TCL_LOGIC_OP_AND_REVERSE 0x00001502
-#define NV50TCL_LOGIC_OP_COPY 0x00001503
-#define NV50TCL_LOGIC_OP_AND_INVERTED 0x00001504
-#define NV50TCL_LOGIC_OP_NOOP 0x00001505
-#define NV50TCL_LOGIC_OP_XOR 0x00001506
-#define NV50TCL_LOGIC_OP_OR 0x00001507
-#define NV50TCL_LOGIC_OP_NOR 0x00001508
-#define NV50TCL_LOGIC_OP_EQUIV 0x00001509
-#define NV50TCL_LOGIC_OP_INVERT 0x0000150a
-#define NV50TCL_LOGIC_OP_OR_REVERSE 0x0000150b
-#define NV50TCL_LOGIC_OP_COPY_INVERTED 0x0000150c
-#define NV50TCL_LOGIC_OP_OR_INVERTED 0x0000150d
-#define NV50TCL_LOGIC_OP_NAND 0x0000150e
-#define NV50TCL_LOGIC_OP_SET 0x0000150f
-#define NV50TCL_CLEAR_BUFFERS 0x000019d0
-#define NV50TCL_COLOR_MASK(x) (0x00001a00+((x)*4))
-#define NV50TCL_COLOR_MASK__SIZE 0x00000008
-#define NV50TCL_COLOR_MASK_R_SHIFT 0
-#define NV50TCL_COLOR_MASK_R_MASK 0x0000000f
-#define NV50TCL_COLOR_MASK_G_SHIFT 4
-#define NV50TCL_COLOR_MASK_G_MASK 0x000000f0
-#define NV50TCL_COLOR_MASK_B_SHIFT 8
-#define NV50TCL_COLOR_MASK_B_MASK 0x00000f00
-#define NV50TCL_COLOR_MASK_A_SHIFT 12
-#define NV50TCL_COLOR_MASK_A_MASK 0x0000f000
-
-
-#define NV50_COMPUTE 0x000050c0
-
-#define NV50_COMPUTE_DMA_UNK0 0x000001a0
-#define NV50_COMPUTE_DMA_STATUS 0x000001a4
-#define NV50_COMPUTE_DMA_UNK1 0x000001b8
-#define NV50_COMPUTE_DMA_UNK2 0x000001bc
-#define NV50_COMPUTE_DMA_UNK3 0x000001c0
-#define NV50_COMPUTE_UNK4_HIGH 0x00000210
-#define NV50_COMPUTE_UNK4_LOW 0x00000214
-#define NV50_COMPUTE_UNK5_HIGH 0x00000218
-#define NV50_COMPUTE_UNK5_LOW 0x0000021c
-#define NV50_COMPUTE_UNK6_HIGH 0x00000294
-#define NV50_COMPUTE_UNK6_LOW 0x00000298
-#define NV50_COMPUTE_CONST_BASE_HIGH 0x000002a4
-#define NV50_COMPUTE_CONST_BASE_LO 0x000002a8
-#define NV50_COMPUTE_CONST_SIZE_SEG 0x000002ac
-#define NV50_COMPUTE_REG_COUNT 0x000002c0
-#define NV50_COMPUTE_STATUS_HIGH 0x00000310
-#define NV50_COMPUTE_STATUS_LOW 0x00000314
-#define NV50_COMPUTE_EXECUTE 0x0000031c
-#define NV50_COMPUTE_USER_PARAM_COUNT 0x00000374
-#define NV50_COMPUTE_GRIDDIM_YX 0x000003a4
-#define NV50_COMPUTE_SHARED_SIZE 0x000003a8
-#define NV50_COMPUTE_BLOCKDIM_YX 0x000003ac
-#define NV50_COMPUTE_BLOCKDIM_Z 0x000003b0
-#define NV50_COMPUTE_CALL_ADDRESS 0x000003b4
-#define NV50_COMPUTE_GLOBAL_BASE_HIGH(x) (0x00000400+((x)*32))
-#define NV50_COMPUTE_GLOBAL_BASE_HIGH__SIZE 0x00000010
-#define NV50_COMPUTE_GLOBAL_BASE_LOW(x) (0x00000404+((x)*32))
-#define NV50_COMPUTE_GLOBAL_BASE_LOW__SIZE 0x00000010
-#define NV50_COMPUTE_GLOBAL_LIMIT_HIGH(x) (0x00000408+((x)*32))
-#define NV50_COMPUTE_GLOBAL_LIMIT_HIGH__SIZE 0x00000010
-#define NV50_COMPUTE_GLOBAL_LIMIT_LOW(x) (0x0000040c+((x)*32))
-#define NV50_COMPUTE_GLOBAL_LIMIT_LOW__SIZE 0x00000010
-#define NV50_COMPUTE_GLOBAL_UNK(x) (0x00000410+((x)*32))
-#define NV50_COMPUTE_GLOBAL_UNK__SIZE 0x00000010
-#define NV50_COMPUTE_USER_PARAM(x) (0x00000600+((x)*4))
-#define NV50_COMPUTE_USER_PARAM__SIZE 0x00000040
-
-
-#define NV54TCL 0x00008297
-
-
-
-#endif /* NOUVEAU_REG_H */
diff --git a/src/gallium/drivers/nouveau/nouveau_device.h b/src/gallium/drivers/nouveau/nouveau_device.h
deleted file mode 100644
index e25e89fedd..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_device.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_DEVICE_H__
-#define __NOUVEAU_DEVICE_H__
-
-struct nouveau_device {
- unsigned chipset;
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_grobj.h b/src/gallium/drivers/nouveau/nouveau_grobj.h
deleted file mode 100644
index 8f5abf9051..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_grobj.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_GROBJ_H__
-#define __NOUVEAU_GROBJ_H__
-
-#include "nouveau_channel.h"
-
-struct nouveau_grobj {
- struct nouveau_channel *channel;
- int grclass;
- uint32_t handle;
- int subc;
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_notifier.h b/src/gallium/drivers/nouveau/nouveau_notifier.h
deleted file mode 100644
index 35adde1e32..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_notifier.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_NOTIFIER_H__
-#define __NOUVEAU_NOTIFIER_H__
-
-#define NV_NOTIFIER_SIZE 32
-#define NV_NOTIFY_TIME_0 0x00000000
-#define NV_NOTIFY_TIME_1 0x00000004
-#define NV_NOTIFY_RETURN_VALUE 0x00000008
-#define NV_NOTIFY_STATE 0x0000000C
-#define NV_NOTIFY_STATE_STATUS_MASK 0xFF000000
-#define NV_NOTIFY_STATE_STATUS_SHIFT 24
-#define NV_NOTIFY_STATE_STATUS_COMPLETED 0x00
-#define NV_NOTIFY_STATE_STATUS_IN_PROCESS 0x01
-#define NV_NOTIFY_STATE_ERROR_CODE_MASK 0x0000FFFF
-#define NV_NOTIFY_STATE_ERROR_CODE_SHIFT 0
-
-struct nouveau_notifier {
- struct nouveau_channel *channel;
- uint32_t handle;
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_pushbuf.h b/src/gallium/drivers/nouveau/nouveau_pushbuf.h
deleted file mode 100644
index 1909765098..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_pushbuf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_PUSHBUF_H__
-#define __NOUVEAU_PUSHBUF_H__
-
-struct nouveau_pushbuf {
- struct nouveau_channel *channel;
- unsigned remaining;
- uint32_t *cur;
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_resource.h b/src/gallium/drivers/nouveau/nouveau_resource.h
deleted file mode 100644
index 1af7961d30..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_resource.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2007 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_RESOURCE_H__
-#define __NOUVEAU_RESOURCE_H__
-
-struct nouveau_resource {
- struct nouveau_resource *prev;
- struct nouveau_resource *next;
-
- int in_use;
- void *priv;
-
- unsigned int start;
- unsigned int size;
-};
-
-#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_stateobj.h b/src/gallium/drivers/nouveau/nouveau_stateobj.h
index 729988b095..4ae4ff4940 100644
--- a/src/gallium/drivers/nouveau/nouveau_stateobj.h
+++ b/src/gallium/drivers/nouveau/nouveau_stateobj.h
@@ -147,8 +147,9 @@ so_emit_reloc_markers(struct nouveau_winsys *nvws, struct nouveau_stateobj *so)
struct nouveau_stateobj_reloc *r = &so->reloc[i];
nvws->push_reloc(nvws, pb->cur++, r->bo, r->packet,
- (r->flags &
- (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)) |
+ (r->flags & (NOUVEAU_BO_VRAM |
+ NOUVEAU_BO_GART |
+ NOUVEAU_BO_RDWR)) |
NOUVEAU_BO_DUMMY, 0, 0);
nvws->push_reloc(nvws, pb->cur++, r->bo, r->data,
r->flags | NOUVEAU_BO_DUMMY, r->vor, r->tor);
diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h
index 25e0b05be1..b86c4b9338 100644
--- a/src/gallium/drivers/nouveau/nouveau_winsys.h
+++ b/src/gallium/drivers/nouveau/nouveau_winsys.h
@@ -50,13 +50,15 @@ struct nouveau_winsys {
uint32_t (*notifier_status)(struct nouveau_notifier *, int id);
uint32_t (*notifier_retval)(struct nouveau_notifier *, int id);
int (*notifier_wait)(struct nouveau_notifier *, int id,
- int status, int timeout);
+ int status, double timeout);
int (*surface_copy)(struct nouveau_winsys *, struct pipe_surface *,
unsigned, unsigned, struct pipe_surface *,
unsigned, unsigned, unsigned, unsigned);
int (*surface_fill)(struct nouveau_winsys *, struct pipe_surface *,
unsigned, unsigned, unsigned, unsigned, unsigned);
+
+ struct nouveau_bo *(*get_bo)(struct pipe_buffer *);
};
extern struct pipe_screen *
diff --git a/src/gallium/drivers/nv04/Makefile b/src/gallium/drivers/nv04/Makefile
index 5ea51a2f42..4ed62dae95 100644
--- a/src/gallium/drivers/nv04/Makefile
+++ b/src/gallium/drivers/nv04/Makefile
@@ -4,6 +4,7 @@ include $(TOP)/configs/current
LIBNAME = nv04
DRIVER_SOURCES = \
+ nv04_surface_2d.c \
nv04_clear.c \
nv04_context.c \
nv04_fragprog.c \
diff --git a/src/gallium/drivers/nv04/nv04_miptree.c b/src/gallium/drivers/nv04/nv04_miptree.c
index 0575dc0afc..993c5ef5dd 100644
--- a/src/gallium/drivers/nv04/nv04_miptree.c
+++ b/src/gallium/drivers/nv04/nv04_miptree.c
@@ -69,6 +69,31 @@ nv04_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
return &mt->base;
}
+static struct pipe_texture *
+nv04_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
+ const unsigned *stride, struct pipe_buffer *pb)
+{
+ struct nv04_miptree *mt;
+
+ /* Only supports 2D, non-mipmapped textures for the moment */
+ if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
+ pt->depth[0] != 1)
+ return NULL;
+
+ mt = CALLOC_STRUCT(nv04_miptree);
+ if (!mt)
+ return NULL;
+
+ mt->base = *pt;
+ mt->base.refcount = 1;
+ mt->base.screen = pscreen;
+ mt->level[0].pitch = stride[0];
+ mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
+
+ pipe_buffer_reference(pscreen, &mt->buffer, pb);
+ return &mt->base;
+}
+
static void
nv04_miptree_release(struct pipe_screen *pscreen, struct pipe_texture **ppt)
{
@@ -144,6 +169,7 @@ void
nv04_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv04_miptree_create;
+ pscreen->texture_blanket = nv04_miptree_blanket;
pscreen->texture_release = nv04_miptree_release;
pscreen->get_tex_surface = nv04_miptree_surface_new;
pscreen->tex_surface_release = nv04_miptree_surface_del;
diff --git a/src/gallium/drivers/nv04/nv04_screen.c b/src/gallium/drivers/nv04/nv04_screen.c
index e5e3d4772a..9ef38bc244 100644
--- a/src/gallium/drivers/nv04/nv04_screen.c
+++ b/src/gallium/drivers/nv04/nv04_screen.c
@@ -149,10 +149,19 @@ nv04_screen_destroy(struct pipe_screen *pscreen)
nvws->notifier_free(&screen->sync);
nvws->grobj_free(&screen->fahrenheit);
+ nv04_surface_2d_takedown(&screen->eng2d);
FREE(pscreen);
}
+static struct pipe_buffer *
+nv04_surface_buffer(struct pipe_surface *surf)
+{
+ struct nv04_miptree *mt = (struct nv04_miptree *)surf->texture;
+
+ return mt->buffer;
+}
+
struct pipe_screen *
nv04_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
{
@@ -181,6 +190,10 @@ nv04_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
}
+ /* 2D engine setup */
+ screen->eng2d = nv04_surface_2d_init(nvws);
+ screen->eng2d->buf = nv04_surface_buffer;
+
/* 3D object */
ret = nvws->grobj_alloc(nvws, fahrenheit_class, &screen->fahrenheit);
if (ret) {
diff --git a/src/gallium/drivers/nv04/nv04_screen.h b/src/gallium/drivers/nv04/nv04_screen.h
index 99a49cdf7a..540aec907b 100644
--- a/src/gallium/drivers/nv04/nv04_screen.h
+++ b/src/gallium/drivers/nv04/nv04_screen.h
@@ -2,6 +2,7 @@
#define __NV04_SCREEN_H__
#include "pipe/p_screen.h"
+#include "nv04_surface_2d.h"
struct nv04_screen {
struct pipe_screen pipe;
@@ -10,6 +11,7 @@ struct nv04_screen {
unsigned chipset;
/* HW graphics objects */
+ struct nv04_surface_2d *eng2d;
struct nouveau_grobj *fahrenheit;
struct nouveau_grobj *context_surfaces_3d;
struct nouveau_notifier *sync;
diff --git a/src/gallium/drivers/nv04/nv04_surface.c b/src/gallium/drivers/nv04/nv04_surface.c
index 0d0983f9d4..14abf16679 100644
--- a/src/gallium/drivers/nv04/nv04_surface.c
+++ b/src/gallium/drivers/nv04/nv04_surface.c
@@ -39,10 +39,18 @@ nv04_surface_copy(struct pipe_context *pipe, boolean do_flip,
unsigned width, unsigned height)
{
struct nv04_context *nv04 = nv04_context(pipe);
- struct nouveau_winsys *nvws = nv04->nvws;
+ struct nv04_surface_2d *eng2d = nv04->screen->eng2d;
- nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy,
- width, height);
+ if (do_flip) {
+ desty += height;
+ while (height--) {
+ eng2d->copy(eng2d, dest, destx, desty--, src,
+ srcx, srcy++, width, 1);
+ }
+ return;
+ }
+
+ eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
@@ -51,9 +59,9 @@ nv04_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned height, unsigned value)
{
struct nv04_context *nv04 = nv04_context(pipe);
- struct nouveau_winsys *nvws = nv04->nvws;
+ struct nv04_surface_2d *eng2d = nv04->screen->eng2d;
- nvws->surface_fill(nvws, dest, destx, desty, width, height, value);
+ eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c
new file mode 100644
index 0000000000..230cfd17dd
--- /dev/null
+++ b/src/gallium/drivers/nv04/nv04_surface_2d.c
@@ -0,0 +1,448 @@
+#include "pipe/p_context.h"
+#include "pipe/p_format.h"
+#include "util/u_memory.h"
+
+#include "nouveau/nouveau_winsys.h"
+#include "nouveau/nouveau_util.h"
+#include "nv04_surface_2d.h"
+
+static INLINE int
+nv04_surface_format(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_A8_UNORM:
+ return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
+ case PIPE_FORMAT_R16_SNORM:
+ case PIPE_FORMAT_R5G6B5_UNORM:
+ return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
+ case PIPE_FORMAT_X8R8G8B8_UNORM:
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
+ case PIPE_FORMAT_Z24S8_UNORM:
+ return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
+ default:
+ return -1;
+ }
+}
+
+static INLINE int
+nv04_rect_format(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_A8_UNORM:
+ return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
+ case PIPE_FORMAT_R5G6B5_UNORM:
+ return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ case PIPE_FORMAT_Z24S8_UNORM:
+ return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
+ default:
+ return -1;
+ }
+}
+
+static INLINE int
+nv04_scaled_image_format(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_A1R5G5B5_UNORM:
+ return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
+ case PIPE_FORMAT_X8R8G8B8_UNORM:
+ return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
+ case PIPE_FORMAT_R5G6B5_UNORM:
+ case PIPE_FORMAT_R16_SNORM:
+ return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
+ default:
+ return -1;
+ }
+}
+
+static INLINE unsigned
+nv04_swizzle_bits(unsigned x, unsigned y)
+{
+ unsigned u = (x & 0x001) << 0 |
+ (x & 0x002) << 1 |
+ (x & 0x004) << 2 |
+ (x & 0x008) << 3 |
+ (x & 0x010) << 4 |
+ (x & 0x020) << 5 |
+ (x & 0x040) << 6 |
+ (x & 0x080) << 7 |
+ (x & 0x100) << 8 |
+ (x & 0x200) << 9 |
+ (x & 0x400) << 10 |
+ (x & 0x800) << 11;
+
+ unsigned v = (y & 0x001) << 1 |
+ (y & 0x002) << 2 |
+ (y & 0x004) << 3 |
+ (y & 0x008) << 4 |
+ (y & 0x010) << 5 |
+ (y & 0x020) << 6 |
+ (y & 0x040) << 7 |
+ (y & 0x080) << 8 |
+ (y & 0x100) << 9 |
+ (y & 0x200) << 10 |
+ (y & 0x400) << 11 |
+ (y & 0x800) << 12;
+ return v | u;
+}
+
+static int
+nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
+ struct pipe_surface *dst, int dx, int dy,
+ struct pipe_surface *src, int sx, int sy,
+ int w, int h)
+{
+ struct nouveau_channel *chan = ctx->nvws->channel;
+ struct nouveau_grobj *swzsurf = ctx->swzsurf;
+ struct nouveau_grobj *sifm = ctx->sifm;
+ struct nouveau_bo *src_bo = ctx->nvws->get_bo(ctx->buf(src));
+ struct nouveau_bo *dst_bo = ctx->nvws->get_bo(ctx->buf(dst));
+ const unsigned max_w = 1024;
+ const unsigned max_h = 1024;
+ const unsigned sub_w = w > max_w ? max_w : w;
+ const unsigned sub_h = h > max_h ? max_h : h;
+ unsigned cx;
+ unsigned cy;
+
+ /* POT or GTFO */
+ assert(!(w & (w - 1)) && !(h & (h - 1)));
+
+ BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
+ OUT_RELOCo(chan, dst_bo,
+ NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+ BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
+ OUT_RING (chan, nv04_surface_format(dst->format) |
+ log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
+ log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
+
+ BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
+ OUT_RELOCo(chan, src_bo,
+ NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
+ OUT_RING (chan, swzsurf->handle);
+
+ for (cy = 0; cy < h; cy += sub_h) {
+ for (cx = 0; cx < w; cx += sub_w) {
+ BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
+ OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(cx, cy) *
+ dst->block.size, NOUVEAU_BO_GART |
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+ BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
+ OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
+ OUT_RING (chan, nv04_scaled_image_format(src->format));
+ OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, sub_h << 16 | sub_w);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, sub_h << 16 | sub_w);
+ OUT_RING (chan, 1 << 20);
+ OUT_RING (chan, 1 << 20);
+
+ BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
+ OUT_RING (chan, sub_h << 16 | sub_w);
+ OUT_RING (chan, src->stride |
+ NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
+ NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
+ OUT_RELOCl(chan, src_bo, src->offset + cy * src->stride +
+ cx * src->block.size, NOUVEAU_BO_GART |
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ OUT_RING (chan, 0);
+ }
+ }
+
+ return 0;
+}
+
+static int
+nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
+ struct pipe_surface *dst, int dx, int dy,
+ struct pipe_surface *src, int sx, int sy, int w, int h)
+{
+ struct nouveau_channel *chan = ctx->nvws->channel;
+ struct nouveau_grobj *m2mf = ctx->m2mf;
+ struct nouveau_bo *src_bo = ctx->nvws->get_bo(ctx->buf(src));
+ struct nouveau_bo *dst_bo = ctx->nvws->get_bo(ctx->buf(dst));
+ unsigned dst_offset, src_offset;
+
+ dst_offset = dst->offset + (dy * dst->stride) + (dx * dst->block.size);
+ src_offset = src->offset + (sy * src->stride) + (sx * src->block.size);
+
+ WAIT_RING (chan, 3 + ((h / 2047) + 1) * 9);
+ BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
+ OUT_RELOCo(chan, src_bo,
+ NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ OUT_RELOCo(chan, dst_bo,
+ NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+ while (h) {
+ int count = (h > 2047) ? 2047 : h;
+
+ BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
+ OUT_RELOCl(chan, src_bo, src_offset,
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
+ OUT_RELOCl(chan, dst_bo, dst_offset,
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
+ OUT_RING (chan, src->stride);
+ OUT_RING (chan, dst->stride);
+ OUT_RING (chan, w * src->block.size);
+ OUT_RING (chan, count);
+ OUT_RING (chan, 0x0101);
+ OUT_RING (chan, 0);
+
+ h -= count;
+ src_offset += src->stride * count;
+ dst_offset += dst->stride * count;
+ }
+
+ return 0;
+}
+
+static int
+nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
+ int dx, int dy, struct pipe_surface *src, int sx, int sy,
+ int w, int h)
+{
+ struct nouveau_channel *chan = ctx->nvws->channel;
+ struct nouveau_grobj *surf2d = ctx->surf2d;
+ struct nouveau_grobj *blit = ctx->blit;
+ struct nouveau_bo *src_bo = ctx->nvws->get_bo(ctx->buf(src));
+ struct nouveau_bo *dst_bo = ctx->nvws->get_bo(ctx->buf(dst));
+ int format;
+
+ format = nv04_surface_format(dst->format);
+ if (format < 0)
+ return 1;
+
+ WAIT_RING (chan, 12);
+ BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
+ OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
+ OUT_RING (chan, format);
+ OUT_RING (chan, (dst->stride << 16) | src->stride);
+ OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+ BEGIN_RING(chan, blit, 0x0300, 3);
+ OUT_RING (chan, (sy << 16) | sx);
+ OUT_RING (chan, (dy << 16) | dx);
+ OUT_RING (chan, ( h << 16) | w);
+
+ return 0;
+}
+
+static void
+nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
+ int dx, int dy, struct pipe_surface *src, int sx, int sy,
+ int w, int h)
+{
+ int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
+ int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
+
+ assert(src->format == dst->format);
+
+ /* Setup transfer to swizzle the texture to vram if needed */
+ if (src_linear && !dst_linear && w > 1 && h > 1) {
+ nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
+ return;
+ }
+
+ /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
+ * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
+ */
+ if ((src->offset & 63) || (dst->offset & 63) ||
+ (src->stride & 63) || (dst->stride & 63)) {
+ nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
+ return;
+ }
+
+ nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
+}
+
+static void
+nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
+ int dx, int dy, int w, int h, unsigned value)
+{
+ struct nouveau_channel *chan = ctx->nvws->channel;
+ struct nouveau_grobj *surf2d = ctx->surf2d;
+ struct nouveau_grobj *rect = ctx->rect;
+ struct nouveau_bo *dst_bo = ctx->nvws->get_bo(ctx->buf(dst));
+ int cs2d_format, gdirect_format;
+
+ cs2d_format = nv04_surface_format(dst->format);
+ assert(cs2d_format >= 0);
+
+ gdirect_format = nv04_rect_format(dst->format);
+ assert(gdirect_format >= 0);
+
+ WAIT_RING (chan, 16);
+ BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
+ OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
+ OUT_RING (chan, cs2d_format);
+ OUT_RING (chan, (dst->stride << 16) | dst->stride);
+ OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+ BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
+ OUT_RING (chan, gdirect_format);
+ BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
+ OUT_RING (chan, value);
+ BEGIN_RING(chan, rect,
+ NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
+ OUT_RING (chan, (dx << 16) | dy);
+ OUT_RING (chan, ( w << 16) | h);
+}
+
+void
+nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
+{
+ struct nv04_surface_2d *ctx;
+
+ if (!pctx || !*pctx)
+ return;
+ ctx = *pctx;
+ *pctx = NULL;
+
+ nouveau_notifier_free(&ctx->ntfy);
+ nouveau_grobj_free(&ctx->m2mf);
+ nouveau_grobj_free(&ctx->surf2d);
+ nouveau_grobj_free(&ctx->swzsurf);
+ nouveau_grobj_free(&ctx->rect);
+ nouveau_grobj_free(&ctx->blit);
+ nouveau_grobj_free(&ctx->sifm);
+
+ FREE(ctx);
+}
+
+struct nv04_surface_2d *
+nv04_surface_2d_init(struct nouveau_winsys *nvws)
+{
+ struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
+ struct nouveau_channel *chan = nvws->channel;
+ unsigned handle = 0x88000000, class;
+ int ret;
+
+ if (!ctx)
+ return NULL;
+
+ ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
+ OUT_RING (chan, ctx->ntfy->handle);
+
+ if (chan->device->chipset < 0x10)
+ class = NV04_CONTEXT_SURFACES_2D;
+ else
+ class = NV10_CONTEXT_SURFACES_2D;
+
+ ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ BEGIN_RING(chan, ctx->surf2d,
+ NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
+ OUT_RING (chan, chan->vram->handle);
+ OUT_RING (chan, chan->vram->handle);
+
+ if (chan->device->chipset < 0x10)
+ class = NV04_IMAGE_BLIT;
+ else
+ class = NV12_IMAGE_BLIT;
+
+ ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
+ OUT_RING (chan, ctx->ntfy->handle);
+ BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
+ OUT_RING (chan, ctx->surf2d->handle);
+ BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_OPERATION, 1);
+ OUT_RING (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
+
+ ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
+ &ctx->rect);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
+ OUT_RING (chan, ctx->ntfy->handle);
+ BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
+ OUT_RING (chan, ctx->surf2d->handle);
+ BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
+ OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
+ BEGIN_RING(chan, ctx->rect,
+ NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
+ OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
+
+ switch (chan->device->chipset & 0xf0) {
+ case 0x00:
+ case 0x10:
+ class = NV04_SWIZZLED_SURFACE;
+ break;
+ case 0x20:
+ class = NV20_SWIZZLED_SURFACE;
+ break;
+ case 0x30:
+ class = NV30_SWIZZLED_SURFACE;
+ break;
+ case 0x40:
+ case 0x60:
+ class = NV40_SWIZZLED_SURFACE;
+ break;
+ default:
+ /* Famous last words: this really can't happen.. */
+ assert(0);
+ break;
+ }
+
+ ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ if (chan->device->chipset < 0x10) {
+ class = NV04_SCALED_IMAGE_FROM_MEMORY;
+ } else
+ if (chan->device->chipset < 0x40) {
+ class = NV10_SCALED_IMAGE_FROM_MEMORY;
+ } else {
+ class = NV40_SCALED_IMAGE_FROM_MEMORY;
+ }
+
+ ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
+ if (ret) {
+ nv04_surface_2d_takedown(&ctx);
+ return NULL;
+ }
+
+ ctx->nvws = nvws;
+ ctx->copy = nv04_surface_copy;
+ ctx->fill = nv04_surface_fill;
+ return ctx;
+}
diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.h b/src/gallium/drivers/nv04/nv04_surface_2d.h
new file mode 100644
index 0000000000..21b8f86960
--- /dev/null
+++ b/src/gallium/drivers/nv04/nv04_surface_2d.h
@@ -0,0 +1,29 @@
+#ifndef __NV04_SURFACE_2D_H__
+#define __NV04_SURFACE_2D_H__
+
+struct nv04_surface_2d {
+ struct nouveau_winsys *nvws;
+ struct nouveau_notifier *ntfy;
+ struct nouveau_grobj *surf2d;
+ struct nouveau_grobj *swzsurf;
+ struct nouveau_grobj *m2mf;
+ struct nouveau_grobj *rect;
+ struct nouveau_grobj *blit;
+ struct nouveau_grobj *sifm;
+
+ struct pipe_buffer *(*buf)(struct pipe_surface *);
+
+ void (*copy)(struct nv04_surface_2d *, struct pipe_surface *dst,
+ int dx, int dy, struct pipe_surface *src, int sx, int sy,
+ int w, int h);
+ void (*fill)(struct nv04_surface_2d *, struct pipe_surface *dst,
+ int dx, int dy, int w, int h, unsigned value);
+};
+
+struct nv04_surface_2d *
+nv04_surface_2d_init(struct nouveau_winsys *nvws);
+
+void
+nv04_surface_2d_takedown(struct nv04_surface_2d **);
+
+#endif
diff --git a/src/gallium/drivers/nv10/nv10_miptree.c b/src/gallium/drivers/nv10/nv10_miptree.c
index 909278213e..9616135461 100644
--- a/src/gallium/drivers/nv10/nv10_miptree.c
+++ b/src/gallium/drivers/nv10/nv10_miptree.c
@@ -51,6 +51,31 @@ nv10_miptree_layout(struct nv10_miptree *nv10mt)
}
static struct pipe_texture *
+nv10_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
+ const unsigned *stride, struct pipe_buffer *pb)
+{
+ struct nv10_miptree *mt;
+
+ /* Only supports 2D, non-mipmapped textures for the moment */
+ if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
+ pt->depth[0] != 1)
+ return NULL;
+
+ mt = CALLOC_STRUCT(nv10_miptree);
+ if (!mt)
+ return NULL;
+
+ mt->base = *pt;
+ mt->base.refcount = 1;
+ mt->base.screen = pscreen;
+ mt->level[0].pitch = stride[0];
+ mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
+
+ pipe_buffer_reference(pscreen, &mt->buffer, pb);
+ return &mt->base;
+}
+
+static struct pipe_texture *
nv10_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt)
{
struct pipe_winsys *ws = screen->winsys;
@@ -141,6 +166,7 @@ nv10_miptree_surface_release(struct pipe_screen *screen,
void nv10_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv10_miptree_create;
+ pscreen->texture_blanket = nv10_miptree_blanket;
pscreen->texture_release = nv10_miptree_release;
pscreen->get_tex_surface = nv10_miptree_surface_get;
pscreen->tex_surface_release = nv10_miptree_surface_release;
diff --git a/src/gallium/drivers/nv10/nv10_screen.c b/src/gallium/drivers/nv10/nv10_screen.c
index 2f945a193c..f417b06c94 100644
--- a/src/gallium/drivers/nv10/nv10_screen.c
+++ b/src/gallium/drivers/nv10/nv10_screen.c
@@ -152,6 +152,14 @@ nv10_screen_destroy(struct pipe_screen *pscreen)
FREE(pscreen);
}
+static struct pipe_buffer *
+nv10_surface_buffer(struct pipe_surface *surf)
+{
+ struct nv10_miptree *mt = (struct nv10_miptree *)surf->texture;
+
+ return mt->buffer;
+}
+
struct pipe_screen *
nv10_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
{
@@ -164,6 +172,10 @@ nv10_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
screen->nvws = nvws;
+ /* 2D engine setup */
+ screen->eng2d = nv04_surface_2d_init(nvws);
+ screen->eng2d->buf = nv10_surface_buffer;
+
/* 3D object */
if (chipset>=0x20)
celsius_class=NV11TCL;
diff --git a/src/gallium/drivers/nv10/nv10_screen.h b/src/gallium/drivers/nv10/nv10_screen.h
index 3f8750a13f..60102a369a 100644
--- a/src/gallium/drivers/nv10/nv10_screen.h
+++ b/src/gallium/drivers/nv10/nv10_screen.h
@@ -2,6 +2,7 @@
#define __NV10_SCREEN_H__
#include "pipe/p_screen.h"
+#include "nv04/nv04_surface_2d.h"
struct nv10_screen {
struct pipe_screen pipe;
@@ -9,6 +10,7 @@ struct nv10_screen {
struct nouveau_winsys *nvws;
/* HW graphics objects */
+ struct nv04_surface_2d *eng2d;
struct nouveau_grobj *celsius;
struct nouveau_notifier *sync;
};
diff --git a/src/gallium/drivers/nv10/nv10_surface.c b/src/gallium/drivers/nv10/nv10_surface.c
index 78fd7b42da..2538151063 100644
--- a/src/gallium/drivers/nv10/nv10_surface.c
+++ b/src/gallium/drivers/nv10/nv10_surface.c
@@ -39,10 +39,18 @@ nv10_surface_copy(struct pipe_context *pipe, boolean do_flip,
unsigned width, unsigned height)
{
struct nv10_context *nv10 = nv10_context(pipe);
- struct nouveau_winsys *nvws = nv10->nvws;
+ struct nv04_surface_2d *eng2d = nv10->screen->eng2d;
- nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy,
- width, height);
+ if (do_flip) {
+ desty += height;
+ while (height--) {
+ eng2d->copy(eng2d, dest, destx, desty--, src,
+ srcx, srcy++, width, 1);
+ }
+ return;
+ }
+
+ eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
@@ -51,9 +59,9 @@ nv10_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned height, unsigned value)
{
struct nv10_context *nv10 = nv10_context(pipe);
- struct nouveau_winsys *nvws = nv10->nvws;
+ struct nv04_surface_2d *eng2d = nv10->screen->eng2d;
- nvws->surface_fill(nvws, dest, destx, desty, width, height, value);
+ eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
diff --git a/src/gallium/drivers/nv20/nv20_miptree.c b/src/gallium/drivers/nv20/nv20_miptree.c
index 8e4cc80902..ef7e9c5428 100644
--- a/src/gallium/drivers/nv20/nv20_miptree.c
+++ b/src/gallium/drivers/nv20/nv20_miptree.c
@@ -51,10 +51,37 @@ nv20_miptree_layout(struct nv20_miptree *nv20mt)
}
static struct pipe_texture *
+nv20_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
+ const unsigned *stride, struct pipe_buffer *pb)
+{
+ struct nv20_miptree *mt;
+
+ /* Only supports 2D, non-mipmapped textures for the moment */
+ if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
+ pt->depth[0] != 1)
+ return NULL;
+
+ mt = CALLOC_STRUCT(nv20_miptree);
+ if (!mt)
+ return NULL;
+
+ mt->base = *pt;
+ mt->base.refcount = 1;
+ mt->base.screen = pscreen;
+ mt->level[0].pitch = stride[0];
+ mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
+
+ pipe_buffer_reference(pscreen, &mt->buffer, pb);
+ return &mt->base;
+}
+
+static struct pipe_texture *
nv20_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt)
{
struct pipe_winsys *ws = screen->winsys;
struct nv20_miptree *mt;
+ unsigned buf_usage = PIPE_BUFFER_USAGE_PIXEL |
+ NOUVEAU_BUFFER_USAGE_TEXTURE;
mt = MALLOC(sizeof(struct nv20_miptree));
if (!mt)
@@ -63,10 +90,35 @@ nv20_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt)
mt->base.refcount = 1;
mt->base.screen = screen;
+ /* Swizzled textures must be POT */
+ if (pt->width[0] & (pt->width[0] - 1) ||
+ pt->height[0] & (pt->height[0] - 1))
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ else
+ if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY |
+ PIPE_TEXTURE_USAGE_DISPLAY_TARGET))
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ else
+ if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC)
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ else {
+ switch (pt->format) {
+ /* TODO: Figure out which formats can be swizzled */
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ case PIPE_FORMAT_X8R8G8B8_UNORM:
+ case PIPE_FORMAT_R16_SNORM:
+ break;
+ default:
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ }
+ }
+
+ if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC)
+ buf_usage |= PIPE_BUFFER_USAGE_CPU_READ_WRITE;
+
nv20_miptree_layout(mt);
- mt->buffer = ws->buffer_create(ws, 256, PIPE_BUFFER_USAGE_PIXEL,
- mt->total_size);
+ mt->buffer = ws->buffer_create(ws, 256, buf_usage, mt->total_size);
if (!mt->buffer) {
FREE(mt);
return NULL;
@@ -146,6 +198,7 @@ nv20_miptree_surface_release(struct pipe_screen *pscreen,
void nv20_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv20_miptree_create;
+ pscreen->texture_blanket = nv20_miptree_blanket;
pscreen->texture_release = nv20_miptree_release;
pscreen->get_tex_surface = nv20_miptree_surface_get;
pscreen->tex_surface_release = nv20_miptree_surface_release;
diff --git a/src/gallium/drivers/nv20/nv20_screen.c b/src/gallium/drivers/nv20/nv20_screen.c
index c9171fa178..5f2b7b4f71 100644
--- a/src/gallium/drivers/nv20/nv20_screen.c
+++ b/src/gallium/drivers/nv20/nv20_screen.c
@@ -152,6 +152,14 @@ nv20_screen_destroy(struct pipe_screen *pscreen)
FREE(pscreen);
}
+static struct pipe_buffer *
+nv20_surface_buffer(struct pipe_surface *surf)
+{
+ struct nv20_miptree *mt = (struct nv20_miptree *)surf->texture;
+
+ return mt->buffer;
+}
+
struct pipe_screen *
nv20_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
{
@@ -164,6 +172,10 @@ nv20_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
screen->nvws = nvws;
+ /* 2D engine setup */
+ screen->eng2d = nv04_surface_2d_init(nvws);
+ screen->eng2d->buf = nv20_surface_buffer;
+
/* 3D object */
if (chipset >= 0x25)
kelvin_class = NV25TCL;
diff --git a/src/gallium/drivers/nv20/nv20_screen.h b/src/gallium/drivers/nv20/nv20_screen.h
index 8f2f2e341d..bf2f2c0d9f 100644
--- a/src/gallium/drivers/nv20/nv20_screen.h
+++ b/src/gallium/drivers/nv20/nv20_screen.h
@@ -2,6 +2,7 @@
#define __NV20_SCREEN_H__
#include "pipe/p_screen.h"
+#include "nv04/nv04_surface_2d.h"
struct nv20_screen {
struct pipe_screen pipe;
@@ -9,6 +10,7 @@ struct nv20_screen {
struct nouveau_winsys *nvws;
/* HW graphics objects */
+ struct nv04_surface_2d *eng2d;
struct nouveau_grobj *kelvin;
struct nouveau_notifier *sync;
};
diff --git a/src/gallium/drivers/nv20/nv20_surface.c b/src/gallium/drivers/nv20/nv20_surface.c
index 9b4c028eae..6cd607583c 100644
--- a/src/gallium/drivers/nv20/nv20_surface.c
+++ b/src/gallium/drivers/nv20/nv20_surface.c
@@ -39,10 +39,18 @@ nv20_surface_copy(struct pipe_context *pipe, boolean do_flip,
unsigned width, unsigned height)
{
struct nv20_context *nv20 = nv20_context(pipe);
- struct nouveau_winsys *nvws = nv20->nvws;
+ struct nv04_surface_2d *eng2d = nv20->screen->eng2d;
- nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy,
- width, height);
+ if (do_flip) {
+ desty += height;
+ while (height--) {
+ eng2d->copy(eng2d, dest, destx, desty--, src,
+ srcx, srcy++, width, 1);
+ }
+ return;
+ }
+
+ eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
@@ -51,9 +59,9 @@ nv20_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned height, unsigned value)
{
struct nv20_context *nv20 = nv20_context(pipe);
- struct nouveau_winsys *nvws = nv20->nvws;
+ struct nv04_surface_2d *eng2d = nv20->screen->eng2d;
- nvws->surface_fill(nvws, dest, destx, desty, width, height, value);
+ eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
diff --git a/src/gallium/drivers/nv20/nv20_vertprog.c b/src/gallium/drivers/nv20/nv20_vertprog.c
index a885fcd7a5..5db0e807ff 100644
--- a/src/gallium/drivers/nv20/nv20_vertprog.c
+++ b/src/gallium/drivers/nv20/nv20_vertprog.c
@@ -613,7 +613,7 @@ nv20_vertprog_translate(struct nv20_context *nv20,
imm = &parse.FullToken.FullImmediate;
assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
-// assert(imm->Immediate.Size == 4);
+ assert(imm->Immediate.NrTokens == 4 + 1);
vpc->imm[vpc->nr_imm++] =
constant(vpc, -1,
imm->u.ImmediateFloat32[0].Float,
diff --git a/src/gallium/drivers/nv30/nv30_miptree.c b/src/gallium/drivers/nv30/nv30_miptree.c
index c55756971b..b11ed8c24e 100644
--- a/src/gallium/drivers/nv30/nv30_miptree.c
+++ b/src/gallium/drivers/nv30/nv30_miptree.c
@@ -8,10 +8,14 @@ static void
nv30_miptree_layout(struct nv30_miptree *nv30mt)
{
struct pipe_texture *pt = &nv30mt->base;
- boolean swizzled = FALSE;
uint width = pt->width[0], height = pt->height[0], depth = pt->depth[0];
uint offset = 0;
- int nr_faces, l, f, pitch;
+ int nr_faces, l, f;
+ uint wide_pitch = pt->tex_usage & (PIPE_TEXTURE_USAGE_SAMPLER |
+ PIPE_TEXTURE_USAGE_DEPTH_STENCIL |
+ PIPE_TEXTURE_USAGE_RENDER_TARGET |
+ PIPE_TEXTURE_USAGE_DISPLAY_TARGET |
+ PIPE_TEXTURE_USAGE_PRIMARY);
if (pt->target == PIPE_TEXTURE_CUBE) {
nr_faces = 6;
@@ -22,7 +26,6 @@ nv30_miptree_layout(struct nv30_miptree *nv30mt)
nr_faces = 1;
}
- pitch = pt->width[0];
for (l = 0; l <= pt->last_level; l++) {
pt->width[l] = width;
pt->height[l] = height;
@@ -30,11 +33,11 @@ nv30_miptree_layout(struct nv30_miptree *nv30mt)
pt->nblocksx[l] = pf_get_nblocksx(&pt->block, width);
pt->nblocksy[l] = pf_get_nblocksy(&pt->block, height);
- if (swizzled)
- pitch = pt->nblocksx[l];
- pitch = align(pitch, 64);
+ if (wide_pitch && (pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
+ nv30mt->level[l].pitch = align(pt->width[0] * pt->block.size, 64);
+ else
+ nv30mt->level[l].pitch = pt->width[l] * pt->block.size;
- nv30mt->level[l].pitch = pitch * pt->block.size;
nv30mt->level[l].image_offset =
CALLOC(nr_faces, sizeof(unsigned));
@@ -44,10 +47,18 @@ nv30_miptree_layout(struct nv30_miptree *nv30mt)
}
for (f = 0; f < nr_faces; f++) {
- for (l = 0; l <= pt->last_level; l++) {
+ for (l = 0; l < pt->last_level; l++) {
nv30mt->level[l].image_offset[f] = offset;
- offset += nv30mt->level[l].pitch * pt->height[l];
+
+ if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR) &&
+ pt->width[l + 1] > 1 && pt->height[l + 1] > 1)
+ offset += align(nv30mt->level[l].pitch * pt->height[l], 64);
+ else
+ offset += nv30mt->level[l].pitch * pt->height[l];
}
+
+ nv30mt->level[l].image_offset[f] = offset;
+ offset += nv30mt->level[l].pitch * pt->height[l];
}
nv30mt->total_size = offset;
@@ -74,7 +85,8 @@ nv30_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else
if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY |
- PIPE_TEXTURE_USAGE_DISPLAY_TARGET))
+ PIPE_TEXTURE_USAGE_DISPLAY_TARGET |
+ PIPE_TEXTURE_USAGE_DEPTH_STENCIL))
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else
if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC)
@@ -85,7 +97,11 @@ nv30_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
case PIPE_FORMAT_R16_SNORM:
- break;
+ {
+ if (debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE))
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ break;
+ }
default:
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
}
@@ -105,6 +121,31 @@ nv30_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
return &mt->base;
}
+static struct pipe_texture *
+nv30_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
+ const unsigned *stride, struct pipe_buffer *pb)
+{
+ struct nv30_miptree *mt;
+
+ /* Only supports 2D, non-mipmapped textures for the moment */
+ if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
+ pt->depth[0] != 1)
+ return NULL;
+
+ mt = CALLOC_STRUCT(nv30_miptree);
+ if (!mt)
+ return NULL;
+
+ mt->base = *pt;
+ mt->base.refcount = 1;
+ mt->base.screen = pscreen;
+ mt->level[0].pitch = stride[0];
+ mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
+
+ pipe_buffer_reference(pscreen, &mt->buffer, pb);
+ return &mt->base;
+}
+
static void
nv30_miptree_release(struct pipe_screen *pscreen, struct pipe_texture **ppt)
{
@@ -123,8 +164,8 @@ nv30_miptree_release(struct pipe_screen *pscreen, struct pipe_texture **ppt)
}
if (mt->shadow_tex) {
- assert(mt->shadow_surface);
- pscreen->tex_surface_release(pscreen, &mt->shadow_surface);
+ if (mt->shadow_surface)
+ pscreen->tex_surface_release(pscreen, &mt->shadow_surface);
nv30_miptree_release(pscreen, &mt->shadow_tex);
}
@@ -187,6 +228,7 @@ void
nv30_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv30_miptree_create;
+ pscreen->texture_blanket = nv30_miptree_blanket;
pscreen->texture_release = nv30_miptree_release;
pscreen->get_tex_surface = nv30_miptree_surface_new;
pscreen->tex_surface_release = nv30_miptree_surface_del;
diff --git a/src/gallium/drivers/nv30/nv30_screen.c b/src/gallium/drivers/nv30/nv30_screen.c
index 9738436dc4..c97a73f0b1 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -127,6 +127,14 @@ nv30_screen_surface_format_supported(struct pipe_screen *pscreen,
return FALSE;
}
+static struct pipe_buffer *
+nv30_surface_buffer(struct pipe_surface *surf)
+{
+ struct nv30_miptree *mt = (struct nv30_miptree *)surf->texture;
+
+ return mt->buffer;
+}
+
static void *
nv30_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
unsigned flags )
@@ -134,7 +142,6 @@ nv30_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
struct pipe_winsys *ws = screen->winsys;
struct pipe_surface *surface_to_map;
void *map;
- struct nv30_miptree *nv30mt = (struct nv30_miptree *)surface->texture;
if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
struct nv30_miptree *mt = (struct nv30_miptree *)surface->texture;
@@ -163,7 +170,7 @@ nv30_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
assert(surface_to_map);
- map = ws->buffer_map(ws, nv30mt->buffer, flags);
+ map = ws->buffer_map(ws, nv30_surface_buffer(surface_to_map), flags);
if (!map)
return NULL;
@@ -175,7 +182,6 @@ nv30_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
{
struct pipe_winsys *ws = screen->winsys;
struct pipe_surface *surface_to_unmap;
- struct nv30_miptree *nv30mt = (struct nv30_miptree *)surface->texture;
/* TODO: Copy from shadow just before push buffer is flushed instead.
There are probably some programs that map/unmap excessively
@@ -192,15 +198,16 @@ nv30_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
assert(surface_to_unmap);
- ws->buffer_unmap(ws, nv30mt->buffer);
+ ws->buffer_unmap(ws, nv30_surface_buffer(surface_to_unmap));
if (surface_to_unmap != surface) {
struct nv30_screen *nvscreen = nv30_screen(screen);
- nvscreen->nvws->surface_copy(nvscreen->nvws,
- surface, 0, 0,
- surface_to_unmap, 0, 0,
- surface->width, surface->height);
+ nvscreen->eng2d->copy(nvscreen->eng2d, surface, 0, 0,
+ surface_to_unmap, 0, 0,
+ surface->width, surface->height);
+
+ screen->tex_surface_release(screen, &surface_to_unmap);
}
}
@@ -233,6 +240,10 @@ nv30_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
screen->nvws = nvws;
+ /* 2D engine setup */
+ screen->eng2d = nv04_surface_2d_init(nvws);
+ screen->eng2d->buf = nv30_surface_buffer;
+
/* 3D object */
switch (chipset & 0xf0) {
case 0x30:
diff --git a/src/gallium/drivers/nv30/nv30_screen.h b/src/gallium/drivers/nv30/nv30_screen.h
index b7ddc2a959..b11e470f94 100644
--- a/src/gallium/drivers/nv30/nv30_screen.h
+++ b/src/gallium/drivers/nv30/nv30_screen.h
@@ -2,6 +2,7 @@
#define __NV30_SCREEN_H__
#include "pipe/p_screen.h"
+#include "nv04/nv04_surface_2d.h"
struct nv30_screen {
struct pipe_screen pipe;
@@ -11,6 +12,7 @@ struct nv30_screen {
unsigned cur_pctx;
/* HW graphics objects */
+ struct nv04_surface_2d *eng2d;
struct nouveau_grobj *rankine;
struct nouveau_notifier *sync;
diff --git a/src/gallium/drivers/nv30/nv30_surface.c b/src/gallium/drivers/nv30/nv30_surface.c
index 806131dcc9..0f8dc12045 100644
--- a/src/gallium/drivers/nv30/nv30_surface.c
+++ b/src/gallium/drivers/nv30/nv30_surface.c
@@ -30,7 +30,6 @@
#include "pipe/p_defines.h"
#include "pipe/internal/p_winsys_screen.h"
#include "pipe/p_inlines.h"
-
#include "util/u_tile.h"
static void
@@ -40,22 +39,18 @@ nv30_surface_copy(struct pipe_context *pipe, boolean do_flip,
unsigned width, unsigned height)
{
struct nv30_context *nv30 = nv30_context(pipe);
- struct nouveau_winsys *nvws = nv30->nvws;
+ struct nv04_surface_2d *eng2d = nv30->screen->eng2d;
if (do_flip) {
- /*XXX: This dodgyness will do for now for correctness. But,
- * need to investigate whether the 2D engine is able to
- * manage a flip (perhaps SIFM?), if not, use the 3D engine
- */
desty += height;
while (height--) {
- nvws->surface_copy(nvws, dest, destx, desty--, src,
- srcx, srcy++, width, 1);
+ eng2d->copy(eng2d, dest, destx, desty--, src,
+ srcx, srcy++, width, 1);
}
- } else {
- nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy,
- width, height);
+ return;
}
+
+ eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
@@ -64,9 +59,9 @@ nv30_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned height, unsigned value)
{
struct nv30_context *nv30 = nv30_context(pipe);
- struct nouveau_winsys *nvws = nv30->nvws;
+ struct nv04_surface_2d *eng2d = nv30->screen->eng2d;
- nvws->surface_fill(nvws, dest, destx, desty, width, height, value);
+ eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
diff --git a/src/gallium/drivers/nv30/nv30_vertprog.c b/src/gallium/drivers/nv30/nv30_vertprog.c
index 72824559e8..d262725057 100644
--- a/src/gallium/drivers/nv30/nv30_vertprog.c
+++ b/src/gallium/drivers/nv30/nv30_vertprog.c
@@ -613,7 +613,7 @@ nv30_vertprog_translate(struct nv30_context *nv30,
imm = &parse.FullToken.FullImmediate;
assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
-// assert(imm->Immediate.Size == 4);
+ assert(imm->Immediate.NrTokens == 4 + 1);
vpc->imm[vpc->nr_imm++] =
constant(vpc, -1,
imm->u.ImmediateFloat32[0].Float,
diff --git a/src/gallium/drivers/nv40/nv40_miptree.c b/src/gallium/drivers/nv40/nv40_miptree.c
index b1fba11d2f..e38b1e7f5c 100644
--- a/src/gallium/drivers/nv40/nv40_miptree.c
+++ b/src/gallium/drivers/nv40/nv40_miptree.c
@@ -10,7 +10,12 @@ nv40_miptree_layout(struct nv40_miptree *mt)
struct pipe_texture *pt = &mt->base;
uint width = pt->width[0], height = pt->height[0], depth = pt->depth[0];
uint offset = 0;
- int nr_faces, l, f, pitch;
+ int nr_faces, l, f;
+ uint wide_pitch = pt->tex_usage & (PIPE_TEXTURE_USAGE_SAMPLER |
+ PIPE_TEXTURE_USAGE_DEPTH_STENCIL |
+ PIPE_TEXTURE_USAGE_RENDER_TARGET |
+ PIPE_TEXTURE_USAGE_DISPLAY_TARGET |
+ PIPE_TEXTURE_USAGE_PRIMARY);
if (pt->target == PIPE_TEXTURE_CUBE) {
nr_faces = 6;
@@ -21,7 +26,6 @@ nv40_miptree_layout(struct nv40_miptree *mt)
nr_faces = 1;
}
- pitch = pt->width[0];
for (l = 0; l <= pt->last_level; l++) {
pt->width[l] = width;
pt->height[l] = height;
@@ -29,11 +33,11 @@ nv40_miptree_layout(struct nv40_miptree *mt)
pt->nblocksx[l] = pf_get_nblocksx(&pt->block, width);
pt->nblocksy[l] = pf_get_nblocksy(&pt->block, height);
- if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
- pitch = pt->nblocksx[l];
- pitch = align(pitch, 64);
+ if (wide_pitch && (pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
+ mt->level[l].pitch = align(pt->width[0] * pt->block.size, 64);
+ else
+ mt->level[l].pitch = pt->width[l] * pt->block.size;
- mt->level[l].pitch = pitch * pt->block.size;
mt->level[l].image_offset =
CALLOC(nr_faces, sizeof(unsigned));
@@ -43,10 +47,18 @@ nv40_miptree_layout(struct nv40_miptree *mt)
}
for (f = 0; f < nr_faces; f++) {
- for (l = 0; l <= pt->last_level; l++) {
+ for (l = 0; l < pt->last_level; l++) {
mt->level[l].image_offset[f] = offset;
- offset += mt->level[l].pitch * pt->height[l];
+
+ if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR) &&
+ pt->width[l + 1] > 1 && pt->height[l + 1] > 1)
+ offset += align(mt->level[l].pitch * pt->height[l], 64);
+ else
+ offset += mt->level[l].pitch * pt->height[l];
}
+
+ mt->level[l].image_offset[f] = offset;
+ offset += mt->level[l].pitch * pt->height[l];
}
mt->total_size = offset;
@@ -75,7 +87,8 @@ nv40_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else
if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY |
- PIPE_TEXTURE_USAGE_DISPLAY_TARGET))
+ PIPE_TEXTURE_USAGE_DISPLAY_TARGET |
+ PIPE_TEXTURE_USAGE_DEPTH_STENCIL))
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else
if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC)
@@ -86,7 +99,11 @@ nv40_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
case PIPE_FORMAT_R16_SNORM:
+ {
+ if (debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE))
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
break;
+ }
default:
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
}
@@ -106,6 +123,31 @@ nv40_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
return &mt->base;
}
+static struct pipe_texture *
+nv40_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
+ const unsigned *stride, struct pipe_buffer *pb)
+{
+ struct nv40_miptree *mt;
+
+ /* Only supports 2D, non-mipmapped textures for the moment */
+ if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
+ pt->depth[0] != 1)
+ return NULL;
+
+ mt = CALLOC_STRUCT(nv40_miptree);
+ if (!mt)
+ return NULL;
+
+ mt->base = *pt;
+ mt->base.refcount = 1;
+ mt->base.screen = pscreen;
+ mt->level[0].pitch = stride[0];
+ mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
+
+ pipe_buffer_reference(pscreen, &mt->buffer, pb);
+ return &mt->base;
+}
+
static void
nv40_miptree_release(struct pipe_screen *pscreen, struct pipe_texture **ppt)
{
@@ -124,8 +166,8 @@ nv40_miptree_release(struct pipe_screen *pscreen, struct pipe_texture **ppt)
}
if (mt->shadow_tex) {
- assert(mt->shadow_surface);
- pscreen->tex_surface_release(pscreen, &mt->shadow_surface);
+ if (mt->shadow_surface)
+ pscreen->tex_surface_release(pscreen, &mt->shadow_surface);
nv40_miptree_release(pscreen, &mt->shadow_tex);
}
@@ -188,6 +230,7 @@ void
nv40_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv40_miptree_create;
+ pscreen->texture_blanket = nv40_miptree_blanket;
pscreen->texture_release = nv40_miptree_release;
pscreen->get_tex_surface = nv40_miptree_surface_new;
pscreen->tex_surface_release = nv40_miptree_surface_del;
diff --git a/src/gallium/drivers/nv40/nv40_screen.c b/src/gallium/drivers/nv40/nv40_screen.c
index 41d342d27d..2372bc8441 100644
--- a/src/gallium/drivers/nv40/nv40_screen.c
+++ b/src/gallium/drivers/nv40/nv40_screen.c
@@ -136,6 +136,14 @@ nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
return FALSE;
}
+static struct pipe_buffer *
+nv40_surface_buffer(struct pipe_surface *surf)
+{
+ struct nv40_miptree *mt = (struct nv40_miptree *)surf->texture;
+
+ return mt->buffer;
+}
+
static void *
nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
unsigned flags )
@@ -143,7 +151,6 @@ nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
struct pipe_winsys *ws = screen->winsys;
struct pipe_surface *surface_to_map;
void *map;
- struct nv40_miptree *mt;
if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
@@ -171,8 +178,7 @@ nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
surface_to_map = surface;
assert(surface_to_map);
- mt = (struct nv40_miptree *)surface_to_map->texture;
- map = ws->buffer_map(ws, mt->buffer, flags);
+ map = ws->buffer_map(ws, nv40_surface_buffer(surface_to_map), flags);
if (!map)
return NULL;
@@ -184,7 +190,6 @@ nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
{
struct pipe_winsys *ws = screen->winsys;
struct pipe_surface *surface_to_unmap;
- struct nv40_miptree *mt;
/* TODO: Copy from shadow just before push buffer is flushed instead.
There are probably some programs that map/unmap excessively
@@ -201,16 +206,16 @@ nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
assert(surface_to_unmap);
- mt = (struct nv40_miptree *)surface_to_unmap->texture;
- ws->buffer_unmap(ws, mt->buffer);
+ ws->buffer_unmap(ws, nv40_surface_buffer(surface_to_unmap));
if (surface_to_unmap != surface) {
struct nv40_screen *nvscreen = nv40_screen(screen);
- nvscreen->nvws->surface_copy(nvscreen->nvws,
- surface, 0, 0,
- surface_to_unmap, 0, 0,
- surface->width, surface->height);
+ nvscreen->eng2d->copy(nvscreen->eng2d, surface, 0, 0,
+ surface_to_unmap, 0, 0,
+ surface->width, surface->height);
+
+ screen->tex_surface_release(screen, &surface_to_unmap);
}
}
@@ -243,6 +248,10 @@ nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
screen->nvws = nvws;
+ /* 2D engine setup */
+ screen->eng2d = nv04_surface_2d_init(nvws);
+ screen->eng2d->buf = nv40_surface_buffer;
+
/* 3D object */
switch (chipset & 0xf0) {
case 0x40:
diff --git a/src/gallium/drivers/nv40/nv40_screen.h b/src/gallium/drivers/nv40/nv40_screen.h
index c04a1275a0..4500aa0e5c 100644
--- a/src/gallium/drivers/nv40/nv40_screen.h
+++ b/src/gallium/drivers/nv40/nv40_screen.h
@@ -2,6 +2,7 @@
#define __NV40_SCREEN_H__
#include "pipe/p_screen.h"
+#include "nv04/nv04_surface_2d.h"
struct nv40_screen {
struct pipe_screen pipe;
@@ -11,6 +12,7 @@ struct nv40_screen {
unsigned cur_pctx;
/* HW graphics objects */
+ struct nv04_surface_2d *eng2d;
struct nouveau_grobj *curie;
struct nouveau_notifier *sync;
diff --git a/src/gallium/drivers/nv40/nv40_surface.c b/src/gallium/drivers/nv40/nv40_surface.c
index aa51d04051..c4a5fb20d9 100644
--- a/src/gallium/drivers/nv40/nv40_surface.c
+++ b/src/gallium/drivers/nv40/nv40_surface.c
@@ -30,7 +30,6 @@
#include "pipe/p_defines.h"
#include "pipe/internal/p_winsys_screen.h"
#include "pipe/p_inlines.h"
-
#include "util/u_tile.h"
static void
@@ -40,22 +39,18 @@ nv40_surface_copy(struct pipe_context *pipe, boolean do_flip,
unsigned width, unsigned height)
{
struct nv40_context *nv40 = nv40_context(pipe);
- struct nouveau_winsys *nvws = nv40->nvws;
+ struct nv04_surface_2d *eng2d = nv40->screen->eng2d;
if (do_flip) {
- /*XXX: This dodgyness will do for now for correctness. But,
- * need to investigate whether the 2D engine is able to
- * manage a flip (perhaps SIFM?), if not, use the 3D engine
- */
desty += height;
while (height--) {
- nvws->surface_copy(nvws, dest, destx, desty--, src,
- srcx, srcy++, width, 1);
+ eng2d->copy(eng2d, dest, destx, desty--, src,
+ srcx, srcy++, width, 1);
}
- } else {
- nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy,
- width, height);
+ return;
}
+
+ eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
@@ -64,9 +59,9 @@ nv40_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned height, unsigned value)
{
struct nv40_context *nv40 = nv40_context(pipe);
- struct nouveau_winsys *nvws = nv40->nvws;
+ struct nv04_surface_2d *eng2d = nv40->screen->eng2d;
- nvws->surface_fill(nvws, dest, destx, desty, width, height, value);
+ eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
diff --git a/src/gallium/drivers/nv40/nv40_vertprog.c b/src/gallium/drivers/nv40/nv40_vertprog.c
index 1392fe956f..0862386638 100644
--- a/src/gallium/drivers/nv40/nv40_vertprog.c
+++ b/src/gallium/drivers/nv40/nv40_vertprog.c
@@ -784,7 +784,7 @@ nv40_vertprog_translate(struct nv40_context *nv40,
imm = &parse.FullToken.FullImmediate;
assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
-// assert(imm->Immediate.Size == 4);
+ assert(imm->Immediate.NrTokens == 4 + 1);
vpc->imm[vpc->nr_imm++] =
constant(vpc, -1,
imm->u.ImmediateFloat32[0].Float,
diff --git a/src/gallium/drivers/nv50/nv50_clear.c b/src/gallium/drivers/nv50/nv50_clear.c
index 6380f397ea..f9bc3b53ca 100644
--- a/src/gallium/drivers/nv50/nv50_clear.c
+++ b/src/gallium/drivers/nv50/nv50_clear.c
@@ -31,6 +31,8 @@ nv50_clear(struct pipe_context *pipe, struct pipe_surface *ps,
unsigned clearValue)
{
struct nv50_context *nv50 = nv50_context(pipe);
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
struct pipe_framebuffer_state fb, s_fb = nv50->framebuffer;
struct pipe_scissor_state sc, s_sc = nv50->scissor;
unsigned dirty = nv50->dirty;
@@ -59,21 +61,21 @@ nv50_clear(struct pipe_context *pipe, struct pipe_surface *ps,
switch (ps->format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
- BEGIN_RING(tesla, 0x0d80, 4);
- OUT_RINGf (ubyte_to_float((clearValue >> 16) & 0xff));
- OUT_RINGf (ubyte_to_float((clearValue >> 8) & 0xff));
- OUT_RINGf (ubyte_to_float((clearValue >> 0) & 0xff));
- OUT_RINGf (ubyte_to_float((clearValue >> 24) & 0xff));
- BEGIN_RING(tesla, 0x19d0, 1);
- OUT_RING (0x3c);
+ BEGIN_RING(chan, tesla, 0x0d80, 4);
+ OUT_RINGf (chan, ubyte_to_float((clearValue >> 16) & 0xff));
+ OUT_RINGf (chan, ubyte_to_float((clearValue >> 8) & 0xff));
+ OUT_RINGf (chan, ubyte_to_float((clearValue >> 0) & 0xff));
+ OUT_RINGf (chan, ubyte_to_float((clearValue >> 24) & 0xff));
+ BEGIN_RING(chan, tesla, 0x19d0, 1);
+ OUT_RING (chan, 0x3c);
break;
case PIPE_FORMAT_Z24S8_UNORM:
- BEGIN_RING(tesla, 0x0d90, 1);
- OUT_RINGf ((float)(clearValue >> 8) * (1.0 / 16777215.0));
- BEGIN_RING(tesla, 0x0da0, 1);
- OUT_RING (clearValue & 0xff);
- BEGIN_RING(tesla, 0x19d0, 1);
- OUT_RING (0x03);
+ BEGIN_RING(chan, tesla, 0x0d90, 1);
+ OUT_RINGf (chan, (float)(clearValue >> 8) * (1.0 / 16777215.0));
+ BEGIN_RING(chan, tesla, 0x0da0, 1);
+ OUT_RING (chan, clearValue & 0xff);
+ BEGIN_RING(chan, tesla, 0x19d0, 1);
+ OUT_RING (chan, 0x03);
break;
default:
pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height,
diff --git a/src/gallium/drivers/nv50/nv50_context.c b/src/gallium/drivers/nv50/nv50_context.c
index 99776239d2..565a5da668 100644
--- a/src/gallium/drivers/nv50/nv50_context.c
+++ b/src/gallium/drivers/nv50/nv50_context.c
@@ -33,7 +33,7 @@ nv50_flush(struct pipe_context *pipe, unsigned flags,
{
struct nv50_context *nv50 = (struct nv50_context *)pipe;
- FIRE_RING(fence);
+ FIRE_RING(nv50->screen->nvws->channel);
}
static void
diff --git a/src/gallium/drivers/nv50/nv50_context.h b/src/gallium/drivers/nv50/nv50_context.h
index 6c9e18429a..1e9d45cb34 100644
--- a/src/gallium/drivers/nv50/nv50_context.h
+++ b/src/gallium/drivers/nv50/nv50_context.h
@@ -15,10 +15,6 @@
#include "nouveau/nouveau_gldefs.h"
#include "nouveau/nouveau_stateobj.h"
-#define NOUVEAU_PUSH_CONTEXT(ctx) \
- struct nv50_screen *ctx = nv50->screen
-#include "nouveau/nouveau_push.h"
-
#include "nv50_screen.h"
#include "nv50_program.h"
@@ -171,6 +167,11 @@ extern void nv50_init_query_functions(struct nv50_context *nv50);
extern void nv50_screen_init_miptree_functions(struct pipe_screen *pscreen);
+extern int
+nv50_surface_do_copy(struct nv50_screen *screen, struct pipe_surface *dst,
+ int dx, int dy, struct pipe_surface *src, int sx, int sy,
+ int w, int h);
+
/* nv50_draw.c */
extern struct draw_stage *nv50_draw_render_stage(struct nv50_context *nv50);
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c b/src/gallium/drivers/nv50/nv50_miptree.c
index c6e65c9816..91091d53f5 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -104,6 +104,31 @@ nv50_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *tmp)
return &mt->base;
}
+static struct pipe_texture *
+nv50_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
+ const unsigned *stride, struct pipe_buffer *pb)
+{
+ struct nv50_miptree *mt;
+
+ /* Only supports 2D, non-mipmapped textures for the moment */
+ if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
+ pt->depth[0] != 1)
+ return NULL;
+
+ mt = CALLOC_STRUCT(nv50_miptree);
+ if (!mt)
+ return NULL;
+
+ mt->base = *pt;
+ mt->base.refcount = 1;
+ mt->base.screen = pscreen;
+ mt->image_nr = 1;
+ mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
+
+ pipe_buffer_reference(pscreen, &mt->buffer, pb);
+ return &mt->base;
+}
+
static INLINE void
mark_dirty(uint32_t *flags, unsigned image)
{
@@ -141,7 +166,7 @@ void
nv50_miptree_sync(struct pipe_screen *pscreen, struct nv50_miptree *mt,
unsigned level, unsigned image)
{
- struct nouveau_winsys *nvws = nv50_screen(pscreen)->nvws;
+ struct nv50_screen *nvscreen = nv50_screen(pscreen);
struct nv50_miptree_level *lvl = &mt->level[level];
struct pipe_surface *dst, *src;
unsigned face = 0, zslice = 0;
@@ -172,7 +197,7 @@ nv50_miptree_sync(struct pipe_screen *pscreen, struct nv50_miptree *mt,
dst = pscreen->get_tex_surface(pscreen, &mt->base, face, level, zslice,
PIPE_BUFFER_USAGE_GPU_READ);
- nvws->surface_copy(nvws, dst, 0, 0, src, 0, 0, dst->width, dst->height);
+ nv50_surface_do_copy(nvscreen, dst, 0, 0, src, 0, 0, dst->width, dst->height);
pscreen->tex_surface_release(pscreen, &dst);
pscreen->tex_surface_release(pscreen, &src);
@@ -183,7 +208,7 @@ static void
nv50_miptree_sync_cpu(struct pipe_screen *pscreen, struct nv50_miptree *mt,
unsigned level, unsigned image)
{
- struct nouveau_winsys *nvws = nv50_screen(pscreen)->nvws;
+ struct nv50_screen *nvscreen = nv50_screen(pscreen);
struct nv50_miptree_level *lvl = &mt->level[level];
struct pipe_surface *dst, *src;
unsigned face = 0, zslice = 0;
@@ -204,7 +229,7 @@ nv50_miptree_sync_cpu(struct pipe_screen *pscreen, struct nv50_miptree *mt,
dst = pscreen->get_tex_surface(pscreen, &mt->base, face, level, zslice,
PIPE_BUFFER_USAGE_CPU_READ);
- nvws->surface_copy(nvws, dst, 0, 0, src, 0, 0, dst->width, dst->height);
+ nv50_surface_do_copy(nvscreen, dst, 0, 0, src, 0, 0, dst->width, dst->height);
pscreen->tex_surface_release(pscreen, &dst);
pscreen->tex_surface_release(pscreen, &src);
@@ -287,6 +312,7 @@ void
nv50_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv50_miptree_create;
+ pscreen->texture_blanket = nv50_miptree_blanket;
pscreen->texture_release = nv50_miptree_release;
pscreen->get_tex_surface = nv50_miptree_surface_new;
pscreen->tex_surface_release = nv50_miptree_surface_del;
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index b902c8cf53..14c5d47e79 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -1545,13 +1545,16 @@ static void
nv50_program_upload_data(struct nv50_context *nv50, float *map,
unsigned start, unsigned count)
{
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
+
while (count) {
unsigned nr = count > 2047 ? 2047 : count;
- BEGIN_RING(tesla, 0x00000f00, 1);
- OUT_RING ((NV50_CB_PMISC << 0) | (start << 8));
- BEGIN_RING(tesla, 0x40000f04, nr);
- OUT_RINGp (map, nr);
+ BEGIN_RING(chan, tesla, 0x00000f00, 1);
+ OUT_RING (chan, (NV50_CB_PMISC << 0) | (start << 8));
+ BEGIN_RING(chan, tesla, 0x40000f04, nr);
+ OUT_RINGp (chan, map, nr);
map += nr;
start += nr;
@@ -1598,6 +1601,8 @@ nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
static void
nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
{
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
struct pipe_winsys *ws = nv50->pipe.winsys;
struct nv50_program_exec *e;
struct nouveau_stateobj *so;
@@ -1664,14 +1669,14 @@ nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
nr = MIN2(count, 2047);
nr = MIN2(nvws->channel->pushbuf->remaining, nr);
if (nvws->channel->pushbuf->remaining < (nr + 3)) {
- FIRE_RING(NULL);
+ FIRE_RING(chan);
continue;
}
- BEGIN_RING(tesla, 0x0f00, 1);
- OUT_RING ((start << 8) | NV50_CB_PUPLOAD);
- BEGIN_RING(tesla, 0x40000f04, nr);
- OUT_RINGp (up + start, nr);
+ BEGIN_RING(chan, tesla, 0x0f00, 1);
+ OUT_RING (chan, (start << 8) | NV50_CB_PUPLOAD);
+ BEGIN_RING(chan, tesla, 0x40000f04, nr);
+ OUT_RINGp (chan, up + start, nr);
start += nr;
count -= nr;
diff --git a/src/gallium/drivers/nv50/nv50_query.c b/src/gallium/drivers/nv50/nv50_query.c
index 1b3a41340a..20745ceab8 100644
--- a/src/gallium/drivers/nv50/nv50_query.c
+++ b/src/gallium/drivers/nv50/nv50_query.c
@@ -71,12 +71,14 @@ static void
nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
{
struct nv50_context *nv50 = nv50_context(pipe);
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
struct nv50_query *q = nv50_query(pq);
- BEGIN_RING(tesla, 0x1530, 1);
- OUT_RING (1);
- BEGIN_RING(tesla, 0x1514, 1);
- OUT_RING (1);
+ BEGIN_RING(chan, tesla, 0x1530, 1);
+ OUT_RING (chan, 1);
+ BEGIN_RING(chan, tesla, 0x1514, 1);
+ OUT_RING (chan, 1);
q->ready = FALSE;
}
@@ -85,14 +87,17 @@ static void
nv50_query_end(struct pipe_context *pipe, struct pipe_query *pq)
{
struct nv50_context *nv50 = nv50_context(pipe);
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
struct nv50_query *q = nv50_query(pq);
- BEGIN_RING(tesla, 0x1b00, 4);
- OUT_RELOCh(q->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
- OUT_RELOCl(q->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
- OUT_RING (0x00000000);
- OUT_RING (0x0100f002);
- FIRE_RING (NULL);
+ WAIT_RING (chan, 5);
+ BEGIN_RING(chan, tesla, 0x1b00, 4);
+ OUT_RELOCh(chan, q->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ OUT_RELOCl(chan, q->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ OUT_RING (chan, 0x00000000);
+ OUT_RING (chan, 0x0100f002);
+ FIRE_RING (chan);
}
static boolean
diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c
index 6cddddacd5..58d7a621a8 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -173,6 +173,14 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
screen->nvws = nvws;
+ /* 2D object */
+ ret = nvws->grobj_alloc(nvws, NV50_2D, &screen->eng2d);
+ if (ret) {
+ NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
+ nv50_screen_destroy(&screen->pipe);
+ return NULL;
+ }
+
/* 3D object */
if ((chipset & 0xf0) != 0x50 && (chipset & 0xf0) != 0x80) {
NOUVEAU_ERR("Not a G8x chipset\n");
@@ -218,6 +226,22 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
return NULL;
}
+ /* Static 2D init */
+ so = so_new(64, 0);
+ so_method(so, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
+ so_data (so, screen->sync->handle);
+ so_data (so, screen->nvws->channel->vram->handle);
+ so_data (so, screen->nvws->channel->vram->handle);
+ so_data (so, screen->nvws->channel->vram->handle);
+ so_method(so, screen->eng2d, NV50_2D_OPERATION, 1);
+ so_data (so, NV50_2D_OPERATION_SRCCOPY);
+ so_method(so, screen->eng2d, 0x0290, 1);
+ so_data (so, 0);
+ so_method(so, screen->eng2d, 0x0888, 1);
+ so_data (so, 1);
+ so_emit(nvws, so);
+ so_ref(NULL, &so);
+
/* Static tesla init */
so = so_new(256, 20);
diff --git a/src/gallium/drivers/nv50/nv50_screen.h b/src/gallium/drivers/nv50/nv50_screen.h
index 400ddcef06..c888ca071c 100644
--- a/src/gallium/drivers/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nv50/nv50_screen.h
@@ -11,6 +11,7 @@ struct nv50_screen {
unsigned cur_pctx;
struct nouveau_grobj *tesla;
+ struct nouveau_grobj *eng2d;
struct nouveau_notifier *sync;
struct pipe_buffer *constbuf;
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c
index 602d76ac74..948112ffa9 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -47,9 +47,11 @@ nv50_state_validate_fb(struct nv50_context *nv50)
so_method(so, tesla, NV50TCL_RT_ADDRESS_HIGH(i), 5);
so_reloc (so, nv50_surface_buffer(fb->cbufs[i]), fb->cbufs[i]->offset,
- NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH, 0, 0);
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH |
+ NOUVEAU_BO_RDWR, 0, 0);
so_reloc (so, nv50_surface_buffer(fb->cbufs[i]), fb->cbufs[i]->offset,
- NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW, 0, 0);
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW |
+ NOUVEAU_BO_RDWR, 0, 0);
switch (fb->cbufs[i]->format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
so_data(so, 0xcf);
@@ -82,9 +84,11 @@ nv50_state_validate_fb(struct nv50_context *nv50)
so_method(so, tesla, NV50TCL_ZETA_ADDRESS_HIGH, 5);
so_reloc (so, nv50_surface_buffer(fb->zsbuf), fb->zsbuf->offset,
- NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH, 0, 0);
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH |
+ NOUVEAU_BO_RDWR, 0, 0);
so_reloc (so, nv50_surface_buffer(fb->zsbuf), fb->zsbuf->offset,
- NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW, 0, 0);
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW |
+ NOUVEAU_BO_RDWR, 0, 0);
switch (fb->zsbuf->format) {
case PIPE_FORMAT_Z24S8_UNORM:
so_data(so, 0x16);
diff --git a/src/gallium/drivers/nv50/nv50_surface.c b/src/gallium/drivers/nv50/nv50_surface.c
index 8ebbc84817..f2dd2eb30b 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -20,6 +20,9 @@
* SOFTWARE.
*/
+#define __NOUVEAU_PUSH_H__
+#include <stdint.h>
+#include "nouveau/nouveau_pushbuf.h"
#include "nv50_context.h"
#include "pipe/p_defines.h"
#include "pipe/internal/p_winsys_screen.h"
@@ -27,6 +30,118 @@
#include "util/u_tile.h"
+static INLINE int
+nv50_format(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ case PIPE_FORMAT_Z24S8_UNORM:
+ return NV50_2D_DST_FORMAT_32BPP;
+ case PIPE_FORMAT_X8R8G8B8_UNORM:
+ return NV50_2D_DST_FORMAT_24BPP;
+ case PIPE_FORMAT_R5G6B5_UNORM:
+ return NV50_2D_DST_FORMAT_16BPP;
+ case PIPE_FORMAT_A8_UNORM:
+ return NV50_2D_DST_FORMAT_8BPP;
+ default:
+ return -1;
+ }
+}
+
+static int
+nv50_surface_set(struct nv50_screen *screen, struct pipe_surface *ps, int dst)
+{
+ struct nouveau_channel *chan = screen->nvws->channel;
+ struct nouveau_grobj *eng2d = screen->eng2d;
+ struct nouveau_bo *bo;
+ int format, mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
+ int flags = NOUVEAU_BO_VRAM | (dst ? NOUVEAU_BO_WR : NOUVEAU_BO_RD);
+
+ bo = screen->nvws->get_bo(nv50_miptree(ps->texture)->buffer);
+ if (!bo)
+ return 1;
+
+ format = nv50_format(ps->format);
+ if (format < 0)
+ return 1;
+
+ if (!bo->tiled) {
+ BEGIN_RING(chan, eng2d, mthd, 2);
+ OUT_RING (chan, format);
+ OUT_RING (chan, 1);
+ BEGIN_RING(chan, eng2d, mthd + 0x14, 5);
+ OUT_RING (chan, ps->stride);
+ OUT_RING (chan, ps->width);
+ OUT_RING (chan, ps->height);
+ OUT_RELOCh(chan, bo, ps->offset, flags);
+ OUT_RELOCl(chan, bo, ps->offset, flags);
+ } else {
+ BEGIN_RING(chan, eng2d, mthd, 5);
+ OUT_RING (chan, format);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, 1);
+ OUT_RING (chan, 0);
+ BEGIN_RING(chan, eng2d, mthd + 0x18, 4);
+ OUT_RING (chan, ps->width);
+ OUT_RING (chan, ps->height);
+ OUT_RELOCh(chan, bo, ps->offset, flags);
+ OUT_RELOCl(chan, bo, ps->offset, flags);
+ }
+
+#if 0
+ if (dst) {
+ BEGIN_RING(chan, eng2d, NV50_2D_CLIP_X, 4);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, surf->width);
+ OUT_RING (chan, surf->height);
+ }
+#endif
+
+ return 0;
+}
+
+int
+nv50_surface_do_copy(struct nv50_screen *screen, struct pipe_surface *dst,
+ int dx, int dy, struct pipe_surface *src, int sx, int sy,
+ int w, int h)
+{
+ struct nouveau_channel *chan = screen->nvws->channel;
+ struct nouveau_grobj *eng2d = screen->eng2d;
+ int ret;
+
+ WAIT_RING (chan, 32);
+
+ ret = nv50_surface_set(screen, dst, 1);
+ if (ret)
+ return ret;
+
+ ret = nv50_surface_set(screen, src, 0);
+ if (ret)
+ return ret;
+
+ BEGIN_RING(chan, eng2d, 0x088c, 1);
+ OUT_RING (chan, 0);
+ BEGIN_RING(chan, eng2d, NV50_2D_BLIT_DST_X, 4);
+ OUT_RING (chan, dx);
+ OUT_RING (chan, dy);
+ OUT_RING (chan, w);
+ OUT_RING (chan, h);
+ BEGIN_RING(chan, eng2d, 0x08c0, 4);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, 1);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, 1);
+ BEGIN_RING(chan, eng2d, 0x08d0, 4);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, sx);
+ OUT_RING (chan, 0);
+ OUT_RING (chan, sy);
+
+ return 0;
+}
+
static void
nv50_surface_copy(struct pipe_context *pipe, boolean flip,
struct pipe_surface *dest, unsigned destx, unsigned desty,
@@ -34,17 +149,19 @@ nv50_surface_copy(struct pipe_context *pipe, boolean flip,
unsigned width, unsigned height)
{
struct nv50_context *nv50 = (struct nv50_context *)pipe;
- struct nouveau_winsys *nvws = nv50->screen->nvws;
+ struct nv50_screen *screen = nv50->screen;
+
+ assert(src->format == dest->format);
if (flip) {
desty += height;
while (height--) {
- nvws->surface_copy(nvws, dest, destx, desty--, src,
- srcx, srcy++, width, 1);
+ nv50_surface_do_copy(screen, dest, destx, desty--, src,
+ srcx, srcy++, width, 1);
}
} else {
- nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy,
- width, height);
+ nv50_surface_do_copy(screen, dest, destx, desty, src, srcx,
+ srcy, width, height);
}
}
@@ -54,9 +171,30 @@ nv50_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned height, unsigned value)
{
struct nv50_context *nv50 = (struct nv50_context *)pipe;
- struct nouveau_winsys *nvws = nv50->screen->nvws;
+ struct nv50_screen *screen = nv50->screen;
+ struct nouveau_channel *chan = screen->nvws->channel;
+ struct nouveau_grobj *eng2d = screen->eng2d;
+ int format, ret;
+
+ format = nv50_format(dest->format);
+ if (format < 0)
+ return;
+
+ WAIT_RING (chan, 32);
+
+ ret = nv50_surface_set(screen, dest, 1);
+ if (ret)
+ return;
- nvws->surface_fill(nvws, dest, destx, desty, width, height, value);
+ BEGIN_RING(chan, eng2d, 0x0580, 3);
+ OUT_RING (chan, 4);
+ OUT_RING (chan, format);
+ OUT_RING (chan, value);
+ BEGIN_RING(chan, eng2d, NV50_2D_RECT_X1, 4);
+ OUT_RING (chan, destx);
+ OUT_RING (chan, desty);
+ OUT_RING (chan, width);
+ OUT_RING (chan, height);
}
static void *
diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c
index 239407c92b..675f9b20cb 100644
--- a/src/gallium/drivers/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nv50/nv50_tex.c
@@ -117,13 +117,15 @@ nv50_tex_construct(struct nouveau_stateobj *so, struct nv50_miptree *mt)
return 1;
}
- so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW, 0, 0);
+ so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW |
+ NOUVEAU_BO_RD, 0, 0);
so_data (so, 0xd0005000);
so_data (so, 0x00300000);
so_data (so, mt->base.width[0]);
so_data (so, (mt->base.depth[0] << 16) | mt->base.height[0]);
so_data (so, 0x03000000);
- so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH, 0, 0);
+ so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH |
+ NOUVEAU_BO_RD, 0, 0);
return 0;
}
diff --git a/src/gallium/drivers/nv50/nv50_vbo.c b/src/gallium/drivers/nv50/nv50_vbo.c
index c482a4c241..0c970adb03 100644
--- a/src/gallium/drivers/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nv50/nv50_vbo.c
@@ -53,25 +53,27 @@ nv50_draw_arrays(struct pipe_context *pipe, unsigned mode, unsigned start,
unsigned count)
{
struct nv50_context *nv50 = nv50_context(pipe);
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
nv50_state_validate(nv50);
- BEGIN_RING(tesla, 0x142c, 1);
- OUT_RING (0);
- BEGIN_RING(tesla, 0x142c, 1);
- OUT_RING (0);
- BEGIN_RING(tesla, 0x1440, 1);
- OUT_RING (0);
- BEGIN_RING(tesla, 0x1334, 1);
- OUT_RING (0);
-
- BEGIN_RING(tesla, NV50TCL_VERTEX_BEGIN, 1);
- OUT_RING (nv50_prim(mode));
- BEGIN_RING(tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
- OUT_RING (start);
- OUT_RING (count);
- BEGIN_RING(tesla, NV50TCL_VERTEX_END, 1);
- OUT_RING (0);
+ BEGIN_RING(chan, tesla, 0x142c, 1);
+ OUT_RING (chan, 0);
+ BEGIN_RING(chan, tesla, 0x142c, 1);
+ OUT_RING (chan, 0);
+ BEGIN_RING(chan, tesla, 0x1440, 1);
+ OUT_RING (chan, 0);
+ BEGIN_RING(chan, tesla, 0x1334, 1);
+ OUT_RING (chan, 0);
+
+ BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
+ OUT_RING (chan, nv50_prim(mode));
+ BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
+ OUT_RING (chan, start);
+ OUT_RING (chan, count);
+ BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
+ OUT_RING (chan, 0);
pipe->flush(pipe, 0, NULL);
return TRUE;
@@ -81,11 +83,14 @@ static INLINE void
nv50_draw_elements_inline_u08(struct nv50_context *nv50, uint8_t *map,
unsigned start, unsigned count)
{
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
+
map += start;
if (count & 1) {
- BEGIN_RING(tesla, 0x15e8, 1);
- OUT_RING (map[0]);
+ BEGIN_RING(chan, tesla, 0x15e8, 1);
+ OUT_RING (chan, map[0]);
map++;
count--;
}
@@ -94,9 +99,9 @@ nv50_draw_elements_inline_u08(struct nv50_context *nv50, uint8_t *map,
unsigned nr = count > 2046 ? 2046 : count;
int i;
- BEGIN_RING(tesla, 0x400015f0, nr >> 1);
+ BEGIN_RING(chan, tesla, 0x400015f0, nr >> 1);
for (i = 0; i < nr; i += 2)
- OUT_RING ((map[1] << 16) | map[0]);
+ OUT_RING (chan, (map[1] << 16) | map[0]);
count -= nr;
map += nr;
@@ -107,11 +112,14 @@ static INLINE void
nv50_draw_elements_inline_u16(struct nv50_context *nv50, uint16_t *map,
unsigned start, unsigned count)
{
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
+
map += start;
if (count & 1) {
- BEGIN_RING(tesla, 0x15e8, 1);
- OUT_RING (map[0]);
+ BEGIN_RING(chan, tesla, 0x15e8, 1);
+ OUT_RING (chan, map[0]);
map++;
count--;
}
@@ -120,9 +128,9 @@ nv50_draw_elements_inline_u16(struct nv50_context *nv50, uint16_t *map,
unsigned nr = count > 2046 ? 2046 : count;
int i;
- BEGIN_RING(tesla, 0x400015f0, nr >> 1);
+ BEGIN_RING(chan, tesla, 0x400015f0, nr >> 1);
for (i = 0; i < nr; i += 2)
- OUT_RING ((map[1] << 16) | map[0]);
+ OUT_RING (chan, (map[1] << 16) | map[0]);
count -= nr;
map += nr;
@@ -133,13 +141,16 @@ static INLINE void
nv50_draw_elements_inline_u32(struct nv50_context *nv50, uint8_t *map,
unsigned start, unsigned count)
{
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
+
map += start;
while (count) {
unsigned nr = count > 2047 ? 2047 : count;
- BEGIN_RING(tesla, 0x400015e8, nr);
- OUT_RINGp (map, nr);
+ BEGIN_RING(chan, tesla, 0x400015e8, nr);
+ OUT_RINGp (chan, map, nr);
count -= nr;
map += nr;
@@ -152,18 +163,20 @@ nv50_draw_elements(struct pipe_context *pipe,
unsigned mode, unsigned start, unsigned count)
{
struct nv50_context *nv50 = nv50_context(pipe);
+ struct nouveau_channel *chan = nv50->screen->nvws->channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
struct pipe_winsys *ws = pipe->winsys;
void *map = ws->buffer_map(ws, indexBuffer, PIPE_BUFFER_USAGE_CPU_READ);
nv50_state_validate(nv50);
- BEGIN_RING(tesla, 0x142c, 1);
- OUT_RING (0);
- BEGIN_RING(tesla, 0x142c, 1);
- OUT_RING (0);
+ BEGIN_RING(chan, tesla, 0x142c, 1);
+ OUT_RING (chan, 0);
+ BEGIN_RING(chan, tesla, 0x142c, 1);
+ OUT_RING (chan, 0);
- BEGIN_RING(tesla, NV50TCL_VERTEX_BEGIN, 1);
- OUT_RING (nv50_prim(mode));
+ BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
+ OUT_RING (chan, nv50_prim(mode));
switch (indexSize) {
case 1:
nv50_draw_elements_inline_u08(nv50, map, start, count);
@@ -177,8 +190,8 @@ nv50_draw_elements(struct pipe_context *pipe,
default:
assert(0);
}
- BEGIN_RING(tesla, NV50TCL_VERTEX_END, 1);
- OUT_RING (0);
+ BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
+ OUT_RING (chan, 0);
pipe->flush(pipe, 0, NULL);
return TRUE;
diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile
new file mode 100644
index 0000000000..85b3f15ac5
--- /dev/null
+++ b/src/gallium/drivers/r300/Makefile
@@ -0,0 +1,22 @@
+TOP = ../../../..
+include $(TOP)/configs/current
+
+LIBNAME = r300
+
+C_SOURCES = \
+ r300_chipset.c \
+ r300_clear.c \
+ r300_context.c \
+ r300_emit.c \
+ r300_flush.c \
+ r300_screen.c \
+ r300_state.c \
+ r300_state_derived.c \
+ r300_state_shader.c \
+ r300_surface.c \
+ r300_swtcl_emit.c \
+ r300_texture.c
+
+include ../../Makefile.template
+
+symlinks:
diff --git a/src/gallium/drivers/r300/SConscript b/src/gallium/drivers/r300/SConscript
new file mode 100644
index 0000000000..18684c3e7f
--- /dev/null
+++ b/src/gallium/drivers/r300/SConscript
@@ -0,0 +1,17 @@
+Import('*')
+
+env = env.Clone()
+
+r300 = env.ConvenienceLibrary(
+ target = 'r300',
+ source = [
+ 'r300_blit.c',
+ 'r300_clear.c',
+ 'r300_context.c',
+ 'r300_screen.c',
+ 'r300_state.c',
+ 'r300_surface.c',
+ ])
+
+Export('r300')
+
diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c
new file mode 100644
index 0000000000..794fa2b9b8
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_chipset.c
@@ -0,0 +1,348 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_chipset.h"
+#include "pipe/p_debug.h"
+
+/* r300_chipset: A file all to itself for deducing the various properties of
+ * Radeons. */
+
+/* Parse a PCI ID and fill an r300_capabilities struct with information. */
+void r300_parse_chipset(struct r300_capabilities* caps)
+{
+ /* Reasonable defaults */
+ caps->has_tcl = TRUE;
+ caps->is_r500 = FALSE;
+ caps->num_vert_fpus = 4;
+
+
+ /* Note: These are not ordered by PCI ID. I leave that task to GCC,
+ * which will perform the ordering while collating jump tables. Instead,
+ * I've tried to group them according to capabilities and age. */
+ switch (caps->pci_id) {
+ case 0x4144:
+ caps->family = CHIP_FAMILY_R300;
+ break;
+
+ case 0x4145:
+ case 0x4146:
+ case 0x4147:
+ case 0x4E44:
+ case 0x4E45:
+ case 0x4E46:
+ case 0x4E47:
+ caps->family = CHIP_FAMILY_R300;
+ break;
+
+ case 0x4150:
+ case 0x4151:
+ case 0x4152:
+ case 0x4153:
+ case 0x4154:
+ case 0x4155:
+ case 0x4156:
+ case 0x4E50:
+ case 0x4E51:
+ case 0x4E52:
+ case 0x4E53:
+ case 0x4E54:
+ case 0x4E56:
+ caps->family = CHIP_FAMILY_RV350;
+ break;
+
+ case 0x4148:
+ case 0x4149:
+ case 0x414A:
+ case 0x414B:
+ case 0x4E48:
+ case 0x4E49:
+ case 0x4E4B:
+ caps->family = CHIP_FAMILY_R350;
+ break;
+
+ case 0x4E4A:
+ caps->family = CHIP_FAMILY_R360;
+ break;
+
+ case 0x5460:
+ case 0x5462:
+ case 0x5464:
+ case 0x5B60:
+ case 0x5B62:
+ case 0x5B63:
+ case 0x5B64:
+ case 0x5B65:
+ caps->family = CHIP_FAMILY_RV370;
+ break;
+
+ case 0x3150:
+ case 0x3152:
+ case 0x3154:
+ case 0x3E50:
+ case 0x3E54:
+ caps->family = CHIP_FAMILY_RV380;
+ break;
+
+ case 0x4A48:
+ case 0x4A49:
+ case 0x4A4A:
+ case 0x4A4B:
+ case 0x4A4C:
+ case 0x4A4D:
+ case 0x4A4E:
+ case 0x4A4F:
+ case 0x4A50:
+ case 0x4A54:
+ caps->family = CHIP_FAMILY_R420;
+ caps->num_vert_fpus = 6;
+ break;
+
+ case 0x5548:
+ case 0x5549:
+ case 0x554A:
+ case 0x554B:
+ case 0x5550:
+ case 0x5551:
+ case 0x5552:
+ case 0x5554:
+ case 0x5D57:
+ caps->family = CHIP_FAMILY_R423;
+ caps->num_vert_fpus = 6;
+ break;
+
+ case 0x554C:
+ case 0x554D:
+ case 0x554E:
+ case 0x554F:
+ case 0x5D48:
+ case 0x5D49:
+ case 0x5D4A:
+ caps->family = CHIP_FAMILY_R430;
+ caps->num_vert_fpus = 6;
+ break;
+
+ case 0x5D4C:
+ case 0x5D4D:
+ case 0x5D4E:
+ case 0x5D4F:
+ case 0x5D50:
+ case 0x5D52:
+ caps->family = CHIP_FAMILY_R480;
+ caps->num_vert_fpus = 6;
+ break;
+
+ case 0x4B49:
+ case 0x4B4A:
+ case 0x4B4B:
+ case 0x4B4C:
+ caps->family = CHIP_FAMILY_R481;
+ caps->num_vert_fpus = 6;
+ break;
+
+ case 0x5E4C:
+ case 0x5E4F:
+ case 0x564A:
+ case 0x564B:
+ case 0x564F:
+ case 0x5652:
+ case 0x5653:
+ case 0x5657:
+ case 0x5E48:
+ case 0x5E4A:
+ case 0x5E4B:
+ case 0x5E4D:
+ caps->family = CHIP_FAMILY_RV410;
+ caps->num_vert_fpus = 6;
+ break;
+
+ case 0x5954:
+ case 0x5955:
+ caps->family = CHIP_FAMILY_RS480;
+ caps->has_tcl = FALSE;
+ break;
+
+ case 0x5974:
+ case 0x5975:
+ caps->family = CHIP_FAMILY_RS482;
+ caps->has_tcl = FALSE;
+ break;
+
+ case 0x5A41:
+ case 0x5A42:
+ caps->family = CHIP_FAMILY_RS400;
+ caps->has_tcl = FALSE;
+ break;
+
+ case 0x5A61:
+ case 0x5A62:
+ caps->family = CHIP_FAMILY_RC410;
+ caps->has_tcl = FALSE;
+ break;
+
+ case 0x791E:
+ case 0x791F:
+ caps->family = CHIP_FAMILY_RS690;
+ caps->has_tcl = FALSE;
+ break;
+
+ case 0x796C:
+ case 0x796D:
+ case 0x796E:
+ case 0x796F:
+ caps->family = CHIP_FAMILY_RS740;
+ caps->has_tcl = FALSE;
+ break;
+
+ case 0x7100:
+ case 0x7101:
+ case 0x7102:
+ case 0x7103:
+ case 0x7104:
+ case 0x7105:
+ case 0x7106:
+ case 0x7108:
+ case 0x7109:
+ case 0x710A:
+ case 0x710B:
+ case 0x710C:
+ case 0x710E:
+ case 0x710F:
+ caps->family = CHIP_FAMILY_R520;
+ caps->num_vert_fpus = 8;
+ caps->is_r500 = TRUE;
+ break;
+
+ case 0x7140:
+ case 0x7141:
+ case 0x7142:
+ case 0x7143:
+ case 0x7144:
+ case 0x7145:
+ case 0x7146:
+ case 0x7147:
+ case 0x7149:
+ case 0x714A:
+ case 0x714B:
+ case 0x714C:
+ case 0x714D:
+ case 0x714E:
+ case 0x714F:
+ case 0x7151:
+ case 0x7152:
+ case 0x7153:
+ case 0x715E:
+ case 0x715F:
+ case 0x7180:
+ case 0x7181:
+ case 0x7183:
+ case 0x7186:
+ case 0x7187:
+ case 0x7188:
+ case 0x718A:
+ case 0x718B:
+ case 0x718C:
+ case 0x718D:
+ case 0x718F:
+ case 0x7193:
+ case 0x7196:
+ case 0x719B:
+ case 0x719F:
+ case 0x7200:
+ case 0x7210:
+ case 0x7211:
+ caps->family = CHIP_FAMILY_RV515;
+ caps->num_vert_fpus = 2;
+ caps->is_r500 = TRUE;
+ break;
+
+ case 0x71C0:
+ case 0x71C1:
+ case 0x71C2:
+ case 0x71C3:
+ case 0x71C4:
+ case 0x71C5:
+ case 0x71C6:
+ case 0x71C7:
+ case 0x71CD:
+ case 0x71CE:
+ case 0x71D2:
+ case 0x71D4:
+ case 0x71D5:
+ case 0x71D6:
+ case 0x71DA:
+ case 0x71DE:
+ caps->family = CHIP_FAMILY_RV530;
+ caps->num_vert_fpus = 5;
+ caps->is_r500 = TRUE;
+ break;
+
+ case 0x7240:
+ case 0x7243:
+ case 0x7244:
+ case 0x7245:
+ case 0x7246:
+ case 0x7247:
+ case 0x7248:
+ case 0x7249:
+ case 0x724A:
+ case 0x724B:
+ case 0x724C:
+ case 0x724D:
+ case 0x724E:
+ case 0x724F:
+ case 0x7284:
+ caps->family = CHIP_FAMILY_R580;
+ caps->num_vert_fpus = 8;
+ caps->is_r500 = TRUE;
+ break;
+
+ case 0x7280:
+ caps->family = CHIP_FAMILY_RV570;
+ caps->num_vert_fpus = 5;
+ caps->is_r500 = TRUE;
+ break;
+
+ case 0x7281:
+ case 0x7283:
+ case 0x7287:
+ case 0x7288:
+ case 0x7289:
+ case 0x728B:
+ case 0x728C:
+ case 0x7290:
+ case 0x7291:
+ case 0x7293:
+ case 0x7297:
+ caps->family = CHIP_FAMILY_RV560;
+ caps->num_vert_fpus = 5;
+ caps->is_r500 = TRUE;
+ break;
+
+ default:
+ debug_printf("r300: Warning: Unknown chipset 0x%x\n",
+ caps->pci_id);
+ break;
+ }
+
+ /* XXX SW TCL is broken so no forcing it off right now
+ caps->has_tcl = FALSE; */
+}
diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h
new file mode 100644
index 0000000000..a9cd372ec5
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_chipset.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_CHIPSET_H
+#define R300_CHIPSET_H
+
+#include "pipe/p_compiler.h"
+
+/* Structure containing all the possible information about a specific Radeon
+ * in the R3xx, R4xx, and R5xx families. */
+struct r300_capabilities {
+ /* PCI ID */
+ uint32_t pci_id;
+ /* Chipset family */
+ int family;
+ /* The number of vertex floating-point units */
+ int num_vert_fpus;
+ /* The number of fragment pipes */
+ int num_frag_pipes;
+ /* Whether or not TCL is physically present */
+ boolean has_tcl;
+ /* Whether or not this is an RV515 or newer; R500s have many differences
+ * that require extra consideration, compared to their R3xx cousins:
+ * - Extra bit of width and height on texture sizes
+ * - Blend color is split across two registers
+ * - Universal Shader (US) block used for fragment shaders */
+ boolean is_r500;
+};
+
+/* Enumerations for legibility and telling which card we're running on. */
+enum {
+ CHIP_FAMILY_R300 = 0,
+ CHIP_FAMILY_R350,
+ CHIP_FAMILY_R360,
+ CHIP_FAMILY_RV350,
+ CHIP_FAMILY_RV370,
+ CHIP_FAMILY_RV380,
+ CHIP_FAMILY_R420,
+ CHIP_FAMILY_R423,
+ CHIP_FAMILY_R430,
+ CHIP_FAMILY_R480,
+ CHIP_FAMILY_R481,
+ CHIP_FAMILY_RV410,
+ CHIP_FAMILY_RS400,
+ CHIP_FAMILY_RC410,
+ CHIP_FAMILY_RS480,
+ CHIP_FAMILY_RS482,
+ CHIP_FAMILY_RS690,
+ CHIP_FAMILY_RS740,
+ CHIP_FAMILY_RV515,
+ CHIP_FAMILY_R520,
+ CHIP_FAMILY_RV530,
+ CHIP_FAMILY_R580,
+ CHIP_FAMILY_RV560,
+ CHIP_FAMILY_RV570
+};
+
+void r300_parse_chipset(struct r300_capabilities* caps);
+
+#endif /* R300_CHIPSET_H */
diff --git a/src/gallium/drivers/r300/r300_clear.c b/src/gallium/drivers/r300/r300_clear.c
new file mode 100644
index 0000000000..fd28437aaa
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_clear.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_clear.h"
+
+/* This gets its own file because Intel's is in its own file.
+ * I assume there's a good reason. */
+void r300_clear(struct pipe_context* pipe,
+ struct pipe_surface* ps,
+ unsigned color)
+{
+ pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height, color);
+ ps->status = PIPE_SURFACE_STATUS_DEFINED;
+} \ No newline at end of file
diff --git a/src/gallium/drivers/r300/r300_clear.h b/src/gallium/drivers/r300/r300_clear.h
new file mode 100644
index 0000000000..e24a0690c9
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_clear.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "pipe/p_context.h"
+
+void r300_clear(struct pipe_context* pipe,
+ struct pipe_surface* ps,
+ unsigned color);
diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
new file mode 100644
index 0000000000..37dc9e86d6
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_context.h"
+
+static boolean r300_draw_range_elements(struct pipe_context* pipe,
+ struct pipe_buffer* indexBuffer,
+ unsigned indexSize,
+ unsigned minIndex,
+ unsigned maxIndex,
+ unsigned mode,
+ unsigned start,
+ unsigned count)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ int i;
+
+ if (r300->dirty_state) {
+ r300_update_derived_state(r300);
+ r300_emit_dirty_state(r300);
+ }
+
+ for (i = 0; i < r300->vertex_buffer_count; i++) {
+ void* buf = pipe_buffer_map(pipe->screen,
+ r300->vertex_buffers[i].buffer,
+ PIPE_BUFFER_USAGE_CPU_READ);
+ draw_set_mapped_vertex_buffer(r300->draw, i, buf);
+ }
+
+ if (indexBuffer) {
+ void* indices = pipe_buffer_map(pipe->screen, indexBuffer,
+ PIPE_BUFFER_USAGE_CPU_READ);
+ draw_set_mapped_element_buffer_range(r300->draw, indexSize,
+ minIndex, maxIndex, indices);
+ } else {
+ draw_set_mapped_element_buffer(r300->draw, 0, NULL);
+ }
+
+ draw_set_mapped_constant_buffer(r300->draw,
+ r300->shader_constants[PIPE_SHADER_VERTEX].constants,
+ r300->shader_constants[PIPE_SHADER_VERTEX].user_count *
+ (sizeof(float) * 4));
+
+ /* Abandon all hope, ye who enter here. */
+ draw_arrays(r300->draw, mode, start, count);
+
+ for (i = 0; i < r300->vertex_buffer_count; i++) {
+ pipe_buffer_unmap(pipe->screen, r300->vertex_buffers[i].buffer);
+ draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
+ }
+
+ if (indexBuffer) {
+ pipe_buffer_unmap(pipe->screen, indexBuffer);
+ draw_set_mapped_element_buffer_range(r300->draw, 0, start,
+ start + count - 1, NULL);
+ }
+
+ return true;
+}
+
+static boolean r300_draw_elements(struct pipe_context* pipe,
+ struct pipe_buffer* indexBuffer,
+ unsigned indexSize, unsigned mode,
+ unsigned start, unsigned count)
+{
+ return r300_draw_range_elements(pipe, indexBuffer, indexSize, 0, ~0,
+ mode, start, count);
+}
+
+static boolean r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
+ unsigned start, unsigned count)
+{
+ return r300_draw_elements(pipe, NULL, 0, mode, start, count);
+}
+
+static void r300_destroy_context(struct pipe_context* context) {
+ struct r300_context* r300 = r300_context(context);
+
+ draw_destroy(r300->draw);
+
+ FREE(r300->blend_color_state);
+ FREE(r300->scissor_state);
+ FREE(r300);
+}
+
+struct pipe_context* r300_create_context(struct pipe_screen* screen,
+ struct pipe_winsys* winsys,
+ struct r300_winsys* r300_winsys)
+{
+ struct r300_context* r300 = CALLOC_STRUCT(r300_context);
+
+ if (!r300)
+ return NULL;
+
+ r300->winsys = r300_winsys;
+ r300->context.winsys = winsys;
+ r300->context.screen = r300_create_screen(winsys, r300_winsys);
+
+ r300->context.destroy = r300_destroy_context;
+
+ r300->context.clear = r300_clear;
+
+ r300->context.draw_arrays = r300_draw_arrays;
+ r300->context.draw_elements = r300_draw_elements;
+ r300->context.draw_range_elements = r300_draw_range_elements;
+
+ r300->draw = draw_create();
+ draw_set_rasterize_stage(r300->draw, r300_draw_swtcl_stage(r300));
+
+ r300->blend_color_state = CALLOC_STRUCT(r300_blend_color_state);
+ r300->scissor_state = CALLOC_STRUCT(r300_scissor_state);
+
+ r300_init_flush_functions(r300);
+
+ r300_init_surface_functions(r300);
+
+ r300_init_state_functions(r300);
+
+ r300->dirty_state = R300_NEW_KITCHEN_SINK;
+ r300->dirty_hw++;
+
+ return &r300->context;
+}
diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
new file mode 100644
index 0000000000..a3727c8fb4
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_CONTEXT_H
+#define R300_CONTEXT_H
+
+#include "draw/draw_context.h"
+#include "draw/draw_vertex.h"
+#include "pipe/p_context.h"
+#include "tgsi/tgsi_scan.h"
+#include "util/u_memory.h"
+
+#include "r300_clear.h"
+#include "r300_screen.h"
+#include "r300_winsys.h"
+
+struct r300_blend_state {
+ uint32_t blend_control; /* R300_RB3D_CBLEND: 0x4e04 */
+ uint32_t alpha_blend_control; /* R300_RB3D_ABLEND: 0x4e08 */
+ uint32_t rop; /* R300_RB3D_ROPCNTL: 0x4e18 */
+ uint32_t dither; /* R300_RB3D_DITHER_CTL: 0x4e50 */
+};
+
+struct r300_blend_color_state {
+ /* RV515 and earlier */
+ uint32_t blend_color; /* R300_RB3D_BLEND_COLOR: 0x4e10 */
+ /* R520 and newer */
+ uint32_t blend_color_red_alpha; /* R500_RB3D_CONSTANT_COLOR_AR: 0x4ef8 */
+ uint32_t blend_color_green_blue; /* R500_RB3D_CONSTANT_COLOR_GB: 0x4efc */
+};
+
+struct r300_dsa_state {
+ uint32_t alpha_function; /* R300_FG_ALPHA_FUNC: 0x4bd4 */
+ uint32_t alpha_reference; /* R500_FG_ALPHA_VALUE: 0x4be0 */
+ uint32_t z_buffer_control; /* R300_ZB_CNTL: 0x4f00 */
+ uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
+ uint32_t stencil_ref_mask; /* R300_ZB_STENCILREFMASK: 0x4f08 */
+ uint32_t z_buffer_top; /* R300_ZB_ZTOP: 0x4f14 */
+ uint32_t stencil_ref_bf; /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
+};
+
+struct r300_rs_state {
+ /* XXX icky as fucking hell */
+ struct pipe_rasterizer_state rs;
+
+ uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
+ uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
+ uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
+ uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */
+ uint32_t depth_offset_front;/* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */
+ uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */
+ uint32_t depth_offset_back; /* R300_SU_POLY_OFFSET_BACK_OFFSET: 0x42b0 */
+ uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
+ uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
+ uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
+ uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
+};
+
+struct r300_sampler_state {
+ uint32_t filter0; /* R300_TX_FILTER0: 0x4400 */
+ uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */
+ uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
+};
+
+struct r300_scissor_state {
+ uint32_t scissor_top_left; /* R300_SC_SCISSORS_TL: 0x43e0 */
+ uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */
+};
+
+struct r300_texture_state {
+};
+
+#define R300_NEW_BLEND 0x0000001
+#define R300_NEW_BLEND_COLOR 0x0000002
+#define R300_NEW_CONSTANTS 0x0000004
+#define R300_NEW_DSA 0x0000008
+#define R300_NEW_FRAMEBUFFERS 0x0000010
+#define R300_NEW_FRAGMENT_SHADER 0x0000020
+#define R300_NEW_RASTERIZER 0x0000040
+#define R300_NEW_SAMPLER 0x0000080
+#define R300_NEW_SCISSOR 0x0008000
+#define R300_NEW_TEXTURE 0x0010000
+#define R300_NEW_VERTEX_FORMAT 0x1000000
+#define R300_NEW_VERTEX_SHADER 0x2000000
+#define R300_NEW_KITCHEN_SINK 0x3ffffff
+
+/* The next several objects are not pure Radeon state; they inherit from
+ * various Gallium classes. */
+
+struct r300_constant_buffer {
+ /* Buffer of constants */
+ /* XXX first number should be raised */
+ float constants[8][4];
+ /* Number of user-defined constants */
+ int user_count;
+ /* Total number of constants */
+ int count;
+};
+
+struct r3xx_fragment_shader {
+ /* Parent class */
+ struct pipe_shader_state state;
+ struct tgsi_shader_info info;
+
+ /* Has this shader been translated yet? */
+ boolean translated;
+
+ /* Pixel stack size */
+ int stack_size;
+};
+
+struct r300_fragment_shader {
+ /* Parent class */
+ struct r3xx_fragment_shader shader;
+
+ /* Number of ALU instructions */
+ int alu_instruction_count;
+
+ /* Number of texture instructions */
+ int tex_instruction_count;
+
+ /* Number of texture indirections */
+ int indirections;
+
+ /* Indirection node offsets */
+ int offset0;
+ int offset1;
+ int offset2;
+ int offset3;
+
+ /* Machine instructions */
+ struct {
+ uint32_t alu_rgb_inst;
+ uint32_t alu_rgb_addr;
+ uint32_t alu_alpha_inst;
+ uint32_t alu_alpha_addr;
+ } instructions[64]; /* XXX magic num */
+};
+
+struct r500_fragment_shader {
+ /* Parent class */
+ struct r3xx_fragment_shader shader;
+
+ /* Number of used instructions */
+ int instruction_count;
+
+ /* Machine instructions */
+ struct {
+ uint32_t inst0;
+ uint32_t inst1;
+ uint32_t inst2;
+ uint32_t inst3;
+ uint32_t inst4;
+ uint32_t inst5;
+ } instructions[256]; /*< XXX magic number */
+};
+
+struct r300_texture {
+ /* Parent class */
+ struct pipe_texture tex;
+
+ /* Offsets into the buffer. */
+ unsigned offset[PIPE_MAX_TEXTURE_LEVELS];
+
+ /* Total size of this texture, in bytes. */
+ unsigned size;
+
+ /* Pipe buffer backing this texture. */
+ struct pipe_buffer* buffer;
+};
+
+struct r300_context {
+ /* Parent class */
+ struct pipe_context context;
+
+ /* The interface to the windowing system, etc. */
+ struct r300_winsys* winsys;
+ /* Draw module. Used mostly for SW TCL. */
+ struct draw_context* draw;
+
+ /* Various CSO state objects. */
+ /* Blend state. */
+ struct r300_blend_state* blend_state;
+ /* Blend color state. */
+ struct r300_blend_color_state* blend_color_state;
+ /* Shader constants. */
+ struct r300_constant_buffer shader_constants[PIPE_SHADER_TYPES];
+ /* Depth, stencil, and alpha state. */
+ struct r300_dsa_state* dsa_state;
+ /* Fragment shader. */
+ struct r3xx_fragment_shader* fs;
+ /* Framebuffer state. We currently don't need our own version of this. */
+ struct pipe_framebuffer_state framebuffer_state;
+ /* Rasterizer state. */
+ struct r300_rs_state* rs_state;
+ /* Sampler states. */
+ struct r300_sampler_state* sampler_states[8];
+ int sampler_count;
+ /* Scissor state. */
+ struct r300_scissor_state* scissor_state;
+ /* Texture states. */
+ struct r300_texture* textures[8];
+ struct r300_texture_state* texture_states[8];
+ int texture_count;
+ /* Vertex buffers. */
+ struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
+ int vertex_buffer_count;
+ /* Vertex information. */
+ struct vertex_info vertex_info;
+ /* Bitmask of dirty state objects. */
+ uint32_t dirty_state;
+ /* Flag indicating whether or not the HW is dirty. */
+ uint32_t dirty_hw;
+};
+
+/* Convenience cast wrapper. */
+static struct r300_context* r300_context(struct pipe_context* context) {
+ return (struct r300_context*)context;
+}
+
+/* Context initialization. */
+void r300_init_state_functions(struct r300_context* r300);
+void r300_init_surface_functions(struct r300_context* r300);
+
+/* Fun with includes: r300_winsys also declares this prototype.
+ * We'll just step out in that case... */
+#ifndef R300_WINSYS_H
+struct pipe_context* r300_create_context(struct pipe_screen* screen,
+ struct pipe_winsys* winsys,
+ struct r300_winsys* r300_winsys);
+#endif
+
+#endif /* R300_CONTEXT_H */
diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h
new file mode 100644
index 0000000000..d8038ff1e1
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_cs.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_CS_H
+#define R300_CS_H
+
+#include "util/u_math.h"
+
+#include "r300_reg.h"
+#include "r300_winsys.h"
+
+/* Yes, I know macros are ugly. However, they are much prettier than the code
+ * that they neatly hide away, and don't have the cost of function setup,so
+ * we're going to use them. */
+
+#define MAX_CS_SIZE 64 * 1024 / 4
+
+#define VERY_VERBOSE_REGISTERS 0
+
+/* XXX stolen from radeon_drm.h */
+#define RADEON_GEM_DOMAIN_CPU 0x1
+#define RADEON_GEM_DOMAIN_GTT 0x2
+#define RADEON_GEM_DOMAIN_VRAM 0x4
+
+/* XXX stolen from radeon_reg.h */
+#define RADEON_CP_PACKET0 0x0
+
+#define CP_PACKET0(register, count) \
+ (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2))
+
+#define CP_PACKET3(op, count) \
+ (RADEON_CP_PACKET3 | (op) | ((count) << 16))
+
+#define CS_LOCALS(context) \
+ struct r300_winsys* cs_winsys = context->winsys; \
+ struct radeon_cs* cs = cs_winsys->cs; \
+ int cs_count = 0;
+
+#define CHECK_CS(size) \
+ cs_winsys->check_cs(cs, (size))
+
+#define BEGIN_CS(size) do { \
+ CHECK_CS(size); \
+ debug_printf("r300: BEGIN_CS, count %d, in %s (%s:%d)\n", \
+ size, __FUNCTION__, __FILE__, __LINE__); \
+ cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \
+ cs_count = size; \
+} while (0)
+
+#define OUT_CS(value) do { \
+ cs_winsys->write_cs_dword(cs, (value)); \
+ cs_count--; \
+} while (0)
+
+#define OUT_CS_32F(value) do { \
+ cs_winsys->write_cs_dword(cs, fui(value)); \
+ cs_count--; \
+} while (0)
+
+#define OUT_CS_REG(register, value) do { \
+ if (VERY_VERBOSE_REGISTERS) \
+ debug_printf("r300: writing 0x%08X to register 0x%04X\n", \
+ value, register); \
+ assert(register); \
+ OUT_CS(CP_PACKET0(register, 0)); \
+ OUT_CS(value); \
+} while (0)
+
+/* Note: This expects count to be the number of registers,
+ * not the actual packet0 count! */
+#define OUT_CS_REG_SEQ(register, count) do { \
+ if (VERY_VERBOSE_REGISTERS) \
+ debug_printf("r300: writing register sequence of %d to 0x%04X\n", \
+ count, register); \
+ assert(register); \
+ OUT_CS(CP_PACKET0(register, ((count) - 1))); \
+} while (0)
+
+#define OUT_CS_RELOC(bo, offset, rd, wd, flags) do { \
+ debug_printf("r300: writing relocation for buffer %p, offset %d\n", \
+ bo, offset); \
+ assert(bo); \
+ OUT_CS(offset); \
+ cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \
+ cs_count -= 2; \
+} while (0)
+
+#define END_CS do { \
+ debug_printf("r300: END_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \
+ __LINE__); \
+ if (cs_count != 0) \
+ debug_printf("r300: Warning: cs_count off by %d\n", cs_count); \
+ cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__); \
+} while (0)
+
+#define FLUSH_CS do { \
+ debug_printf("r300: FLUSH_CS in %s (%s:%d)\n\n", __FUNCTION__, __FILE__, \
+ __LINE__); \
+ cs_winsys->flush_cs(cs); \
+} while (0)
+
+#include "r300_cs_inlines.h"
+
+#endif /* R300_CS_H */
diff --git a/src/gallium/drivers/r300/r300_cs_inlines.h b/src/gallium/drivers/r300/r300_cs_inlines.h
new file mode 100644
index 0000000000..03bb608eb9
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_cs_inlines.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+/* r300_cs_inlines: This is just a handful of useful inlines for sending
+ * (very) common instructions to the CS buffer. Should only be included from
+ * r300_cs.h, probably. */
+
+#ifdef R300_CS_H
+
+#define RADEON_ONE_REG_WR (1 << 15)
+
+#define OUT_CS_ONE_REG(register, count) do { \
+ if (VERY_VERBOSE_REGISTERS) \
+ debug_printf("r300: writing data sequence of %d to 0x%04X\n", \
+ count, register); \
+ assert(register); \
+ OUT_CS(CP_PACKET0(register, ((count) - 1)) | RADEON_ONE_REG_WR); \
+} while (0)
+
+#define R300_PACIFY do { \
+ OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 14) | (1 << 15) | (1 << 16) | (1 << 17) | \
+ (1 << 18)); \
+} while (0)
+
+#define R300_SCREENDOOR do { \
+ OUT_CS_REG(R300_SC_SCREENDOOR, 0x0); \
+ R300_PACIFY; \
+ OUT_CS_REG(R300_SC_SCREENDOOR, 0xffffff); \
+} while (0)
+
+#endif /* R300_CS_H */
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
new file mode 100644
index 0000000000..a2819294a4
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+/* r300_emit: Functions for emitting state. */
+
+#include "r300_emit.h"
+
+void r300_emit_blend_state(struct r300_context* r300,
+ struct r300_blend_state* blend)
+{
+ CS_LOCALS(r300);
+ BEGIN_CS(7);
+ OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2);
+ OUT_CS(blend->blend_control);
+ OUT_CS(blend->alpha_blend_control);
+ OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
+ OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
+ END_CS;
+}
+
+void r300_emit_blend_color_state(struct r300_context* r300,
+ struct r300_blend_color_state* bc)
+{
+ struct r300_screen* r300screen =
+ (struct r300_screen*)r300->context.screen;
+ CS_LOCALS(r300);
+ if (r300screen->caps->is_r500) {
+ BEGIN_CS(3);
+ OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
+ OUT_CS(bc->blend_color_red_alpha);
+ OUT_CS(bc->blend_color_green_blue);
+ END_CS;
+ } else {
+ BEGIN_CS(2);
+ OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
+ END_CS;
+ }
+}
+
+void r300_emit_dsa_state(struct r300_context* r300,
+ struct r300_dsa_state* dsa)
+{
+ struct r300_screen* r300screen =
+ (struct r300_screen*)r300->context.screen;
+ CS_LOCALS(r300);
+ BEGIN_CS(r300screen->caps->is_r500 ? 8 : 8);
+ OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
+ /* XXX figure out the r300 counterpart for this */
+ if (r300screen->caps->is_r500) {
+ /* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */
+ }
+ OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
+ OUT_CS(dsa->z_buffer_control);
+ OUT_CS(dsa->z_stencil_control);
+ OUT_CS(dsa->stencil_ref_mask);
+ OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
+ if (r300screen->caps->is_r500) {
+ /* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */
+ }
+ END_CS;
+}
+
+void r300_emit_fragment_shader(struct r300_context* r300,
+ struct r300_fragment_shader* fs)
+{
+ CS_LOCALS(r300);
+ int i;
+ BEGIN_CS(0);
+
+ OUT_CS_REG(R300_US_CONFIG, MAX2(fs->indirections - 1, 0));
+ OUT_CS_REG(R300_US_PIXSIZE, fs->shader.stack_size);
+ /* XXX figure out exactly how big the sizes are on this reg */
+ OUT_CS_REG(R300_US_CODE_OFFSET, 0x0);
+ /* XXX figure these ones out a bit better kthnx */
+ OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_3, R300_RGBA_OUT);
+
+ for (i = 0; i < fs->alu_instruction_count; i++) {
+ OUT_CS_REG(R300_US_ALU_RGB_INST_0 + (4 * i),
+ fs->instructions[i].alu_rgb_inst);
+ OUT_CS_REG(R300_US_ALU_RGB_ADDR_0 + (4 * i),
+ fs->instructions[i].alu_rgb_addr);
+ OUT_CS_REG(R300_US_ALU_ALPHA_INST_0 + (4 * i),
+ fs->instructions[i].alu_alpha_inst);
+ OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0 + (4 * i),
+ fs->instructions[i].alu_alpha_addr);
+ }
+
+ END_CS;
+}
+
+void r500_emit_fragment_shader(struct r300_context* r300,
+ struct r500_fragment_shader* fs)
+{
+ CS_LOCALS(r300);
+ int i = 0;
+ BEGIN_CS(9 + (fs->instruction_count * 6));
+ OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_CS_REG(R500_US_PIXSIZE, fs->shader.stack_size);
+ OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(fs->instruction_count));
+
+ OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
+ OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA,
+ fs->instruction_count * 6);
+ for (i = 0; i < fs->instruction_count; i++) {
+ OUT_CS(fs->instructions[i].inst0);
+ OUT_CS(fs->instructions[i].inst1);
+ OUT_CS(fs->instructions[i].inst2);
+ OUT_CS(fs->instructions[i].inst3);
+ OUT_CS(fs->instructions[i].inst4);
+ OUT_CS(fs->instructions[i].inst5);
+ }
+ END_CS;
+}
+
+/* Translate pipe_format into US_OUT_FMT. Note that formats are stored from
+ * C3 to C0. */
+uint32_t translate_out_fmt(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ return R300_US_OUT_FMT_C4_8 |
+ R300_C0_SEL_B | R300_C1_SEL_G |
+ R300_C2_SEL_R | R300_C3_SEL_A;
+ default:
+ return R300_US_OUT_FMT_UNUSED;
+ }
+ return 0;
+}
+
+/* XXX add pitch, stride */
+void r300_emit_fb_state(struct r300_context* r300,
+ struct pipe_framebuffer_state* fb)
+{
+ CS_LOCALS(r300);
+ struct r300_texture* tex;
+ int i;
+
+ BEGIN_CS((5 * fb->nr_cbufs) + (fb->zsbuf ? 5 : 0) + 4);
+ for (i = 0; i < fb->nr_cbufs; i++) {
+ tex = (struct r300_texture*)fb->cbufs[i]->texture;
+ OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
+ OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+
+ OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
+ translate_out_fmt(fb->cbufs[i]->format));
+ }
+
+ if (fb->zsbuf) {
+ tex = (struct r300_texture*)fb->zsbuf->texture;
+ OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
+ OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+ if (fb->zsbuf->format == PIPE_FORMAT_Z24S8_UNORM) {
+ OUT_CS_REG(R300_ZB_FORMAT,
+ R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL);
+ } else {
+ OUT_CS_REG(R300_ZB_FORMAT, 0x0);
+ }
+ }
+
+ OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+ END_CS;
+}
+
+void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
+{
+ struct r300_screen* r300screen =
+ (struct r300_screen*)r300->context.screen;
+ CS_LOCALS(r300);
+ BEGIN_CS(13);
+ OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
+ OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
+ OUT_CS(rs->depth_scale_front);
+ OUT_CS(rs->depth_offset_front);
+ OUT_CS(rs->depth_scale_back);
+ OUT_CS(rs->depth_offset_back);
+ OUT_CS(rs->polygon_offset_enable);
+ OUT_CS(rs->cull_mode);
+ OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
+ OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
+ END_CS;
+}
+
+void r300_emit_scissor_state(struct r300_context* r300,
+ struct r300_scissor_state* scissor)
+{
+ CS_LOCALS(r300);
+ BEGIN_CS(3);
+ OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
+ OUT_CS(scissor->scissor_top_left);
+ OUT_CS(scissor->scissor_bottom_right);
+ END_CS;
+}
+
+/* Emit all dirty state. */
+void r300_emit_dirty_state(struct r300_context* r300)
+{
+ struct r300_screen* r300screen =
+ (struct r300_screen*)r300->context.screen;
+ CS_LOCALS(r300);
+
+ if (!(r300->dirty_state) && !(r300->dirty_hw)) {
+ return;
+ }
+
+ /* XXX check size */
+
+ if (r300->dirty_state & R300_NEW_BLEND) {
+ r300_emit_blend_state(r300, r300->blend_state);
+ }
+
+ if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
+ r300_emit_blend_color_state(r300, r300->blend_color_state);
+ }
+
+ if (r300->dirty_state & R300_NEW_DSA) {
+ r300_emit_dsa_state(r300, r300->dsa_state);
+ }
+
+ if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
+ if (r300screen->caps->is_r500) {
+ r500_emit_fragment_shader(r300,
+ (struct r500_fragment_shader*)r300->fs);
+ } else {
+ r300_emit_fragment_shader(r300,
+ (struct r300_fragment_shader*)r300->fs);
+ }
+ }
+
+ if (r300->dirty_state & R300_NEW_RASTERIZER) {
+ r300_emit_rs_state(r300, r300->rs_state);
+ }
+
+ if (r300->dirty_state & R300_NEW_SCISSOR) {
+ r300_emit_scissor_state(r300, r300->scissor_state);
+ }
+
+ r300->dirty_state = 0;
+}
diff --git a/src/gallium/drivers/r300/r300_emit.h b/src/gallium/drivers/r300/r300_emit.h
new file mode 100644
index 0000000000..f21ca33171
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_emit.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_EMIT_H
+#define R300_EMIT_H
+
+#include "util/u_math.h"
+
+#include "r300_context.h"
+#include "r300_cs.h"
+#include "r300_screen.h"
+
+void r300_emit_blend_state(struct r300_context* r300,
+ struct r300_blend_state* blend);
+
+void r300_emit_blend_color_state(struct r300_context* r300,
+ struct r300_blend_color_state* bc);
+
+void r300_emit_dsa_state(struct r300_context* r300,
+ struct r300_dsa_state* dsa);
+
+void r300_emit_fragment_shader(struct r300_context* r300,
+ struct r300_fragment_shader* fs);
+
+void r500_emit_fragment_shader(struct r300_context* r300,
+ struct r500_fragment_shader* fs);
+
+void r300_emit_fb_state(struct r300_context* r300,
+ struct pipe_framebuffer_state* fb);
+
+void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs);
+
+void r300_emit_scissor_state(struct r300_context* r300,
+ struct r300_scissor_state* scissor);
+
+
+/* Emit all dirty state. */
+void r300_emit_dirty_state(struct r300_context* r300);
+
+#endif /* R300_EMIT_H */
diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
new file mode 100644
index 0000000000..3766f0a0a7
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_flush.h"
+
+static void r300_flush(struct pipe_context* pipe,
+ unsigned flags,
+ struct pipe_fence_handle** fence)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ CS_LOCALS(r300);
+
+ if (r300->dirty_hw) {
+ FLUSH_CS;
+ r300->dirty_state = R300_NEW_KITCHEN_SINK;
+ r300->dirty_hw = 0;
+ }
+}
+
+void r300_init_flush_functions(struct r300_context* r300)
+{
+ r300->context.flush = r300_flush;
+}
diff --git a/src/gallium/drivers/r300/r300_flush.h b/src/gallium/drivers/r300/r300_flush.h
new file mode 100644
index 0000000000..a1b224b39c
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_flush.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_FLUSH_H
+#define R300_FLUSH_H
+
+#include "pipe/p_context.h"
+
+#include "r300_context.h"
+#include "r300_cs.h"
+
+void r300_init_flush_functions(struct r300_context* r300);
+
+#endif /* R300_FLUSH_H */
diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
new file mode 100644
index 0000000000..468e0a2e44
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -0,0 +1,3250 @@
+/**************************************************************************
+
+Copyright (C) 2004-2005 Nicolai Haehnle et al.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+on the rights to use, copy, modify, merge, publish, distribute, sub
+license, and/or sell copies of the Software, and to permit persons to whom
+the Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the next
+paragraph) shall be included in all copies or substantial portions of the
+Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/* *INDENT-OFF* */
+
+#ifndef _R300_REG_H
+#define _R300_REG_H
+
+#define R300_MC_INIT_MISC_LAT_TIMER 0x180
+# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
+# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4
+# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8
+# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12
+# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16
+# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20
+# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
+# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
+
+
+#define R300_MC_INIT_GFX_LAT_TIMER 0x154
+# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
+# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
+# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8
+# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12
+# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
+# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
+# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24
+# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
+
+/*
+ * This file contains registers and constants for the R300. They have been
+ * found mostly by examining command buffers captured using glxtest, as well
+ * as by extrapolating some known registers and constants from the R200.
+ * I am fairly certain that they are correct unless stated otherwise
+ * in comments.
+ */
+
+#define R300_SE_VPORT_XSCALE 0x1D98
+#define R300_SE_VPORT_XOFFSET 0x1D9C
+#define R300_SE_VPORT_YSCALE 0x1DA0
+#define R300_SE_VPORT_YOFFSET 0x1DA4
+#define R300_SE_VPORT_ZSCALE 0x1DA8
+#define R300_SE_VPORT_ZOFFSET 0x1DAC
+
+
+/*
+ * Vertex Array Processing (VAP) Control
+ */
+#define R300_VAP_CNTL 0x2080
+# define R300_PVS_NUM_SLOTS_SHIFT 0
+# define R300_PVS_NUM_CNTLRS_SHIFT 4
+# define R300_PVS_NUM_FPUS_SHIFT 8
+# define R300_VF_MAX_VTX_NUM_SHIFT 18
+# define R300_GL_CLIP_SPACE_DEF (0 << 22)
+# define R300_DX_CLIP_SPACE_DEF (1 << 22)
+# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
+
+/* This register is written directly and also starts data section
+ * in many 3d CP_PACKET3's
+ */
+#define R300_VAP_VF_CNTL 0x2084
+# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
+# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
+# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
+# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
+# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
+# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
+# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
+# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
+# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
+# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
+# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
+# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
+
+# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
+ /* State based - direct writes to registers trigger vertex
+ generation */
+# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
+# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
+# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
+# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
+
+ /* I don't think I saw these three used.. */
+# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
+# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
+# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
+
+ /* index size - when not set the indices are assumed to be 16 bit */
+# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
+ /* number of vertices */
+# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
+
+#define R500_VAP_INDEX_OFFSET 0x208c
+
+#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
+# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
+# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16)
+
+#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
+ /* each of the following is 3 bits wide, specifies number
+ of components */
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
+# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
+# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0
+# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1
+# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2
+# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3
+# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
+
+#define R300_SE_VTE_CNTL 0x20b0
+# define R300_VPORT_X_SCALE_ENA (1 << 0)
+# define R300_VPORT_X_OFFSET_ENA (1 << 1)
+# define R300_VPORT_Y_SCALE_ENA (1 << 2)
+# define R300_VPORT_Y_OFFSET_ENA (1 << 3)
+# define R300_VPORT_Z_SCALE_ENA (1 << 4)
+# define R300_VPORT_Z_OFFSET_ENA (1 << 5)
+# define R300_VTX_XY_FMT (1 << 8)
+# define R300_VTX_Z_FMT (1 << 9)
+# define R300_VTX_W0_FMT (1 << 10)
+# define R300_SERIAL_PROC_ENA (1 << 11)
+
+#define R300_VAP_VTX_SIZE 0x20b4
+
+/* BEGIN: Vertex data assembly - lots of uncertainties */
+
+/* gap */
+
+/* Maximum Vertex Indx Clamp */
+#define R300_VAP_VF_MAX_VTX_INDX 0x2134
+/* Minimum Vertex Indx Clamp */
+#define R300_VAP_VF_MIN_VTX_INDX 0x2138
+
+/** Vertex assembler/processor control status */
+#define R300_VAP_CNTL_STATUS 0x2140
+/* No swap at all (default) */
+# define R300_VC_NO_SWAP (0 << 0)
+/* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */
+# define R300_VC_16BIT_SWAP (1 << 0)
+/* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */
+# define R300_VC_32BIT_SWAP (2 << 0)
+/* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */
+# define R300_VC_HALF_DWORD_SWAP (3 << 0)
+/* The TCL engine will not be used (as it is logically or even physically removed) */
+# define R300_VAP_TCL_BYPASS (1 << 8)
+/* Read only flag if TCL engine is busy. */
+# define R300_VAP_PVS_BUSY (1 << 11)
+/* TODO: gap for MAX_MPS */
+/* Read only flag if the vertex store is busy. */
+# define R300_VAP_VS_BUSY (1 << 24)
+/* Read only flag if the reciprocal engine is busy. */
+# define R300_VAP_RCP_BUSY (1 << 25)
+/* Read only flag if the viewport transform engine is busy. */
+# define R300_VAP_VTE_BUSY (1 << 26)
+/* Read only flag if the memory interface unit is busy. */
+# define R300_VAP_MUI_BUSY (1 << 27)
+/* Read only flag if the vertex cache is busy. */
+# define R300_VAP_VC_BUSY (1 << 28)
+/* Read only flag if the vertex fetcher is busy. */
+# define R300_VAP_VF_BUSY (1 << 29)
+/* Read only flag if the register pipeline is busy. */
+# define R300_VAP_REGPIPE_BUSY (1 << 30)
+/* Read only flag if the VAP engine is busy. */
+# define R300_VAP_VAP_BUSY (1 << 31)
+
+/* gap */
+
+/* Where do we get our vertex data?
+ *
+ * Vertex data either comes either from immediate mode registers or from
+ * vertex arrays.
+ * There appears to be no mixed mode (though we can force the pitch of
+ * vertex arrays to 0, effectively reusing the same element over and over
+ * again).
+ *
+ * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
+ * if these registers influence vertex array processing.
+ *
+ * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
+ *
+ * In both cases, vertex attributes are then passed through INPUT_ROUTE.
+ *
+ * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
+ * into the vertex processor's input registers.
+ * The first word routes the first input, the second word the second, etc.
+ * The corresponding input is routed into the register with the given index.
+ * The list is ended by a word with INPUT_ROUTE_END set.
+ *
+ * Always set COMPONENTS_4 in immediate mode.
+ */
+
+#define R300_VAP_PROG_STREAM_CNTL_0 0x2150
+# define R300_DATA_TYPE_0_SHIFT 0
+# define R300_DATA_TYPE_FLOAT_1 0
+# define R300_DATA_TYPE_FLOAT_2 1
+# define R300_DATA_TYPE_FLOAT_3 2
+# define R300_DATA_TYPE_FLOAT_4 3
+# define R300_DATA_TYPE_BYTE 4
+# define R300_DATA_TYPE_D3DCOLOR 5
+# define R300_DATA_TYPE_SHORT_2 6
+# define R300_DATA_TYPE_SHORT_4 7
+# define R300_DATA_TYPE_VECTOR_3_TTT 8
+# define R300_DATA_TYPE_VECTOR_3_EET 9
+# define R300_SKIP_DWORDS_SHIFT 4
+# define R300_DST_VEC_LOC_SHIFT 8
+# define R300_LAST_VEC (1 << 13)
+# define R300_SIGNED (1 << 14)
+# define R300_NORMALIZE (1 << 15)
+# define R300_DATA_TYPE_1_SHIFT 16
+#define R300_VAP_PROG_STREAM_CNTL_1 0x2154
+#define R300_VAP_PROG_STREAM_CNTL_2 0x2158
+#define R300_VAP_PROG_STREAM_CNTL_3 0x215C
+#define R300_VAP_PROG_STREAM_CNTL_4 0x2160
+#define R300_VAP_PROG_STREAM_CNTL_5 0x2164
+#define R300_VAP_PROG_STREAM_CNTL_6 0x2168
+#define R300_VAP_PROG_STREAM_CNTL_7 0x216C
+/* gap */
+
+/* Notes:
+ * - always set up to produce at least two attributes:
+ * if vertex program uses only position, fglrx will set normal, too
+ * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
+ */
+#define R300_VAP_VTX_STATE_CNTL 0x2180
+# define R300_COLOR_0_ASSEMBLY_SHIFT 0
+# define R300_SEL_COLOR 0
+# define R300_SEL_USER_COLOR_0 1
+# define R300_SEL_USER_COLOR_1 2
+# define R300_COLOR_1_ASSEMBLY_SHIFT 2
+# define R300_COLOR_2_ASSEMBLY_SHIFT 4
+# define R300_COLOR_3_ASSEMBLY_SHIFT 6
+# define R300_COLOR_4_ASSEMBLY_SHIFT 8
+# define R300_COLOR_5_ASSEMBLY_SHIFT 10
+# define R300_COLOR_6_ASSEMBLY_SHIFT 12
+# define R300_COLOR_7_ASSEMBLY_SHIFT 14
+# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16)
+
+/*
+ * Each bit in this field applies to the corresponding vector in the VSM
+ * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit
+ * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream.
+ */
+#define R300_VAP_VSM_VTX_ASSM 0x2184
+# define R300_INPUT_CNTL_POS 0x00000001
+# define R300_INPUT_CNTL_NORMAL 0x00000002
+# define R300_INPUT_CNTL_COLOR 0x00000004
+# define R300_INPUT_CNTL_TC0 0x00000400
+# define R300_INPUT_CNTL_TC1 0x00000800
+# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
+# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
+# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
+# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
+# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
+# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
+
+/* Programmable Stream Control Signed Normalize Control */
+#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc
+# define SGN_NORM_ZERO 0
+# define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1
+# define SGN_NORM_NO_ZERO 2
+
+/* gap */
+
+/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
+ * are set to a swizzling bit pattern, other words are 0.
+ *
+ * In immediate mode, the pattern is always set to xyzw. In vertex array
+ * mode, the swizzling pattern is e.g. used to set zw components in texture
+ * coordinates with only tweo components.
+ */
+#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
+# define R300_SWIZZLE0_SHIFT 0
+# define R300_SWIZZLE_SELECT_X_SHIFT 0
+# define R300_SWIZZLE_SELECT_Y_SHIFT 3
+# define R300_SWIZZLE_SELECT_Z_SHIFT 6
+# define R300_SWIZZLE_SELECT_W_SHIFT 9
+
+# define R300_SWIZZLE_SELECT_X 0
+# define R300_SWIZZLE_SELECT_Y 1
+# define R300_SWIZZLE_SELECT_Z 2
+# define R300_SWIZZLE_SELECT_W 3
+# define R300_SWIZZLE_SELECT_FP_ZERO 4
+# define R300_SWIZZLE_SELECT_FP_ONE 5
+/* alternate forms for r300_emit.c */
+# define R300_INPUT_ROUTE_SELECT_X 0
+# define R300_INPUT_ROUTE_SELECT_Y 1
+# define R300_INPUT_ROUTE_SELECT_Z 2
+# define R300_INPUT_ROUTE_SELECT_W 3
+# define R300_INPUT_ROUTE_SELECT_ZERO 4
+# define R300_INPUT_ROUTE_SELECT_ONE 5
+
+# define R300_WRITE_ENA_SHIFT 12
+# define R300_WRITE_ENA_X 1
+# define R300_WRITE_ENA_Y 2
+# define R300_WRITE_ENA_Z 4
+# define R300_WRITE_ENA_W 8
+# define R300_SWIZZLE1_SHIFT 16
+#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
+#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8
+#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec
+#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0
+#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4
+#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8
+#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc
+
+/* END: Vertex data assembly */
+
+/* gap */
+
+/* BEGIN: Upload vertex program and data */
+
+/*
+ * The programmable vertex shader unit has a memory bank of unknown size
+ * that can be written to in 16 byte units by writing the address into
+ * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
+ *
+ * Pointers into the memory bank are always in multiples of 16 bytes.
+ *
+ * The memory bank is divided into areas with fixed meaning.
+ *
+ * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
+ * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
+ * whereas the difference between known addresses suggests size 512.
+ *
+ * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
+ * Native reported limits and the VPI layout suggest size 256, whereas
+ * difference between known addresses suggests size 512.
+ *
+ * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
+ * floating point pointsize. The exact purpose of this state is uncertain,
+ * as there is also the R300_RE_POINTSIZE register.
+ *
+ * Multiple vertex programs and parameter sets can be loaded at once,
+ * which could explain the size discrepancy.
+ */
+#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
+# define R300_PVS_CODE_START 0
+# define R300_MAX_PVS_CODE_LINES 256
+# define R500_MAX_PVS_CODE_LINES 1024
+# define R300_PVS_CONST_START 512
+# define R500_PVS_CONST_START 1024
+# define R300_MAX_PVS_CONST_VECS 256
+# define R500_MAX_PVS_CONST_VECS 1024
+# define R300_PVS_UCP_START 1024
+# define R500_PVS_UCP_START 1536
+# define R300_POINT_VPORT_SCALE_OFFSET 1030
+# define R500_POINT_VPORT_SCALE_OFFSET 1542
+# define R300_POINT_GEN_TEX_OFFSET 1031
+# define R500_POINT_GEN_TEX_OFFSET 1543
+
+/*
+ * These are obsolete defines form r300_context.h, but they might give some
+ * clues when investigating the addresses further...
+ */
+#if 0
+#define VSF_DEST_PROGRAM 0x0
+#define VSF_DEST_MATRIX0 0x200
+#define VSF_DEST_MATRIX1 0x204
+#define VSF_DEST_MATRIX2 0x208
+#define VSF_DEST_VECTOR0 0x20c
+#define VSF_DEST_VECTOR1 0x20d
+#define VSF_DEST_UNKNOWN1 0x400
+#define VSF_DEST_UNKNOWN2 0x406
+#endif
+
+/* gap */
+
+#define R300_VAP_PVS_UPLOAD_DATA 0x2208
+
+/* END: Upload vertex program and data */
+
+/* gap */
+
+/* I do not know the purpose of this register. However, I do know that
+ * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
+ * for normal rendering.
+ *
+ * 2007-11-05: This register is the user clip plane control register, but there
+ * also seems to be a rendering mode control; the NORMAL/CLEAR defines.
+ *
+ * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view
+ */
+#define R300_VAP_CLIP_CNTL 0x221C
+# define R300_VAP_UCP_ENABLE_0 (1 << 0)
+# define R300_VAP_UCP_ENABLE_1 (1 << 1)
+# define R300_VAP_UCP_ENABLE_2 (1 << 2)
+# define R300_VAP_UCP_ENABLE_3 (1 << 3)
+# define R300_VAP_UCP_ENABLE_4 (1 << 4)
+# define R300_VAP_UCP_ENABLE_5 (1 << 5)
+# define R300_PS_UCP_MODE_DIST_COP (0 << 14)
+# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14)
+# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14)
+# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14)
+# define R300_CLIP_DISABLE (1 << 16)
+# define R300_UCP_CULL_ONLY_ENABLE (1 << 17)
+# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18)
+# define R500_COLOR2_IS_TEXTURE (1 << 20)
+# define R500_COLOR3_IS_TEXTURE (1 << 21)
+
+/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
+ * plane is per-pixel and the second plane is per-vertex.
+ *
+ * This was determined by experimentation alone but I believe it is correct.
+ *
+ * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
+ */
+#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
+#define R300_VAP_GB_VERT_DISC_ADJ 0x2224
+#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
+#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
+
+/* gap */
+
+/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
+ * rendering commands and overwriting vertex program parameters.
+ * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
+ * avoids bugs caused by still running shaders reading bad data from memory.
+ */
+#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
+
+/* This register is used to define the number of core clocks to wait for a
+ * vertex to be received by the VAP input controller (while the primitive
+ * path is backed up) before forcing any accumulated vertices to be submitted
+ * to the vertex processing path.
+ */
+#define VAP_PVS_VTX_TIMEOUT_REG 0x2288
+# define R300_2288_R300 0x00750000 /* -- nh */
+# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
+
+/* gap */
+
+/* Addresses are relative to the vertex program instruction area of the
+ * memory bank. PROGRAM_END points to the last instruction of the active
+ * program
+ *
+ * The meaning of the two UNKNOWN fields is obviously not known. However,
+ * experiments so far have shown that both *must* point to an instruction
+ * inside the vertex program, otherwise the GPU locks up.
+ *
+ * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
+ * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
+ * position takes place.
+ *
+ * Most likely this is used to ignore rest of the program in cases
+ * where group of verts arent visible. For some reason this "section"
+ * is sometimes accepted other instruction that have no relationship with
+ * position calculations.
+ */
+#define R300_VAP_PVS_CODE_CNTL_0 0x22D0
+# define R300_PVS_FIRST_INST_SHIFT 0
+# define R300_PVS_XYZW_VALID_INST_SHIFT 10
+# define R300_PVS_LAST_INST_SHIFT 20
+/* Addresses are relative the the vertex program parameters area. */
+#define R300_VAP_PVS_CONST_CNTL 0x22D4
+# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0
+# define R300_PVS_MAX_CONST_ADDR_SHIFT 16
+#define R300_VAP_PVS_CODE_CNTL_1 0x22D8
+# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
+#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
+
+/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
+ * immediate vertices
+ */
+#define R300_VAP_VTX_COLOR_R 0x2464
+#define R300_VAP_VTX_COLOR_G 0x2468
+#define R300_VAP_VTX_COLOR_B 0x246C
+#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
+#define R300_VAP_VTX_POS_0_Y_1 0x2494
+#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
+#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
+#define R300_VAP_VTX_POS_0_Y_2 0x24A4
+#define R300_VAP_VTX_POS_0_Z_2 0x24A8
+/* write 0 to indicate end of packet? */
+#define R300_VAP_VTX_END_OF_PKT 0x24AC
+
+/* gap */
+
+/* These are values from r300_reg/r300_reg.h - they are known to be correct
+ * and are here so we can use one register file instead of several
+ * - Vladimir
+ */
+#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
+# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
+# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
+# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
+# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
+# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
+# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
+# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
+
+#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
+ /* each of the following is 3 bits wide, specifies number
+ of components */
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
+# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
+
+/* UNK30 seems to enables point to quad transformation on textures
+ * (or something closely related to that).
+ * This bit is rather fatal at the time being due to lackings at pixel
+ * shader side
+ * Specifies top of Raster pipe specific enable controls.
+ */
+#define R300_GB_ENABLE 0x4008
+# define R300_GB_POINT_STUFF_DISABLE (0 << 0)
+# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */
+# define R300_GB_LINE_STUFF_DISABLE (0 << 1)
+# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */
+# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2)
+# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */
+# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4)
+# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */
+# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */
+
+ /* each of the following is 2 bits wide */
+#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */
+#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */
+#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */
+# define R300_GB_TEX0_SOURCE_SHIFT 16
+# define R300_GB_TEX1_SOURCE_SHIFT 18
+# define R300_GB_TEX2_SOURCE_SHIFT 20
+# define R300_GB_TEX3_SOURCE_SHIFT 22
+# define R300_GB_TEX4_SOURCE_SHIFT 24
+# define R300_GB_TEX5_SOURCE_SHIFT 26
+# define R300_GB_TEX6_SOURCE_SHIFT 28
+# define R300_GB_TEX7_SOURCE_SHIFT 30
+
+/* MSPOS - positions for multisample antialiasing (?) */
+#define R300_GB_MSPOS0 0x4010
+ /* shifts - each of the fields is 4 bits */
+# define R300_GB_MSPOS0__MS_X0_SHIFT 0
+# define R300_GB_MSPOS0__MS_Y0_SHIFT 4
+# define R300_GB_MSPOS0__MS_X1_SHIFT 8
+# define R300_GB_MSPOS0__MS_Y1_SHIFT 12
+# define R300_GB_MSPOS0__MS_X2_SHIFT 16
+# define R300_GB_MSPOS0__MS_Y2_SHIFT 20
+# define R300_GB_MSPOS0__MSBD0_Y 24
+# define R300_GB_MSPOS0__MSBD0_X 28
+
+#define R300_GB_MSPOS1 0x4014
+# define R300_GB_MSPOS1__MS_X3_SHIFT 0
+# define R300_GB_MSPOS1__MS_Y3_SHIFT 4
+# define R300_GB_MSPOS1__MS_X4_SHIFT 8
+# define R300_GB_MSPOS1__MS_Y4_SHIFT 12
+# define R300_GB_MSPOS1__MS_X5_SHIFT 16
+# define R300_GB_MSPOS1__MS_Y5_SHIFT 20
+# define R300_GB_MSPOS1__MSBD1 24
+
+/* Specifies the graphics pipeline configuration for rasterization. */
+#define R300_GB_TILE_CONFIG 0x4018
+# define R300_GB_TILE_DISABLE (0 << 0)
+# define R300_GB_TILE_ENABLE (1 << 0)
+# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */
+# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */
+# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */
+# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */
+# define R300_GB_TILE_SIZE_8 (0 << 4)
+# define R300_GB_TILE_SIZE_16 (1 << 4)
+# define R300_GB_TILE_SIZE_32 (2 << 4)
+# define R300_GB_SUPER_SIZE_1 (0 << 6)
+# define R300_GB_SUPER_SIZE_2 (1 << 6)
+# define R300_GB_SUPER_SIZE_4 (2 << 6)
+# define R300_GB_SUPER_SIZE_8 (3 << 6)
+# define R300_GB_SUPER_SIZE_16 (4 << 6)
+# define R300_GB_SUPER_SIZE_32 (5 << 6)
+# define R300_GB_SUPER_SIZE_64 (6 << 6)
+# define R300_GB_SUPER_SIZE_128 (7 << 6)
+# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
+# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
+# define R300_GB_SUPER_TILE_A (0 << 15)
+# define R300_GB_SUPER_TILE_B (1 << 15)
+# define R300_GB_SUBPIXEL_1_12 (0 << 16)
+# define R300_GB_SUBPIXEL_1_16 (1 << 16)
+# define GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17)
+# define GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17)
+# define GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17)
+# define GB_TILE_CONFIG_QUADS_PER_RAS_32 (3 << 17)
+# define GB_TILE_CONFIG_BB_SCAN_INTERCEPT (0 << 19)
+# define GB_TILE_CONFIG_BB_SCAN_BOUND_BOX (1 << 19)
+# define GB_TILE_CONFIG_ALT_SCAN_EN_LR (0 << 20)
+# define GB_TILE_CONFIG_ALT_SCAN_EN_LRL (1 << 20)
+# define GB_TILE_CONFIG_ALT_OFFSET (0 << 21)
+# define GB_TILE_CONFIG_SUBPRECISION (0 << 22)
+# define GB_TILE_CONFIG_ALT_TILING_DEF (0 << 23)
+# define GB_TILE_CONFIG_ALT_TILING_3_2 (1 << 23)
+# define GB_TILE_CONFIG_Z_EXTENDED_24_1 (0 << 24)
+# define GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24)
+
+/* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */
+#define R300_GB_FIFO_SIZE 0x4024
+ /* each of the following is 2 bits wide */
+#define R300_GB_FIFO_SIZE_32 0
+#define R300_GB_FIFO_SIZE_64 1
+#define R300_GB_FIFO_SIZE_128 2
+#define R300_GB_FIFO_SIZE_256 3
+# define R300_SC_IFIFO_SIZE_SHIFT 0
+# define R300_SC_TZFIFO_SIZE_SHIFT 2
+# define R300_SC_BFIFO_SIZE_SHIFT 4
+
+# define R300_US_OFIFO_SIZE_SHIFT 12
+# define R300_US_WFIFO_SIZE_SHIFT 14
+ /* the following use the same constants as above, but meaning is
+ is times 2 (i.e. instead of 32 words it means 64 */
+# define R300_RS_TFIFO_SIZE_SHIFT 6
+# define R300_RS_CFIFO_SIZE_SHIFT 8
+# define R300_US_RAM_SIZE_SHIFT 10
+ /* watermarks, 3 bits wide */
+# define R300_RS_HIGHWATER_COL_SHIFT 16
+# define R300_RS_HIGHWATER_TEX_SHIFT 19
+# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
+# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
+
+#define GB_Z_PEQ_CONFIG 0x4028
+# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0)
+# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0)
+
+/* Specifies various polygon specific selects (fog, depth, perspective). */
+#define R300_GB_SELECT 0x401c
+# define R300_GB_FOG_SELECT_C0A (0 << 0)
+# define R300_GB_FOG_SELECT_C1A (1 << 0)
+# define R300_GB_FOG_SELECT_C2A (2 << 0)
+# define R300_GB_FOG_SELECT_C3A (3 << 0)
+# define R300_GB_FOG_SELECT_1_1_W (4 << 0)
+# define R300_GB_FOG_SELECT_Z (5 << 0)
+# define R300_GB_DEPTH_SELECT_Z (0 << 3)
+# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3)
+# define R300_GB_W_SELECT_1_W (0 << 4)
+# define R300_GB_W_SELECT_1 (1 << 4)
+# define R300_GB_FOG_STUFF_DISABLE (0 << 5)
+# define R300_GB_FOG_STUFF_ENABLE (1 << 5)
+# define R300_GB_FOG_STUFF_TEX_SHIFT 6
+# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0
+# define R300_GB_FOG_STUFF_COMP_SHIFT 10
+# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00
+
+/* Specifies the graphics pipeline configuration for antialiasing. */
+#define R300_GB_AA_CONFIG 0x4020
+# define GB_AA_CONFIG_AA_DISABLE (0 << 0)
+# define GB_AA_CONFIG_AA_ENABLE (1 << 0)
+# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2 (0 << 1)
+# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3 (1 << 1)
+# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4 (2 << 1)
+# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6 (3 << 1)
+
+/* Selects which of 4 pipes are active. */
+#define GB_PIPE_SELECT 0x402c
+# define GB_PIPE_SELECT_PIPE0_ID_SHIFT 0
+# define GB_PIPE_SELECT_PIPE1_ID_SHIFT 2
+# define GB_PIPE_SELECT_PIPE2_ID_SHIFT 4
+# define GB_PIPE_SELECT_PIPE3_ID_SHIFT 6
+# define GB_PIPE_SELECT_PIPE_MASK_SHIFT 8
+# define GB_PIPE_SELECT_MAX_PIPE 12
+# define GB_PIPE_SELECT_BAD_PIPES 14
+# define GB_PIPE_SELECT_CONFIG_PIPES 18
+
+
+/* Specifies the sizes of the various FIFO`s in the sc/rs. */
+#define GB_FIFO_SIZE1 0x4070
+/* High water mark for SC input fifo */
+# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_SHIFT 0
+# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_MASK 0x0000003f
+/* High water mark for SC input fifo (B) */
+# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_SHIFT 6
+# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_MASK 0x00000fc0
+/* High water mark for RS colors' fifo */
+# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_SHIFT 12
+# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_MASK 0x0003f000
+/* High water mark for RS textures' fifo */
+# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18
+# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000
+
+/* This table specifies the source location and format for up to 16 texture
+ * addresses (i[0]:i[15]) and four colors (c[0]:c[3])
+ */
+#define R500_RS_IP_0 0x4074
+#define R500_RS_IP_1 0x4078
+#define R500_RS_IP_2 0x407C
+#define R500_RS_IP_3 0x4080
+#define R500_RS_IP_4 0x4084
+#define R500_RS_IP_5 0x4088
+#define R500_RS_IP_6 0x408C
+#define R500_RS_IP_7 0x4090
+#define R500_RS_IP_8 0x4094
+#define R500_RS_IP_9 0x4098
+#define R500_RS_IP_10 0x409C
+#define R500_RS_IP_11 0x40A0
+#define R500_RS_IP_12 0x40A4
+#define R500_RS_IP_13 0x40A8
+#define R500_RS_IP_14 0x40AC
+#define R500_RS_IP_15 0x40B0
+#define R500_RS_IP_PTR_K0 62
+#define R500_RS_IP_PTR_K1 63
+#define R500_RS_IP_TEX_PTR_S_SHIFT 0
+#define R500_RS_IP_TEX_PTR_T_SHIFT 6
+#define R500_RS_IP_TEX_PTR_R_SHIFT 12
+#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
+#define R500_RS_IP_COL_PTR_SHIFT 24
+#define R500_RS_IP_COL_FMT_SHIFT 27
+# define R500_RS_COL_PTR(x) (x << 24)
+# define R500_RS_COL_FMT(x) (x << 27)
+/* gap */
+#define R500_RS_IP_OFFSET_DIS (0 << 31)
+#define R500_RS_IP_OFFSET_EN (1 << 31)
+
+/* gap */
+
+/* Zero to flush caches. */
+#define R300_TX_INVALTAGS 0x4100
+#define R300_TX_FLUSH 0x0
+
+/* The upper enable bits are guessed, based on fglrx reported limits. */
+#define R300_TX_ENABLE 0x4104
+# define R300_TX_ENABLE_0 (1 << 0)
+# define R300_TX_ENABLE_1 (1 << 1)
+# define R300_TX_ENABLE_2 (1 << 2)
+# define R300_TX_ENABLE_3 (1 << 3)
+# define R300_TX_ENABLE_4 (1 << 4)
+# define R300_TX_ENABLE_5 (1 << 5)
+# define R300_TX_ENABLE_6 (1 << 6)
+# define R300_TX_ENABLE_7 (1 << 7)
+# define R300_TX_ENABLE_8 (1 << 8)
+# define R300_TX_ENABLE_9 (1 << 9)
+# define R300_TX_ENABLE_10 (1 << 10)
+# define R300_TX_ENABLE_11 (1 << 11)
+# define R300_TX_ENABLE_12 (1 << 12)
+# define R300_TX_ENABLE_13 (1 << 13)
+# define R300_TX_ENABLE_14 (1 << 14)
+# define R300_TX_ENABLE_15 (1 << 15)
+
+#define R500_TX_FILTER_4 0x4110
+# define R500_TX_WEIGHT_1_SHIFT (0)
+# define R500_TX_WEIGHT_0_SHIFT (11)
+# define R500_TX_WEIGHT_PAIR (1<<22)
+# define R500_TX_PHASE_SHIFT (23)
+# define R500_TX_DIRECTION_HORIZONTAL (0<<27)
+# define R500_TX_DIRECTION_VERITCAL (1<<27)
+
+/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
+#define R300_GA_POINT_S0 0x4200
+
+/* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
+#define R300_GA_POINT_T0 0x4204
+
+/* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
+#define R300_GA_POINT_S1 0x4208
+
+/* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
+#define R300_GA_POINT_T1 0x420c
+
+/* Specifies amount to shift integer position of vertex (screen space) before
+ * converting to float for triangle stipple.
+ */
+#define R300_GA_TRIANGLE_STIPPLE 0x4214
+# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0
+# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f
+# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16
+# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000
+
+/* The pointsize is given in multiples of 6. The pointsize can be enormous:
+ * Clear() renders a single point that fills the entire framebuffer.
+ * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in
+ * 8b precision).
+ */
+#define R300_GA_POINT_SIZE 0x421C
+# define R300_POINTSIZE_Y_SHIFT 0
+# define R300_POINTSIZE_Y_MASK 0x0000ffff
+# define R300_POINTSIZE_X_SHIFT 16
+# define R300_POINTSIZE_X_MASK 0xffff0000
+# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
+
+/* Blue fill color */
+#define R500_GA_FILL_R 0x4220
+
+/* Blue fill color */
+#define R500_GA_FILL_G 0x4224
+
+/* Blue fill color */
+#define R500_GA_FILL_B 0x4228
+
+/* Alpha fill color */
+#define R500_GA_FILL_A 0x422c
+
+
+/* Specifies maximum and minimum point & sprite sizes for per vertex size
+ * specification. The lower part (15:0) is MIN and (31:16) is max.
+ */
+#define R300_GA_POINT_MINMAX 0x4230
+# define R300_GA_POINT_MINMAX_MIN_SHIFT 0
+# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0)
+# define R300_GA_POINT_MINMAX_MAX_SHIFT 16
+# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16)
+
+/* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b
+ * subprecision); (16.0) fixed format.
+ *
+ * The line width is given in multiples of 6.
+ * In default mode lines are classified as vertical lines.
+ * HO: horizontal
+ * VE: vertical or horizontal
+ * HO & VE: no classification
+ */
+#define R300_GA_LINE_CNTL 0x4234
+# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0
+# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff
+# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16)
+# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16)
+# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */
+# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */
+# define R500_GA_LINE_CNTL_SORT_NO (0 << 18)
+# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18)
+/** TODO: looks wrong */
+# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6)
+/** TODO: looks wrong */
+# define R300_LINE_CNT_HO (1 << 16)
+/** TODO: looks wrong */
+# define R300_LINE_CNT_VE (1 << 17)
+
+/* Line Stipple configuration information. */
+#define R300_GA_LINE_STIPPLE_CONFIG 0x4238
+# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0)
+# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0)
+# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0)
+# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2
+# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc
+
+/* Used to load US instructions and constants */
+#define R500_GA_US_VECTOR_INDEX 0x4250
+# define R500_GA_US_VECTOR_INDEX_SHIFT 0
+# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff
+# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16)
+# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16)
+# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17)
+# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17)
+
+/* Data register for loading US instructions and constants */
+#define R500_GA_US_VECTOR_DATA 0x4254
+
+/* Specifies color properties and mappings of textures. */
+#define R500_GA_COLOR_CONTROL_PS3 0x4258
+# define R500_TEX0_SHADING_PS3_SOLID (0 << 0)
+# define R500_TEX0_SHADING_PS3_FLAT (1 << 0)
+# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0)
+# define R500_TEX1_SHADING_PS3_SOLID (0 << 2)
+# define R500_TEX1_SHADING_PS3_FLAT (1 << 2)
+# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2)
+# define R500_TEX2_SHADING_PS3_SOLID (0 << 4)
+# define R500_TEX2_SHADING_PS3_FLAT (1 << 4)
+# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4)
+# define R500_TEX3_SHADING_PS3_SOLID (0 << 6)
+# define R500_TEX3_SHADING_PS3_FLAT (1 << 6)
+# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6)
+# define R500_TEX4_SHADING_PS3_SOLID (0 << 8)
+# define R500_TEX4_SHADING_PS3_FLAT (1 << 8)
+# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8)
+# define R500_TEX5_SHADING_PS3_SOLID (0 << 10)
+# define R500_TEX5_SHADING_PS3_FLAT (1 << 10)
+# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10)
+# define R500_TEX6_SHADING_PS3_SOLID (0 << 12)
+# define R500_TEX6_SHADING_PS3_FLAT (1 << 12)
+# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12)
+# define R500_TEX7_SHADING_PS3_SOLID (0 << 14)
+# define R500_TEX7_SHADING_PS3_FLAT (1 << 14)
+# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14)
+# define R500_TEX8_SHADING_PS3_SOLID (0 << 16)
+# define R500_TEX8_SHADING_PS3_FLAT (1 << 16)
+# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16)
+# define R500_TEX9_SHADING_PS3_SOLID (0 << 18)
+# define R500_TEX9_SHADING_PS3_FLAT (1 << 18)
+# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18)
+# define R500_TEX10_SHADING_PS3_SOLID (0 << 20)
+# define R500_TEX10_SHADING_PS3_FLAT (1 << 20)
+# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20)
+# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22)
+# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22)
+# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26)
+# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26)
+
+/* Returns idle status of various G3D block, captured when GA_IDLE written or
+ * when hard or soft reset asserted.
+ */
+#define R500_GA_IDLE 0x425c
+# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0)
+# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1)
+# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2)
+# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3)
+# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4)
+# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5)
+# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6)
+# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7)
+# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8)
+# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9)
+# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10)
+# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11)
+# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12)
+# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13)
+# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14)
+# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15)
+# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16)
+# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17)
+# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18)
+# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19)
+# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20)
+# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21)
+# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22)
+# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23)
+# define R500_GA_IDLE_SU_IDLE (0 << 24)
+# define R500_GA_IDLE_GA_IDLE (0 << 25)
+# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26)
+
+/* Current value of stipple accumulator. */
+#define R300_GA_LINE_STIPPLE_VALUE 0x4260
+
+/* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */
+#define R300_GA_LINE_S0 0x4264
+/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */
+#define R300_GA_LINE_S1 0x4268
+
+/* GA Input fifo high water marks */
+#define R500_GA_FIFO_CNTL 0x4270
+# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007
+# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0
+# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038
+# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3
+# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0
+# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6
+
+/* GA enhance/tweaks */
+#define R300_GA_ENHANCE 0x4274
+# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0)
+# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */
+# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1)
+# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */
+# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */
+# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */
+# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3)
+# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */
+
+#define R300_GA_COLOR_CONTROL 0x4278
+# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0)
+# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0)
+# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0)
+# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2)
+# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2)
+# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2)
+# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4)
+# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4)
+# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4)
+# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6)
+# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6)
+# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6)
+# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8)
+# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8)
+# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8)
+# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10)
+# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10)
+# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10)
+# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12)
+# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12)
+# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12)
+# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14)
+# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14)
+# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14)
+# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16)
+# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16)
+# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16)
+# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16)
+
+/** TODO: might be candidate for removal */
+# define R300_RE_SHADE_MODEL_SMOOTH ( \
+ R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \
+ R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
+ R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \
+ R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
+ R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
+/** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */
+# define R300_RE_SHADE_MODEL_FLAT ( \
+ R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \
+ R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
+ R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \
+ R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
+ R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
+
+/* Specifies red & green components of fill color -- S312 format -- Backwards comp. */
+#define R300_GA_SOLID_RG 0x427c
+# define GA_SOLID_RG_COLOR_GREEN_SHIFT 0
+# define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff
+# define GA_SOLID_RG_COLOR_RED_SHIFT 16
+# define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000
+/* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */
+#define R300_GA_SOLID_BA 0x4280
+# define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0
+# define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff
+# define GA_SOLID_BA_COLOR_BLUE_SHIFT 16
+# define GA_SOLID_BA_COLOR_BLUE_MASK 0xffff0000
+
+/* Polygon Mode
+ * Dangerous
+ */
+#define R300_GA_POLY_MODE 0x4288
+# define R300_GA_POLY_MODE_DISABLE (0 << 0)
+# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */
+/* reserved */
+# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4)
+# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4)
+# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4)
+/* reserved */
+# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7)
+# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7)
+# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7)
+/* reserved */
+
+/* Specifies the rouding mode for geometry & color SPFP to FP conversions. */
+#define R300_GA_ROUND_MODE 0x428c
+# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0)
+# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0)
+# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2)
+# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2)
+# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4)
+# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4)
+# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5)
+# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5)
+# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6
+# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0
+
+/* Specifies x & y offsets for vertex data after conversion to FP.
+ * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b
+ * subprecision).
+ */
+#define R300_GA_OFFSET 0x4290
+# define R300_GA_OFFSET_X_OFFSET_SHIFT 0
+# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff
+# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16
+# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000
+
+/* Specifies the scale to apply to fog. */
+#define R300_GA_FOG_SCALE 0x4294
+/* Specifies the offset to apply to fog. */
+#define R300_GA_FOG_OFFSET 0x4298
+/* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */
+#define R300_GA_SOFT_RESET 0x429c
+
+/* Not sure why there are duplicate of factor and constant values.
+ * My best guess so far is that there are seperate zbiases for test and write.
+ * Ordering might be wrong.
+ * Some of the tests indicate that fgl has a fallback implementation of zbias
+ * via pixel shaders.
+ */
+#define R300_SU_TEX_WRAP 0x42A0
+#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4
+#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8
+#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC
+#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0
+
+/* This register needs to be set to (1<<1) for RV350 to correctly
+ * perform depth test (see --vb-triangles in r300_demo)
+ * Don't know about other chips. - Vladimir
+ * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
+ * My guess is that there are two bits for each zbias primitive
+ * (FILL, LINE, POINT).
+ * One to enable depth test and one for depth write.
+ * Yet this doesnt explain why depth writes work ...
+ */
+#define R300_SU_POLY_OFFSET_ENABLE 0x42B4
+# define R300_FRONT_ENABLE (1 << 0)
+# define R300_BACK_ENABLE (1 << 1)
+# define R300_PARA_ENABLE (1 << 2)
+
+#define R300_SU_CULL_MODE 0x42B8
+# define R300_CULL_FRONT (1 << 0)
+# define R300_CULL_BACK (1 << 1)
+# define R300_FRONT_FACE_CCW (0 << 2)
+# define R300_FRONT_FACE_CW (1 << 2)
+
+/* SU Depth Scale value */
+#define R300_SU_DEPTH_SCALE 0x42c0
+/* SU Depth Offset value */
+#define R300_SU_DEPTH_OFFSET 0x42c4
+
+
+/* BEGIN: Rasterization / Interpolators - many guesses */
+
+/*
+ * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
+ * on the vertex program, *not* the fragment program)
+ */
+#define R300_RS_COUNT 0x4300
+# define R300_IT_COUNT_SHIFT 0
+# define R300_IT_COUNT_MASK 0x0000007f
+# define R300_IC_COUNT_SHIFT 7
+# define R300_IC_COUNT_MASK 0x00000780
+# define R300_W_ADDR_SHIFT 12
+# define R300_W_ADDR_MASK 0x0003f000
+# define R300_HIRES_DIS (0 << 18)
+# define R300_HIRES_EN (1 << 18)
+
+#define R300_RS_INST_COUNT 0x4304
+# define R300_RS_INST_COUNT_SHIFT 0
+# define R300_RS_INST_COUNT_MASK 0x0000000f
+# define R300_RS_TX_OFFSET_SHIFT 5
+# define R300_RS_TX_OFFSET_MASK 0x000000e0
+
+/* gap */
+
+/* Only used for texture coordinates.
+ * Use the source field to route texture coordinate input from the
+ * vertex program to the desired interpolator. Note that the source
+ * field is relative to the outputs the vertex program *actually*
+ * writes. If a vertex program only writes texcoord[1], this will
+ * be source index 0.
+ * Set INTERP_USED on all interpolators that produce data used by
+ * the fragment program. INTERP_USED looks like a swizzling mask,
+ * but I haven't seen it used that way.
+ *
+ * Note: The _UNKNOWN constants are always set in their respective
+ * register. I don't know if this is necessary.
+ */
+#define R300_RS_IP_0 0x4310
+#define R300_RS_IP_1 0x4314
+#define R300_RS_IP_2 0x4318
+#define R300_RS_IP_3 0x431C
+# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */
+# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */
+# define R300_RS_TEX_PTR(x) (x << 0)
+# define R300_RS_COL_PTR(x) (x << 6)
+# define R300_RS_COL_FMT(x) (x << 9)
+# define R300_RS_COL_FMT_RGBA 0
+# define R300_RS_COL_FMT_RGB0 1
+# define R300_RS_COL_FMT_RGB1 2
+# define R300_RS_COL_FMT_000A 4
+# define R300_RS_COL_FMT_0000 5
+# define R300_RS_COL_FMT_0001 6
+# define R300_RS_COL_FMT_111A 8
+# define R300_RS_COL_FMT_1110 9
+# define R300_RS_COL_FMT_1111 10
+# define R300_RS_SEL_S(x) (x << 13)
+# define R300_RS_SEL_T(x) (x << 16)
+# define R300_RS_SEL_R(x) (x << 19)
+# define R300_RS_SEL_Q(x) (x << 22)
+# define R300_RS_SEL_C0 0
+# define R300_RS_SEL_C1 1
+# define R300_RS_SEL_C2 2
+# define R300_RS_SEL_C3 3
+# define R300_RS_SEL_K0 4
+# define R300_RS_SEL_K1 5
+
+
+/* */
+#define R500_RS_INST_0 0x4320
+#define R500_RS_INST_1 0x4324
+#define R500_RS_INST_2 0x4328
+#define R500_RS_INST_3 0x432c
+#define R500_RS_INST_4 0x4330
+#define R500_RS_INST_5 0x4334
+#define R500_RS_INST_6 0x4338
+#define R500_RS_INST_7 0x433c
+#define R500_RS_INST_8 0x4340
+#define R500_RS_INST_9 0x4344
+#define R500_RS_INST_10 0x4348
+#define R500_RS_INST_11 0x434c
+#define R500_RS_INST_12 0x4350
+#define R500_RS_INST_13 0x4354
+#define R500_RS_INST_14 0x4358
+#define R500_RS_INST_15 0x435c
+#define R500_RS_INST_TEX_ID_SHIFT 0
+#define R500_RS_INST_TEX_CN_WRITE (1 << 4)
+#define R500_RS_INST_TEX_ADDR_SHIFT 5
+#define R500_RS_INST_COL_ID_SHIFT 12
+#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
+#define R500_RS_INST_COL_CN_WRITE (1 << 16)
+#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
+#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
+#define R500_RS_INST_COL_ADDR_SHIFT 18
+#define R500_RS_INST_TEX_ADJ (1 << 25)
+#define R500_RS_INST_W_CN (1 << 26)
+
+/* These DWORDs control how vertex data is routed into fragment program
+ * registers, after interpolators.
+ */
+#define R300_RS_INST_0 0x4330
+#define R300_RS_INST_1 0x4334
+#define R300_RS_INST_2 0x4338
+#define R300_RS_INST_3 0x433C
+#define R300_RS_INST_4 0x4340
+#define R300_RS_INST_5 0x4344
+#define R300_RS_INST_6 0x4348
+#define R300_RS_INST_7 0x434C
+# define R300_RS_INST_TEX_ID(x) ((x) << 0)
+# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
+# define R300_RS_INST_TEX_ADDR_SHIFT 6
+# define R300_RS_INST_COL_ID(x) ((x) << 11)
+# define R300_RS_INST_COL_CN_WRITE (1 << 14)
+# define R300_RS_INST_COL_ADDR_SHIFT 17
+# define R300_RS_INST_TEX_ADJ (1 << 22)
+# define R300_RS_COL_BIAS_UNUSED_SHIFT 23
+
+/* END: Rasterization / Interpolators - many guesses */
+
+/* Hierarchical Z Enable */
+#define R300_SC_HYPERZ 0x43a4
+# define R300_SC_HYPERZ_DISABLE (0 << 0)
+# define R300_SC_HYPERZ_ENABLE (1 << 0)
+# define R300_SC_HYPERZ_MIN (0 << 1)
+# define R300_SC_HYPERZ_MAX (1 << 1)
+# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
+# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
+# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
+# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
+# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
+# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
+# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
+# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
+# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
+# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
+# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
+# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
+
+#define R300_SC_EDGERULE 0x43a8
+
+/* BEGIN: Scissors and cliprects */
+
+/* There are four clipping rectangles. Their corner coordinates are inclusive.
+ * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
+ * on whether the pixel is inside cliprects 0-3, respectively. For example,
+ * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
+ * the number 3 (binary 0011).
+ * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
+ * the pixel is rasterized.
+ *
+ * In addition to this, there is a scissors rectangle. Only pixels inside the
+ * scissors rectangle are drawn. (coordinates are inclusive)
+ *
+ * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
+ * for the purpose of clipping and scissors.
+ */
+#define R300_SC_CLIPRECT_TL_0 0x43B0
+#define R300_SC_CLIPRECT_BR_0 0x43B4
+#define R300_SC_CLIPRECT_TL_1 0x43B8
+#define R300_SC_CLIPRECT_BR_1 0x43BC
+#define R300_SC_CLIPRECT_TL_2 0x43C0
+#define R300_SC_CLIPRECT_BR_2 0x43C4
+#define R300_SC_CLIPRECT_TL_3 0x43C8
+#define R300_SC_CLIPRECT_BR_3 0x43CC
+# define R300_CLIPRECT_OFFSET 1440
+# define R300_CLIPRECT_MASK 0x1FFF
+# define R300_CLIPRECT_X_SHIFT 0
+# define R300_CLIPRECT_X_MASK (0x1FFF << 0)
+# define R300_CLIPRECT_Y_SHIFT 13
+# define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
+#define R300_SC_CLIP_RULE 0x43D0
+# define R300_CLIP_OUT (1 << 0)
+# define R300_CLIP_0 (1 << 1)
+# define R300_CLIP_1 (1 << 2)
+# define R300_CLIP_10 (1 << 3)
+# define R300_CLIP_2 (1 << 4)
+# define R300_CLIP_20 (1 << 5)
+# define R300_CLIP_21 (1 << 6)
+# define R300_CLIP_210 (1 << 7)
+# define R300_CLIP_3 (1 << 8)
+# define R300_CLIP_30 (1 << 9)
+# define R300_CLIP_31 (1 << 10)
+# define R300_CLIP_310 (1 << 11)
+# define R300_CLIP_32 (1 << 12)
+# define R300_CLIP_320 (1 << 13)
+# define R300_CLIP_321 (1 << 14)
+# define R300_CLIP_3210 (1 << 15)
+
+/* gap */
+
+#define R300_SC_SCISSORS_TL 0x43E0
+#define R300_SC_SCISSORS_BR 0x43E4
+# define R300_SCISSORS_OFFSET 1440
+# define R300_SCISSORS_X_SHIFT 0
+# define R300_SCISSORS_X_MASK (0x1FFF << 0)
+# define R300_SCISSORS_Y_SHIFT 13
+# define R300_SCISSORS_Y_MASK (0x1FFF << 13)
+
+/* Screen door sample mask */
+#define R300_SC_SCREENDOOR 0x43e8
+
+/* END: Scissors and cliprects */
+
+/* BEGIN: Texture specification */
+
+/*
+ * The texture specification dwords are grouped by meaning and not by texture
+ * unit. This means that e.g. the offset for texture image unit N is found in
+ * register TX_OFFSET_0 + (4*N)
+ */
+#define R300_TX_FILTER0_0 0x4400
+#define R300_TX_FILTER0_1 0x4404
+#define R300_TX_FILTER0_2 0x4408
+#define R300_TX_FILTER0_3 0x440c
+#define R300_TX_FILTER0_4 0x4410
+#define R300_TX_FILTER0_5 0x4414
+#define R300_TX_FILTER0_6 0x4418
+#define R300_TX_FILTER0_7 0x441c
+#define R300_TX_FILTER0_8 0x4420
+#define R300_TX_FILTER0_9 0x4424
+#define R300_TX_FILTER0_10 0x4428
+#define R300_TX_FILTER0_11 0x442c
+#define R300_TX_FILTER0_12 0x4430
+#define R300_TX_FILTER0_13 0x4434
+#define R300_TX_FILTER0_14 0x4438
+#define R300_TX_FILTER0_15 0x443c
+# define R300_TX_REPEAT 0
+# define R300_TX_MIRRORED 1
+# define R300_TX_CLAMP_TO_EDGE 2
+# define R300_TX_MIRROR_ONCE_TO_EDGE 3
+# define R300_TX_CLAMP 4
+# define R300_TX_MIRROR_ONCE 5
+# define R300_TX_CLAMP_TO_BORDER 6
+# define R300_TX_MIRROR_ONCE_TO_BORDER 7
+# define R300_TX_WRAP_S_SHIFT 0
+# define R300_TX_WRAP_S_MASK (7 << 0)
+# define R300_TX_WRAP_T_SHIFT 3
+# define R300_TX_WRAP_T_MASK (7 << 3)
+# define R300_TX_WRAP_R_SHIFT 6
+# define R300_TX_WRAP_R_MASK (7 << 6)
+# define R300_TX_MAG_FILTER_4 (0 << 9)
+# define R300_TX_MAG_FILTER_NEAREST (1 << 9)
+# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
+# define R300_TX_MAG_FILTER_ANISO (3 << 9)
+# define R300_TX_MAG_FILTER_MASK (3 << 9)
+# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
+# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
+# define R300_TX_MIN_FILTER_ANISO (3 << 11)
+# define R300_TX_MIN_FILTER_MASK (3 << 11)
+# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13)
+# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13)
+# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13)
+# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13)
+# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
+# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21)
+# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21)
+# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21)
+# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21)
+# define R300_TX_MAX_ANISO_MASK (7 << 21)
+
+#define R300_TX_FILTER1_0 0x4440
+# define R300_CHROMA_KEY_MODE_DISABLE 0
+# define R300_CHROMA_KEY_FORCE 1
+# define R300_CHROMA_KEY_BLEND 2
+# define R300_MC_ROUND_NORMAL (0<<2)
+# define R300_MC_ROUND_MPEG4 (1<<2)
+# define R300_LOD_BIAS_SHIFT 3
+# define R300_LOD_BIAS_MASK 0x1ff8
+# define R300_EDGE_ANISO_EDGE_DIAG (0<<13)
+# define R300_EDGE_ANISO_EDGE_ONLY (1<<13)
+# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14)
+# define R300_MC_COORD_TRUNCATE_MPEG (1<<14)
+# define R300_TX_TRI_PERF_0_8 (0<<15)
+# define R300_TX_TRI_PERF_1_8 (1<<15)
+# define R300_TX_TRI_PERF_1_4 (2<<15)
+# define R300_TX_TRI_PERF_3_8 (3<<15)
+# define R300_ANISO_THRESHOLD_MASK (7<<17)
+
+# define R500_MACRO_SWITCH (1<<22)
+# define R500_BORDER_FIX (1<<31)
+
+#define R300_TX_SIZE_0 0x4480
+# define R300_TX_WIDTHMASK_SHIFT 0
+# define R300_TX_WIDTHMASK_MASK (2047 << 0)
+# define R300_TX_HEIGHTMASK_SHIFT 11
+# define R300_TX_HEIGHTMASK_MASK (2047 << 11)
+# define R300_TX_DEPTHMASK_SHIFT 22
+# define R300_TX_DEPTHMASK_MASK (0xf << 22)
+# define R300_TX_MAX_MIP_LEVEL_SHIFT 26
+# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
+# define R300_TX_SIZE_PROJECTED (1<<30)
+# define R300_TX_SIZE_TXPITCH_EN (1<<31)
+#define R300_TX_FORMAT_0 0x44C0
+ /* The interpretation of the format word by Wladimir van der Laan */
+ /* The X, Y, Z and W refer to the layout of the components.
+ They are given meanings as R, G, B and Alpha by the swizzle
+ specification */
+# define R300_TX_FORMAT_X8 0x0
+# define R500_TX_FORMAT_X1 0x0 // bit set in format 2
+# define R300_TX_FORMAT_X16 0x1
+# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2
+# define R300_TX_FORMAT_Y4X4 0x2
+# define R300_TX_FORMAT_Y8X8 0x3
+# define R300_TX_FORMAT_Y16X16 0x4
+# define R300_TX_FORMAT_Z3Y3X2 0x5
+# define R300_TX_FORMAT_Z5Y6X5 0x6
+# define R300_TX_FORMAT_Z6Y5X5 0x7
+# define R300_TX_FORMAT_Z11Y11X10 0x8
+# define R300_TX_FORMAT_Z10Y11X11 0x9
+# define R300_TX_FORMAT_W4Z4Y4X4 0xA
+# define R300_TX_FORMAT_W1Z5Y5X5 0xB
+# define R300_TX_FORMAT_W8Z8Y8X8 0xC
+# define R300_TX_FORMAT_W2Z10Y10X10 0xD
+# define R300_TX_FORMAT_W16Z16Y16X16 0xE
+# define R300_TX_FORMAT_DXT1 0xF
+# define R300_TX_FORMAT_DXT3 0x10
+# define R300_TX_FORMAT_DXT5 0x11
+# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
+# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
+# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
+# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
+
+ /* These two values are wrong, but they're the only values that
+ * produce any even vaguely correct results. Can r300 only do 16-bit
+ * depth textures?
+ */
+# define R300_TX_FORMAT_X24_Y8 0x1e
+# define R300_TX_FORMAT_X32 0x1e
+
+ /* 0x16 - some 16 bit green format.. ?? */
+# define R300_TX_FORMAT_3D (1 << 25)
+# define R300_TX_FORMAT_CUBIC_MAP (2 << 25)
+
+ /* gap */
+ /* Floating point formats */
+ /* Note - hardware supports both 16 and 32 bit floating point */
+# define R300_TX_FORMAT_FL_I16 0x18
+# define R300_TX_FORMAT_FL_I16A16 0x19
+# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
+# define R300_TX_FORMAT_FL_I32 0x1B
+# define R300_TX_FORMAT_FL_I32A32 0x1C
+# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
+ /* alpha modes, convenience mostly */
+ /* if you have alpha, pick constant appropriate to the
+ number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
+# define R300_TX_FORMAT_ALPHA_1CH 0x000
+# define R300_TX_FORMAT_ALPHA_2CH 0x200
+# define R300_TX_FORMAT_ALPHA_4CH 0x600
+# define R300_TX_FORMAT_ALPHA_NONE 0xA00
+ /* Swizzling */
+ /* constants */
+# define R300_TX_FORMAT_X 0
+# define R300_TX_FORMAT_Y 1
+# define R300_TX_FORMAT_Z 2
+# define R300_TX_FORMAT_W 3
+# define R300_TX_FORMAT_ZERO 4
+# define R300_TX_FORMAT_ONE 5
+ /* 2.0*Z, everything above 1.0 is set to 0.0 */
+# define R300_TX_FORMAT_CUT_Z 6
+ /* 2.0*W, everything above 1.0 is set to 0.0 */
+# define R300_TX_FORMAT_CUT_W 7
+
+# define R300_TX_FORMAT_B_SHIFT 18
+# define R300_TX_FORMAT_G_SHIFT 15
+# define R300_TX_FORMAT_R_SHIFT 12
+# define R300_TX_FORMAT_A_SHIFT 9
+ /* Convenience macro to take care of layout and swizzling */
+# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
+ ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
+ | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
+ | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
+ | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
+ | (R300_TX_FORMAT_##FMT) \
+ )
+ /* These can be ORed with result of R300_EASY_TX_FORMAT()
+ We don't really know what they do. Take values from a
+ constant color ? */
+# define R300_TX_FORMAT_CONST_X (1<<5)
+# define R300_TX_FORMAT_CONST_Y (2<<5)
+# define R300_TX_FORMAT_CONST_Z (4<<5)
+# define R300_TX_FORMAT_CONST_W (8<<5)
+
+# define R300_TX_FORMAT_YUV_MODE 0x00800000
+
+#define R300_TX_FORMAT2_0 0x4500 /* obvious missing in gap */
+# define R300_TX_PITCHMASK_SHIFT 0
+# define R300_TX_PITCHMASK_MASK (2047 << 0)
+# define R500_TXFORMAT_MSB (1 << 14)
+# define R500_TXWIDTH_BIT11 (1 << 15)
+# define R500_TXHEIGHT_BIT11 (1 << 16)
+# define R500_POW2FIX2FLT (1 << 17)
+# define R500_SEL_FILTER4_TC0 (0 << 18)
+# define R500_SEL_FILTER4_TC1 (1 << 18)
+# define R500_SEL_FILTER4_TC2 (2 << 18)
+# define R500_SEL_FILTER4_TC3 (3 << 18)
+
+#define R300_TX_OFFSET_0 0x4540
+#define R300_TX_OFFSET_1 0x4544
+#define R300_TX_OFFSET_2 0x4548
+#define R300_TX_OFFSET_3 0x454C
+#define R300_TX_OFFSET_4 0x4550
+#define R300_TX_OFFSET_5 0x4554
+#define R300_TX_OFFSET_6 0x4558
+#define R300_TX_OFFSET_7 0x455C
+ /* BEGIN: Guess from R200 */
+# define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
+# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
+# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
+# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
+# define R300_TXO_MACRO_TILE (1 << 2)
+# define R300_TXO_MICRO_TILE_LINEAR (0 << 3)
+# define R300_TXO_MICRO_TILE (1 << 3)
+# define R300_TXO_MICRO_TILE_SQUARE (2 << 3)
+# define R300_TXO_OFFSET_MASK 0xffffffe0
+# define R300_TXO_OFFSET_SHIFT 5
+ /* END: Guess from R200 */
+
+/* 32 bit chroma key */
+#define R300_TX_CHROMA_KEY_0 0x4580
+#define R300_TX_CHROMA_KEY_1 0x4584
+#define R300_TX_CHROMA_KEY_2 0x4588
+#define R300_TX_CHROMA_KEY_3 0x458c
+#define R300_TX_CHROMA_KEY_4 0x4590
+#define R300_TX_CHROMA_KEY_5 0x4594
+#define R300_TX_CHROMA_KEY_6 0x4598
+#define R300_TX_CHROMA_KEY_7 0x459c
+#define R300_TX_CHROMA_KEY_8 0x45a0
+#define R300_TX_CHROMA_KEY_9 0x45a4
+#define R300_TX_CHROMA_KEY_10 0x45a8
+#define R300_TX_CHROMA_KEY_11 0x45ac
+#define R300_TX_CHROMA_KEY_12 0x45b0
+#define R300_TX_CHROMA_KEY_13 0x45b4
+#define R300_TX_CHROMA_KEY_14 0x45b8
+#define R300_TX_CHROMA_KEY_15 0x45bc
+/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
+
+/* Border Color */
+#define R300_TX_BORDER_COLOR_0 0x45c0
+#define R300_TX_BORDER_COLOR_1 0x45c4
+#define R300_TX_BORDER_COLOR_2 0x45c8
+#define R300_TX_BORDER_COLOR_3 0x45cc
+#define R300_TX_BORDER_COLOR_4 0x45d0
+#define R300_TX_BORDER_COLOR_5 0x45d4
+#define R300_TX_BORDER_COLOR_6 0x45d8
+#define R300_TX_BORDER_COLOR_7 0x45dc
+#define R300_TX_BORDER_COLOR_8 0x45e0
+#define R300_TX_BORDER_COLOR_9 0x45e4
+#define R300_TX_BORDER_COLOR_10 0x45e8
+#define R300_TX_BORDER_COLOR_11 0x45ec
+#define R300_TX_BORDER_COLOR_12 0x45f0
+#define R300_TX_BORDER_COLOR_13 0x45f4
+#define R300_TX_BORDER_COLOR_14 0x45f8
+#define R300_TX_BORDER_COLOR_15 0x45fc
+
+
+/* END: Texture specification */
+
+/* BEGIN: Fragment program instruction set */
+
+/* Fragment programs are written directly into register space.
+ * There are separate instruction streams for texture instructions and ALU
+ * instructions.
+ * In order to synchronize these streams, the program is divided into up
+ * to 4 nodes. Each node begins with a number of TEX operations, followed
+ * by a number of ALU operations.
+ * The first node can have zero TEX ops, all subsequent nodes must have at
+ * least
+ * one TEX ops.
+ * All nodes must have at least one ALU op.
+ *
+ * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
+ * 1 node, a value of 3 means 4 nodes.
+ * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
+ * offsets into the respective instruction streams, while *_END points to the
+ * last instruction relative to this offset.
+ */
+#define R300_US_CONFIG 0x4600
+# define R300_PFS_CNTL_LAST_NODES_SHIFT 0
+# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
+# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
+#define R300_US_PIXSIZE 0x4604
+/* There is an unshifted value here which has so far always been equal to the
+ * index of the highest used temporary register.
+ */
+#define R300_US_CODE_OFFSET 0x4608
+# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
+# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
+# define R300_PFS_CNTL_ALU_END_SHIFT 6
+# define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
+# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 13
+# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 13)
+# define R300_PFS_CNTL_TEX_END_SHIFT 18
+# define R300_PFS_CNTL_TEX_END_MASK (31 << 18)
+
+/* gap */
+
+/* Nodes are stored backwards. The last active node is always stored in
+ * PFS_NODE_3.
+ * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
+ * first node is stored in NODE_2, the second node is stored in NODE_3.
+ *
+ * Offsets are relative to the master offset from PFS_CNTL_2.
+ */
+#define R300_US_CODE_ADDR_0 0x4610
+#define R300_US_CODE_ADDR_1 0x4614
+#define R300_US_CODE_ADDR_2 0x4618
+#define R300_US_CODE_ADDR_3 0x461C
+# define R300_ALU_START_SHIFT 0
+# define R300_ALU_START_MASK (63 << 0)
+# define R300_ALU_SIZE_SHIFT 6
+# define R300_ALU_SIZE_MASK (63 << 6)
+# define R300_TEX_START_SHIFT 12
+# define R300_TEX_START_MASK (31 << 12)
+# define R300_TEX_SIZE_SHIFT 17
+# define R300_TEX_SIZE_MASK (31 << 17)
+# define R300_RGBA_OUT (1 << 22)
+# define R300_W_OUT (1 << 23)
+
+/* TEX
+ * As far as I can tell, texture instructions cannot write into output
+ * registers directly. A subsequent ALU instruction is always necessary,
+ * even if it's just MAD o0, r0, 1, 0
+ */
+#define R300_US_TEX_INST_0 0x4620
+# define R300_SRC_ADDR_SHIFT 0
+# define R300_SRC_ADDR_MASK (31 << 0)
+# define R300_DST_ADDR_SHIFT 6
+# define R300_DST_ADDR_MASK (31 << 6)
+# define R300_TEX_ID_SHIFT 11
+# define R300_TEX_ID_MASK (15 << 11)
+# define R300_TEX_INST_SHIFT 15
+# define R300_TEX_OP_NOP 0
+# define R300_TEX_OP_LD 1
+# define R300_TEX_OP_KIL 2
+# define R300_TEX_OP_TXP 3
+# define R300_TEX_OP_TXB 4
+# define R300_TEX_INST_MASK (7 << 15)
+
+/* Output format from the unfied shader */
+#define R300_US_OUT_FMT_0 0x46A4
+# define R300_US_OUT_FMT_C4_8 (0 << 0)
+# define R300_US_OUT_FMT_C4_10 (1 << 0)
+# define R300_US_OUT_FMT_C4_10_GAMMA (2 << 0)
+# define R300_US_OUT_FMT_C_16 (3 << 0)
+# define R300_US_OUT_FMT_C2_16 (4 << 0)
+# define R300_US_OUT_FMT_C4_16 (5 << 0)
+# define R300_US_OUT_FMT_C_16_MPEG (6 << 0)
+# define R300_US_OUT_FMT_C2_16_MPEG (7 << 0)
+# define R300_US_OUT_FMT_C2_4 (8 << 0)
+# define R300_US_OUT_FMT_C_3_3_2 (9 << 0)
+# define R300_US_OUT_FMT_C_6_5_6 (10 << 0)
+# define R300_US_OUT_FMT_C_11_11_10 (11 << 0)
+# define R300_US_OUT_FMT_C_10_11_11 (12 << 0)
+# define R300_US_OUT_FMT_C_2_10_10_10 (13 << 0)
+/* reserved */
+# define R300_US_OUT_FMT_UNUSED (15 << 0)
+# define R300_US_OUT_FMT_C_16_FP (16 << 0)
+# define R300_US_OUT_FMT_C2_16_FP (17 << 0)
+# define R300_US_OUT_FMT_C4_16_FP (18 << 0)
+# define R300_US_OUT_FMT_C_32_FP (19 << 0)
+# define R300_US_OUT_FMT_C2_32_FP (20 << 0)
+# define R300_US_OUT_FMT_C4_32_FP (21 << 0)
+# define R300_C0_SEL_A (0 << 8)
+# define R300_C0_SEL_R (1 << 8)
+# define R300_C0_SEL_G (2 << 8)
+# define R300_C0_SEL_B (3 << 8)
+# define R300_C1_SEL_A (0 << 10)
+# define R300_C1_SEL_R (1 << 10)
+# define R300_C1_SEL_G (2 << 10)
+# define R300_C1_SEL_B (3 << 10)
+# define R300_C2_SEL_A (0 << 12)
+# define R300_C2_SEL_R (1 << 12)
+# define R300_C2_SEL_G (2 << 12)
+# define R300_C2_SEL_B (3 << 12)
+# define R300_C3_SEL_A (0 << 14)
+# define R300_C3_SEL_R (1 << 14)
+# define R300_C3_SEL_G (2 << 14)
+# define R300_C3_SEL_B (3 << 14)
+# define R300_OUT_SIGN(x) (x << 16)
+# define R500_ROUND_ADJ (1 << 20)
+
+/* ALU
+ * The ALU instructions register blocks are enumerated according to the order
+ * in which fglrx. I assume there is space for 64 instructions, since
+ * each block has space for a maximum of 64 DWORDs, and this matches reported
+ * native limits.
+ *
+ * The basic functional block seems to be one MAD for each color and alpha,
+ * and an adder that adds all components after the MUL.
+ * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
+ * - DP4: Use OUTC_DP4, OUTA_DP4
+ * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
+ * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
+ * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
+ * - CMP: If ARG2 < 0, return ARG1, else return ARG0
+ * - FLR: use FRC+MAD
+ * - XPD: use MAD+MAD
+ * - SGE, SLT: use MAD+CMP
+ * - RSQ: use ABS modifier for argument
+ * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
+ * (e.g. RCP) into color register
+ * - apparently, there's no quick DST operation
+ * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
+ * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
+ * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
+ *
+ * Operand selection
+ * First stage selects three sources from the available registers and
+ * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
+ * fglrx sorts the three source fields: Registers before constants,
+ * lower indices before higher indices; I do not know whether this is
+ * necessary.
+ *
+ * fglrx fills unused sources with "read constant 0"
+ * According to specs, you cannot select more than two different constants.
+ *
+ * Second stage selects the operands from the sources. This is defined in
+ * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
+ * zero and one.
+ * Swizzling and negation happens in this stage, as well.
+ *
+ * Important: Color and alpha seem to be mostly separate, i.e. their sources
+ * selection appears to be fully independent (the register storage is probably
+ * physically split into a color and an alpha section).
+ * However (because of the apparent physical split), there is some interaction
+ * WRT swizzling. If, for example, you want to load an R component into an
+ * Alpha operand, this R component is taken from a *color* source, not from
+ * an alpha source. The corresponding register doesn't even have to appear in
+ * the alpha sources list. (I hope this all makes sense to you)
+ *
+ * Destination selection
+ * The destination register index is in FPI1 (color) and FPI3 (alpha)
+ * together with enable bits.
+ * There are separate enable bits for writing into temporary registers
+ * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
+ * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
+ * same index must be used for both).
+ *
+ * Note: There is a special form for LRP
+ * - Argument order is the same as in ARB_fragment_program.
+ * - Operation is MAD
+ * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
+ * - Set FPI0/FPI2_SPECIAL_LRP
+ * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
+ */
+#define R300_US_ALU_RGB_ADDR_0 0x46C0
+# define R300_ALU_SRC0C_SHIFT 0
+# define R300_ALU_SRC0C_MASK (31 << 0)
+# define R300_ALU_SRC0C_CONST (1 << 5)
+# define R300_ALU_SRC1C_SHIFT 6
+# define R300_ALU_SRC1C_MASK (31 << 6)
+# define R300_ALU_SRC1C_CONST (1 << 11)
+# define R300_ALU_SRC2C_SHIFT 12
+# define R300_ALU_SRC2C_MASK (31 << 12)
+# define R300_ALU_SRC2C_CONST (1 << 17)
+# define R300_ALU_SRC_MASK 0x0003ffff
+# define R300_ALU_DSTC_SHIFT 18
+# define R300_ALU_DSTC_MASK (31 << 18)
+# define R300_ALU_DSTC_REG_MASK_SHIFT 23
+# define R300_ALU_DSTC_REG_X (1 << 23)
+# define R300_ALU_DSTC_REG_Y (1 << 24)
+# define R300_ALU_DSTC_REG_Z (1 << 25)
+# define R300_ALU_DSTC_OUTPUT_MASK_SHIFT 26
+# define R300_ALU_DSTC_OUTPUT_X (1 << 26)
+# define R300_ALU_DSTC_OUTPUT_Y (1 << 27)
+# define R300_ALU_DSTC_OUTPUT_Z (1 << 28)
+
+#define R300_US_ALU_ALPHA_ADDR_0 0x47C0
+# define R300_ALU_SRC0A_SHIFT 0
+# define R300_ALU_SRC0A_MASK (31 << 0)
+# define R300_ALU_SRC0A_CONST (1 << 5)
+# define R300_ALU_SRC1A_SHIFT 6
+# define R300_ALU_SRC1A_MASK (31 << 6)
+# define R300_ALU_SRC1A_CONST (1 << 11)
+# define R300_ALU_SRC2A_SHIFT 12
+# define R300_ALU_SRC2A_MASK (31 << 12)
+# define R300_ALU_SRC2A_CONST (1 << 17)
+# define R300_ALU_SRC_MASK 0x0003ffff
+# define R300_ALU_DSTA_SHIFT 18
+# define R300_ALU_DSTA_MASK (31 << 18)
+# define R300_ALU_DSTA_REG (1 << 23)
+# define R300_ALU_DSTA_OUTPUT (1 << 24)
+# define R300_ALU_DSTA_DEPTH (1 << 27)
+
+#define R300_US_ALU_RGB_INST_0 0x48C0
+# define R300_ALU_ARGC_SRC0C_XYZ 0
+# define R300_ALU_ARGC_SRC0C_XXX 1
+# define R300_ALU_ARGC_SRC0C_YYY 2
+# define R300_ALU_ARGC_SRC0C_ZZZ 3
+# define R300_ALU_ARGC_SRC1C_XYZ 4
+# define R300_ALU_ARGC_SRC1C_XXX 5
+# define R300_ALU_ARGC_SRC1C_YYY 6
+# define R300_ALU_ARGC_SRC1C_ZZZ 7
+# define R300_ALU_ARGC_SRC2C_XYZ 8
+# define R300_ALU_ARGC_SRC2C_XXX 9
+# define R300_ALU_ARGC_SRC2C_YYY 10
+# define R300_ALU_ARGC_SRC2C_ZZZ 11
+# define R300_ALU_ARGC_SRC0A 12
+# define R300_ALU_ARGC_SRC1A 13
+# define R300_ALU_ARGC_SRC2A 14
+# define R300_ALU_ARGC_SRCP_XYZ 15
+# define R300_ALU_ARGC_SRCP_XXX 16
+# define R300_ALU_ARGC_SRCP_YYY 17
+# define R300_ALU_ARGC_SRCP_ZZZ 18
+# define R300_ALU_ARGC_SRCP_WWW 19
+# define R300_ALU_ARGC_ZERO 20
+# define R300_ALU_ARGC_ONE 21
+# define R300_ALU_ARGC_HALF 22
+# define R300_ALU_ARGC_SRC0C_YZX 23
+# define R300_ALU_ARGC_SRC1C_YZX 24
+# define R300_ALU_ARGC_SRC2C_YZX 25
+# define R300_ALU_ARGC_SRC0C_ZXY 26
+# define R300_ALU_ARGC_SRC1C_ZXY 27
+# define R300_ALU_ARGC_SRC2C_ZXY 28
+# define R300_ALU_ARGC_SRC0CA_WZY 29
+# define R300_ALU_ARGC_SRC1CA_WZY 30
+# define R300_ALU_ARGC_SRC2CA_WZY 31
+
+# define R300_ALU_ARG0C_SHIFT 0
+# define R300_ALU_ARG0C_MASK (31 << 0)
+# define R300_ALU_ARG0C_NOP (0 << 5)
+# define R300_ALU_ARG0C_NEG (1 << 5)
+# define R300_ALU_ARG0C_ABS (2 << 5)
+# define R300_ALU_ARG0C_NAB (3 << 5)
+# define R300_ALU_ARG1C_SHIFT 7
+# define R300_ALU_ARG1C_MASK (31 << 7)
+# define R300_ALU_ARG1C_NOP (0 << 12)
+# define R300_ALU_ARG1C_NEG (1 << 12)
+# define R300_ALU_ARG1C_ABS (2 << 12)
+# define R300_ALU_ARG1C_NAB (3 << 12)
+# define R300_ALU_ARG2C_SHIFT 14
+# define R300_ALU_ARG2C_MASK (31 << 14)
+# define R300_ALU_ARG2C_NOP (0 << 19)
+# define R300_ALU_ARG2C_NEG (1 << 19)
+# define R300_ALU_ARG2C_ABS (2 << 19)
+# define R300_ALU_ARG2C_NAB (3 << 19)
+# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
+# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
+# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
+# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
+
+# define R300_ALU_OUTC_MAD (0 << 23)
+# define R300_ALU_OUTC_DP3 (1 << 23)
+# define R300_ALU_OUTC_DP4 (2 << 23)
+# define R300_ALU_OUTC_D2A (3 << 23)
+# define R300_ALU_OUTC_MIN (4 << 23)
+# define R300_ALU_OUTC_MAX (5 << 23)
+# define R300_ALU_OUTC_CMPH (7 << 23)
+# define R300_ALU_OUTC_CMP (8 << 23)
+# define R300_ALU_OUTC_FRC (9 << 23)
+# define R300_ALU_OUTC_REPL_ALPHA (10 << 23)
+
+# define R300_ALU_OUTC_MOD_NOP (0 << 27)
+# define R300_ALU_OUTC_MOD_MUL2 (1 << 27)
+# define R300_ALU_OUTC_MOD_MUL4 (2 << 27)
+# define R300_ALU_OUTC_MOD_MUL8 (3 << 27)
+# define R300_ALU_OUTC_MOD_DIV2 (4 << 27)
+# define R300_ALU_OUTC_MOD_DIV4 (5 << 27)
+# define R300_ALU_OUTC_MOD_DIV8 (6 << 27)
+
+# define R300_ALU_OUTC_CLAMP (1 << 30)
+# define R300_ALU_INSERT_NOP (1 << 31)
+
+#define R300_US_ALU_ALPHA_INST_0 0x49C0
+# define R300_ALU_ARGA_SRC0C_X 0
+# define R300_ALU_ARGA_SRC0C_Y 1
+# define R300_ALU_ARGA_SRC0C_Z 2
+# define R300_ALU_ARGA_SRC1C_X 3
+# define R300_ALU_ARGA_SRC1C_Y 4
+# define R300_ALU_ARGA_SRC1C_Z 5
+# define R300_ALU_ARGA_SRC2C_X 6
+# define R300_ALU_ARGA_SRC2C_Y 7
+# define R300_ALU_ARGA_SRC2C_Z 8
+# define R300_ALU_ARGA_SRC0A 9
+# define R300_ALU_ARGA_SRC1A 10
+# define R300_ALU_ARGA_SRC2A 11
+# define R300_ALU_ARGA_SRCP_X 12
+# define R300_ALU_ARGA_SRCP_Y 13
+# define R300_ALU_ARGA_SRCP_Z 14
+# define R300_ALU_ARGA_SRCP_W 15
+
+# define R300_ALU_ARGA_ZERO 16
+# define R300_ALU_ARGA_ONE 17
+# define R300_ALU_ARGA_HALF 18
+# define R300_ALU_ARG0A_SHIFT 0
+# define R300_ALU_ARG0A_MASK (31 << 0)
+# define R300_ALU_ARG0A_NOP (0 << 5)
+# define R300_ALU_ARG0A_NEG (1 << 5)
+# define R300_ALU_ARG0A_ABS (2 << 5)
+# define R300_ALU_ARG0A_NAB (3 << 5)
+# define R300_ALU_ARG1A_SHIFT 7
+# define R300_ALU_ARG1A_MASK (31 << 7)
+# define R300_ALU_ARG1A_NOP (0 << 12)
+# define R300_ALU_ARG1A_NEG (1 << 12)
+# define R300_ALU_ARG1A_ABS (2 << 12)
+# define R300_ALU_ARG1A_NAB (3 << 12)
+# define R300_ALU_ARG2A_SHIFT 14
+# define R300_ALU_ARG2A_MASK (31 << 14)
+# define R300_ALU_ARG2A_NOP (0 << 19)
+# define R300_ALU_ARG2A_NEG (1 << 19)
+# define R300_ALU_ARG2A_ABS (2 << 19)
+# define R300_ALU_ARG2A_NAB (3 << 19)
+# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
+# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
+# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
+# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
+
+# define R300_ALU_OUTA_MAD (0 << 23)
+# define R300_ALU_OUTA_DP4 (1 << 23)
+# define R300_ALU_OUTA_MIN (2 << 23)
+# define R300_ALU_OUTA_MAX (3 << 23)
+# define R300_ALU_OUTA_CND (5 << 23)
+# define R300_ALU_OUTA_CMP (6 << 23)
+# define R300_ALU_OUTA_FRC (7 << 23)
+# define R300_ALU_OUTA_EX2 (8 << 23)
+# define R300_ALU_OUTA_LG2 (9 << 23)
+# define R300_ALU_OUTA_RCP (10 << 23)
+# define R300_ALU_OUTA_RSQ (11 << 23)
+
+# define R300_ALU_OUTA_MOD_NOP (0 << 27)
+# define R300_ALU_OUTA_MOD_MUL2 (1 << 27)
+# define R300_ALU_OUTA_MOD_MUL4 (2 << 27)
+# define R300_ALU_OUTA_MOD_MUL8 (3 << 27)
+# define R300_ALU_OUTA_MOD_DIV2 (4 << 27)
+# define R300_ALU_OUTA_MOD_DIV4 (5 << 27)
+# define R300_ALU_OUTA_MOD_DIV8 (6 << 27)
+
+# define R300_ALU_OUTA_CLAMP (1 << 30)
+/* END: Fragment program instruction set */
+
+/* Fog: Fog Blending Enable */
+#define R300_FG_FOG_BLEND 0x4bc0
+# define R300_FG_FOG_BLEND_DISABLE (0 << 0)
+# define R300_FG_FOG_BLEND_ENABLE (1 << 0)
+# define R300_FG_FOG_BLEND_FN_LINEAR (0 << 1)
+# define R300_FG_FOG_BLEND_FN_EXP (1 << 1)
+# define R300_FG_FOG_BLEND_FN_EXP2 (2 << 1)
+# define R300_FG_FOG_BLEND_FN_CONSTANT (3 << 1)
+# define R300_FG_FOG_BLEND_FN_MASK (3 << 1)
+
+/* Fog: Red Component of Fog Color */
+#define R300_FG_FOG_COLOR_R 0x4bc8
+/* Fog: Green Component of Fog Color */
+#define R300_FG_FOG_COLOR_G 0x4bcc
+/* Fog: Blue Component of Fog Color */
+#define R300_FG_FOG_COLOR_B 0x4bd0
+# define R300_FG_FOG_COLOR_MASK 0x000003ff
+
+/* Fog: Constant Factor for Fog Blending */
+#define R300_FG_FOG_FACTOR 0x4bc4
+# define FG_FOG_FACTOR_MASK 0x000003ff
+
+/* Fog: Alpha function */
+#define R300_FG_ALPHA_FUNC 0x4bd4
+# define R300_FG_ALPHA_FUNC_VAL_MASK 0x000000ff
+# define R300_FG_ALPHA_FUNC_NEVER (0 << 8)
+# define R300_FG_ALPHA_FUNC_LESS (1 << 8)
+# define R300_FG_ALPHA_FUNC_EQUAL (2 << 8)
+# define R300_FG_ALPHA_FUNC_LE (3 << 8)
+# define R300_FG_ALPHA_FUNC_GREATER (4 << 8)
+# define R300_FG_ALPHA_FUNC_NOTEQUAL (5 << 8)
+# define R300_FG_ALPHA_FUNC_GE (6 << 8)
+# define R300_FG_ALPHA_FUNC_ALWAYS (7 << 8)
+# define R300_ALPHA_TEST_OP_MASK (7 << 8)
+# define R300_FG_ALPHA_FUNC_DISABLE (0 << 11)
+# define R300_FG_ALPHA_FUNC_ENABLE (1 << 11)
+
+# define R500_FG_ALPHA_FUNC_10BIT (0 << 12)
+# define R500_FG_ALPHA_FUNC_8BIT (1 << 12)
+
+# define R300_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16)
+# define R300_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16)
+# define R300_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17)
+# define R300_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17)
+
+# define R300_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20)
+# define R300_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20)
+
+# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24)
+# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */
+# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25)
+# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25)
+
+# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28)
+# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28)
+
+
+/* Fog: Where does the depth come from? */
+#define R300_FG_DEPTH_SRC 0x4bd8
+# define R300_FG_DEPTH_SRC_SCAN (0 << 0)
+# define R300_FG_DEPTH_SRC_SHADER (1 << 0)
+
+/* Fog: Alpha Compare Value */
+#define R500_FG_ALPHA_VALUE 0x4be0
+# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff
+
+/* gap */
+
+/* Fragment program parameters in 7.16 floating point */
+#define R300_PFS_PARAM_0_X 0x4C00
+#define R300_PFS_PARAM_0_Y 0x4C04
+#define R300_PFS_PARAM_0_Z 0x4C08
+#define R300_PFS_PARAM_0_W 0x4C0C
+/* last consts */
+#define R300_PFS_PARAM_31_X 0x4DF0
+#define R300_PFS_PARAM_31_Y 0x4DF4
+#define R300_PFS_PARAM_31_Z 0x4DF8
+#define R300_PFS_PARAM_31_W 0x4DFC
+
+/* Unpipelined. */
+#define R300_RB3D_CCTL 0x4e00
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5)
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5)
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5)
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5)
+# define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7)
+# define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7)
+# define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9)
+# define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9)
+# define R300_RB3D_CCTL_CMASK_DISABLE (0 << 10)
+# define R300_RB3D_CCTL_CMASK_ENABLE (1 << 10)
+/* reserved */
+# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12)
+# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12)
+# define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13)
+# define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13)
+# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14)
+# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14)
+
+
+/* Notes:
+ * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
+ * the application
+ * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
+ * are set to the same
+ * function (both registers are always set up completely in any case)
+ * - Most blend flags are simply copied from R200 and not tested yet
+ */
+#define R300_RB3D_CBLEND 0x4E04
+#define R300_RB3D_ABLEND 0x4E08
+/* the following only appear in CBLEND */
+# define R300_ALPHA_BLEND_ENABLE (1 << 0)
+# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
+# define R300_READ_ENABLE (1 << 2)
+# define R300_DISCARD_SRC_PIXELS_DIS (0 << 3)
+# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3)
+# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3)
+# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3)
+# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3)
+# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3)
+# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3)
+
+/* the following are shared between CBLEND and ABLEND */
+# define R300_FCN_MASK (3 << 12)
+# define R300_COMB_FCN_ADD_CLAMP (0 << 12)
+# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
+# define R300_COMB_FCN_SUB_CLAMP (2 << 12)
+# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
+# define R300_COMB_FCN_MIN (4 << 12)
+# define R300_COMB_FCN_MAX (5 << 12)
+# define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
+# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
+# define R300_BLEND_GL_ZERO (32)
+# define R300_BLEND_GL_ONE (33)
+# define R300_BLEND_GL_SRC_COLOR (34)
+# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
+# define R300_BLEND_GL_DST_COLOR (36)
+# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
+# define R300_BLEND_GL_SRC_ALPHA (38)
+# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
+# define R300_BLEND_GL_DST_ALPHA (40)
+# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
+# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
+# define R300_BLEND_GL_CONST_COLOR (43)
+# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
+# define R300_BLEND_GL_CONST_ALPHA (45)
+# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
+# define R300_BLEND_MASK (63)
+# define R300_SRC_BLEND_SHIFT (16)
+# define R300_DST_BLEND_SHIFT (24)
+
+/* Constant color used by the blender. Pipelined through the blender.
+ * Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE,
+ * RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead.
+ */
+#define R300_RB3D_BLEND_COLOR 0x4E10
+
+
+/* 3D Color Channel Mask. If all the channels used in the current color format
+ * are disabled, then the cb will discard all the incoming quads. Pipelined
+ * through the blender.
+ */
+#define RB3D_COLOR_CHANNEL_MASK 0x4E0C
+# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 (1 << 0)
+# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 (1 << 1)
+# define RB3D_COLOR_CHANNEL_MASK_RED_MASK0 (1 << 2)
+# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 (1 << 3)
+# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK1 (1 << 4)
+# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK1 (1 << 5)
+# define RB3D_COLOR_CHANNEL_MASK_RED_MASK1 (1 << 6)
+# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK1 (1 << 7)
+# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK2 (1 << 8)
+# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK2 (1 << 9)
+# define RB3D_COLOR_CHANNEL_MASK_RED_MASK2 (1 << 10)
+# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK2 (1 << 11)
+# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK3 (1 << 12)
+# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK3 (1 << 13)
+# define RB3D_COLOR_CHANNEL_MASK_RED_MASK3 (1 << 14)
+# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK3 (1 << 15)
+
+/* Clear color that is used when the color mask is set to 00. Unpipelined.
+ * Program this register with a 32-bit value in ARGB8888 or ARGB2101010
+ * formats, ignoring the fields.
+ */
+#define RB3D_COLOR_CLEAR_VALUE 0x4e14
+
+/* gap */
+
+/* Color Compare Color. Stalls the 2d/3d datapath until it is idle. */
+#define RB3D_CLRCMP_CLR 0x4e20
+
+/* Color Compare Mask. Stalls the 2d/3d datapath until it is idle. */
+#define RB3D_CLRCMP_MSK 0x4e24
+
+/* Color Buffer Address Offset of multibuffer 0. Unpipelined. */
+#define R300_RB3D_COLOROFFSET0 0x4E28
+# define R300_COLOROFFSET_MASK 0xFFFFFFE0
+/* Color Buffer Address Offset of multibuffer 1. Unpipelined. */
+#define R300_RB3D_COLOROFFSET1 0x4E2C
+/* Color Buffer Address Offset of multibuffer 2. Unpipelined. */
+#define R300_RB3D_COLOROFFSET2 0x4E30
+/* Color Buffer Address Offset of multibuffer 3. Unpipelined. */
+#define R300_RB3D_COLOROFFSET3 0x4E34
+
+/* Color buffer format and tiling control for all the multibuffers and the
+ * pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any
+ * of the registers are changed.
+ *
+ * Bit 16: Larger tiles
+ * Bit 17: 4x2 tiles
+ * Bit 18: Extremely weird tile like, but some pixels duplicated?
+ */
+#define R300_RB3D_COLORPITCH0 0x4E38
+# define R300_COLORPITCH_MASK 0x00003FFE
+# define R300_COLOR_TILE_DISABLE (0 << 16)
+# define R300_COLOR_TILE_ENABLE (1 << 16)
+# define R300_COLOR_MICROTILE_DISABLE (0 << 17)
+# define R300_COLOR_MICROTILE_ENABLE (1 << 17)
+# define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */
+# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19)
+# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19)
+# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19)
+# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19)
+# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21)
+# define R500_COLOR_FORMAT_UV1010 (1 << 21)
+# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */
+# define R300_COLOR_FORMAT_ARGB1555 (3 << 21)
+# define R300_COLOR_FORMAT_RGB565 (4 << 21)
+# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21)
+# define R300_COLOR_FORMAT_ARGB8888 (6 << 21)
+# define R300_COLOR_FORMAT_ARGB32323232 (7 << 21)
+/* reserved */
+# define R300_COLOR_FORMAT_I8 (9 << 21)
+# define R300_COLOR_FORMAT_ARGB16161616 (10 << 21)
+# define R300_COLOR_FORMAT_VYUY (11 << 21)
+# define R300_COLOR_FORMAT_YVYU (12 << 21)
+# define R300_COLOR_FORMAT_UV88 (13 << 21)
+# define R500_COLOR_FORMAT_I10 (14 << 21)
+# define R300_COLOR_FORMAT_ARGB4444 (15 << 21)
+#define R300_RB3D_COLORPITCH1 0x4E3C
+#define R300_RB3D_COLORPITCH2 0x4E40
+#define R300_RB3D_COLORPITCH3 0x4E44
+
+/* gap */
+
+/* Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then
+ * a flush or free will not occur upon a write to this register, but a sync
+ * will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE
+ * are zero but DC_FINISH is one, then a sync will be sent immediately -- the
+ * cb will not wait for all the previous operations to complete before sending
+ * the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to
+ * zero.
+ *
+ * Set to 0A before 3D operations, set to 02 afterwards.
+ */
+#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4)
+# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4)
+
+#define R300_RB3D_DITHER_CTL 0x4E50
+# define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0)
+# define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0)
+# define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0)
+/* reserved */
+# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2)
+# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2)
+# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2)
+/* reserved */
+
+/* Resolve buffer destination address. The cache must be empty before changing
+ * this register if the cb is in resolve mode. Unpipelined
+ */
+#define R300_RB3D_AARESOLVE_OFFSET 0x4e80
+# define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5
+# define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */
+
+/* Resolve Buffer Pitch and Tiling Control. The cache must be empty before
+ * changing this register if the cb is in resolve mode. Unpipelined
+ */
+#define R300_RB3D_AARESOLVE_PITCH 0x4e84
+# define R300_RB3D_AARESOLVE_PITCH_SHIFT 1
+# define R300_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */
+
+/* Resolve Buffer Control. Unpipelined */
+#define R300_RB3D_AARESOLVE_CTL 0x4e88
+# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0)
+# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0)
+# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1)
+# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1)
+# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2)
+# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2)
+
+
+/* Discard src pixels less than or equal to threshold. */
+#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0
+/* Discard src pixels greater than or equal to threshold. */
+#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24
+# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000
+
+/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */
+#define R300_RB3D_ROPCNTL 0x4e18
+# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004
+# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8)
+# define R300_RB3D_ROPCNTL_ROP_SHIFT 8
+
+/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */
+#define R300_RB3D_CLRCMP_FLIPE 0x4e1c
+
+/* Sets the fifo sizes */
+#define R500_RB3D_FIFO_SIZE 0x4ef4
+# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0)
+# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0)
+# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0)
+# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0)
+
+/* Constant color used by the blender. Pipelined through the blender. */
+#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
+# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff
+# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0
+# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000
+# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16
+
+/* Constant color used by the blender. Pipelined through the blender. */
+#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc
+# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff
+# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0
+# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000
+# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16
+
+/* gap */
+/* There seems to be no "write only" setting, so use Z-test = ALWAYS
+ * for this.
+ * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
+ */
+#define R300_ZB_CNTL 0x4F00
+# define R300_STENCIL_ENABLE (1 << 0)
+# define R300_Z_ENABLE (1 << 1)
+# define R300_Z_WRITE_ENABLE (1 << 2)
+# define R300_Z_SIGNED_COMPARE (1 << 3)
+# define R300_STENCIL_FRONT_BACK (1 << 4)
+
+#define R300_ZB_ZSTENCILCNTL 0x4f04
+ /* functions */
+# define R300_ZS_NEVER 0
+# define R300_ZS_LESS 1
+# define R300_ZS_LEQUAL 2
+# define R300_ZS_EQUAL 3
+# define R300_ZS_GEQUAL 4
+# define R300_ZS_GREATER 5
+# define R300_ZS_NOTEQUAL 6
+# define R300_ZS_ALWAYS 7
+# define R300_ZS_MASK 7
+ /* operations */
+# define R300_ZS_KEEP 0
+# define R300_ZS_ZERO 1
+# define R300_ZS_REPLACE 2
+# define R300_ZS_INCR 3
+# define R300_ZS_DECR 4
+# define R300_ZS_INVERT 5
+# define R300_ZS_INCR_WRAP 6
+# define R300_ZS_DECR_WRAP 7
+# define R300_Z_FUNC_SHIFT 0
+ /* front and back refer to operations done for front
+ and back faces, i.e. separate stencil function support */
+# define R300_S_FRONT_FUNC_SHIFT 3
+# define R300_S_FRONT_SFAIL_OP_SHIFT 6
+# define R300_S_FRONT_ZPASS_OP_SHIFT 9
+# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
+# define R300_S_BACK_FUNC_SHIFT 15
+# define R300_S_BACK_SFAIL_OP_SHIFT 18
+# define R300_S_BACK_ZPASS_OP_SHIFT 21
+# define R300_S_BACK_ZFAIL_OP_SHIFT 24
+
+#define R300_ZB_STENCILREFMASK 0x4f08
+# define R300_STENCILREF_SHIFT 0
+# define R300_STENCILREF_MASK 0x000000ff
+# define R300_STENCILMASK_SHIFT 8
+# define R300_STENCILMASK_MASK 0x0000ff00
+# define R300_STENCILWRITEMASK_SHIFT 16
+# define R300_STENCILWRITEMASK_MASK 0x00ff0000
+
+/* gap */
+
+#define R300_ZB_FORMAT 0x4f10
+# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
+# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
+# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
+/* reserved up to (15 << 0) */
+# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
+# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
+
+#define R300_ZB_ZTOP 0x4F14
+# define R300_ZTOP_DISABLE (0 << 0)
+# define R300_ZTOP_ENABLE (1 << 0)
+
+/* gap */
+
+#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
+
+#define R300_ZB_BW_CNTL 0x4f1c
+# define R300_HIZ_DISABLE (0 << 0)
+# define R300_HIZ_ENABLE (1 << 0)
+# define R300_HIZ_MIN (0 << 1)
+# define R300_HIZ_MAX (1 << 1)
+# define R300_FAST_FILL_DISABLE (0 << 2)
+# define R300_FAST_FILL_ENABLE (1 << 2)
+# define R300_RD_COMP_DISABLE (0 << 3)
+# define R300_RD_COMP_ENABLE (1 << 3)
+# define R300_WR_COMP_DISABLE (0 << 4)
+# define R300_WR_COMP_ENABLE (1 << 4)
+# define R300_ZB_CB_CLEAR_RMW (0 << 5)
+# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
+# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
+# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
+
+# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
+# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
+# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
+# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
+
+# define R500_BMASK_ENABLE (0 << 10)
+# define R500_BMASK_DISABLE (1 << 10)
+# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
+# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
+# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
+# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
+# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
+# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
+# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
+# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
+# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
+# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
+# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
+# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
+# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
+# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
+# define R500_PEQ_PACKING_DISABLE (0 << 18)
+# define R500_PEQ_PACKING_ENABLE (1 << 18)
+# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
+# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
+
+
+/* gap */
+
+/* Z Buffer Address Offset.
+ * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
+ */
+#define R300_ZB_DEPTHOFFSET 0x4f20
+
+/* Z Buffer Pitch and Endian Control */
+#define R300_ZB_DEPTHPITCH 0x4f24
+# define R300_DEPTHPITCH_MASK 0x00003FFC
+# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
+# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
+# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
+# define R300_DEPTHMICROTILE_TILED (1 << 17)
+# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
+# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
+# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
+# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
+# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
+
+/* Z Buffer Clear Value */
+#define R300_ZB_DEPTHCLEARVALUE 0x4f28
+
+/* Hierarchical Z Memory Offset */
+#define R300_ZB_HIZ_OFFSET 0x4f44
+
+/* Hierarchical Z Write Index */
+#define R300_ZB_HIZ_WRINDEX 0x4f48
+
+/* Hierarchical Z Data */
+#define R300_ZB_HIZ_DWORD 0x4f4c
+
+/* Hierarchical Z Read Index */
+#define R300_ZB_HIZ_RDINDEX 0x4f50
+
+/* Hierarchical Z Pitch */
+#define R300_ZB_HIZ_PITCH 0x4f54
+
+/* Z Buffer Z Pass Counter Data */
+#define R300_ZB_ZPASS_DATA 0x4f58
+
+/* Z Buffer Z Pass Counter Address */
+#define R300_ZB_ZPASS_ADDR 0x4f5c
+
+/* Depth buffer X and Y coordinate offset */
+#define R300_ZB_DEPTHXY_OFFSET 0x4f60
+# define R300_DEPTHX_OFFSET_SHIFT 1
+# define R300_DEPTHX_OFFSET_MASK 0x000007FE
+# define R300_DEPTHY_OFFSET_SHIFT 17
+# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
+
+/* Sets the fifo sizes */
+#define R500_ZB_FIFO_SIZE 0x4fd0
+# define R500_OP_FIFO_SIZE_FULL (0 << 0)
+# define R500_OP_FIFO_SIZE_HALF (1 << 0)
+# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
+# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
+
+/* Stencil Reference Value and Mask for backfacing quads */
+/* R300_ZB_STENCILREFMASK handles front face */
+#define R500_ZB_STENCILREFMASK_BF 0x4fd4
+# define R500_STENCILREF_SHIFT 0
+# define R500_STENCILREF_MASK 0x000000ff
+# define R500_STENCILMASK_SHIFT 8
+# define R500_STENCILMASK_MASK 0x0000ff00
+# define R500_STENCILWRITEMASK_SHIFT 16
+# define R500_STENCILWRITEMASK_MASK 0x00ff0000
+
+/**
+ * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION
+ *
+ * The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector
+ * Engine instruction or a Math Engine instruction.
+ */
+
+/*\{*/
+
+enum {
+ /* R3XX */
+ VECTOR_NO_OP = 0,
+ VE_DOT_PRODUCT = 1,
+ VE_MULTIPLY = 2,
+ VE_ADD = 3,
+ VE_MULTIPLY_ADD = 4,
+ VE_DISTANCE_VECTOR = 5,
+ VE_FRACTION = 6,
+ VE_MAXIMUM = 7,
+ VE_MINIMUM = 8,
+ VE_SET_GREATER_THAN_EQUAL = 9,
+ VE_SET_LESS_THAN = 10,
+ VE_MULTIPLYX2_ADD = 11,
+ VE_MULTIPLY_CLAMP = 12,
+ VE_FLT2FIX_DX = 13,
+ VE_FLT2FIX_DX_RND = 14,
+ /* R5XX */
+ VE_PRED_SET_EQ_PUSH = 15,
+ VE_PRED_SET_GT_PUSH = 16,
+ VE_PRED_SET_GTE_PUSH = 17,
+ VE_PRED_SET_NEQ_PUSH = 18,
+ VE_COND_WRITE_EQ = 19,
+ VE_COND_WRITE_GT = 20,
+ VE_COND_WRITE_GTE = 21,
+ VE_COND_WRITE_NEQ = 22,
+ VE_COND_MUX_EQ = 23,
+ VE_COND_MUX_GT = 24,
+ VE_COND_MUX_GTE = 25,
+ VE_SET_GREATER_THAN = 26,
+ VE_SET_EQUAL = 27,
+ VE_SET_NOT_EQUAL = 28,
+};
+
+enum {
+ /* R3XX */
+ MATH_NO_OP = 0,
+ ME_EXP_BASE2_DX = 1,
+ ME_LOG_BASE2_DX = 2,
+ ME_EXP_BASEE_FF = 3,
+ ME_LIGHT_COEFF_DX = 4,
+ ME_POWER_FUNC_FF = 5,
+ ME_RECIP_DX = 6,
+ ME_RECIP_FF = 7,
+ ME_RECIP_SQRT_DX = 8,
+ ME_RECIP_SQRT_FF = 9,
+ ME_MULTIPLY = 10,
+ ME_EXP_BASE2_FULL_DX = 11,
+ ME_LOG_BASE2_FULL_DX = 12,
+ ME_POWER_FUNC_FF_CLAMP_B = 13,
+ ME_POWER_FUNC_FF_CLAMP_B1 = 14,
+ ME_POWER_FUNC_FF_CLAMP_01 = 15,
+ ME_SIN = 16,
+ ME_COS = 17,
+ /* R5XX */
+ ME_LOG_BASE2_IEEE = 18,
+ ME_RECIP_IEEE = 19,
+ ME_RECIP_SQRT_IEEE = 20,
+ ME_PRED_SET_EQ = 21,
+ ME_PRED_SET_GT = 22,
+ ME_PRED_SET_GTE = 23,
+ ME_PRED_SET_NEQ = 24,
+ ME_PRED_SET_CLR = 25,
+ ME_PRED_SET_INV = 26,
+ ME_PRED_SET_POP = 27,
+ ME_PRED_SET_RESTORE = 28,
+};
+
+enum {
+ /* R3XX */
+ PVS_MACRO_OP_2CLK_MADD = 0,
+ PVS_MACRO_OP_2CLK_M2X_ADD = 1,
+};
+
+enum {
+ PVS_SRC_REG_TEMPORARY = 0, /* Intermediate Storage */
+ PVS_SRC_REG_INPUT = 1, /* Input Vertex Storage */
+ PVS_SRC_REG_CONSTANT = 2, /* Constant State Storage */
+ PVS_SRC_REG_ALT_TEMPORARY = 3, /* Alternate Intermediate Storage */
+};
+
+enum {
+ PVS_DST_REG_TEMPORARY = 0, /* Intermediate Storage */
+ PVS_DST_REG_A0 = 1, /* Address Register Storage */
+ PVS_DST_REG_OUT = 2, /* Output Memory. Used for all outputs */
+ PVS_DST_REG_OUT_REPL_X = 3, /* Output Memory & Replicate X to all channels */
+ PVS_DST_REG_ALT_TEMPORARY = 4, /* Alternate Intermediate Storage */
+ PVS_DST_REG_INPUT = 5, /* Output Memory & Replicate X to all channels */
+};
+
+enum {
+ PVS_SRC_SELECT_X = 0, /* Select X Component */
+ PVS_SRC_SELECT_Y = 1, /* Select Y Component */
+ PVS_SRC_SELECT_Z = 2, /* Select Z Component */
+ PVS_SRC_SELECT_W = 3, /* Select W Component */
+ PVS_SRC_SELECT_FORCE_0 = 4, /* Force Component to 0.0 */
+ PVS_SRC_SELECT_FORCE_1 = 5, /* Force Component to 1.0 */
+};
+
+/* PVS Opcode & Destination Operand Description */
+
+enum {
+ PVS_DST_OPCODE_MASK = 0x3f,
+ PVS_DST_OPCODE_SHIFT = 0,
+ PVS_DST_MATH_INST_MASK = 0x1,
+ PVS_DST_MATH_INST_SHIFT = 6,
+ PVS_DST_MACRO_INST_MASK = 0x1,
+ PVS_DST_MACRO_INST_SHIFT = 7,
+ PVS_DST_REG_TYPE_MASK = 0xf,
+ PVS_DST_REG_TYPE_SHIFT = 8,
+ PVS_DST_ADDR_MODE_1_MASK = 0x1,
+ PVS_DST_ADDR_MODE_1_SHIFT = 12,
+ PVS_DST_OFFSET_MASK = 0x7f,
+ PVS_DST_OFFSET_SHIFT = 13,
+ PVS_DST_WE_X_MASK = 0x1,
+ PVS_DST_WE_X_SHIFT = 20,
+ PVS_DST_WE_Y_MASK = 0x1,
+ PVS_DST_WE_Y_SHIFT = 21,
+ PVS_DST_WE_Z_MASK = 0x1,
+ PVS_DST_WE_Z_SHIFT = 22,
+ PVS_DST_WE_W_MASK = 0x1,
+ PVS_DST_WE_W_SHIFT = 23,
+ PVS_DST_VE_SAT_MASK = 0x1,
+ PVS_DST_VE_SAT_SHIFT = 24,
+ PVS_DST_ME_SAT_MASK = 0x1,
+ PVS_DST_ME_SAT_SHIFT = 25,
+ PVS_DST_PRED_ENABLE_MASK = 0x1,
+ PVS_DST_PRED_ENABLE_SHIFT = 26,
+ PVS_DST_PRED_SENSE_MASK = 0x1,
+ PVS_DST_PRED_SENSE_SHIFT = 27,
+ PVS_DST_DUAL_MATH_OP_MASK = 0x3,
+ PVS_DST_DUAL_MATH_OP_SHIFT = 27,
+ PVS_DST_ADDR_SEL_MASK = 0x3,
+ PVS_DST_ADDR_SEL_SHIFT = 29,
+ PVS_DST_ADDR_MODE_0_MASK = 0x1,
+ PVS_DST_ADDR_MODE_0_SHIFT = 31,
+};
+
+/* PVS Source Operand Description */
+
+enum {
+ PVS_SRC_REG_TYPE_MASK = 0x3,
+ PVS_SRC_REG_TYPE_SHIFT = 0,
+ SPARE_0_MASK = 0x1,
+ SPARE_0_SHIFT = 2,
+ PVS_SRC_ABS_XYZW_MASK = 0x1,
+ PVS_SRC_ABS_XYZW_SHIFT = 3,
+ PVS_SRC_ADDR_MODE_0_MASK = 0x1,
+ PVS_SRC_ADDR_MODE_0_SHIFT = 4,
+ PVS_SRC_OFFSET_MASK = 0xff,
+ PVS_SRC_OFFSET_SHIFT = 5,
+ PVS_SRC_SWIZZLE_X_MASK = 0x7,
+ PVS_SRC_SWIZZLE_X_SHIFT = 13,
+ PVS_SRC_SWIZZLE_Y_MASK = 0x7,
+ PVS_SRC_SWIZZLE_Y_SHIFT = 16,
+ PVS_SRC_SWIZZLE_Z_MASK = 0x7,
+ PVS_SRC_SWIZZLE_Z_SHIFT = 19,
+ PVS_SRC_SWIZZLE_W_MASK = 0x7,
+ PVS_SRC_SWIZZLE_W_SHIFT = 22,
+ PVS_SRC_MODIFIER_X_MASK = 0x1,
+ PVS_SRC_MODIFIER_X_SHIFT = 25,
+ PVS_SRC_MODIFIER_Y_MASK = 0x1,
+ PVS_SRC_MODIFIER_Y_SHIFT = 26,
+ PVS_SRC_MODIFIER_Z_MASK = 0x1,
+ PVS_SRC_MODIFIER_Z_SHIFT = 27,
+ PVS_SRC_MODIFIER_W_MASK = 0x1,
+ PVS_SRC_MODIFIER_W_SHIFT = 28,
+ PVS_SRC_ADDR_SEL_MASK = 0x3,
+ PVS_SRC_ADDR_SEL_SHIFT = 29,
+ PVS_SRC_ADDR_MODE_1_MASK = 0x0,
+ PVS_SRC_ADDR_MODE_1_SHIFT = 32,
+};
+
+/*\}*/
+
+/* BEGIN: Packet 3 commands */
+
+/* A primitive emission dword. */
+#define R300_PRIM_TYPE_NONE (0 << 0)
+#define R300_PRIM_TYPE_POINT (1 << 0)
+#define R300_PRIM_TYPE_LINE (2 << 0)
+#define R300_PRIM_TYPE_LINE_STRIP (3 << 0)
+#define R300_PRIM_TYPE_TRI_LIST (4 << 0)
+#define R300_PRIM_TYPE_TRI_FAN (5 << 0)
+#define R300_PRIM_TYPE_TRI_STRIP (6 << 0)
+#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)
+#define R300_PRIM_TYPE_RECT_LIST (8 << 0)
+#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
+#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
+ /* GUESS (based on r200) */
+#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
+#define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
+#define R300_PRIM_TYPE_QUADS (13 << 0)
+#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
+#define R300_PRIM_TYPE_POLYGON (15 << 0)
+#define R300_PRIM_TYPE_MASK 0xF
+#define R300_PRIM_WALK_IND (1 << 4)
+#define R300_PRIM_WALK_LIST (2 << 4)
+#define R300_PRIM_WALK_RING (3 << 4)
+#define R300_PRIM_WALK_MASK (3 << 4)
+ /* GUESS (based on r200) */
+#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
+#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
+#define R300_PRIM_NUM_VERTICES_SHIFT 16
+#define R300_PRIM_NUM_VERTICES_MASK 0xffff
+
+
+
+/*
+ * The R500 unified shader (US) registers come in banks of 512 each, one
+ * for each instruction slot in the shader. You can't touch them directly.
+ * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
+ * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
+ * instruction is fully specified.
+ */
+#define R500_US_ALU_ALPHA_INST_0 0xa800
+# define R500_ALPHA_OP_MAD 0
+# define R500_ALPHA_OP_DP 1
+# define R500_ALPHA_OP_MIN 2
+# define R500_ALPHA_OP_MAX 3
+/* #define R500_ALPHA_OP_RESERVED 4 */
+# define R500_ALPHA_OP_CND 5
+# define R500_ALPHA_OP_CMP 6
+# define R500_ALPHA_OP_FRC 7
+# define R500_ALPHA_OP_EX2 8
+# define R500_ALPHA_OP_LN2 9
+# define R500_ALPHA_OP_RCP 10
+# define R500_ALPHA_OP_RSQ 11
+# define R500_ALPHA_OP_SIN 12
+# define R500_ALPHA_OP_COS 13
+# define R500_ALPHA_OP_MDH 14
+# define R500_ALPHA_OP_MDV 15
+# define R500_ALPHA_ADDRD(x) (x << 4)
+# define R500_ALPHA_ADDRD_REL (1 << 11)
+# define R500_ALPHA_SEL_A_SHIFT 12
+# define R500_ALPHA_SEL_A_SRC0 (0 << 12)
+# define R500_ALPHA_SEL_A_SRC1 (1 << 12)
+# define R500_ALPHA_SEL_A_SRC2 (2 << 12)
+# define R500_ALPHA_SEL_A_SRCP (3 << 12)
+# define R500_ALPHA_SWIZ_A_R (0 << 14)
+# define R500_ALPHA_SWIZ_A_G (1 << 14)
+# define R500_ALPHA_SWIZ_A_B (2 << 14)
+# define R500_ALPHA_SWIZ_A_A (3 << 14)
+# define R500_ALPHA_SWIZ_A_0 (4 << 14)
+# define R500_ALPHA_SWIZ_A_HALF (5 << 14)
+# define R500_ALPHA_SWIZ_A_1 (6 << 14)
+/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
+# define R500_ALPHA_MOD_A_NOP (0 << 17)
+# define R500_ALPHA_MOD_A_NEG (1 << 17)
+# define R500_ALPHA_MOD_A_ABS (2 << 17)
+# define R500_ALPHA_MOD_A_NAB (3 << 17)
+# define R500_ALPHA_SEL_B_SHIFT 19
+# define R500_ALPHA_SEL_B_SRC0 (0 << 19)
+# define R500_ALPHA_SEL_B_SRC1 (1 << 19)
+# define R500_ALPHA_SEL_B_SRC2 (2 << 19)
+# define R500_ALPHA_SEL_B_SRCP (3 << 19)
+# define R500_ALPHA_SWIZ_B_R (0 << 21)
+# define R500_ALPHA_SWIZ_B_G (1 << 21)
+# define R500_ALPHA_SWIZ_B_B (2 << 21)
+# define R500_ALPHA_SWIZ_B_A (3 << 21)
+# define R500_ALPHA_SWIZ_B_0 (4 << 21)
+# define R500_ALPHA_SWIZ_B_HALF (5 << 21)
+# define R500_ALPHA_SWIZ_B_1 (6 << 21)
+/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
+# define R500_ALPHA_MOD_B_NOP (0 << 24)
+# define R500_ALPHA_MOD_B_NEG (1 << 24)
+# define R500_ALPHA_MOD_B_ABS (2 << 24)
+# define R500_ALPHA_MOD_B_NAB (3 << 24)
+# define R500_ALPHA_OMOD_IDENTITY (0 << 26)
+# define R500_ALPHA_OMOD_MUL_2 (1 << 26)
+# define R500_ALPHA_OMOD_MUL_4 (2 << 26)
+# define R500_ALPHA_OMOD_MUL_8 (3 << 26)
+# define R500_ALPHA_OMOD_DIV_2 (4 << 26)
+# define R500_ALPHA_OMOD_DIV_4 (5 << 26)
+# define R500_ALPHA_OMOD_DIV_8 (6 << 26)
+# define R500_ALPHA_OMOD_DISABLE (7 << 26)
+# define R500_ALPHA_TARGET(x) (x << 29)
+# define R500_ALPHA_W_OMASK (1 << 31)
+#define R500_US_ALU_ALPHA_ADDR_0 0x9800
+# define R500_ALPHA_ADDR0(x) (x << 0)
+# define R500_ALPHA_ADDR0_CONST (1 << 8)
+# define R500_ALPHA_ADDR0_REL (1 << 9)
+# define R500_ALPHA_ADDR1(x) (x << 10)
+# define R500_ALPHA_ADDR1_CONST (1 << 18)
+# define R500_ALPHA_ADDR1_REL (1 << 19)
+# define R500_ALPHA_ADDR2(x) (x << 20)
+# define R500_ALPHA_ADDR2_CONST (1 << 28)
+# define R500_ALPHA_ADDR2_REL (1 << 29)
+# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
+# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
+# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
+# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30)
+#define R500_US_ALU_RGBA_INST_0 0xb000
+# define R500_ALU_RGBA_OP_MAD (0 << 0)
+# define R500_ALU_RGBA_OP_DP3 (1 << 0)
+# define R500_ALU_RGBA_OP_DP4 (2 << 0)
+# define R500_ALU_RGBA_OP_D2A (3 << 0)
+# define R500_ALU_RGBA_OP_MIN (4 << 0)
+# define R500_ALU_RGBA_OP_MAX (5 << 0)
+/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
+# define R500_ALU_RGBA_OP_CND (7 << 0)
+# define R500_ALU_RGBA_OP_CMP (8 << 0)
+# define R500_ALU_RGBA_OP_FRC (9 << 0)
+# define R500_ALU_RGBA_OP_SOP (10 << 0)
+# define R500_ALU_RGBA_OP_MDH (11 << 0)
+# define R500_ALU_RGBA_OP_MDV (12 << 0)
+# define R500_ALU_RGBA_ADDRD(x) (x << 4)
+# define R500_ALU_RGBA_ADDRD_REL (1 << 11)
+# define R500_ALU_RGBA_SEL_C_SHIFT 12
+# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
+# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
+# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
+# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
+# define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
+# define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
+# define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
+# define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
+# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
+# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
+# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
+/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
+# define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
+# define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
+# define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
+# define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
+# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
+# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
+# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
+/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
+# define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
+# define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
+# define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
+# define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
+# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
+# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
+# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
+/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
+# define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
+# define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
+# define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
+# define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
+# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25
+# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
+# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
+# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
+# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
+# define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
+# define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
+# define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
+# define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
+# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
+# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
+# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
+/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
+# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
+# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
+# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
+# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
+#define R500_US_ALU_RGB_INST_0 0xa000
+# define R500_ALU_RGB_SEL_A_SHIFT 0
+# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
+# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
+# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
+# define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
+# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
+# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
+# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
+# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
+# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
+# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
+# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
+/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
+# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
+# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
+# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
+# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
+# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
+# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
+# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
+/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
+# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
+# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
+# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
+# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
+# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
+# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
+# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
+/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
+# define R500_ALU_RGB_MOD_A_NOP (0 << 11)
+# define R500_ALU_RGB_MOD_A_NEG (1 << 11)
+# define R500_ALU_RGB_MOD_A_ABS (2 << 11)
+# define R500_ALU_RGB_MOD_A_NAB (3 << 11)
+# define R500_ALU_RGB_SEL_B_SHIFT 13
+# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
+# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
+# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
+# define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
+# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
+# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
+# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
+# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
+# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
+# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
+# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
+/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
+# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
+# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
+# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
+# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
+# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
+# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
+# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
+/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
+# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
+# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
+# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
+# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
+# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
+# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
+# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
+/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
+# define R500_ALU_RGB_MOD_B_NOP (0 << 24)
+# define R500_ALU_RGB_MOD_B_NEG (1 << 24)
+# define R500_ALU_RGB_MOD_B_ABS (2 << 24)
+# define R500_ALU_RGB_MOD_B_NAB (3 << 24)
+# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
+# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
+# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
+# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
+# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
+# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
+# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
+# define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
+# define R500_ALU_RGB_TARGET(x) (x << 29)
+# define R500_ALU_RGB_WMASK (1 << 31)
+#define R500_US_ALU_RGB_ADDR_0 0x9000
+# define R500_RGB_ADDR0(x) (x << 0)
+# define R500_RGB_ADDR0_CONST (1 << 8)
+# define R500_RGB_ADDR0_REL (1 << 9)
+# define R500_RGB_ADDR1(x) (x << 10)
+# define R500_RGB_ADDR1_CONST (1 << 18)
+# define R500_RGB_ADDR1_REL (1 << 19)
+# define R500_RGB_ADDR2(x) (x << 20)
+# define R500_RGB_ADDR2_CONST (1 << 28)
+# define R500_RGB_ADDR2_REL (1 << 29)
+# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
+# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
+# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
+# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30)
+#define R500_US_CMN_INST_0 0xb800
+# define R500_INST_TYPE_MASK (3 << 0)
+# define R500_INST_TYPE_ALU (0 << 0)
+# define R500_INST_TYPE_OUT (1 << 0)
+# define R500_INST_TYPE_FC (2 << 0)
+# define R500_INST_TYPE_TEX (3 << 0)
+# define R500_INST_TEX_SEM_WAIT (1 << 2)
+# define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
+# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
+# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
+# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
+# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
+# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
+# define R500_INST_RGB_PRED_INV (1 << 6)
+# define R500_INST_WRITE_INACTIVE (1 << 7)
+# define R500_INST_LAST (1 << 8)
+# define R500_INST_NOP (1 << 9)
+# define R500_INST_ALU_WAIT (1 << 10)
+# define R500_INST_RGB_WMASK_R (1 << 11)
+# define R500_INST_RGB_WMASK_G (1 << 12)
+# define R500_INST_RGB_WMASK_B (1 << 13)
+# define R500_INST_ALPHA_WMASK (1 << 14)
+# define R500_INST_RGB_OMASK_R (1 << 15)
+# define R500_INST_RGB_OMASK_G (1 << 16)
+# define R500_INST_RGB_OMASK_B (1 << 17)
+# define R500_INST_RGB_OMASK_RGB (7 << 15)
+# define R500_INST_ALPHA_OMASK (1 << 18)
+# define R500_INST_RGB_CLAMP (1 << 19)
+# define R500_INST_ALPHA_CLAMP (1 << 20)
+# define R500_INST_ALU_RESULT_SEL (1 << 21)
+# define R500_INST_ALPHA_PRED_INV (1 << 22)
+# define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
+# define R500_INST_ALU_RESULT_OP_LT (1 << 23)
+# define R500_INST_ALU_RESULT_OP_GE (2 << 23)
+# define R500_INST_ALU_RESULT_OP_NE (3 << 23)
+# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
+# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
+# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
+# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
+# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
+# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
+/* XXX next four are kind of guessed */
+# define R500_INST_STAT_WE_R (1 << 28)
+# define R500_INST_STAT_WE_G (1 << 29)
+# define R500_INST_STAT_WE_B (1 << 30)
+# define R500_INST_STAT_WE_A (1 << 31)
+
+/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
+#define R500_US_CODE_ADDR 0x4630
+# define R500_US_CODE_START_ADDR(x) (x << 0)
+# define R500_US_CODE_END_ADDR(x) (x << 16)
+#define R500_US_CODE_OFFSET 0x4638
+# define R500_US_CODE_OFFSET_ADDR(x) (x << 0)
+#define R500_US_CODE_RANGE 0x4634
+# define R500_US_CODE_RANGE_ADDR(x) (x << 0)
+# define R500_US_CODE_RANGE_SIZE(x) (x << 16)
+#define R500_US_CONFIG 0x4600
+# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
+#define R500_US_FC_ADDR_0 0xa000
+# define R500_FC_BOOL_ADDR(x) (x << 0)
+# define R500_FC_INT_ADDR(x) (x << 8)
+# define R500_FC_JUMP_ADDR(x) (x << 16)
+# define R500_FC_JUMP_GLOBAL (1 << 31)
+#define R500_US_FC_BOOL_CONST 0x4620
+# define R500_FC_KBOOL(x) (x)
+#define R500_US_FC_CTRL 0x4624
+# define R500_FC_TEST_EN (1 << 30)
+# define R500_FC_FULL_FC_EN (1 << 31)
+#define R500_US_FC_INST_0 0x9800
+# define R500_FC_OP_JUMP (0 << 0)
+# define R500_FC_OP_LOOP (1 << 0)
+# define R500_FC_OP_ENDLOOP (2 << 0)
+# define R500_FC_OP_REP (3 << 0)
+# define R500_FC_OP_ENDREP (4 << 0)
+# define R500_FC_OP_BREAKLOOP (5 << 0)
+# define R500_FC_OP_BREAKREP (6 << 0)
+# define R500_FC_OP_CONTINUE (7 << 0)
+# define R500_FC_B_ELSE (1 << 4)
+# define R500_FC_JUMP_ANY (1 << 5)
+# define R500_FC_A_OP_NONE (0 << 6)
+# define R500_FC_A_OP_POP (1 << 6)
+# define R500_FC_A_OP_PUSH (2 << 6)
+# define R500_FC_JUMP_FUNC(x) (x << 8)
+# define R500_FC_B_POP_CNT(x) (x << 16)
+# define R500_FC_B_OP0_NONE (0 << 24)
+# define R500_FC_B_OP0_DECR (1 << 24)
+# define R500_FC_B_OP0_INCR (2 << 24)
+# define R500_FC_B_OP1_DECR (0 << 26)
+# define R500_FC_B_OP1_NONE (1 << 26)
+# define R500_FC_B_OP1_INCR (2 << 26)
+# define R500_FC_IGNORE_UNCOVERED (1 << 28)
+#define R500_US_FC_INT_CONST_0 0x4c00
+# define R500_FC_INT_CONST_KR(x) (x << 0)
+# define R500_FC_INT_CONST_KG(x) (x << 8)
+# define R500_FC_INT_CONST_KB(x) (x << 16)
+/* _0 through _15 */
+#define R500_US_FORMAT0_0 0x4640
+# define R500_FORMAT_TXWIDTH(x) (x << 0)
+# define R500_FORMAT_TXHEIGHT(x) (x << 11)
+# define R500_FORMAT_TXDEPTH(x) (x << 22)
+#define R500_US_PIXSIZE 0x4604
+# define R500_PIX_SIZE(x) (x)
+#define R500_US_TEX_ADDR_0 0x9800
+# define R500_TEX_SRC_ADDR(x) (x << 0)
+# define R500_TEX_SRC_ADDR_REL (1 << 7)
+# define R500_TEX_SRC_S_SWIZ_R (0 << 8)
+# define R500_TEX_SRC_S_SWIZ_G (1 << 8)
+# define R500_TEX_SRC_S_SWIZ_B (2 << 8)
+# define R500_TEX_SRC_S_SWIZ_A (3 << 8)
+# define R500_TEX_SRC_T_SWIZ_R (0 << 10)
+# define R500_TEX_SRC_T_SWIZ_G (1 << 10)
+# define R500_TEX_SRC_T_SWIZ_B (2 << 10)
+# define R500_TEX_SRC_T_SWIZ_A (3 << 10)
+# define R500_TEX_SRC_R_SWIZ_R (0 << 12)
+# define R500_TEX_SRC_R_SWIZ_G (1 << 12)
+# define R500_TEX_SRC_R_SWIZ_B (2 << 12)
+# define R500_TEX_SRC_R_SWIZ_A (3 << 12)
+# define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
+# define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
+# define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
+# define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
+# define R500_TEX_DST_ADDR(x) (x << 16)
+# define R500_TEX_DST_ADDR_REL (1 << 23)
+# define R500_TEX_DST_R_SWIZ_R (0 << 24)
+# define R500_TEX_DST_R_SWIZ_G (1 << 24)
+# define R500_TEX_DST_R_SWIZ_B (2 << 24)
+# define R500_TEX_DST_R_SWIZ_A (3 << 24)
+# define R500_TEX_DST_G_SWIZ_R (0 << 26)
+# define R500_TEX_DST_G_SWIZ_G (1 << 26)
+# define R500_TEX_DST_G_SWIZ_B (2 << 26)
+# define R500_TEX_DST_G_SWIZ_A (3 << 26)
+# define R500_TEX_DST_B_SWIZ_R (0 << 28)
+# define R500_TEX_DST_B_SWIZ_G (1 << 28)
+# define R500_TEX_DST_B_SWIZ_B (2 << 28)
+# define R500_TEX_DST_B_SWIZ_A (3 << 28)
+# define R500_TEX_DST_A_SWIZ_R (0 << 30)
+# define R500_TEX_DST_A_SWIZ_G (1 << 30)
+# define R500_TEX_DST_A_SWIZ_B (2 << 30)
+# define R500_TEX_DST_A_SWIZ_A (3 << 30)
+#define R500_US_TEX_ADDR_DXDY_0 0xa000
+# define R500_DX_ADDR(x) (x << 0)
+# define R500_DX_ADDR_REL (1 << 7)
+# define R500_DX_S_SWIZ_R (0 << 8)
+# define R500_DX_S_SWIZ_G (1 << 8)
+# define R500_DX_S_SWIZ_B (2 << 8)
+# define R500_DX_S_SWIZ_A (3 << 8)
+# define R500_DX_T_SWIZ_R (0 << 10)
+# define R500_DX_T_SWIZ_G (1 << 10)
+# define R500_DX_T_SWIZ_B (2 << 10)
+# define R500_DX_T_SWIZ_A (3 << 10)
+# define R500_DX_R_SWIZ_R (0 << 12)
+# define R500_DX_R_SWIZ_G (1 << 12)
+# define R500_DX_R_SWIZ_B (2 << 12)
+# define R500_DX_R_SWIZ_A (3 << 12)
+# define R500_DX_Q_SWIZ_R (0 << 14)
+# define R500_DX_Q_SWIZ_G (1 << 14)
+# define R500_DX_Q_SWIZ_B (2 << 14)
+# define R500_DX_Q_SWIZ_A (3 << 14)
+# define R500_DY_ADDR(x) (x << 16)
+# define R500_DY_ADDR_REL (1 << 17)
+# define R500_DY_S_SWIZ_R (0 << 24)
+# define R500_DY_S_SWIZ_G (1 << 24)
+# define R500_DY_S_SWIZ_B (2 << 24)
+# define R500_DY_S_SWIZ_A (3 << 24)
+# define R500_DY_T_SWIZ_R (0 << 26)
+# define R500_DY_T_SWIZ_G (1 << 26)
+# define R500_DY_T_SWIZ_B (2 << 26)
+# define R500_DY_T_SWIZ_A (3 << 26)
+# define R500_DY_R_SWIZ_R (0 << 28)
+# define R500_DY_R_SWIZ_G (1 << 28)
+# define R500_DY_R_SWIZ_B (2 << 28)
+# define R500_DY_R_SWIZ_A (3 << 28)
+# define R500_DY_Q_SWIZ_R (0 << 30)
+# define R500_DY_Q_SWIZ_G (1 << 30)
+# define R500_DY_Q_SWIZ_B (2 << 30)
+# define R500_DY_Q_SWIZ_A (3 << 30)
+#define R500_US_TEX_INST_0 0x9000
+# define R500_TEX_ID(x) (x << 16)
+# define R500_TEX_INST_NOP (0 << 22)
+# define R500_TEX_INST_LD (1 << 22)
+# define R500_TEX_INST_TEXKILL (2 << 22)
+# define R500_TEX_INST_PROJ (3 << 22)
+# define R500_TEX_INST_LODBIAS (4 << 22)
+# define R500_TEX_INST_LOD (5 << 22)
+# define R500_TEX_INST_DXDY (6 << 22)
+# define R500_TEX_SEM_ACQUIRE (1 << 25)
+# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
+# define R500_TEX_UNSCALED (1 << 27)
+#define R300_US_W_FMT 0x46b4
+# define R300_W_FMT_W0 (0 << 0)
+# define R300_W_FMT_W24 (1 << 0)
+# define R300_W_FMT_W24FP (2 << 0)
+# define R300_W_SRC_US (0 << 2)
+# define R300_W_SRC_RAS (1 << 2)
+
+
+/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
+ * Two parameter dwords:
+ * 0. VAP_VTX_FMT: The first parameter is not written to hardware
+ * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
+ */
+#define R300_PACKET3_3D_DRAW_VBUF 0x00002800
+
+/* Draw a primitive from immediate vertices in this packet
+ * Up to 16382 dwords:
+ * 0. VAP_VTX_FMT: The first parameter is not written to hardware
+ * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
+ * 2 to end: Up to 16380 dwords of vertex data.
+ */
+#define R300_PACKET3_3D_DRAW_IMMD 0x00002900
+
+/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and
+ * immediate vertices in this packet
+ * Up to 16382 dwords:
+ * 0. VAP_VTX_FMT: The first parameter is not written to hardware
+ * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
+ * 2 to end: Up to 16380 dwords of vertex data.
+ */
+#define R300_PACKET3_3D_DRAW_INDX 0x00002A00
+
+
+/* Specify the full set of vertex arrays as (address, stride).
+ * The first parameter is the number of vertex arrays specified.
+ * The rest of the command is a variable length list of blocks, where
+ * each block is three dwords long and specifies two arrays.
+ * The first dword of a block is split into two words, the lower significant
+ * word refers to the first array, the more significant word to the second
+ * array in the block.
+ * The low byte of each word contains the size of an array entry in dwords,
+ * the high byte contains the stride of the array.
+ * The second dword of a block contains the pointer to the first array,
+ * the third dword of a block contains the pointer to the second array.
+ * Note that if the total number of arrays is odd, the third dword of
+ * the last block is omitted.
+ */
+#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
+
+#define R300_PACKET3_INDX_BUFFER 0x00003300
+# define R300_EB_UNK1_SHIFT 24
+# define R300_EB_UNK1 (0x80<<24)
+# define R300_EB_UNK2 0x0810
+
+/* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */
+#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
+/* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */
+#define R300_PACKET3_3D_DRAW_IMMD_2 0x00003500
+/* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */
+#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
+
+/* Clears a portion of hierachical Z RAM
+ * 3 dword parameters
+ * 0. START
+ * 1. COUNT: 13:0 (max is 0x3FFF)
+ * 2. CLEAR_VALUE: Value to write into HIZ RAM.
+ */
+#define R300_PACKET3_3D_CLEAR_HIZ 0x00003700
+
+/* Draws a set of primitives using vertex buffers pointed by the state data.
+ * At least 2 Parameters:
+ * 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword.
+ * 2 to end: Data or indices (see other 3D_DRAW_* packets for details)
+ */
+#define R300_PACKET3_3D_DRAW_128 0x00003900
+
+/* END: Packet 3 commands */
+
+
+/* Color formats for 2d packets
+ */
+#define R300_CP_COLOR_FORMAT_CI8 2
+#define R300_CP_COLOR_FORMAT_ARGB1555 3
+#define R300_CP_COLOR_FORMAT_RGB565 4
+#define R300_CP_COLOR_FORMAT_ARGB8888 6
+#define R300_CP_COLOR_FORMAT_RGB332 7
+#define R300_CP_COLOR_FORMAT_RGB8 9
+#define R300_CP_COLOR_FORMAT_ARGB4444 15
+
+/*
+ * CP type-3 packets
+ */
+#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
+
+/* XXX Corbin's stuff from radeon and r200 */
+
+#define RADEON_WAIT_UNTIL 0x1720
+# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
+# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
+# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
+# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
+
+#define RADEON_CP_PACKET3 0xC0000000
+
+#define R200_3D_DRAW_IMMD_2 0xC0003500
+
+#endif /* _R300_REG_H */
+
+/* *INDENT-ON* */
+
+/* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */
diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c
new file mode 100644
index 0000000000..d7354ad893
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_screen.h"
+
+/* Return the identifier behind whom the brave coders responsible for this
+ * amalgamation of code, sweat, and duct tape, routinely obscure their names.
+ *
+ * ...I should have just put "Corbin Simpson", but I'm not that cool.
+ *
+ * (Or egotistical. Yet.) */
+static const char* r300_get_vendor(struct pipe_screen* pscreen)
+{
+ return "X.Org R300 Project";
+}
+
+static const char* chip_families[] = {
+ "R300",
+ "R350",
+ "R360",
+ "RV350",
+ "RV370",
+ "RV380",
+ "R420",
+ "R423",
+ "R430",
+ "R480",
+ "R481",
+ "RV410",
+ "RS400",
+ "RC410",
+ "RS480",
+ "RS482",
+ "RS690",
+ "RS740",
+ "RV515",
+ "R520",
+ "RV530",
+ "R580",
+ "RV560",
+ "RV570"
+};
+
+static const char* r300_get_name(struct pipe_screen* pscreen)
+{
+ struct r300_screen* r300screen = r300_screen(pscreen);
+
+ return chip_families[r300screen->caps->family];
+}
+
+static int r300_get_param(struct pipe_screen* pscreen, int param)
+{
+ struct r300_screen* r300screen = r300_screen(pscreen);
+
+ switch (param) {
+ /* XXX cases marked "IN THEORY" are possible on the hardware,
+ * but haven't been implemented yet. */
+ case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
+ /* XXX I'm told this goes up to 16 */
+ return 8;
+ case PIPE_CAP_NPOT_TEXTURES:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_TWO_SIDED_STENCIL:
+ if (r300screen->caps->is_r500) {
+ return 1;
+ } else {
+ return 0;
+ }
+ return 0;
+ case PIPE_CAP_GLSL:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_S3TC:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_ANISOTROPIC_FILTER:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_POINT_SPRITE:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_MAX_RENDER_TARGETS:
+ return 4;
+ case PIPE_CAP_OCCLUSION_QUERY:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_TEXTURE_SHADOW_MAP:
+ /* IN THEORY */
+ return 0;
+ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ if (r300screen->caps->is_r500) {
+ /* 13 == 4096x4096 */
+ return 13;
+ } else {
+ /* 12 == 2048x2048 */
+ return 12;
+ }
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+ /* So, technically, the limit is the same as above, but some math
+ * shows why this is silly. Assuming RGBA, 4cpp, we can see that
+ * 4096*4096*4096 = 64.0 GiB exactly, so it's not exactly
+ * practical. However, if at some point a game really wants this,
+ * then we can remove or raise this limit. */
+ if (r300screen->caps->is_r500) {
+ /* 9 == 256x256x256 */
+ return 9;
+ } else {
+ /* 8 == 128*128*128 */
+ return 8;
+ }
+ case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+ if (r300screen->caps->is_r500) {
+ /* 13 == 4096x4096 */
+ return 13;
+ } else {
+ /* 12 == 2048x2048 */
+ return 12;
+ }
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ return 1;
+ case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
+ return 1;
+ case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
+ /* XXX guessing (what a terrible guess) */
+ return 2;
+ default:
+ debug_printf("r300: Implementation error: Bad param %d\n",
+ param);
+ return 0;
+ }
+}
+
+static float r300_get_paramf(struct pipe_screen* pscreen, int param)
+{
+ switch (param) {
+ case PIPE_CAP_MAX_LINE_WIDTH:
+ case PIPE_CAP_MAX_LINE_WIDTH_AA:
+ /* XXX this is the biggest thing that will fit in that register.
+ * Perhaps the actual rendering limits are less? */
+ return 10922.0f;
+ case PIPE_CAP_MAX_POINT_WIDTH:
+ case PIPE_CAP_MAX_POINT_WIDTH_AA:
+ /* XXX this is the biggest thing that will fit in that register.
+ * Perhaps the actual rendering limits are less? */
+ return 10922.0f;
+ case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+ return 16.0f;
+ case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+ return 16.0f;
+ default:
+ debug_printf("r300: Implementation error: Bad paramf %d\n",
+ param);
+ return 0.0f;
+ }
+}
+
+/* XXX even moar formats */
+static boolean check_tex_2d_format(enum pipe_format format)
+{
+ switch (format) {
+ /* Colorbuffer */
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ /* Texture */
+ case PIPE_FORMAT_I8_UNORM:
+ /* Z buffer */
+ case PIPE_FORMAT_Z16_UNORM:
+ /* Z buffer with stencil */
+ case PIPE_FORMAT_Z24S8_UNORM:
+ return TRUE;
+
+ /* These formats are explicitly not supported, in order to keep
+ * people from wasting their time trying to implement them... */
+ case PIPE_FORMAT_S8Z24_UNORM:
+ return FALSE;
+
+ default:
+ debug_printf("r300: Warning: Got unknown format: %s, in %s\n",
+ pf_name(format), __FUNCTION__);
+ break;
+ }
+
+ return FALSE;
+}
+
+/* XXX moar targets */
+static boolean r300_is_format_supported(struct pipe_screen* pscreen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned tex_usage,
+ unsigned geom_flags)
+{
+ switch (target) {
+ case PIPE_TEXTURE_2D:
+ return check_tex_2d_format(format);
+ default:
+ debug_printf("r300: Warning: Got unknown format target: %d\n",
+ format);
+ break;
+ }
+
+ return FALSE;
+}
+
+static void* r300_surface_map(struct pipe_screen* screen,
+ struct pipe_surface* surface,
+ unsigned flags)
+{
+ struct r300_texture* tex = (struct r300_texture*)surface->texture;
+ char* map = pipe_buffer_map(screen, tex->buffer, flags);
+
+ if (!map) {
+ return NULL;
+ }
+
+ return map + surface->offset;
+}
+
+static void r300_surface_unmap(struct pipe_screen* screen,
+ struct pipe_surface* surface)
+{
+ struct r300_texture* tex = (struct r300_texture*)surface->texture;
+ pipe_buffer_unmap(screen, tex->buffer);
+}
+
+static void r300_destroy_screen(struct pipe_screen* pscreen)
+{
+ struct r300_screen* r300screen = r300_screen(pscreen);
+
+ FREE(r300screen->caps);
+ FREE(r300screen);
+}
+
+struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys,
+ struct r300_winsys* r300_winsys)
+{
+ struct r300_screen* r300screen = CALLOC_STRUCT(r300_screen);
+ struct r300_capabilities* caps = CALLOC_STRUCT(r300_capabilities);
+
+ if (!r300screen || !caps)
+ return NULL;
+
+ caps->pci_id = r300_winsys->pci_id;
+ caps->num_frag_pipes = r300_winsys->gb_pipes;
+
+ r300_parse_chipset(caps);
+
+ r300screen->caps = caps;
+ r300screen->screen.winsys = winsys;
+ r300screen->screen.destroy = r300_destroy_screen;
+ r300screen->screen.get_name = r300_get_name;
+ r300screen->screen.get_vendor = r300_get_vendor;
+ r300screen->screen.get_param = r300_get_param;
+ r300screen->screen.get_paramf = r300_get_paramf;
+ r300screen->screen.is_format_supported = r300_is_format_supported;
+ r300screen->screen.surface_map = r300_surface_map;
+ r300screen->screen.surface_unmap = r300_surface_unmap;
+
+ r300_init_screen_texture_functions(&r300screen->screen);
+ u_simple_screen_init(&r300screen->screen);
+
+ return &r300screen->screen;
+}
diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h
new file mode 100644
index 0000000000..2e25f61dbf
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_screen.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_SCREEN_H
+#define R300_SCREEN_H
+
+#include "pipe/p_inlines.h"
+#include "pipe/p_screen.h"
+#include "util/u_memory.h"
+#include "util/u_simple_screen.h"
+
+#include "r300_chipset.h"
+#include "r300_texture.h"
+#include "r300_winsys.h"
+
+struct r300_screen {
+ /* Parent class */
+ struct pipe_screen screen;
+
+ /* Chipset capabilities */
+ struct r300_capabilities* caps;
+};
+
+/* Convenience cast wrapper. */
+static struct r300_screen* r300_screen(struct pipe_screen* screen) {
+ return (struct r300_screen*)screen;
+}
+
+/* Creates a new r300 screen. */
+struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys,
+ struct r300_winsys* r300_winsys);
+
+#endif /* R300_SCREEN_H */
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
new file mode 100644
index 0000000000..eae1a5698d
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -0,0 +1,852 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "util/u_math.h"
+#include "util/u_pack_color.h"
+
+#include "pipe/p_debug.h"
+#include "pipe/internal/p_winsys_screen.h"
+
+#include "r300_context.h"
+#include "r300_reg.h"
+#include "r300_state_shader.h"
+
+/* r300_state: Functions used to intialize state context by translating
+ * Gallium state objects into semi-native r300 state objects.
+ *
+ * XXX break this file up into pieces if it gets too big! */
+
+/* Pack a float into a dword. */
+static uint32_t pack_float_32(float f)
+{
+ union {
+ float f;
+ uint32_t u;
+ } u;
+
+ u.f = f;
+ return u.u;
+}
+
+static uint32_t translate_blend_function(int blend_func) {
+ switch (blend_func) {
+ case PIPE_BLEND_ADD:
+ return R300_COMB_FCN_ADD_CLAMP;
+ case PIPE_BLEND_SUBTRACT:
+ return R300_COMB_FCN_SUB_CLAMP;
+ case PIPE_BLEND_REVERSE_SUBTRACT:
+ return R300_COMB_FCN_RSUB_CLAMP;
+ case PIPE_BLEND_MIN:
+ return R300_COMB_FCN_MIN;
+ case PIPE_BLEND_MAX:
+ return R300_COMB_FCN_MAX;
+ default:
+ debug_printf("r300: Unknown blend function %d\n", blend_func);
+ break;
+ }
+ return 0;
+}
+
+/* XXX we can also offer the D3D versions of some of these... */
+static uint32_t translate_blend_factor(int blend_fact) {
+ switch (blend_fact) {
+ case PIPE_BLENDFACTOR_ONE:
+ return R300_BLEND_GL_ONE;
+ case PIPE_BLENDFACTOR_SRC_COLOR:
+ return R300_BLEND_GL_SRC_COLOR;
+ case PIPE_BLENDFACTOR_SRC_ALPHA:
+ return R300_BLEND_GL_SRC_ALPHA;
+ case PIPE_BLENDFACTOR_DST_ALPHA:
+ return R300_BLEND_GL_DST_ALPHA;
+ case PIPE_BLENDFACTOR_DST_COLOR:
+ return R300_BLEND_GL_DST_COLOR;
+ case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+ return R300_BLEND_GL_SRC_ALPHA_SATURATE;
+ case PIPE_BLENDFACTOR_CONST_COLOR:
+ return R300_BLEND_GL_CONST_COLOR;
+ case PIPE_BLENDFACTOR_CONST_ALPHA:
+ return R300_BLEND_GL_CONST_ALPHA;
+ /* XXX WTF are these?
+ case PIPE_BLENDFACTOR_SRC1_COLOR:
+ case PIPE_BLENDFACTOR_SRC1_ALPHA: */
+ case PIPE_BLENDFACTOR_ZERO:
+ return R300_BLEND_GL_ZERO;
+ case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+ return R300_BLEND_GL_ONE_MINUS_SRC_COLOR;
+ case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+ return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA;
+ case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+ return R300_BLEND_GL_ONE_MINUS_DST_ALPHA;
+ case PIPE_BLENDFACTOR_INV_DST_COLOR:
+ return R300_BLEND_GL_ONE_MINUS_DST_COLOR;
+ case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+ return R300_BLEND_GL_ONE_MINUS_CONST_COLOR;
+ case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+ return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA;
+ /* XXX see above
+ case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+ case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: */
+ default:
+ debug_printf("r300: Unknown blend factor %d\n", blend_fact);
+ break;
+ }
+ return 0;
+}
+
+/* Create a new blend state based on the CSO blend state.
+ *
+ * This encompasses alpha blending, logic/raster ops, and blend dithering. */
+static void* r300_create_blend_state(struct pipe_context* pipe,
+ const struct pipe_blend_state* state)
+{
+ struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
+
+ if (state->blend_enable) {
+ /* XXX for now, always do separate alpha...
+ * is it faster to do it with one reg? */
+ blend->blend_control = R300_ALPHA_BLEND_ENABLE |
+ R300_SEPARATE_ALPHA_ENABLE |
+ R300_READ_ENABLE |
+ translate_blend_function(state->rgb_func) |
+ (translate_blend_factor(state->rgb_src_factor) <<
+ R300_SRC_BLEND_SHIFT) |
+ (translate_blend_factor(state->rgb_dst_factor) <<
+ R300_DST_BLEND_SHIFT);
+ blend->alpha_blend_control =
+ translate_blend_function(state->alpha_func) |
+ (translate_blend_factor(state->alpha_src_factor) <<
+ R300_SRC_BLEND_SHIFT) |
+ (translate_blend_factor(state->alpha_dst_factor) <<
+ R300_DST_BLEND_SHIFT);
+ }
+
+ /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
+ /* XXX are logicops still allowed if blending's disabled?
+ * Does Gallium take care of it for us? */
+ if (state->logicop_enable) {
+ blend->rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
+ (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
+ }
+
+ if (state->dither) {
+ blend->dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
+ R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
+ }
+
+ return (void*)blend;
+}
+
+/* Bind blend state. */
+static void r300_bind_blend_state(struct pipe_context* pipe,
+ void* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+
+ r300->blend_state = (struct r300_blend_state*)state;
+ r300->dirty_state |= R300_NEW_BLEND;
+}
+
+/* Free blend state. */
+static void r300_delete_blend_state(struct pipe_context* pipe,
+ void* state)
+{
+ FREE(state);
+}
+
+/* Set blend color.
+ * Setup both R300 and R500 registers, figure out later which one to write. */
+static void r300_set_blend_color(struct pipe_context* pipe,
+ const struct pipe_blend_color* color)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ uint32_t r, g, b, a;
+ ubyte ur, ug, ub, ua;
+
+ r = util_iround(color->color[0] * 1023.0f);
+ g = util_iround(color->color[1] * 1023.0f);
+ b = util_iround(color->color[2] * 1023.0f);
+ a = util_iround(color->color[3] * 1023.0f);
+
+ ur = float_to_ubyte(color->color[0]);
+ ug = float_to_ubyte(color->color[1]);
+ ub = float_to_ubyte(color->color[2]);
+ ua = float_to_ubyte(color->color[3]);
+
+ r300->blend_color_state->blend_color = (a << 24) | (r << 16) | (g << 8) | b;
+
+ r300->blend_color_state->blend_color_red_alpha = ur | (ua << 16);
+ r300->blend_color_state->blend_color_green_blue = ub | (ug << 16);
+
+ r300->dirty_state |= R300_NEW_BLEND_COLOR;
+}
+
+static void r300_set_clip_state(struct pipe_context* pipe,
+ const struct pipe_clip_state* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ /* XXX Draw */
+ draw_flush(r300->draw);
+ draw_set_clip_state(r300->draw, state);
+}
+
+static void
+ r300_set_constant_buffer(struct pipe_context* pipe,
+ uint shader, uint index,
+ const struct pipe_constant_buffer* buffer)
+{
+ struct r300_context* r300 = r300_context(pipe);
+
+ /* This entire chunk of code seems ever-so-slightly baked.
+ * It's as if I've got pipe_buffer* matryoshkas... */
+ if (buffer && buffer->buffer && buffer->buffer->size) {
+ void* map = pipe->winsys->buffer_map(pipe->winsys, buffer->buffer,
+ PIPE_BUFFER_USAGE_CPU_READ);
+ memcpy(r300->shader_constants[shader].constants,
+ map, buffer->buffer->size);
+ pipe->winsys->buffer_unmap(pipe->winsys, buffer->buffer);
+
+ r300->shader_constants[shader].user_count =
+ buffer->buffer->size / (sizeof(float) * 4);
+ } else {
+ r300->shader_constants[shader].user_count = 0;
+ }
+
+ r300->dirty_state |= R300_NEW_CONSTANTS;
+}
+
+static uint32_t translate_depth_stencil_function(int zs_func) {
+ switch (zs_func) {
+ case PIPE_FUNC_NEVER:
+ return R300_ZS_NEVER;
+ case PIPE_FUNC_LESS:
+ return R300_ZS_LESS;
+ case PIPE_FUNC_EQUAL:
+ return R300_ZS_EQUAL;
+ case PIPE_FUNC_LEQUAL:
+ return R300_ZS_LEQUAL;
+ case PIPE_FUNC_GREATER:
+ return R300_ZS_GREATER;
+ case PIPE_FUNC_NOTEQUAL:
+ return R300_ZS_NOTEQUAL;
+ case PIPE_FUNC_GEQUAL:
+ return R300_ZS_GEQUAL;
+ case PIPE_FUNC_ALWAYS:
+ return R300_ZS_ALWAYS;
+ default:
+ debug_printf("r300: Unknown depth/stencil function %d\n",
+ zs_func);
+ break;
+ }
+ return 0;
+}
+
+static uint32_t translate_stencil_op(int s_op) {
+ switch (s_op) {
+ case PIPE_STENCIL_OP_KEEP:
+ return R300_ZS_KEEP;
+ case PIPE_STENCIL_OP_ZERO:
+ return R300_ZS_ZERO;
+ case PIPE_STENCIL_OP_REPLACE:
+ return R300_ZS_REPLACE;
+ case PIPE_STENCIL_OP_INCR:
+ return R300_ZS_INCR;
+ case PIPE_STENCIL_OP_DECR:
+ return R300_ZS_DECR;
+ case PIPE_STENCIL_OP_INCR_WRAP:
+ return R300_ZS_INCR_WRAP;
+ case PIPE_STENCIL_OP_DECR_WRAP:
+ return R300_ZS_DECR_WRAP;
+ case PIPE_STENCIL_OP_INVERT:
+ return R300_ZS_INVERT;
+ default:
+ debug_printf("r300: Unknown stencil op %d", s_op);
+ break;
+ }
+ return 0;
+}
+
+static uint32_t translate_alpha_function(int alpha_func) {
+ switch (alpha_func) {
+ case PIPE_FUNC_NEVER:
+ return R300_FG_ALPHA_FUNC_NEVER;
+ case PIPE_FUNC_LESS:
+ return R300_FG_ALPHA_FUNC_LESS;
+ case PIPE_FUNC_EQUAL:
+ return R300_FG_ALPHA_FUNC_EQUAL;
+ case PIPE_FUNC_LEQUAL:
+ return R300_FG_ALPHA_FUNC_LE;
+ case PIPE_FUNC_GREATER:
+ return R300_FG_ALPHA_FUNC_GREATER;
+ case PIPE_FUNC_NOTEQUAL:
+ return R300_FG_ALPHA_FUNC_NOTEQUAL;
+ case PIPE_FUNC_GEQUAL:
+ return R300_FG_ALPHA_FUNC_GE;
+ case PIPE_FUNC_ALWAYS:
+ return R300_FG_ALPHA_FUNC_ALWAYS;
+ default:
+ debug_printf("r300: Unknown alpha function %d", alpha_func);
+ break;
+ }
+ return 0;
+}
+
+/* Create a new depth, stencil, and alpha state based on the CSO dsa state.
+ *
+ * This contains the depth buffer, stencil buffer, alpha test, and such.
+ * On the Radeon, depth and stencil buffer setup are intertwined, which is
+ * the reason for some of the strange-looking assignments across registers. */
+static void*
+ r300_create_dsa_state(struct pipe_context* pipe,
+ const struct pipe_depth_stencil_alpha_state* state)
+{
+ struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
+
+ /* Depth test setup. */
+ if (state->depth.enabled) {
+ dsa->z_buffer_control |= R300_Z_ENABLE;
+
+ if (state->depth.writemask) {
+ dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
+ }
+
+ dsa->z_stencil_control |=
+ (translate_depth_stencil_function(state->depth.func) <<
+ R300_Z_FUNC_SHIFT);
+ }
+
+ /* Stencil buffer setup. */
+ if (state->stencil[0].enabled) {
+ dsa->z_buffer_control |= R300_STENCIL_ENABLE;
+ dsa->z_stencil_control |=
+ (translate_depth_stencil_function(state->stencil[0].func) <<
+ R300_S_FRONT_FUNC_SHIFT) |
+ (translate_stencil_op(state->stencil[0].fail_op) <<
+ R300_S_FRONT_SFAIL_OP_SHIFT) |
+ (translate_stencil_op(state->stencil[0].zpass_op) <<
+ R300_S_FRONT_ZPASS_OP_SHIFT) |
+ (translate_stencil_op(state->stencil[0].zfail_op) <<
+ R300_S_FRONT_ZFAIL_OP_SHIFT);
+
+ dsa->stencil_ref_mask = (state->stencil[0].ref_value) |
+ (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
+ (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
+
+ if (state->stencil[1].enabled) {
+ dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
+ dsa->z_stencil_control |=
+ (translate_depth_stencil_function(state->stencil[1].func) <<
+ R300_S_BACK_FUNC_SHIFT) |
+ (translate_stencil_op(state->stencil[1].fail_op) <<
+ R300_S_BACK_SFAIL_OP_SHIFT) |
+ (translate_stencil_op(state->stencil[1].zpass_op) <<
+ R300_S_BACK_ZPASS_OP_SHIFT) |
+ (translate_stencil_op(state->stencil[1].zfail_op) <<
+ R300_S_BACK_ZFAIL_OP_SHIFT);
+
+ dsa->stencil_ref_bf = (state->stencil[1].ref_value) |
+ (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
+ (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
+ }
+ }
+
+ /* Alpha test setup. */
+ if (state->alpha.enabled) {
+ dsa->alpha_function = translate_alpha_function(state->alpha.func) |
+ R300_FG_ALPHA_FUNC_ENABLE;
+ dsa->alpha_reference = CLAMP(state->alpha.ref_value * 1023.0f,
+ 0, 1023);
+ } else {
+ dsa->z_buffer_top = R300_ZTOP_ENABLE;
+ }
+
+ return (void*)dsa;
+}
+
+/* Bind DSA state. */
+static void r300_bind_dsa_state(struct pipe_context* pipe,
+ void* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+
+ r300->dsa_state = (struct r300_dsa_state*)state;
+ r300->dirty_state |= R300_NEW_DSA;
+}
+
+/* Free DSA state. */
+static void r300_delete_dsa_state(struct pipe_context* pipe,
+ void* state)
+{
+ FREE(state);
+}
+
+static void r300_set_edgeflags(struct pipe_context* pipe,
+ const unsigned* bitfield)
+{
+ /* XXX you know it's bad when i915 has this blank too */
+}
+
+static void
+ r300_set_framebuffer_state(struct pipe_context* pipe,
+ const struct pipe_framebuffer_state* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+
+ draw_flush(r300->draw);
+
+ r300->framebuffer_state = *state;
+
+ r300->dirty_state |= R300_NEW_FRAMEBUFFERS;
+}
+
+/* Create fragment shader state. */
+static void* r300_create_fs_state(struct pipe_context* pipe,
+ const struct pipe_shader_state* shader)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ struct r3xx_fragment_shader* fs = NULL;
+
+ if (r300_screen(r300->context.screen)->caps->is_r500) {
+ fs =
+ (struct r3xx_fragment_shader*)CALLOC_STRUCT(r500_fragment_shader);
+ } else {
+ fs =
+ (struct r3xx_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
+ }
+
+ /* Copy state directly into shader. */
+ fs->state = *shader;
+
+ return (void*)fs;
+}
+
+/* Bind fragment shader state. */
+static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ struct r3xx_fragment_shader* fs = (struct r3xx_fragment_shader*)shader;
+
+ if (fs == NULL) {
+ r300->fs = NULL;
+ return;
+ } else if (!fs->translated) {
+ if (r300_screen(r300->context.screen)->caps->is_r500) {
+ r500_translate_fragment_shader(r300, (struct r500_fragment_shader*)fs);
+ } else {
+ r300_translate_fragment_shader(r300, (struct r300_fragment_shader*)fs);
+ }
+ }
+
+ fs->translated = true;
+ r300->fs = fs;
+
+ r300->dirty_state |= R300_NEW_FRAGMENT_SHADER;
+}
+
+/* Delete fragment shader state. */
+static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
+{
+ FREE(shader);
+}
+
+static void r300_set_polygon_stipple(struct pipe_context* pipe,
+ const struct pipe_poly_stipple* state)
+{
+ /* XXX */
+}
+
+static INLINE int pack_float_16_6x(float f) {
+ return ((int)(f * 6.0) & 0xffff);
+}
+
+/* Create a new rasterizer state based on the CSO rasterizer state.
+ *
+ * This is a very large chunk of state, and covers most of the graphics
+ * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
+ *
+ * In a not entirely unironic sidenote, this state has nearly nothing to do
+ * with the actual block on the Radeon called the rasterizer (RS). */
+static void* r300_create_rs_state(struct pipe_context* pipe,
+ const struct pipe_rasterizer_state* state)
+{
+ struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
+
+ /* XXX this is part of HW TCL */
+ /* XXX endian control */
+ rs->vap_control_status = R300_VAP_TCL_BYPASS;
+
+ rs->point_size = pack_float_16_6x(state->point_size) |
+ (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
+
+ rs->line_control = pack_float_16_6x(state->line_width) |
+ R300_GA_LINE_CNTL_END_TYPE_COMP;
+
+ /* Radeons don't think in "CW/CCW", they think in "front/back". */
+ if (state->front_winding == PIPE_WINDING_CW) {
+ rs->cull_mode = R300_FRONT_FACE_CW;
+
+ if (state->offset_cw) {
+ rs->polygon_offset_enable |= R300_FRONT_ENABLE;
+ }
+ if (state->offset_ccw) {
+ rs->polygon_offset_enable |= R300_BACK_ENABLE;
+ }
+ } else {
+ rs->cull_mode = R300_FRONT_FACE_CCW;
+
+ if (state->offset_ccw) {
+ rs->polygon_offset_enable |= R300_FRONT_ENABLE;
+ }
+ if (state->offset_cw) {
+ rs->polygon_offset_enable |= R300_BACK_ENABLE;
+ }
+ }
+ if (state->front_winding & state->cull_mode) {
+ rs->cull_mode |= R300_CULL_FRONT;
+ }
+ if (~(state->front_winding) & state->cull_mode) {
+ rs->cull_mode |= R300_CULL_BACK;
+ }
+
+ if (rs->polygon_offset_enable) {
+ rs->depth_offset_front = rs->depth_offset_back =
+ pack_float_32(state->offset_units);
+ rs->depth_scale_front = rs->depth_scale_back =
+ pack_float_32(state->offset_scale);
+ }
+
+ if (state->line_stipple_enable) {
+ rs->line_stipple_config =
+ R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
+ (pack_float_32((float)state->line_stipple_factor) &
+ R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
+ /* XXX this might need to be scaled up */
+ rs->line_stipple_value = state->line_stipple_pattern;
+ }
+
+ rs->rs = *state;
+
+ return (void*)rs;
+}
+
+/* Bind rasterizer state. */
+static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ struct r300_rs_state* rs = (struct r300_rs_state*)state;
+
+ draw_set_rasterizer_state(r300->draw, &rs->rs);
+
+ r300->rs_state = rs;
+ r300->dirty_state |= R300_NEW_RASTERIZER;
+}
+
+/* Free rasterizer state. */
+static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
+{
+ FREE(state);
+}
+
+static uint32_t translate_wrap(int wrap) {
+ switch (wrap) {
+ case PIPE_TEX_WRAP_REPEAT:
+ return R300_TX_REPEAT;
+ case PIPE_TEX_WRAP_CLAMP:
+ return R300_TX_CLAMP;
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+ return R300_TX_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+ return R300_TX_CLAMP_TO_BORDER;
+ case PIPE_TEX_WRAP_MIRROR_REPEAT:
+ return R300_TX_REPEAT | R300_TX_MIRRORED;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP:
+ return R300_TX_CLAMP | R300_TX_MIRRORED;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+ return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+ return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED;
+ default:
+ debug_printf("r300: Unknown texture wrap %d", wrap);
+ return 0;
+ }
+}
+
+static uint32_t translate_tex_filters(int min, int mag, int mip) {
+ uint32_t retval = 0;
+ switch (min) {
+ case PIPE_TEX_FILTER_NEAREST:
+ retval |= R300_TX_MIN_FILTER_NEAREST;
+ case PIPE_TEX_FILTER_LINEAR:
+ retval |= R300_TX_MIN_FILTER_LINEAR;
+ case PIPE_TEX_FILTER_ANISO:
+ retval |= R300_TX_MIN_FILTER_ANISO;
+ default:
+ debug_printf("r300: Unknown texture filter %d", min);
+ break;
+ }
+ switch (mag) {
+ case PIPE_TEX_FILTER_NEAREST:
+ retval |= R300_TX_MAG_FILTER_NEAREST;
+ case PIPE_TEX_FILTER_LINEAR:
+ retval |= R300_TX_MAG_FILTER_LINEAR;
+ case PIPE_TEX_FILTER_ANISO:
+ retval |= R300_TX_MAG_FILTER_ANISO;
+ default:
+ debug_printf("r300: Unknown texture filter %d", mag);
+ break;
+ }
+ switch (mip) {
+ case PIPE_TEX_MIPFILTER_NONE:
+ retval |= R300_TX_MIN_FILTER_MIP_NONE;
+ case PIPE_TEX_MIPFILTER_NEAREST:
+ retval |= R300_TX_MIN_FILTER_MIP_NEAREST;
+ case PIPE_TEX_MIPFILTER_LINEAR:
+ retval |= R300_TX_MIN_FILTER_MIP_LINEAR;
+ default:
+ debug_printf("r300: Unknown texture filter %d", mip);
+ break;
+ }
+
+ return retval;
+}
+
+static uint32_t anisotropy(float max_aniso) {
+ if (max_aniso >= 16.0f) {
+ return R300_TX_MAX_ANISO_16_TO_1;
+ } else if (max_aniso >= 8.0f) {
+ return R300_TX_MAX_ANISO_8_TO_1;
+ } else if (max_aniso >= 4.0f) {
+ return R300_TX_MAX_ANISO_4_TO_1;
+ } else if (max_aniso >= 2.0f) {
+ return R300_TX_MAX_ANISO_2_TO_1;
+ } else {
+ return R300_TX_MAX_ANISO_1_TO_1;
+ }
+}
+
+static void*
+ r300_create_sampler_state(struct pipe_context* pipe,
+ const struct pipe_sampler_state* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
+ int lod_bias;
+
+ sampler->filter0 |=
+ (translate_wrap(state->wrap_s) << R300_TX_WRAP_S_SHIFT) |
+ (translate_wrap(state->wrap_t) << R300_TX_WRAP_T_SHIFT) |
+ (translate_wrap(state->wrap_r) << R300_TX_WRAP_R_SHIFT);
+
+ sampler->filter0 |= translate_tex_filters(state->min_img_filter,
+ state->mag_img_filter,
+ state->min_mip_filter);
+
+ lod_bias = CLAMP((int)(state->lod_bias * 32), -(1 << 9), (1 << 9) - 1);
+
+ sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT;
+
+ sampler->filter1 |= anisotropy(state->max_anisotropy);
+
+ util_pack_color(state->border_color, PIPE_FORMAT_A8R8G8B8_UNORM,
+ &sampler->border_color);
+
+ /* R500-specific fixups and optimizations */
+ if (r300_screen(r300->context.screen)->caps->is_r500) {
+ sampler->filter1 |= R500_BORDER_FIX;
+ }
+
+ return (void*)sampler;
+}
+
+static void r300_bind_sampler_states(struct pipe_context* pipe,
+ unsigned count,
+ void** states)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ int i;
+
+ if (count > 8) {
+ return;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (r300->sampler_states[i] != states[i]) {
+ r300->sampler_states[i] = (struct r300_sampler_state*)states[i];
+ r300->dirty_state |= (R300_NEW_SAMPLER << i);
+ }
+ }
+
+ r300->sampler_count = count;
+}
+
+static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
+{
+ FREE(state);
+}
+
+static void r300_set_sampler_textures(struct pipe_context* pipe,
+ unsigned count,
+ struct pipe_texture** texture)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ int i;
+
+ /* XXX magic num */
+ if (count > 8) {
+ return;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (r300->textures[i] != (struct r300_texture*)texture[i]) {
+ pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
+ texture[i]);
+ r300->dirty_state |= (R300_NEW_TEXTURE << i);
+ }
+ }
+
+ for (i = count; i < 8; i++) {
+ if (r300->textures[i]) {
+ pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
+ NULL);
+ r300->dirty_state |= (R300_NEW_TEXTURE << i);
+ }
+ }
+
+ r300->texture_count = count;
+}
+
+static void r300_set_scissor_state(struct pipe_context* pipe,
+ const struct pipe_scissor_state* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ draw_flush(r300->draw);
+
+ r300->scissor_state->scissor_top_left =
+ (state->minx << R300_SCISSORS_X_SHIFT) |
+ (state->miny << R300_SCISSORS_Y_SHIFT);
+ r300->scissor_state->scissor_bottom_right =
+ (state->maxx << R300_SCISSORS_X_SHIFT) |
+ (state->maxy << R300_SCISSORS_Y_SHIFT);
+
+ r300->dirty_state |= R300_NEW_SCISSOR;
+}
+
+static void r300_set_viewport_state(struct pipe_context* pipe,
+ const struct pipe_viewport_state* state)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ /* XXX handing this off to Draw for now */
+ draw_set_viewport_state(r300->draw, state);
+}
+
+static void r300_set_vertex_buffers(struct pipe_context* pipe,
+ unsigned count,
+ const struct pipe_vertex_buffer* buffers)
+{
+ struct r300_context* r300 = r300_context(pipe);
+
+ memcpy(r300->vertex_buffers, buffers,
+ sizeof(struct pipe_vertex_buffer) * count);
+
+ r300->vertex_buffer_count = count;
+
+ draw_flush(r300->draw);
+ draw_set_vertex_buffers(r300->draw, count, buffers);
+}
+
+static void r300_set_vertex_elements(struct pipe_context* pipe,
+ unsigned count,
+ const struct pipe_vertex_element* elements)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ /* XXX Draw */
+ draw_flush(r300->draw);
+ draw_set_vertex_elements(r300->draw, count, elements);
+}
+
+static void* r300_create_vs_state(struct pipe_context* pipe,
+ const struct pipe_shader_state* state)
+{
+ struct r300_context* context = r300_context(pipe);
+ /* XXX handing this off to Draw for now */
+ return draw_create_vertex_shader(context->draw, state);
+}
+
+static void r300_bind_vs_state(struct pipe_context* pipe, void* state) {
+ struct r300_context* context = r300_context(pipe);
+ /* XXX handing this off to Draw for now */
+ draw_bind_vertex_shader(context->draw, (struct draw_vertex_shader*)state);
+}
+
+static void r300_delete_vs_state(struct pipe_context* pipe, void* state)
+{
+ struct r300_context* context = r300_context(pipe);
+ /* XXX handing this off to Draw for now */
+ draw_delete_vertex_shader(context->draw, (struct draw_vertex_shader*)state);
+}
+
+void r300_init_state_functions(struct r300_context* r300)
+{
+ r300->context.create_blend_state = r300_create_blend_state;
+ r300->context.bind_blend_state = r300_bind_blend_state;
+ r300->context.delete_blend_state = r300_delete_blend_state;
+
+ r300->context.set_blend_color = r300_set_blend_color;
+
+ r300->context.set_clip_state = r300_set_clip_state;
+
+ r300->context.set_constant_buffer = r300_set_constant_buffer;
+
+ r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
+ r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
+ r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
+
+ r300->context.set_edgeflags = r300_set_edgeflags;
+
+ r300->context.set_framebuffer_state = r300_set_framebuffer_state;
+
+ r300->context.create_fs_state = r300_create_fs_state;
+ r300->context.bind_fs_state = r300_bind_fs_state;
+ r300->context.delete_fs_state = r300_delete_fs_state;
+
+ r300->context.set_polygon_stipple = r300_set_polygon_stipple;
+
+ r300->context.create_rasterizer_state = r300_create_rs_state;
+ r300->context.bind_rasterizer_state = r300_bind_rs_state;
+ r300->context.delete_rasterizer_state = r300_delete_rs_state;
+
+ r300->context.create_sampler_state = r300_create_sampler_state;
+ r300->context.bind_sampler_states = r300_bind_sampler_states;
+ r300->context.delete_sampler_state = r300_delete_sampler_state;
+
+ r300->context.set_sampler_textures = r300_set_sampler_textures;
+
+ r300->context.set_scissor_state = r300_set_scissor_state;
+
+ r300->context.set_viewport_state = r300_set_viewport_state;
+
+ r300->context.set_vertex_buffers = r300_set_vertex_buffers;
+ r300->context.set_vertex_elements = r300_set_vertex_elements;
+
+ r300->context.create_vs_state = r300_create_vs_state;
+ r300->context.bind_vs_state = r300_bind_vs_state;
+ r300->context.delete_vs_state = r300_delete_vs_state;
+}
diff --git a/src/gallium/drivers/r300/r300_state_derived.c b/src/gallium/drivers/r300/r300_state_derived.c
new file mode 100644
index 0000000000..df19f20fc8
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_state_derived.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_state_derived.h"
+
+/* r300_state_derived: Various bits of state which are dependent upon
+ * currently bound CSO data. */
+
+/* Update the vertex_info struct in our r300_context.
+ *
+ * The vertex_info struct describes the post-TCL format of vertices. It is
+ * required for Draw when doing SW TCL, and also for describing the
+ * dreaded RS block on R300 chipsets. */
+/* XXX this function should be able to handle vert shaders as well as draw */
+static void r300_update_vertex_layout(struct r300_context* r300)
+{
+ struct vertex_info vinfo;
+ boolean pos = false, psize = false, fog = false;
+ int i, texs = 0, cols = 0;
+
+ struct tgsi_shader_info* info = &r300->fs->info;
+ memset(&vinfo, 0, sizeof(vinfo));
+
+ /* This is rather lame. Since draw_find_vs_output doesn't return an error
+ * when it can't find an output, we have to pre-iterate and count each
+ * output ourselves. */
+ for (i = 0; i < info->num_inputs; i++) {
+ switch (info->input_semantic_name[i]) {
+ case TGSI_SEMANTIC_POSITION:
+ pos = true;
+ break;
+ case TGSI_SEMANTIC_COLOR:
+ cols++;
+ break;
+ case TGSI_SEMANTIC_FOG:
+ fog = true;
+ break;
+ case TGSI_SEMANTIC_PSIZE:
+ psize = true;
+ break;
+ case TGSI_SEMANTIC_GENERIC:
+ texs++;
+ break;
+ default:
+ debug_printf("r300: Unknown vertex input %d\n",
+ info->input_semantic_name[i]);
+ break;
+ }
+ }
+
+ /* Do the actual vertex_info setup.
+ *
+ * vertex_info has four uints of hardware-specific data in it.
+ * vinfo.hwfmt[0] is VAP_OUT_VTX_FMT_0
+ * vinfo.hwfmt[1] is VAP_OUT_VTX_FMT_1 */
+
+ if (pos) {
+ draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_POS,
+ draw_find_vs_output(r300->draw, TGSI_SEMANTIC_POSITION, 0));
+ vinfo.hwfmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
+ } else {
+ debug_printf("r300: No vertex input for position in SW TCL;\n"
+ " this will probably end poorly.\n");
+ }
+
+ if (psize) {
+ draw_emit_vertex_attr(&vinfo, EMIT_1F, INTERP_LINEAR,
+ draw_find_vs_output(r300->draw, TGSI_SEMANTIC_PSIZE, 0));
+ vinfo.hwfmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
+ }
+
+ for (i = 0; i < cols; i++) {
+ draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR,
+ draw_find_vs_output(r300->draw, TGSI_SEMANTIC_COLOR, i));
+ vinfo.hwfmt[0] |= (R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << i);
+ }
+
+ if (fog) {
+ draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE,
+ draw_find_vs_output(r300->draw, TGSI_SEMANTIC_FOG, 0));
+ vinfo.hwfmt[0] |=
+ (R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << cols);
+ }
+
+ for (i = 0; i < texs; i++) {
+ draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR,
+ draw_find_vs_output(r300->draw, TGSI_SEMANTIC_GENERIC, i));
+ vinfo.hwfmt[1] |= (4 << (3 * i));
+ }
+
+ draw_compute_vertex_size(&vinfo);
+
+ if (memcmp(&r300->vertex_info, &vinfo, sizeof(struct vertex_info))) {
+ memcpy(&r300->vertex_info, &vinfo, sizeof(struct vertex_info));
+ r300->dirty_state |= R300_NEW_VERTEX_FORMAT;
+ }
+}
+
+/* Set up the RS block. This is the part of the chipset that actually does
+ * the rasterization of vertices into fragments. This is also the part of the
+ * chipset that locks up if any part of it is even slightly wrong. */
+void r300_update_rs_block(struct r300_context* r300)
+{
+}
+
+void r300_update_derived_state(struct r300_context* r300)
+{
+ if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
+ r300_update_vertex_layout(r300);
+ }
+
+ if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
+ r300_update_rs_block(r300);
+ }
+}
diff --git a/src/gallium/drivers/r300/r300_state_derived.h b/src/gallium/drivers/r300/r300_state_derived.h
new file mode 100644
index 0000000000..72ba6b928d
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_state_derived.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_STATE_DERIVED_H
+#define R300_STATE_DERIVED_H
+
+#include "draw/draw_vertex.h"
+
+#include "r300_context.h"
+#include "r300_reg.h"
+
+void r300_update_derived_state(struct r300_context* r300);
+
+#endif /* R300_STATE_DERIVED_H */
diff --git a/src/gallium/drivers/r300/r300_state_shader.c b/src/gallium/drivers/r300/r300_state_shader.c
new file mode 100644
index 0000000000..d10ac55580
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_state_shader.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_state_shader.h"
+
+static void r300_copy_passthrough_shader(struct r300_fragment_shader* fs)
+{
+ struct r300_fragment_shader* pt = &r300_passthrough_fragment_shader;
+ fs->shader.stack_size = pt->shader.stack_size;
+ fs->alu_instruction_count = pt->alu_instruction_count;
+ fs->tex_instruction_count = pt->tex_instruction_count;
+ fs->indirections = pt->indirections;
+ fs->instructions[0] = pt->instructions[0];
+}
+
+static void r500_copy_passthrough_shader(struct r500_fragment_shader* fs)
+{
+ struct r500_fragment_shader* pt = &r500_passthrough_fragment_shader;
+ fs->shader.stack_size = pt->shader.stack_size;
+ fs->instruction_count = pt->instruction_count;
+ fs->instructions[0] = pt->instructions[0];
+}
+
+void r300_translate_fragment_shader(struct r300_context* r300,
+ struct r300_fragment_shader* fs)
+{
+ r300_copy_passthrough_shader(fs);
+}
+
+void r500_translate_fragment_shader(struct r300_context* r300,
+ struct r500_fragment_shader* fs)
+{
+ r500_copy_passthrough_shader(fs);
+}
diff --git a/src/gallium/drivers/r300/r300_state_shader.h b/src/gallium/drivers/r300/r300_state_shader.h
new file mode 100644
index 0000000000..1d5d9ee943
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_state_shader.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_STATE_SHADER_H
+#define R300_STATE_SHADER_H
+
+#include "r300_context.h"
+#include "r300_reg.h"
+#include "r300_screen.h"
+
+void r300_translate_fragment_shader(struct r300_context* r300,
+ struct r300_fragment_shader* fs);
+
+void r500_translate_fragment_shader(struct r300_context* r300,
+ struct r500_fragment_shader* fs);
+
+static const struct r300_fragment_shader r300_passthrough_fragment_shader = {
+ /* XXX This is the emission code. TODO: decode
+ OUT_CS_REG(R300_US_CONFIG, 0);
+ OUT_CS_REG(R300_US_CODE_OFFSET, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
+ OUT_CS_REG(R300_US_CODE_ADDR_3, 0x400000);
+*/
+ .alu_instruction_count = 1,
+ .tex_instruction_count = 0,
+ .indirections = 1,
+ .shader.stack_size = 2,
+
+ /* XXX decode these */
+ .instructions[0].alu_rgb_inst = 0x50A80,
+ .instructions[0].alu_rgb_inst = 0x1C000000,
+ .instructions[0].alu_alpha_inst = 0x40889,
+ .instructions[0].alu_alpha_inst = 0x1000000,
+};
+
+static const struct r500_fragment_shader r500_passthrough_fragment_shader = {
+ .shader.stack_size = 0,
+ .instruction_count = 1,
+ .instructions[0].inst0 = R500_INST_TYPE_OUT |
+ R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
+ R500_INST_RGB_OMASK_RGB | R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP,
+ .instructions[0].inst1 =
+ R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
+ R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST,
+ .instructions[0].inst2 =
+ R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
+ R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST,
+ .instructions[0].inst3 =
+ R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B,
+ .instructions[0].inst4 =
+ R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A,
+ .instructions[0].inst5 =
+ R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0,
+};
+
+#endif /* R300_STATE_SHADER_H */
diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c
new file mode 100644
index 0000000000..b2c4f4251d
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_surface.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ * Joakim Sindholt <opensource@zhasha.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_surface.h"
+
+/* Provides pipe_context's "surface_fill". Commonly used for clearing
+ * buffers. */
+static void r300_surface_fill(struct pipe_context* pipe,
+ struct pipe_surface* dest,
+ unsigned x, unsigned y,
+ unsigned w, unsigned h,
+ unsigned color)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ CS_LOCALS(r300);
+ struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps;
+ struct r300_texture* tex = (struct r300_texture*)dest->texture;
+ int i;
+ float r, g, b, a;
+ r = (float)((color >> 16) & 0xff) / 255.0f;
+ g = (float)((color >> 8) & 0xff) / 255.0f;
+ b = (float)((color >> 0) & 0xff) / 255.0f;
+ debug_printf("r300: Filling surface %p at (%d,%d),"
+ " dimensions %dx%d (stride %d), color 0x%x\n",
+ dest, x, y, w, h, dest->stride, color);
+
+ /* Fallback? */
+ if (0) {
+ debug_printf("r300: Falling back on surface clear...");
+ void* map = pipe->screen->surface_map(pipe->screen, dest,
+ PIPE_BUFFER_USAGE_CPU_WRITE);
+ pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
+ pipe->screen->surface_unmap(pipe->screen, dest);
+ return;
+ }
+
+ BEGIN_CS(163 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2));
+ /* Flush PVS. */
+ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
+
+ OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
+ R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
+ R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
+ R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
+ /* Vertex size. */
+ OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
+ /* Max and min vertex index clamp. */
+ OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
+ OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
+ /* XXX endian */
+ OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
+ /* XXX magic number not in r300_reg */
+ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
+ OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
+ OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ /* XXX is this too long? */
+ OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF);
+ OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
+ R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
+ /* XXX more magic numbers */
+ OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
+ OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
+ /* XXX why doesn't classic Mesa write the number of pipes, too? */
+ OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE |
+ R300_GB_TILE_SIZE_16);
+ OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
+ OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
+ /* XXX point tex stuffing */
+ OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
+ OUT_CS_32F(0.0);
+ OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
+ OUT_CS_32F(1.0);
+ OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
+ (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
+ /* XXX should this be related to the actual point size? */
+ OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 |
+ (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT));
+ /* XXX this big chunk should be refactored into rs_state */
+ OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006);
+ OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB);
+ OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000);
+ OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
+ OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
+ OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
+ OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA);
+ OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
+ OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
+ OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
+ OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
+ OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
+ OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
+ OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, 0x00000000);
+ OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, 0x00000000);
+ OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, 0x00000000);
+ OUT_CS_REG(R300_SU_CULL_MODE, 0x00000000);
+ OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
+ OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
+ OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
+ OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
+ OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
+ OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
+ OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
+ OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
+ OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
+ OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
+ OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
+
+ /* XXX: Oh the wonderful unknown.
+ * Not writing these 8 regs seems to make no difference at all and seeing
+ * as how they're not documented, we should leave them out for now.
+ OUT_CS_REG_SEQ(0x4E54, 8);
+ for (i = 0; i < 8; i++) {
+ OUT_CS(0x00000000);
+ } */
+ OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
+ OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
+ OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
+ OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
+ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
+ OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
+ OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
+ /* XXX Moar unknown that should probably be left out.
+ OUT_CS_REG(0x4F30, 0x00000000);
+ OUT_CS_REG(0x4F34, 0x00000000); */
+ OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
+ ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
+ R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
+ } else {
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
+ ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
+ R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
+ }
+ OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
+ OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
+ OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
+ OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
+ OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
+ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
+ OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
+ OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
+ OUT_CS_REG(R300_TX_ENABLE, 0x0);
+ /* XXX viewport setup */
+ OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F((float)x);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F((float)y);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(0.0);
+
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
+ R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
+ }
+
+ /* The size of the point we're about to draw, in sixths of pixels */
+ OUT_CS_REG(R300_GA_POINT_SIZE,
+ ((h * 6) & R300_POINTSIZE_Y_MASK) |
+ ((w * 6) << R300_POINTSIZE_X_SHIFT));
+
+ /* XXX */
+ OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
+
+ /* Pixel scissors */
+ OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
+ OUT_CS((x << R300_SCISSORS_X_SHIFT) | (y << R300_SCISSORS_Y_SHIFT));
+ OUT_CS((w << R300_SCISSORS_X_SHIFT) | (h << R300_SCISSORS_Y_SHIFT));
+
+ /* RS block setup */
+ if (caps->is_r500) {
+ /* XXX We seem to be in disagreement about how many of these we have
+ * RS:RS_IP_[0-15] [R/W] 32 bits Access: 8/16/32 MMReg:0x4074-0x40b0
+ * Now that's from the docs. I don't care what the mesa driver says */
+ OUT_CS_REG_SEQ(R500_RS_IP_0, 16);
+ for (i = 0; i < 16; i++) {
+ OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
+ }
+ OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
+ OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
+ OUT_CS(0x00000000);
+ OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
+ } else {
+ OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
+ for (i = 0; i < 8; i++) {
+ OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1));
+ }
+ OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
+ OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
+ /* XXX Shouldn't this be 0? */
+ OUT_CS(1);
+ OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
+ }
+ END_CS;
+
+ /* Fragment shader setup */
+ if (caps->is_r500) {
+ r500_emit_fragment_shader(r300, &r500_passthrough_fragment_shader);
+ } else {
+ r300_emit_fragment_shader(r300, &r300_passthrough_fragment_shader);
+ }
+
+ BEGIN_CS(8 + (caps->has_tcl ? 20 : 2));
+ OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
+ OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
+ OUT_CS(R300_US_OUT_FMT_UNUSED);
+ OUT_CS(R300_US_OUT_FMT_UNUSED);
+ OUT_CS(R300_US_OUT_FMT_UNUSED);
+ OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
+ /* XXX these magic numbers should be explained when
+ * this becomes a cached state object */
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_CNTL, 0xA |
+ (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
+ (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
+ OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
+ OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
+ OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
+ /* XXX translate these back into normal instructions */
+ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
+ OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
+ OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
+ OUT_CS(0x00F00203);
+ OUT_CS(0x00D10001);
+ OUT_CS(0x01248001);
+ OUT_CS(0x00000000);
+ OUT_CS(0x00F02203);
+ OUT_CS(0x00D10021);
+ OUT_CS(0x01248021);
+ OUT_CS(0x00000000);
+ } else {
+ OUT_CS_REG(R300_VAP_CNTL, 0xA |
+ (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
+ (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
+ }
+ END_CS;
+
+ r300_emit_blend_state(r300, &blend_clear_state);
+ r300_emit_blend_color_state(r300, &blend_color_clear_state);
+ r300_emit_dsa_state(r300, &dsa_clear_state);
+
+ BEGIN_CS(24);
+ /* Flush colorbuffer and blend caches. */
+ OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
+ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+
+ OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
+ OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+ /* XXX (dest->stride >> 2) should be the buffer width in pixels however,
+ * this little calculation is only good as long as the buffer is 32bpp */
+ OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) |
+ R300_COLOR_FORMAT_ARGB8888);
+ OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
+ /* XXX Packet3 */
+ OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
+ OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
+ (1 << R300_PRIM_NUM_VERTICES_SHIFT));
+ OUT_CS_32F(w / 2.0);
+ OUT_CS_32F(h / 2.0);
+ /* XXX this should be the depth value to clear to */
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(r);
+ OUT_CS_32F(g);
+ OUT_CS_32F(b);
+ OUT_CS_32F(1.0);
+
+ /* XXX figure out why this is 0xA and not 0x2 */
+ OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+ /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
+
+ END_CS;
+
+ r300->dirty_hw++;
+}
+
+void r300_init_surface_functions(struct r300_context* r300)
+{
+ r300->context.surface_fill = r300_surface_fill;
+}
diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h
new file mode 100644
index 0000000000..17d6c62fe8
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_surface.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_SURFACE_H
+#define R300_SURFACE_H
+
+#include "pipe/p_context.h"
+#include "pipe/p_screen.h"
+
+#include "util/u_rect.h"
+
+#include "r300_context.h"
+#include "r300_cs.h"
+#include "r300_emit.h"
+#include "r300_state_shader.h"
+
+const struct r300_blend_state blend_clear_state = {
+ .blend_control = 0x0,
+ .alpha_blend_control = 0x0,
+ .rop = 0x0,
+ .dither = 0x0,
+};
+
+const struct r300_blend_color_state blend_color_clear_state = {
+ .blend_color = 0x0,
+ .blend_color_red_alpha = 0x0,
+ .blend_color_green_blue = 0x0,
+};
+
+const struct r300_dsa_state dsa_clear_state = {
+ .alpha_function = 0x0,
+ .alpha_reference = 0x0,
+ .z_buffer_control = 0x0,
+ .z_stencil_control = 0x0,
+ .stencil_ref_mask = R300_STENCILWRITEMASK_MASK,
+ .z_buffer_top = R300_ZTOP_ENABLE,
+ .stencil_ref_bf = 0x0,
+};
+
+#endif /* R300_SURFACE_H */
diff --git a/src/gallium/drivers/r300/r300_swtcl_emit.c b/src/gallium/drivers/r300/r300_swtcl_emit.c
new file mode 100644
index 0000000000..76ef48962b
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_swtcl_emit.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "draw/draw_pipe.h"
+#include "util/u_memory.h"
+
+#include "r300_cs.h"
+#include "r300_context.h"
+#include "r300_reg.h"
+
+/* r300_swtcl_emit: Primitive vertex emission using an immediate
+ * vertex buffer and no HW TCL. */
+
+struct swtcl_stage {
+ /* Parent class */
+ struct draw_stage draw;
+
+ struct r300_context* r300;
+};
+
+static INLINE struct swtcl_stage* swtcl_stage(struct draw_stage* draw) {
+ return (struct swtcl_stage*)draw;
+}
+
+static INLINE void r300_emit_vertex(struct r300_context* r300,
+ const struct vertex_header* vertex)
+{
+ struct vertex_info* vinfo = &r300->vertex_info;
+ CS_LOCALS(r300);
+ uint i, j;
+
+ for (i = 0; i < vinfo->num_attribs; i++) {
+ j = vinfo->attrib[i].src_index;
+ switch (vinfo->attrib[i].emit) {
+ case EMIT_1F:
+ OUT_CS_32F(vertex->data[j][0]);
+ break;
+ case EMIT_2F:
+ OUT_CS_32F(vertex->data[j][0]);
+ OUT_CS_32F(vertex->data[j][1]);
+ break;
+ case EMIT_3F:
+ OUT_CS_32F(vertex->data[j][0]);
+ OUT_CS_32F(vertex->data[j][1]);
+ OUT_CS_32F(vertex->data[j][2]);
+ break;
+ case EMIT_4F:
+ OUT_CS_32F(vertex->data[j][0]);
+ OUT_CS_32F(vertex->data[j][1]);
+ OUT_CS_32F(vertex->data[j][2]);
+ OUT_CS_32F(vertex->data[j][3]);
+ break;
+ default:
+ debug_printf("r300: Unknown emit value %d\n",
+ vinfo->attrib[i].emit);
+ break;
+ }
+ }
+}
+
+static INLINE void r300_emit_prim(struct draw_stage* draw,
+ struct prim_header* prim,
+ unsigned hwprim,
+ unsigned count)
+{
+ struct r300_context* r300 = swtcl_stage(draw)->r300;
+ CS_LOCALS(r300);
+ int i;
+
+ r300_emit_dirty_state(r300);
+
+ BEGIN_CS(3);
+ OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
+ OUT_CS(r300->vertex_info.hwfmt[0]);
+ OUT_CS(r300->vertex_info.hwfmt[1]);
+ END_CS;
+
+ BEGIN_CS(2 + (count * r300->vertex_info.size) + 2);
+ OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, count));
+ OUT_CS(hwprim | R300_PRIM_WALK_RING |
+ (count << R300_PRIM_NUM_VERTICES_SHIFT));
+
+ for (i = 0; i < count; i++) {
+ r300_emit_vertex(r300, prim->v[i]);
+ }
+
+ END_CS;
+}
+
+/* Just as an aside...
+ *
+ * Radeons can do many more primitives:
+ * - Line strip
+ * - Triangle fan
+ * - Triangle strip
+ * - Line loop
+ * - Quads
+ * - Quad strip
+ * - Polygons
+ *
+ * The following were just the only ones in Draw. */
+
+static void r300_emit_point(struct draw_stage* draw, struct prim_header* prim)
+{
+ r300_emit_prim(draw, prim, R300_PRIM_TYPE_POINT, 1);
+}
+
+static void r300_emit_line(struct draw_stage* draw, struct prim_header* prim)
+{
+ r300_emit_prim(draw, prim, R300_PRIM_TYPE_LINE, 2);
+}
+
+static void r300_emit_tri(struct draw_stage* draw, struct prim_header* prim)
+{
+ r300_emit_prim(draw, prim, R300_PRIM_TYPE_TRI_LIST, 3);
+}
+
+static void r300_swtcl_flush(struct draw_stage* draw, unsigned flags)
+{
+}
+
+static void r300_reset_stipple(struct draw_stage* draw)
+{
+ /* XXX */
+}
+
+static void r300_swtcl_destroy(struct draw_stage* draw)
+{
+ FREE(draw);
+}
+
+struct draw_stage* r300_draw_swtcl_stage(struct r300_context* r300)
+{
+ struct swtcl_stage* swtcl = CALLOC_STRUCT(swtcl_stage);
+
+ swtcl->r300 = r300;
+ swtcl->draw.point = r300_emit_point;
+ swtcl->draw.line = r300_emit_line;
+ swtcl->draw.tri = r300_emit_tri;
+ swtcl->draw.flush = r300_swtcl_flush;
+ swtcl->draw.reset_stipple_counter = r300_reset_stipple;
+ swtcl->draw.destroy = r300_swtcl_destroy;
+
+ return &swtcl->draw;
+}
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
new file mode 100644
index 0000000000..bd35e089f9
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "r300_texture.h"
+
+static int minify(int i)
+{
+ return MAX2(1, i >> 1);
+}
+
+static void r300_setup_miptree(struct r300_texture* tex)
+{
+ struct pipe_texture* base = &tex->tex;
+ int stride, size, offset;
+
+ for (int i = 0; i <= base->last_level; i++) {
+ if (i > 0) {
+ base->width[i] = minify(base->width[i-1]);
+ base->height[i] = minify(base->height[i-1]);
+ base->depth[i] = minify(base->depth[i-1]);
+ }
+
+ base->nblocksx[i] = pf_get_nblocksx(&base->block, base->width[i]);
+ base->nblocksy[i] = pf_get_nblocksy(&base->block, base->width[i]);
+
+ /* Radeons enjoy things in multiples of 32. */
+ /* XXX NPOT -> 64, not 32 */
+ stride = (base->nblocksx[i] * base->block.size + 63) & ~63;
+ size = stride * base->nblocksy[i] * base->depth[i];
+
+ /* XXX 64 for NPOT */
+ tex->offset[i] = (tex->size + 63) & ~63;
+ tex->size = tex->offset[i] + size;
+ }
+}
+
+/* Create a new texture. */
+static struct pipe_texture*
+ r300_texture_create(struct pipe_screen* screen,
+ const struct pipe_texture* template)
+{
+ /* XXX struct r300_screen* r300screen = r300_screen(screen); */
+
+ struct r300_texture* tex = CALLOC_STRUCT(r300_texture);
+
+ if (!tex) {
+ return NULL;
+ }
+
+ tex->tex = *template;
+ tex->tex.refcount = 1;
+ tex->tex.screen = screen;
+
+ r300_setup_miptree(tex);
+
+ tex->buffer = screen->buffer_create(screen, 64,
+ PIPE_BUFFER_USAGE_PIXEL,
+ tex->size);
+
+ if (!tex->buffer) {
+ FREE(tex);
+ return NULL;
+ }
+
+ return (struct pipe_texture*)tex;
+}
+
+static void r300_texture_release(struct pipe_screen* screen,
+ struct pipe_texture** texture)
+{
+ if (!*texture) {
+ return;
+ }
+
+ (*texture)->refcount--;
+
+ if ((*texture)->refcount <= 0) {
+ struct r300_texture* tex = (struct r300_texture*)*texture;
+
+ pipe_buffer_reference(screen, &tex->buffer, NULL);
+
+ FREE(tex);
+ }
+
+ *texture = NULL;
+}
+
+static struct pipe_surface* r300_get_tex_surface(struct pipe_screen* screen,
+ struct pipe_texture* texture,
+ unsigned face,
+ unsigned level,
+ unsigned zslice,
+ unsigned flags)
+{
+ struct r300_texture* tex = (struct r300_texture*)texture;
+ struct pipe_surface* surface = CALLOC_STRUCT(pipe_surface);
+ unsigned offset;
+
+ /* XXX this is certainly dependent on tex target */
+ offset = tex->offset[level];
+
+ if (surface) {
+ surface->refcount = 1;
+ pipe_texture_reference(&surface->texture, texture);
+ surface->format = texture->format;
+ surface->width = texture->width[level];
+ surface->height = texture->height[level];
+ surface->block = texture->block;
+ surface->nblocksx = texture->nblocksx[level];
+ surface->nblocksy = texture->nblocksy[level];
+ /* XXX save the actual stride instead plz kthnxbai */
+ surface->stride =
+ (texture->nblocksx[level] * texture->block.size + 63) & ~63;
+ surface->offset = offset;
+ surface->usage = flags;
+ surface->status = PIPE_SURFACE_STATUS_DEFINED;
+ }
+
+ return surface;
+}
+
+static void r300_tex_surface_release(struct pipe_screen* screen,
+ struct pipe_surface** surface)
+{
+ struct pipe_surface* s = *surface;
+
+ s->refcount--;
+
+ if (s->refcount <= 0) {
+ pipe_texture_reference(&s->texture, NULL);
+ FREE(s);
+ }
+
+ *surface = NULL;
+}
+
+static struct pipe_texture*
+ r300_texture_blanket(struct pipe_screen* screen,
+ const struct pipe_texture* base,
+ const unsigned* stride,
+ struct pipe_buffer* buffer)
+{
+ struct r300_texture* tex;
+
+ if (base->target != PIPE_TEXTURE_2D ||
+ base->last_level != 0 ||
+ base->depth[0] != 1) {
+ return NULL;
+ }
+
+ tex = CALLOC_STRUCT(r300_texture);
+ if (!tex) {
+ return NULL;
+ }
+
+ tex->tex = *base;
+ tex->tex.refcount = 1;
+ tex->tex.screen = screen;
+
+ /* XXX tex->stride = *stride; */
+
+ pipe_buffer_reference(screen, &tex->buffer, buffer);
+
+ return (struct pipe_texture*)tex;
+}
+
+void r300_init_screen_texture_functions(struct pipe_screen* screen)
+{
+ screen->texture_create = r300_texture_create;
+ screen->texture_release = r300_texture_release;
+ screen->get_tex_surface = r300_get_tex_surface;
+ screen->tex_surface_release = r300_tex_surface_release;
+ screen->texture_blanket = r300_texture_blanket;
+}
diff --git a/src/gallium/drivers/r300/r300_texture.h b/src/gallium/drivers/r300/r300_texture.h
new file mode 100644
index 0000000000..7964229a94
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_texture.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_TEXTURE_H
+#define R300_TEXTURE_H
+
+#include "pipe/p_screen.h"
+
+#include "util/u_math.h"
+
+#include "r300_context.h"
+
+void r300_init_screen_texture_functions(struct pipe_screen* screen);
+
+#endif /* R300_TEXTURE_H */
diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h
new file mode 100644
index 0000000000..5a3a212892
--- /dev/null
+++ b/src/gallium/drivers/r300/r300_winsys.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R300_WINSYS_H
+#define R300_WINSYS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The public interface header for the r300 pipe driver.
+ * Any winsys hosting this pipe needs to implement r300_winsys and then
+ * call r300_create_context to start things. */
+
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+
+struct radeon_cs;
+
+struct r300_winsys {
+
+ /* PCI ID */
+ uint32_t pci_id;
+
+ /* GB pipe count */
+ uint32_t gb_pipes;
+
+ /* CS object. This is very much like Intel's batchbuffer.
+ * Fill it full of dwords and relocs and then submit.
+ * Repeat as needed. */
+ /* Note: Unlike Mesa's version of this, we don't keep a copy of the CSM
+ * that was used to create this CS. Is this a good idea? */
+ /* Note: The pipe driver doesn't know how to use this. This is purely
+ * for the winsys. */
+ struct radeon_cs* cs;
+
+ /* Check to see if there's room for commands. */
+ boolean (*check_cs)(struct radeon_cs* cs, int size);
+
+ /* Start a command emit. */
+ void (*begin_cs)(struct radeon_cs* cs,
+ int size,
+ const char* file,
+ const char* function,
+ int line);
+
+ /* Write a dword to the command buffer. */
+ void (*write_cs_dword)(struct radeon_cs* cs, uint32_t dword);
+
+ /* Write a relocated dword to the command buffer. */
+ void (*write_cs_reloc)(struct radeon_cs* cs,
+ struct pipe_buffer* bo,
+ uint32_t rd,
+ uint32_t wd,
+ uint32_t flags);
+
+ /* Finish a command emit. */
+ void (*end_cs)(struct radeon_cs* cs,
+ const char* file,
+ const char* function,
+ int line);
+
+ /* Flush the CS. */
+ void (*flush_cs)(struct radeon_cs* cs);
+};
+
+struct pipe_context* r300_create_context(struct pipe_screen* screen,
+ struct pipe_winsys* winsys,
+ struct r300_winsys* r300_winsys);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* R300_WINSYS_H */
diff --git a/src/gallium/drivers/softpipe/Makefile b/src/gallium/drivers/softpipe/Makefile
index 120bdfd9dd..f186f6df1d 100644
--- a/src/gallium/drivers/softpipe/Makefile
+++ b/src/gallium/drivers/softpipe/Makefile
@@ -14,7 +14,7 @@ C_SOURCES = \
sp_draw_arrays.c \
sp_prim_setup.c \
sp_prim_vbuf.c \
- sp_quad.c \
+ sp_quad_pipe.c \
sp_quad_alpha_test.c \
sp_quad_blend.c \
sp_quad_colormask.c \
diff --git a/src/gallium/drivers/softpipe/SConscript b/src/gallium/drivers/softpipe/SConscript
index c1f7daa8ab..f8720638a7 100644
--- a/src/gallium/drivers/softpipe/SConscript
+++ b/src/gallium/drivers/softpipe/SConscript
@@ -17,7 +17,7 @@ softpipe = env.ConvenienceLibrary(
'sp_setup.c',
'sp_quad_alpha_test.c',
'sp_quad_blend.c',
- 'sp_quad.c',
+ 'sp_quad_pipe.c',
'sp_quad_colormask.c',
'sp_quad_coverage.c',
'sp_quad_depth_test.c',
diff --git a/src/gallium/drivers/softpipe/sp_context.h b/src/gallium/drivers/softpipe/sp_context.h
index e2451c6ecb..59d6df8f2d 100644
--- a/src/gallium/drivers/softpipe/sp_context.h
+++ b/src/gallium/drivers/softpipe/sp_context.h
@@ -32,11 +32,10 @@
#define SP_CONTEXT_H
#include "pipe/p_context.h"
-#include "pipe/p_defines.h"
#include "draw/draw_vertex.h"
-#include "sp_quad.h"
+#include "sp_quad_pipe.h"
#include "sp_tex_sample.h"
@@ -51,7 +50,6 @@
*/
#define SP_NUM_QUAD_THREADS 1
-struct softpipe_winsys;
struct softpipe_vbuf_render;
struct draw_context;
struct draw_stage;
@@ -63,15 +61,15 @@ struct sp_vertex_shader;
struct softpipe_context {
struct pipe_context pipe; /**< base class */
- /* The most recent drawing state as set by the driver:
- */
- const struct pipe_blend_state *blend;
+ /** Constant state objects */
+ const struct pipe_blend_state *blend;
const struct pipe_sampler_state *sampler[PIPE_MAX_SAMPLERS];
- const struct pipe_depth_stencil_alpha_state *depth_stencil;
+ const struct pipe_depth_stencil_alpha_state *depth_stencil;
const struct pipe_rasterizer_state *rasterizer;
const struct sp_fragment_shader *fs;
const struct sp_vertex_shader *vs;
+ /** Other rendering state */
struct pipe_blend_color blend_color;
struct pipe_clip_state clip;
struct pipe_constant_buffer constants[PIPE_SHADER_TYPES];
@@ -82,23 +80,20 @@ struct softpipe_context {
struct pipe_viewport_state viewport;
struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
struct pipe_vertex_element vertex_element[PIPE_MAX_ATTRIBS];
- unsigned dirty;
unsigned num_samplers;
unsigned num_textures;
unsigned num_vertex_elements;
unsigned num_vertex_buffers;
- boolean no_rast;
+ unsigned dirty; /**< Mask of SP_NEW_x flags */
/* Counter for occlusion queries. Note this supports overlapping
* queries.
*/
uint64_t occlusion_count;
- /*
- * Mapped vertex buffers
- */
+ /** Mapped vertex buffers */
ubyte *mapped_vbuffer[PIPE_MAX_ATTRIBS];
/** Mapped constant buffers */
@@ -108,16 +103,11 @@ struct softpipe_context {
struct vertex_info vertex_info;
struct vertex_info vertex_info_vbuf;
+ /** Which vertex shader output slot contains point size */
int psize_slot;
unsigned reduced_api_prim; /**< PIPE_PRIM_POINTS, _LINES or _TRIANGLES */
-#if 0
- /* Stipple derived state:
- */
- ubyte stipple_masks[16][16];
-#endif
-
/** Derived from scissor and surface bounds: */
struct pipe_scissor_state cliprect;
@@ -159,8 +149,9 @@ struct softpipe_context {
struct softpipe_tile_cache *tex_cache[PIPE_MAX_SAMPLERS];
- int use_sse : 1;
- int dump_fs : 1;
+ unsigned use_sse : 1;
+ unsigned dump_fs : 1;
+ unsigned no_rast : 1;
};
diff --git a/src/gallium/drivers/softpipe/sp_draw_arrays.c b/src/gallium/drivers/softpipe/sp_draw_arrays.c
index f888e815b7..f117096bf7 100644
--- a/src/gallium/drivers/softpipe/sp_draw_arrays.c
+++ b/src/gallium/drivers/softpipe/sp_draw_arrays.c
@@ -47,16 +47,22 @@ static void
softpipe_map_constant_buffers(struct softpipe_context *sp)
{
struct pipe_winsys *ws = sp->pipe.winsys;
- uint i;
+ uint i, size;
+
for (i = 0; i < PIPE_SHADER_TYPES; i++) {
if (sp->constants[i].buffer && sp->constants[i].buffer->size)
sp->mapped_constants[i] = ws->buffer_map(ws, sp->constants[i].buffer,
PIPE_BUFFER_USAGE_CPU_READ);
}
+ if (sp->constants[PIPE_SHADER_VERTEX].buffer)
+ size = sp->constants[PIPE_SHADER_VERTEX].buffer->size;
+ else
+ size = 0;
+
draw_set_mapped_constant_buffer(sp->draw,
sp->mapped_constants[PIPE_SHADER_VERTEX],
- sp->constants[PIPE_SHADER_VERTEX].buffer->size);
+ size);
}
static void
diff --git a/src/gallium/drivers/softpipe/sp_fs_exec.c b/src/gallium/drivers/softpipe/sp_fs_exec.c
index 453b0373f0..3c7ba565d6 100644
--- a/src/gallium/drivers/softpipe/sp_fs_exec.c
+++ b/src/gallium/drivers/softpipe/sp_fs_exec.c
@@ -29,7 +29,7 @@
#include "sp_context.h"
#include "sp_state.h"
#include "sp_fs.h"
-#include "sp_headers.h"
+#include "sp_quad.h"
#include "pipe/p_state.h"
diff --git a/src/gallium/drivers/softpipe/sp_fs_sse.c b/src/gallium/drivers/softpipe/sp_fs_sse.c
index 9a273c8764..7e22081132 100644
--- a/src/gallium/drivers/softpipe/sp_fs_sse.c
+++ b/src/gallium/drivers/softpipe/sp_fs_sse.c
@@ -29,7 +29,7 @@
#include "sp_context.h"
#include "sp_state.h"
#include "sp_fs.h"
-#include "sp_headers.h"
+#include "sp_quad.h"
#include "pipe/p_state.h"
diff --git a/src/gallium/drivers/softpipe/sp_headers.h b/src/gallium/drivers/softpipe/sp_headers.h
deleted file mode 100644
index 4a42cb3c19..0000000000
--- a/src/gallium/drivers/softpipe/sp_headers.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-/* Authors: Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef SP_HEADERS_H
-#define SP_HEADERS_H
-
-#include "pipe/p_state.h"
-#include "tgsi/tgsi_exec.h"
-
-#define PRIM_POINT 1
-#define PRIM_LINE 2
-#define PRIM_TRI 3
-
-
-/* The rasterizer generates 2x2 quads of fragment and feeds them to
- * the current fp_machine (see below).
- * Remember that Y=0=top with Y increasing down the window.
- */
-#define QUAD_TOP_LEFT 0
-#define QUAD_TOP_RIGHT 1
-#define QUAD_BOTTOM_LEFT 2
-#define QUAD_BOTTOM_RIGHT 3
-
-#define MASK_TOP_LEFT (1 << QUAD_TOP_LEFT)
-#define MASK_TOP_RIGHT (1 << QUAD_TOP_RIGHT)
-#define MASK_BOTTOM_LEFT (1 << QUAD_BOTTOM_LEFT)
-#define MASK_BOTTOM_RIGHT (1 << QUAD_BOTTOM_RIGHT)
-#define MASK_ALL 0xf
-
-
-/**
- * Encodes everything we need to know about a 2x2 pixel block. Uses
- * "Channel-Serial" or "SoA" layout.
- */
-struct quad_header_input
-{
- int x0;
- int y0;
- float coverage[QUAD_SIZE]; /** fragment coverage for antialiasing */
- unsigned facing:1; /**< Front (0) or back (1) facing? */
- unsigned prim:2; /**< PRIM_POINT, LINE, TRI */
-};
-
-struct quad_header_inout
-{
- unsigned mask:4;
-};
-
-struct quad_header_output
-{
- /** colors in SOA format (rrrr, gggg, bbbb, aaaa) */
- float color[PIPE_MAX_COLOR_BUFS][NUM_CHANNELS][QUAD_SIZE];
- float depth[QUAD_SIZE];
-};
-
-struct quad_header {
- struct quad_header_input input;
- struct quad_header_inout inout;
- struct quad_header_output output;
-
- const struct tgsi_interp_coef *coef;
- const struct tgsi_interp_coef *posCoef;
-
- unsigned nr_attrs;
-};
-
-#endif /* SP_HEADERS_H */
-
diff --git a/src/gallium/drivers/softpipe/sp_quad.h b/src/gallium/drivers/softpipe/sp_quad.h
index 08513cb95f..bd6c6cb912 100644
--- a/src/gallium/drivers/softpipe/sp_quad.h
+++ b/src/gallium/drivers/softpipe/sp_quad.h
@@ -31,39 +31,76 @@
#ifndef SP_QUAD_H
#define SP_QUAD_H
+#include "pipe/p_state.h"
+#include "tgsi/tgsi_exec.h"
-struct softpipe_context;
-struct quad_header;
+#define QUAD_PRIM_POINT 1
+#define QUAD_PRIM_LINE 2
+#define QUAD_PRIM_TRI 3
-struct quad_stage {
- struct softpipe_context *softpipe;
- struct quad_stage *next;
+/* The rasterizer generates 2x2 quads of fragment and feeds them to
+ * the current fp_machine (see below).
+ * Remember that Y=0=top with Y increasing down the window.
+ */
+#define QUAD_TOP_LEFT 0
+#define QUAD_TOP_RIGHT 1
+#define QUAD_BOTTOM_LEFT 2
+#define QUAD_BOTTOM_RIGHT 3
+
+#define MASK_TOP_LEFT (1 << QUAD_TOP_LEFT)
+#define MASK_TOP_RIGHT (1 << QUAD_TOP_RIGHT)
+#define MASK_BOTTOM_LEFT (1 << QUAD_BOTTOM_LEFT)
+#define MASK_BOTTOM_RIGHT (1 << QUAD_BOTTOM_RIGHT)
+#define MASK_ALL 0xf
+
+
+/**
+ * Quad stage inputs (pos, coverage, front/back face, etc)
+ */
+struct quad_header_input
+{
+ int x0, y0; /**< quad window pos, always even */
+ float coverage[QUAD_SIZE]; /**< fragment coverage for antialiasing */
+ unsigned facing:1; /**< Front (0) or back (1) facing? */
+ unsigned prim:2; /**< QUAD_PRIM_POINT, LINE, TRI */
+};
- void (*begin)(struct quad_stage *qs);
- /** the stage action */
- void (*run)(struct quad_stage *qs, struct quad_header *quad);
+/**
+ * Quad stage inputs/outputs.
+ */
+struct quad_header_inout
+{
+ unsigned mask:4;
+};
+
- void (*destroy)(struct quad_stage *qs);
+/**
+ * Quad stage outputs (color & depth).
+ */
+struct quad_header_output
+{
+ /** colors in SOA format (rrrr, gggg, bbbb, aaaa) */
+ float color[PIPE_MAX_COLOR_BUFS][NUM_CHANNELS][QUAD_SIZE];
+ float depth[QUAD_SIZE];
};
-struct quad_stage *sp_quad_polygon_stipple_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_earlyz_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_shade_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_alpha_test_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_stencil_test_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_depth_test_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_occlusion_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_coverage_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_blend_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_colormask_stage( struct softpipe_context *softpipe );
-struct quad_stage *sp_quad_output_stage( struct softpipe_context *softpipe );
+/**
+ * Encodes everything we need to know about a 2x2 pixel block. Uses
+ * "Channel-Serial" or "SoA" layout.
+ */
+struct quad_header {
+ struct quad_header_input input;
+ struct quad_header_inout inout;
+ struct quad_header_output output;
-void sp_build_quad_pipeline(struct softpipe_context *sp);
+ const struct tgsi_interp_coef *coef;
+ const struct tgsi_interp_coef *posCoef;
-void sp_depth_test_quad(struct quad_stage *qs, struct quad_header *quad);
+ unsigned nr_attrs;
+};
#endif /* SP_QUAD_H */
diff --git a/src/gallium/drivers/softpipe/sp_quad_alpha_test.c b/src/gallium/drivers/softpipe/sp_quad_alpha_test.c
index 85c9f037a3..0845bae0e6 100644
--- a/src/gallium/drivers/softpipe/sp_quad_alpha_test.c
+++ b/src/gallium/drivers/softpipe/sp_quad_alpha_test.c
@@ -4,8 +4,8 @@
*/
#include "sp_context.h"
-#include "sp_headers.h"
#include "sp_quad.h"
+#include "sp_quad_pipe.h"
#include "pipe/p_defines.h"
#include "util/u_memory.h"
diff --git a/src/gallium/drivers/softpipe/sp_quad_blend.c b/src/gallium/drivers/softpipe/sp_quad_blend.c
index fb1d430a4f..e134e44337 100644
--- a/src/gallium/drivers/softpipe/sp_quad_blend.c
+++ b/src/gallium/drivers/softpipe/sp_quad_blend.c
@@ -34,10 +34,10 @@
#include "util/u_math.h"
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
+#include "sp_quad.h"
#include "sp_surface.h"
#include "sp_tile_cache.h"
-#include "sp_quad.h"
+#include "sp_quad_pipe.h"
#define VEC4_COPY(DST, SRC) \
diff --git a/src/gallium/drivers/softpipe/sp_quad_bufloop.c b/src/gallium/drivers/softpipe/sp_quad_bufloop.c
index d7d6a6974d..953d8516b9 100644
--- a/src/gallium/drivers/softpipe/sp_quad_bufloop.c
+++ b/src/gallium/drivers/softpipe/sp_quad_bufloop.c
@@ -1,9 +1,9 @@
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
-#include "sp_surface.h"
#include "sp_quad.h"
+#include "sp_surface.h"
+#include "sp_quad_pipe.h"
/**
diff --git a/src/gallium/drivers/softpipe/sp_quad_colormask.c b/src/gallium/drivers/softpipe/sp_quad_colormask.c
index 563c2fc739..dc90e5d5e9 100644
--- a/src/gallium/drivers/softpipe/sp_quad_colormask.c
+++ b/src/gallium/drivers/softpipe/sp_quad_colormask.c
@@ -34,9 +34,9 @@
#include "util/u_math.h"
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
-#include "sp_surface.h"
#include "sp_quad.h"
+#include "sp_surface.h"
+#include "sp_quad_pipe.h"
#include "sp_tile_cache.h"
diff --git a/src/gallium/drivers/softpipe/sp_quad_coverage.c b/src/gallium/drivers/softpipe/sp_quad_coverage.c
index c27fd1482d..4aeee85870 100644
--- a/src/gallium/drivers/softpipe/sp_quad_coverage.c
+++ b/src/gallium/drivers/softpipe/sp_quad_coverage.c
@@ -35,8 +35,8 @@
#include "pipe/p_defines.h"
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
#include "sp_quad.h"
+#include "sp_quad_pipe.h"
/**
@@ -46,10 +46,11 @@ static void
coverage_quad(struct quad_stage *qs, struct quad_header *quad)
{
struct softpipe_context *softpipe = qs->softpipe;
+ const uint prim = quad->input.prim;
- if ((softpipe->rasterizer->poly_smooth && quad->input.prim == PRIM_TRI) ||
- (softpipe->rasterizer->line_smooth && quad->input.prim == PRIM_LINE) ||
- (softpipe->rasterizer->point_smooth && quad->input.prim == PRIM_POINT)) {
+ if ((softpipe->rasterizer->poly_smooth && prim == QUAD_PRIM_TRI) ||
+ (softpipe->rasterizer->line_smooth && prim == QUAD_PRIM_LINE) ||
+ (softpipe->rasterizer->point_smooth && prim == QUAD_PRIM_POINT)) {
uint cbuf;
/* loop over colorbuffer outputs */
diff --git a/src/gallium/drivers/softpipe/sp_quad_depth_test.c b/src/gallium/drivers/softpipe/sp_quad_depth_test.c
index 523bd3e080..d463930bae 100644
--- a/src/gallium/drivers/softpipe/sp_quad_depth_test.c
+++ b/src/gallium/drivers/softpipe/sp_quad_depth_test.c
@@ -32,9 +32,9 @@
#include "pipe/p_defines.h"
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
-#include "sp_surface.h"
#include "sp_quad.h"
+#include "sp_surface.h"
+#include "sp_quad_pipe.h"
#include "sp_tile_cache.h"
diff --git a/src/gallium/drivers/softpipe/sp_quad_earlyz.c b/src/gallium/drivers/softpipe/sp_quad_earlyz.c
index 6e2dde304e..496fd39ed1 100644
--- a/src/gallium/drivers/softpipe/sp_quad_earlyz.c
+++ b/src/gallium/drivers/softpipe/sp_quad_earlyz.c
@@ -31,8 +31,8 @@
#include "pipe/p_defines.h"
#include "util/u_memory.h"
-#include "sp_headers.h"
#include "sp_quad.h"
+#include "sp_quad_pipe.h"
/**
diff --git a/src/gallium/drivers/softpipe/sp_quad_fs.c b/src/gallium/drivers/softpipe/sp_quad_fs.c
index 5dacbbe55f..adca5df73d 100644
--- a/src/gallium/drivers/softpipe/sp_quad_fs.c
+++ b/src/gallium/drivers/softpipe/sp_quad_fs.c
@@ -43,8 +43,8 @@
#include "sp_context.h"
#include "sp_state.h"
-#include "sp_headers.h"
#include "sp_quad.h"
+#include "sp_quad_pipe.h"
#include "sp_texture.h"
#include "sp_tex_sample.h"
diff --git a/src/gallium/drivers/softpipe/sp_quad_occlusion.c b/src/gallium/drivers/softpipe/sp_quad_occlusion.c
index 169bd82876..dfa7ff3b1d 100644
--- a/src/gallium/drivers/softpipe/sp_quad_occlusion.c
+++ b/src/gallium/drivers/softpipe/sp_quad_occlusion.c
@@ -35,9 +35,9 @@
#include "pipe/p_defines.h"
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
-#include "sp_surface.h"
#include "sp_quad.h"
+#include "sp_surface.h"
+#include "sp_quad_pipe.h"
static unsigned count_bits( unsigned val )
{
diff --git a/src/gallium/drivers/softpipe/sp_quad_output.c b/src/gallium/drivers/softpipe/sp_quad_output.c
index a37c8b4c39..92d5f9f3c1 100644
--- a/src/gallium/drivers/softpipe/sp_quad_output.c
+++ b/src/gallium/drivers/softpipe/sp_quad_output.c
@@ -27,9 +27,9 @@
#include "util/u_memory.h"
#include "sp_context.h"
-#include "sp_headers.h"
-#include "sp_surface.h"
#include "sp_quad.h"
+#include "sp_surface.h"
+#include "sp_quad_pipe.h"
#include "sp_tile_cache.h"
diff --git a/src/gallium/drivers/softpipe/sp_quad.c b/src/gallium/drivers/softpipe/sp_quad_pipe.c
index 892ef87ee9..892ef87ee9 100644
--- a/src/gallium/drivers/softpipe/sp_quad.c
+++ b/src/gallium/drivers/softpipe/sp_quad_pipe.c
diff --git a/src/gallium/drivers/softpipe/sp_quad_pipe.h b/src/gallium/drivers/softpipe/sp_quad_pipe.h
new file mode 100644
index 0000000000..0e40586ffc
--- /dev/null
+++ b/src/gallium/drivers/softpipe/sp_quad_pipe.h
@@ -0,0 +1,74 @@
+/**************************************************************************
+ *
+ * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/* Authors: Keith Whitwell <keith@tungstengraphics.com>
+ */
+
+#ifndef SP_QUAD_PIPE_H
+#define SP_QUAD_PIPE_H
+
+
+struct softpipe_context;
+struct quad_header;
+
+
+/**
+ * Fragment processing is performed on 2x2 blocks of pixels called "quads".
+ * Quad processing is performed with a pipeline of stages represented by
+ * this type.
+ */
+struct quad_stage {
+ struct softpipe_context *softpipe;
+
+ struct quad_stage *next;
+
+ void (*begin)(struct quad_stage *qs);
+
+ /** the stage action */
+ void (*run)(struct quad_stage *qs, struct quad_header *quad);
+
+ void (*destroy)(struct quad_stage *qs);
+};
+
+
+struct quad_stage *sp_quad_polygon_stipple_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_earlyz_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_shade_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_alpha_test_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_stencil_test_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_depth_test_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_occlusion_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_coverage_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_blend_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_colormask_stage( struct softpipe_context *softpipe );
+struct quad_stage *sp_quad_output_stage( struct softpipe_context *softpipe );
+
+void sp_build_quad_pipeline(struct softpipe_context *sp);
+
+void sp_depth_test_quad(struct quad_stage *qs, struct quad_header *quad);
+
+#endif /* SP_QUAD_PIPE_H */
diff --git a/src/gallium/drivers/softpipe/sp_quad_stencil.c b/src/gallium/drivers/softpipe/sp_quad_stencil.c
index 7495515764..5e9d447737 100644
--- a/src/gallium/drivers/softpipe/sp_quad_stencil.c
+++ b/src/gallium/drivers/softpipe/sp_quad_stencil.c
@@ -5,10 +5,10 @@
#include "sp_context.h"
-#include "sp_headers.h"
+#include "sp_quad.h"
#include "sp_surface.h"
#include "sp_tile_cache.h"
-#include "sp_quad.h"
+#include "sp_quad_pipe.h"
#include "pipe/p_defines.h"
#include "util/u_memory.h"
diff --git a/src/gallium/drivers/softpipe/sp_quad_stipple.c b/src/gallium/drivers/softpipe/sp_quad_stipple.c
index ccf37f6be5..05e862f097 100644
--- a/src/gallium/drivers/softpipe/sp_quad_stipple.c
+++ b/src/gallium/drivers/softpipe/sp_quad_stipple.c
@@ -4,8 +4,8 @@
*/
#include "sp_context.h"
-#include "sp_headers.h"
#include "sp_quad.h"
+#include "sp_quad_pipe.h"
#include "pipe/p_defines.h"
#include "util/u_memory.h"
@@ -19,11 +19,13 @@ stipple_quad(struct quad_stage *qs, struct quad_header *quad)
static const uint bit31 = 1 << 31;
static const uint bit30 = 1 << 30;
- if (quad->input.prim == PRIM_TRI) {
+ if (quad->input.prim == QUAD_PRIM_TRI) {
struct softpipe_context *softpipe = qs->softpipe;
/* need to invert Y to index into OpenGL's stipple pattern */
int y0, y1;
uint stipple0, stipple1;
+ const int col0 = quad->input.x0 % 32;
+
if (softpipe->rasterizer->origin_lower_left) {
y0 = softpipe->framebuffer.height - 1 - quad->input.y0;
y1 = y0 - 1;
@@ -32,12 +34,11 @@ stipple_quad(struct quad_stage *qs, struct quad_header *quad)
y0 = quad->input.y0;
y1 = y0 + 1;
}
+
stipple0 = softpipe->poly_stipple.stipple[y0 % 32];
stipple1 = softpipe->poly_stipple.stipple[y1 % 32];
-#if 1
- {
- const int col0 = quad->input.x0 % 32;
+ /* turn off quad mask bits that fail the stipple test */
if ((stipple0 & (bit31 >> col0)) == 0)
quad->inout.mask &= ~MASK_TOP_LEFT;
@@ -49,19 +50,11 @@ stipple_quad(struct quad_stage *qs, struct quad_header *quad)
if ((stipple1 & (bit30 >> col0)) == 0)
quad->inout.mask &= ~MASK_BOTTOM_RIGHT;
- }
-#else
- /* We'd like to use this code, but we'd need to redefine
- * MASK_TOP_LEFT to be (1 << 1) and MASK_TOP_RIGHT to be (1 << 0),
- * and similarly for the BOTTOM bits. But that may have undesirable
- * side effects elsewhere.
- */
- const int col0 = 30 - (quad->input.x0 % 32);
- quad->inout.mask &= (((stipple0 >> col0) & 0x3) |
- (((stipple1 >> col0) & 0x3) << 2));
-#endif
- if (!quad->inout.mask)
+
+ if (!quad->inout.mask) {
+ /* all fragments failed stipple test, end of quad pipeline */
return;
+ }
}
qs->next->run(qs->next, quad);
diff --git a/src/gallium/drivers/softpipe/sp_setup.c b/src/gallium/drivers/softpipe/sp_setup.c
index b1adb9cb7a..0925653b5d 100644
--- a/src/gallium/drivers/softpipe/sp_setup.c
+++ b/src/gallium/drivers/softpipe/sp_setup.c
@@ -32,13 +32,12 @@
* \author Brian Paul
*/
-#include "sp_setup.h"
-
#include "sp_context.h"
-#include "sp_headers.h"
+#include "sp_prim_setup.h"
#include "sp_quad.h"
+#include "sp_quad_pipe.h"
+#include "sp_setup.h"
#include "sp_state.h"
-#include "sp_prim_setup.h"
#include "draw/draw_context.h"
#include "draw/draw_private.h"
#include "draw/draw_vertex.h"
@@ -265,17 +264,20 @@ is_inf_or_nan(float x)
}
-static boolean cull_tri( struct setup_context *setup,
- float det )
+/**
+ * Do triangle cull test using tri determinant (sign indicates orientation)
+ * \return true if triangle is to be culled.
+ */
+static INLINE boolean
+cull_tri(const struct setup_context *setup, float det)
{
- if (det != 0)
- {
+ if (det != 0) {
/* if (det < 0 then Z points toward camera and triangle is
* counter-clockwise winding.
*/
unsigned winding = (det < 0) ? PIPE_WINDING_CCW : PIPE_WINDING_CW;
-
- if ((winding & setup->winding) == 0)
+
+ if ((winding & setup->winding) == 0)
return FALSE;
}
@@ -968,7 +970,7 @@ void setup_tri( struct setup_context *setup,
setup_tri_coefficients( setup );
setup_tri_edges( setup );
- setup->quad.input.prim = PRIM_TRI;
+ setup->quad.input.prim = QUAD_PRIM_TRI;
setup->span.y = 0;
setup->span.y_flags = 0;
@@ -1009,7 +1011,7 @@ void setup_tri( struct setup_context *setup,
* for a line.
*/
static void
-line_linear_coeff(struct setup_context *setup,
+line_linear_coeff(const struct setup_context *setup,
struct tgsi_interp_coef *coef,
uint vertSlot, uint i)
{
@@ -1029,9 +1031,9 @@ line_linear_coeff(struct setup_context *setup,
* for a line.
*/
static void
-line_persp_coeff(struct setup_context *setup,
- struct tgsi_interp_coef *coef,
- uint vertSlot, uint i)
+line_persp_coeff(const struct setup_context *setup,
+ struct tgsi_interp_coef *coef,
+ uint vertSlot, uint i)
{
/* XXX double-check/verify this arithmetic */
const float a0 = setup->vmin[vertSlot][i] * setup->vmin[0][3];
@@ -1206,7 +1208,7 @@ setup_line(struct setup_context *setup,
setup->quad.input.x0 = setup->quad.input.y0 = -1;
setup->quad.inout.mask = 0x0;
- setup->quad.input.prim = PRIM_LINE;
+ setup->quad.input.prim = QUAD_PRIM_LINE;
/* XXX temporary: set coverage to 1.0 so the line appears
* if AA mode happens to be enabled.
*/
@@ -1266,7 +1268,7 @@ setup_line(struct setup_context *setup,
static void
-point_persp_coeff(struct setup_context *setup,
+point_persp_coeff(const struct setup_context *setup,
const float (*vert)[4],
struct tgsi_interp_coef *coef,
uint vertSlot, uint i)
@@ -1361,7 +1363,7 @@ setup_point( struct setup_context *setup,
}
}
- setup->quad.input.prim = PRIM_POINT;
+ setup->quad.input.prim = QUAD_PRIM_POINT;
if (halfSize <= 0.5 && !round) {
/* special case for 1-pixel points */
diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c
index 32aa5025e4..adbd0cb7f0 100644
--- a/src/gallium/drivers/softpipe/sp_tex_sample.c
+++ b/src/gallium/drivers/softpipe/sp_tex_sample.c
@@ -34,7 +34,7 @@
*/
#include "sp_context.h"
-#include "sp_headers.h"
+#include "sp_quad.h"
#include "sp_surface.h"
#include "sp_texture.h"
#include "sp_tex_sample.h"
diff --git a/src/gallium/drivers/softpipe/sp_texture.c b/src/gallium/drivers/softpipe/sp_texture.c
index f84b3fb9d4..28a9784b16 100644
--- a/src/gallium/drivers/softpipe/sp_texture.c
+++ b/src/gallium/drivers/softpipe/sp_texture.c
@@ -265,7 +265,7 @@ softpipe_tex_surface_release(struct pipe_screen *screen,
* needed post-processing to put them into hardware layout, this is
* where it would happen. For softpipe, nothing to do.
*/
- assert ((*s)->texture);
+ assert(surf->texture);
if (--surf->refcount == 0) {
pipe_texture_reference(&surf->texture, NULL);
FREE(surf);