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-rw-r--r--src/gallium/drivers/r600/eg_hw_states.c33
-rw-r--r--src/gallium/drivers/r600/r600_blit.c58
-rw-r--r--src/gallium/drivers/r600/r600_buffer.c31
-rw-r--r--src/gallium/drivers/r600/r600_context.h4
-rw-r--r--src/gallium/drivers/r600/r600_hw_states.c40
-rw-r--r--src/gallium/drivers/r600/r600_query.c15
-rw-r--r--src/gallium/drivers/r600/r600_resource.h5
-rw-r--r--src/gallium/drivers/r600/r600_shader.c13
-rw-r--r--src/gallium/drivers/r600/r600_state.c4
-rw-r--r--src/gallium/drivers/r600/r600_texture.c25
-rw-r--r--src/gallium/drivers/r600/radeon.h31
11 files changed, 132 insertions, 127 deletions
diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
index a58adc6bab..e4b5b316b8 100644
--- a/src/gallium/drivers/r600/eg_hw_states.c
+++ b/src/gallium/drivers/r600/eg_hw_states.c
@@ -120,7 +120,7 @@ static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
rstate->nbo = 1;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
@@ -170,7 +170,7 @@ static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
rtex->depth = 1;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
level = state->zsbuf->level;
@@ -544,11 +544,11 @@ static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
if (r) {
return;
}
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
} else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
}
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -860,10 +860,11 @@ static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resourc
struct r600_screen *rscreen = rctx->screen;
radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
- vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+
+ radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
- vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
+ vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) |
S_030008_DATA_FORMAT(format);
vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
@@ -891,7 +892,7 @@ static int eg_draw_vgt_init(struct r600_draw *draw,
draw->draw.states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
draw->draw.states[EG_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
if (rbuffer) {
- draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw.nbo = 1;
@@ -973,7 +974,7 @@ static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rp
state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
S_0286E0_LINEAR_CENTROID_ENA(1);
- state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
state->nbo = 1;
state->placement[0] = RADEON_GEM_DOMAIN_GTT;
return radeon_state_pm4(state);
@@ -998,8 +999,8 @@ static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rp
state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
S_028860_STACK_SIZE(rshader->bc.nstack);
- state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
- state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
state->nbo = 2;
state->placement[0] = RADEON_GEM_DOMAIN_GTT;
state->placement[2] = RADEON_GEM_DOMAIN_GTT;
@@ -1064,12 +1065,12 @@ static void eg_texture_state_cb(struct r600_screen *rscreen, struct r600_resourc
format = r600_translate_colorformat(rtexture->resource.base.b.format);
swap = r600_translate_colorswap(rtexture->resource.base.b.format);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
color_info = 0;
} else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
color_info = S_028C70_SOURCE_FORMAT(1);
@@ -1113,7 +1114,7 @@ static void eg_texture_state_db(struct r600_screen *rscreen, struct r600_resourc
rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
@@ -1202,7 +1203,7 @@ void eg_set_constant_buffer(struct pipe_context *ctx,
rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
if (radeon_state_pm4(rstate))
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 2c22adb62a..0e061c25f7 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -165,7 +165,8 @@ struct r600_blit_states {
static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
{
struct radeon_state *rstate;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
+ void *data;
u32 vbo[] = {
0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000,
0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
@@ -178,16 +179,17 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
};
/* simple shader */
- bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
+ bo = radeon_ws_bo(rscreen->rw, 128, 4096);
if (bo == NULL) {
return -ENOMEM;
}
- if (radeon_bo_map(rscreen->rw, bo)) {
- radeon_bo_decref(rscreen->rw, bo);
+ data = radeon_ws_bo_map(rscreen->rw, bo);
+ if (!data) {
+ radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
return -ENOMEM;
}
- memcpy(bo->data, vbo, 128);
- radeon_bo_unmap(rscreen->rw, bo);
+ memcpy(data, vbo, 128);
+ radeon_ws_bo_unmap(rscreen->rw, bo);
rstate = &bstates->vs_resource0;
radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
@@ -219,7 +221,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
if (radeon_state_pm4(rstate)) {
@@ -232,7 +234,8 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
{
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
+ void *data;
u32 shader_bc_r600[] = {
0x00000004, 0x81000400,
0x00000008, 0xA01C0000,
@@ -271,28 +274,29 @@ static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon
};
/* simple shader */
- bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
+ bo = radeon_ws_bo(rscreen->rw, 128, 4096);
if (bo == NULL) {
return;
}
- if (radeon_bo_map(rscreen->rw, bo)) {
- radeon_bo_decref(rscreen->rw, bo);
+ data = radeon_ws_bo_map(rscreen->rw, bo);
+ if (!data) {
+ radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
return;
}
switch (rscreen->chip_class) {
case R600:
- memcpy(bo->data, shader_bc_r600, 128);
+ memcpy(data, shader_bc_r600, 128);
break;
case R700:
- memcpy(bo->data, shader_bc_r700, 128);
+ memcpy(data, shader_bc_r700, 128);
break;
default:
R600_ERR("unsupported chip family\n");
- radeon_bo_unmap(rscreen->rw, bo);
- radeon_bo_decref(rscreen->rw, bo);
+ radeon_ws_bo_unmap(rscreen->rw, bo);
+ radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
return;
}
- radeon_bo_unmap(rscreen->rw, bo);
+ radeon_ws_bo_unmap(rscreen->rw, bo);
radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
@@ -304,7 +308,7 @@ static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon
rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005;
rstate->bo[0] = bo;
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], bo);
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
@@ -314,7 +318,8 @@ static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon
static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
{
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
+ void *data;
u32 shader_bc_r600[] = {
0x00000002, 0xA00C0000,
0xC0008000, 0x94200688,
@@ -333,28 +338,29 @@ static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon
};
/* simple shader */
- bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
+ bo = radeon_ws_bo(rscreen->rw, 128, 4096);
if (bo == NULL) {
return;
}
- if (radeon_bo_map(rscreen->rw, bo)) {
- radeon_bo_decref(rscreen->rw, bo);
+ data = radeon_ws_bo_map(rscreen->rw, bo);
+ if (!data) {
+ radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
return;
}
switch (rscreen->chip_class) {
case R600:
- memcpy(bo->data, shader_bc_r600, 48);
+ memcpy(data, shader_bc_r600, 48);
break;
case R700:
- memcpy(bo->data, shader_bc_r700, 48);
+ memcpy(data, shader_bc_r700, 48);
break;
default:
R600_ERR("unsupported chip family\n");
- radeon_bo_unmap(rscreen->rw, bo);
- radeon_bo_decref(rscreen->rw, bo);
+ radeon_ws_bo_unmap(rscreen->rw, bo);
+ radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
return;
}
- radeon_bo_unmap(rscreen->rw, bo);
+ radeon_ws_bo_unmap(rscreen->rw, bo);
radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index 06197d3d7d..37abf42d34 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -68,7 +68,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
{
struct r600_screen *rscreen = r600_screen(screen);
struct r600_resource *rbuffer;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
struct pb_desc desc;
/* XXX We probably want a different alignment for buffers and textures. */
unsigned alignment = 4096;
@@ -81,7 +81,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
pipe_reference_init(&rbuffer->base.b.reference, 1);
rbuffer->base.b.screen = screen;
rbuffer->base.vtbl = &r600_buffer_vtbl;
-
+ rbuffer->size = rbuffer->base.b.width0;
if ((rscreen->use_mem_constant == FALSE) && (rbuffer->base.b.bind & PIPE_BIND_CONSTANT_BUFFER)) {
desc.alignment = alignment;
desc.usage = rbuffer->base.b.bind;
@@ -94,7 +94,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
return &rbuffer->base.b;
}
rbuffer->domain = r600_domain_from_usage(rbuffer->base.b.bind);
- bo = radeon_bo(rscreen->rw, 0, rbuffer->base.b.width0, alignment, NULL);
+ bo = radeon_ws_bo(rscreen->rw, rbuffer->base.b.width0, alignment);
if (bo == NULL) {
FREE(rbuffer);
return NULL;
@@ -110,6 +110,7 @@ struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
struct r600_resource *rbuffer;
struct r600_screen *rscreen = r600_screen(screen);
struct pipe_resource templ;
+ void *data;
memset(&templ, 0, sizeof(struct pipe_resource));
templ.target = PIPE_BUFFER;
@@ -124,9 +125,9 @@ struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
if (rbuffer == NULL) {
return NULL;
}
- radeon_bo_map(rscreen->rw, rbuffer->bo);
- memcpy(rbuffer->bo->data, ptr, bytes);
- radeon_bo_unmap(rscreen->rw, rbuffer->bo);
+ data = radeon_ws_bo_map(rscreen->rw, rbuffer->bo);
+ memcpy(data, ptr, bytes);
+ radeon_ws_bo_unmap(rscreen->rw, rbuffer->bo);
return &rbuffer->base.b;
}
@@ -142,7 +143,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
rbuffer->pb = NULL;
}
if (rbuffer->bo) {
- radeon_bo_decref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rbuffer->bo, NULL);
}
memset(rbuffer, 0, sizeof(struct r600_resource));
FREE(rbuffer);
@@ -154,6 +155,7 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
struct r600_resource *rbuffer = (struct r600_resource*)transfer->resource;
struct r600_screen *rscreen = r600_screen(pipe->screen);
int write = 0;
+ uint8_t *data;
if (rbuffer->pb) {
return (uint8_t*)pb_map(rbuffer->pb, transfer->usage, NULL) + transfer->box.x;
@@ -164,10 +166,11 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
if (transfer->usage & PIPE_TRANSFER_WRITE) {
write = 1;
}
- if (radeon_bo_map(rscreen->rw, rbuffer->bo)) {
+ data = radeon_ws_bo_map(rscreen->rw, rbuffer->bo);
+ if (!data)
return NULL;
- }
- return (uint8_t*)rbuffer->bo->data + transfer->box.x;
+
+ return (uint8_t*)data + transfer->box.x;
}
static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
@@ -179,7 +182,7 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
if (rbuffer->pb) {
pb_unmap(rbuffer->pb);
} else {
- radeon_bo_unmap(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_unmap(rscreen->rw, rbuffer->bo);
}
}
@@ -202,16 +205,16 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
{
struct radeon *rw = (struct radeon*)screen->winsys;
struct r600_resource *rbuffer;
- struct radeon_bo *bo = NULL;
+ struct radeon_ws_bo *bo = NULL;
- bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
+ bo = radeon_ws_bo_handle(rw, whandle->handle);
if (bo == NULL) {
return NULL;
}
rbuffer = CALLOC_STRUCT(r600_resource);
if (rbuffer == NULL) {
- radeon_bo_decref(rw, bo);
+ radeon_ws_bo_reference(rw, &bo, NULL);
return NULL;
}
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 73037fdb1b..f82c8f82fe 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -49,7 +49,7 @@ struct r600_query {
boolean flushed;
unsigned state;
/* The buffer where query results are stored. */
- struct radeon_bo *buffer;
+ struct radeon_ws_bo *buffer;
unsigned buffer_size;
/* linked list of queries */
struct list_head list;
@@ -103,7 +103,7 @@ struct r600_context_state {
unsigned type;
struct radeon_state rstate[R600_MAX_RSTATE];
struct r600_shader shader;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
unsigned nrstate;
};
diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
index b7070d7d6e..1974b20d86 100644
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ b/src/gallium/drivers/r600/r600_hw_states.c
@@ -120,7 +120,7 @@ static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
@@ -171,7 +171,7 @@ static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
rtex->depth = 1;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
level = state->zsbuf->level;
@@ -537,11 +537,11 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
if (r) {
return;
}
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
} else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
}
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -873,10 +873,10 @@ static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resou
struct r600_screen *rscreen = rctx->screen;
radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
- vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
- vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
S_038008_DATA_FORMAT(format);
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
@@ -899,7 +899,7 @@ static int r600_draw_vgt_init(struct r600_draw *draw,
draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
draw->draw.states[R600_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
if (rbuffer) {
- draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw.nbo = 1;
@@ -980,7 +980,7 @@ static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *
state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
S_028868_STACK_SIZE(rshader->bc.nstack);
state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
- state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
state->nbo = 1;
state->placement[0] = RADEON_GEM_DOMAIN_GTT;
return radeon_state_pm4(state);
@@ -1005,8 +1005,8 @@ static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *
state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
S_028868_STACK_SIZE(rshader->bc.nstack);
- state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
- state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
state->nbo = 2;
state->placement[0] = RADEON_GEM_DOMAIN_GTT;
state->placement[2] = RADEON_GEM_DOMAIN_GTT;
@@ -1070,18 +1070,18 @@ static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resou
format = r600_translate_colorformat(rtexture->resource.base.b.format);
swap = r600_translate_colorswap(rtexture->resource.base.b.format);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rtexture->uncompressed);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 3;
color_info = 0;
} else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
@@ -1126,7 +1126,7 @@ static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resou
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
S_028000_SLICE_TILE_MAX(slice);
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
@@ -1262,7 +1262,7 @@ void r600_set_constant_buffer_mem(struct pipe_context *ctx,
rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
if (radeon_state_pm4(rstate))
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 68358f9dd7..922d7ace13 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -39,7 +39,7 @@ static void r600_query_begin(struct r600_context *rctx, struct r600_query *rquer
radeon_state_fini(rstate);
radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_BEGIN, 0, 0);
rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
if (radeon_state_pm4(rstate)) {
@@ -55,7 +55,7 @@ static void r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
radeon_state_fini(rstate);
radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_END, 0, 0);
rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
if (radeon_state_pm4(rstate)) {
@@ -79,7 +79,7 @@ static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned q
q->type = query_type;
q->buffer_size = 4096;
- q->buffer = radeon_bo(rscreen->rw, 0, q->buffer_size, 1, NULL);
+ q->buffer = radeon_ws_bo(rscreen->rw, q->buffer_size, 1);
if (!q->buffer) {
FREE(q);
return NULL;
@@ -96,7 +96,7 @@ static void r600_destroy_query(struct pipe_context *ctx,
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_query *q = r600_query(query);
- radeon_bo_decref(rscreen->rw, q->buffer);
+ radeon_ws_bo_reference(rscreen->rw, &q->buffer, NULL);
LIST_DEL(&q->list);
FREE(query);
}
@@ -108,9 +108,8 @@ static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquer
u32 *results;
int i;
- radeon_bo_wait(rscreen->rw, rquery->buffer);
- radeon_bo_map(rscreen->rw, rquery->buffer);
- results = rquery->buffer->data;
+ radeon_ws_bo_wait(rscreen->rw, rquery->buffer);
+ results = radeon_ws_bo_map(rscreen->rw, rquery->buffer);
for (i = 0; i < rquery->num_results; i += 4) {
start = (u64)results[i] | (u64)results[i + 1] << 32;
end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
@@ -118,7 +117,7 @@ static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquer
rquery->result += end - start;
}
}
- radeon_bo_unmap(rscreen->rw, rquery->buffer);
+ radeon_ws_bo_unmap(rscreen->rw, rquery->buffer);
rquery->num_results = 0;
}
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 129667ad20..8a110b1b72 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -34,10 +34,11 @@ struct r600_screen;
*/
struct r600_resource {
struct u_resource base;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
u32 domain;
u32 flink;
struct pb_buffer *pb;
+ u32 size;
};
struct r600_resource_texture {
@@ -55,7 +56,7 @@ struct r600_resource_texture {
unsigned tile_type;
unsigned depth;
unsigned dirty;
- struct radeon_bo *uncompressed;
+ struct radeon_ws_bo *uncompressed;
struct radeon_state scissor[PIPE_MAX_TEXTURE_LEVELS];
struct radeon_state cb[8][PIPE_MAX_TEXTURE_LEVELS];
struct radeon_state db[PIPE_MAX_TEXTURE_LEVELS];
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index ad19238697..10f6d016a3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -157,18 +157,19 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state
struct r600_context *rctx = r600_context(ctx);
struct r600_shader *rshader = &rpshader->shader;
int r;
+ void *data;
/* copy new shader */
- radeon_bo_decref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rpshader->bo, NULL);
rpshader->bo = NULL;
- rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
- 4096, NULL);
+ rpshader->bo = radeon_ws_bo(rscreen->rw, rshader->bc.ndw * 4,
+ 4096);
if (rpshader->bo == NULL) {
return -ENOMEM;
}
- radeon_bo_map(rscreen->rw, rpshader->bo);
- memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
- radeon_bo_unmap(rscreen->rw, rpshader->bo);
+ data = radeon_ws_bo_map(rscreen->rw, rpshader->bo);
+ memcpy(data, rshader->bc.bytecode, rshader->bc.ndw * 4);
+ radeon_ws_bo_unmap(rscreen->rw, rpshader->bo);
/* build state */
rshader->flat_shade = rctx->flat_shade;
switch (rshader->processor_type) {
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 5a4a72d64f..5d6236206f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -613,7 +613,7 @@ static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
rtex = (struct r600_resource_texture*)surf->texture;
rbuffer = &rtex->resource;
/* just need to the bo to the flush list */
- flush->bo[i] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], rbuffer->bo);
flush->placement[i] = RADEON_GEM_DOMAIN_VRAM;
}
flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs;
@@ -636,7 +636,7 @@ static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
rtex = (struct r600_resource_texture*)surf->texture;
rbuffer = &rtex->resource;
/* just need to the bo to the flush list */
- flush->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &flush->bo[0], rbuffer->bo);
flush->placement[0] = RADEON_GEM_DOMAIN_VRAM;
flush->nbo = 1;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 80cfa36ac0..4fa8cf4709 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -120,7 +120,8 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
/* FIXME alignment 4096 enought ? too much ? */
resource->domain = r600_domain_from_usage(resource->base.b.bind);
- resource->bo = radeon_bo(radeon, 0, rtex->size, 4096, NULL);
+ resource->size = rtex->size;
+ resource->bo = radeon_ws_bo(radeon, rtex->size, 4096);
if (resource->bo == NULL) {
FREE(rtex);
return NULL;
@@ -149,10 +150,10 @@ static void r600_texture_destroy(struct pipe_screen *screen,
struct radeon *radeon = (struct radeon *)screen->winsys;
if (resource->bo) {
- radeon_bo_decref(radeon, resource->bo);
+ radeon_ws_bo_reference(radeon, &resource->bo, NULL);
}
if (rtex->uncompressed) {
- radeon_bo_decref(radeon, rtex->uncompressed);
+ radeon_ws_bo_reference(radeon, &rtex->uncompressed, NULL);
}
r600_texture_destroy_state(ptex);
FREE(rtex);
@@ -197,7 +198,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
struct radeon *rw = (struct radeon*)screen->winsys;
struct r600_resource_texture *rtex;
struct r600_resource *resource;
- struct radeon_bo *bo = NULL;
+ struct radeon_ws_bo *bo = NULL;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
@@ -208,7 +209,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
if (rtex == NULL)
return NULL;
- bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
+ bo = radeon_ws_bo_handle(rw, whandle->handle);
if (bo == NULL) {
FREE(rtex);
return NULL;
@@ -316,7 +317,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
enum pipe_format format = transfer->resource->format;
struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
struct r600_resource_texture *rtex;
@@ -343,12 +344,12 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
- if (radeon_bo_map(radeon, bo)) {
+ map = radeon_ws_bo_map(radeon, bo);
+ if (!map) {
return NULL;
}
- radeon_bo_wait(radeon, bo);
+ radeon_ws_bo_wait(radeon, bo);
- map = bo->data;
return map + offset;
}
@@ -358,7 +359,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
struct r600_resource_texture *rtex;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
if (rtransfer->linear_texture) {
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
@@ -370,7 +371,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
bo = ((struct r600_resource *)transfer->resource)->bo;
}
}
- radeon_bo_unmap(radeon, bo);
+ radeon_ws_bo_unmap(radeon, bo);
}
struct u_resource_vtbl r600_texture_vtbl =
@@ -654,7 +655,7 @@ int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_textu
/* allocate uncompressed texture */
if (rtexture->uncompressed == NULL) {
- rtexture->uncompressed = radeon_bo(rscreen->rw, 0, rtexture->size, 4096, NULL);
+ rtexture->uncompressed = radeon_ws_bo(rscreen->rw, rtexture->size, 4096);
if (rtexture->uncompressed == NULL) {
return -ENOMEM;
}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 12e8b993c8..be28ad19ff 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -87,24 +87,17 @@ enum {
enum radeon_family radeon_get_family(struct radeon *rw);
-/*
- * radeon object functions
- */
-struct radeon_bo {
- unsigned refcount;
- unsigned handle;
- unsigned size;
- unsigned alignment;
- unsigned map_count;
- void *data;
-};
-struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
- unsigned size, unsigned alignment, void *ptr);
-int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
-void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
-struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
-struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
-int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
+/* lowlevel WS bo */
+struct radeon_ws_bo;
+struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
+ unsigned size, unsigned alignment);
+struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
+ unsigned handle);
+void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo);
+void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
+void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
+ struct radeon_ws_bo *src);
+int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *bo);
struct radeon_stype_info;
/*
@@ -124,7 +117,7 @@ struct radeon_state {
u32 pm4_crc;
u32 pm4[128];
unsigned nbo;
- struct radeon_bo *bo[4];
+ struct radeon_ws_bo *bo[4];
unsigned nreloc;
unsigned reloc_pm4_id[8];
unsigned reloc_bo_id[8];
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-23 22:24:58 +0000