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-rw-r--r--src/gallium/drivers/r600/r600_blit.c61
-rw-r--r--src/gallium/drivers/r600/r600_context.c9
-rw-r--r--src/gallium/drivers/r600/r600_draw.c46
-rw-r--r--src/gallium/drivers/r600/r600_query.c6
-rw-r--r--src/gallium/drivers/r600/r600_shader.c7
-rw-r--r--src/gallium/drivers/r600/r600_state.c78
-rw-r--r--src/gallium/drivers/r600/r600_texture.c18
-rw-r--r--src/gallium/drivers/r600/radeon.h669
8 files changed, 496 insertions, 398 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index d3b722c82f..72175fbbd5 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
unsigned srcx, unsigned srcy, unsigned srcz,
unsigned width, unsigned height)
{
- util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
+ util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
src, subsrc, srcx, srcy, srcz, width, height);
}
@@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
memcpy(bo->data, vbo, 128);
radeon_bo_unmap(rscreen->rw, bo);
- rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0);
+ rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return -ENOMEM;
@@ -199,35 +199,33 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
/* set states (most default value are 0 and struct already
* initialized to 0, thus avoid resetting them)
*/
- rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080;
- rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
- rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return -ENOMEM;
}
bstates->vs_resource0 = rstate;
- rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1);
+ rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
if (rstate == NULL) {
return -ENOMEM;
}
- rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010;
- rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070;
- rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
- rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
+ rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -305,7 +303,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
- rstate = radeon_state(rscreen->rw, R600_VS_SHADER);
+ rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
@@ -323,8 +321,6 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
- rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
- rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@@ -378,7 +374,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
- rstate = radeon_state(rscreen->rw, R600_PS_SHADER);
+ rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
@@ -395,7 +391,6 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@@ -408,7 +403,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_VGT);
+ rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
if (rstate == NULL)
return NULL;
@@ -430,7 +425,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_DRAW);
+ rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
if (rstate == NULL)
return NULL;
@@ -453,7 +448,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id);
+ rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
if (rstate == NULL)
return NULL;
@@ -476,7 +471,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
+ rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
@@ -505,7 +500,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_DSA);
+ rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
if (rstate == NULL)
return NULL;
@@ -529,7 +524,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_BLEND);
+ rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
if (rstate == NULL)
return NULL;
@@ -548,7 +543,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
+ rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
if (rstate == NULL)
return NULL;
@@ -791,10 +786,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
r600_queries_suspend(ctx);
/* schedule draw*/
- r = radeon_ctx_set_draw(rctx->ctx, draw);
+ r = radeon_ctx_set_draw_new(rctx->ctx, draw);
if (r == -EBUSY) {
r600_flush(ctx, 0, NULL);
- r = radeon_ctx_set_draw(rctx->ctx, draw);
+ r = radeon_ctx_set_draw_new(rctx->ctx, draw);
}
if (r) {
goto out;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 790a85110b..9af28356c5 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -53,10 +53,12 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
/* suspend queries */
r600_queries_suspend(ctx);
+ if (radeon_ctx_pm4(rctx->ctx))
+ goto out;
/* FIXME dumping should be removed once shader support instructions
* without throwing bad code
*/
- if (!rctx->ctx->id)
+ if (!rctx->ctx->cpm4)
goto out;
sprintf(dname, "gallium-%08d.bof", dc);
if (dc < 2) {
@@ -71,7 +73,8 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
}
dc++;
out:
- radeon_ctx_clear(rctx->ctx);
+ rctx->ctx = radeon_ctx_decref(rctx->ctx);
+ rctx->ctx = radeon_ctx(rscreen->rw);
/* resume queries */
r600_queries_resume(ctx);
}
@@ -215,7 +218,7 @@ static void r600_init_config(struct r600_context *rctx)
num_es_stack_entries = 0;
break;
}
- rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG);
+ rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
switch (family) {
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index a1a392ad2b..1eb868c4c7 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -101,21 +101,19 @@ static int r600_draw_common(struct r600_draw *draw)
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
- vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
+ vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
if (vs_resource == NULL)
return -ENOMEM;
vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
vs_resource->nbo = 1;
- vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
- vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
S_038008_DATA_FORMAT(format);
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
- vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
r = radeon_draw_set_new(rctx->draw, vs_resource);
@@ -123,29 +121,22 @@ static int r600_draw_common(struct r600_draw *draw)
return r;
}
/* FIXME start need to change winsys */
+ draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+ if (draw->draw == NULL)
+ return -ENOMEM;
+ draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+ draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
if (draw->index_buffer) {
- draw->draw = radeon_state(rscreen->rw, R600_DRAW);
- if (draw->draw == NULL)
- return -ENOMEM;
- draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
- draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
rbuffer = (struct r600_resource*)draw->index_buffer;
draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw->nbo = 1;
- draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
- } else {
- draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
- if (draw->draw == NULL)
- return -ENOMEM;
- draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
- draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
}
r = radeon_draw_set_new(rctx->draw, draw->draw);
if (r)
return r;
- draw->vgt = radeon_state(rscreen->rw, R600_VGT);
+ draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
if (draw->vgt == NULL)
return -ENOMEM;
draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
@@ -154,18 +145,23 @@ static int r600_draw_common(struct r600_draw *draw)
draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+ draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+ draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+ draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+ draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
r = radeon_draw_set_new(rctx->draw, draw->vgt);
if (r)
return r;
/* FIXME */
- r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
+ r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
if (r == -EBUSY) {
r600_flush(draw->ctx, 0, NULL);
- r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
+ r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
}
if (r)
return r;
+ rctx->draw = radeon_draw_duplicate(rctx->draw);
return 0;
}
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 8b4fe8999f..5929606cd2 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -36,11 +36,10 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN);
+ rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
- rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -56,11 +55,10 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_QUERY_END);
+ rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
- rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 052b4971f3..ebcf19c12b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
unsigned i, tmp;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
- state = radeon_state(rscreen->rw, R600_VS_SHADER);
+ state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < 10; i++) {
@@ -152,8 +152,6 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->nbo = 2;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
- state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
- state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
return radeon_state_pm4(state);
}
@@ -168,7 +166,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rasterizer = &rctx->rasterizer->state.rasterizer;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
- state = radeon_state(rscreen->rw, R600_PS_SHADER);
+ state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < rshader->ninput; i++) {
@@ -208,7 +206,6 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
rpshader->rstate->nbo = 1;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
return radeon_state_pm4(state);
}
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e75575da79..b5e5346163 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -283,17 +283,19 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_context *rctx = r600_context(ctx);
- unsigned nconstant = 0, i, id;
+ unsigned nconstant = 0, i, type, id;
struct radeon_state *rstate;
struct pipe_transfer *transfer;
u32 *ptr;
switch (shader) {
case PIPE_SHADER_VERTEX:
- id = R600_VS_CONSTANT0;
+ id = R600_VS_CONSTANT;
+ type = R600_VS_CONSTANT_TYPE;
break;
case PIPE_SHADER_FRAGMENT:
- id = R600_PS_CONSTANT0;
+ id = R600_PS_CONSTANT;
+ type = R600_PS_CONSTANT_TYPE;
break;
default:
R600_ERR("unsupported %d\n", shader);
@@ -305,7 +307,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
if (ptr == NULL)
return;
for (i = 0; i < nconstant; i++) {
- rstate = radeon_state(rscreen->rw, id + i);
+ rstate = radeon_state(rscreen->rw, type, id + i);
if (rstate == NULL)
return;
rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
@@ -620,7 +622,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
const struct pipe_blend_state *state = &rctx->blend->state.blend;
int i;
- rstate = radeon_state(rscreen->rw, R600_BLEND);
+ rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
if (rstate == NULL)
return NULL;
rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
@@ -679,14 +681,14 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
struct radeon_state *rstate;
const struct pipe_clip_state *state = &rctx->clip->state.clip;
- rstate = radeon_state(rscreen->rw, R600_UCP0 + clip);
+ rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
if (rstate == NULL)
return NULL;
- rstate->states[R600_UCP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
- rstate->states[R600_UCP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
- rstate->states[R600_UCP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
- rstate->states[R600_UCP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
+ rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
+ rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
+ rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
+ rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@@ -709,7 +711,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
unsigned format, swap, ntype;
const struct util_format_description *desc;
- rstate = radeon_state(rscreen->rw, R600_CB0 + cb);
+ rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
if (rstate == NULL)
return NULL;
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@@ -720,9 +722,6 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
- rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
- rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
- rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
rstate->nbo = 3;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
@@ -741,14 +740,14 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
S_0280A0_SOURCE_FORMAT(1) |
S_0280A0_NUMBER_TYPE(ntype);
- rstate->states[R600_CB__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
- rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
- rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+ rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
+ rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+ rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice);
- rstate->states[R600_CB__CB_COLOR0_VIEW] = 0x00000000;
- rstate->states[R600_CB__CB_COLOR0_FRAG] = 0x00000000;
- rstate->states[R600_CB__CB_COLOR0_TILE] = 0x00000000;
- rstate->states[R600_CB__CB_COLOR0_MASK] = 0x00000000;
+ rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
+ rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
+ rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
+ rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return NULL;
@@ -769,7 +768,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
if (state->zsbuf == NULL)
return NULL;
- rstate = radeon_state(rscreen->rw, R600_DB);
+ rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
if (rstate == NULL)
return NULL;
@@ -783,7 +782,6 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
- rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
level = state->zsbuf->level;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
@@ -846,7 +844,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
prov_vtx = 0;
rctx->flat_shade = state->flatshade;
- rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
+ rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
@@ -927,7 +925,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
}
tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
- rstate = radeon_state(rscreen->rw, R600_SCISSOR);
+ rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
if (rstate == NULL)
return NULL;
rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
@@ -962,7 +960,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
+ rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
@@ -995,7 +993,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
if (rctx->ps_shader == NULL) {
return NULL;
}
- rstate = radeon_state(rscreen->rw, R600_DSA);
+ rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
if (rstate == NULL)
return NULL;
@@ -1147,7 +1145,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, id);
+ rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
if (rstate == NULL)
return NULL;
rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
@@ -1248,7 +1246,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
R600_ERR("unknow format %d\n", view->texture->format);
return NULL;
}
- rstate = radeon_state(rscreen->rw, id);
+ rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
if (rstate == NULL) {
return NULL;
}
@@ -1270,36 +1268,34 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
- rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
- rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
pitch = (tmp->pitch[0] / tmp->bpt);
pitch = (pitch + 0x7) & ~0x7;
/* FIXME properly handle first level != 0 */
- rstate->states[R600_RESOURCE__RESOURCE_WORD0] =
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
S_038000_DIM(r600_tex_dim(view->texture->target)) |
S_038000_TILE_MODE(array_mode) |
S_038000_TILE_TYPE(tile_type) |
S_038000_PITCH((pitch / 8) - 1) |
S_038000_TEX_WIDTH(view->texture->width0 - 1);
- rstate->states[R600_RESOURCE__RESOURCE_WORD1] =
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
S_038004_DATA_FORMAT(format);
- rstate->states[R600_RESOURCE__RESOURCE_WORD2] = tmp->offset[0] >> 8;
- rstate->states[R600_RESOURCE__RESOURCE_WORD3] = tmp->offset[1] >> 8;
- rstate->states[R600_RESOURCE__RESOURCE_WORD4] =
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
word4 |
S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
S_038010_REQUEST_SIZE(1) |
S_038010_BASE_LEVEL(view->first_level);
- rstate->states[R600_RESOURCE__RESOURCE_WORD5] =
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
S_038014_LAST_LEVEL(view->last_level) |
S_038014_BASE_ARRAY(0) |
S_038014_LAST_ARRAY(0);
- rstate->states[R600_RESOURCE__RESOURCE_WORD6] =
+ rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@@ -1346,7 +1342,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
target_mask |= (pbs->rt[0].colormask << (4 * i));
}
}
- rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
+ rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1423,7 +1419,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
if (rctx->ps_sampler[i]) {
rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
&rctx->ps_sampler[i]->state.sampler,
- R600_PS_SAMPLER0 + i);
+ R600_PS_SAMPLER + i);
}
}
rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
@@ -1431,7 +1427,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
if (rctx->ps_sampler_view[i]) {
rctx->hw_states.ps_resource[i] = r600_resource(ctx,
&rctx->ps_sampler_view[i]->state.sampler_view,
- R600_PS_RESOURCE0 + i);
+ R600_PS_RESOURCE + i);
}
}
rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 9dc0208eb1..fb84ed9cfe 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_SCISSOR);
+ rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
if (rstate == NULL)
return NULL;
@@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
unsigned format, swap, ntype;
const struct util_format_description *desc;
- rstate = radeon_state(rscreen->rw, R600_CB0);
+ rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
if (rstate == NULL)
return NULL;
rbuffer = &rtexture->resource;
@@ -742,16 +742,13 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
rstate->nbo = 3;
color_info = S_0280A0_SOURCE_FORMAT(1);
}
- rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
- rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
- rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_CLAMP(1) |
S_0280A0_NUMBER_TYPE(ntype);
- rstate->states[R600_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
- rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
- rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+ rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
+ rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+ rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice);
if (radeon_state_pm4(rstate)) {
@@ -769,7 +766,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
struct r600_resource *rbuffer;
unsigned pitch, slice, format;
- rstate = radeon_state(rscreen->rw, R600_DB);
+ rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
if (rstate == NULL)
return NULL;
rbuffer = &rtexture->resource;
@@ -787,7 +784,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
S_028000_SLICE_TILE_MAX(slice);
- rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
@@ -819,7 +815,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
{
struct radeon_state *rstate;
- rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
+ rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 777fe3e792..b2cc74f696 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -104,18 +104,26 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
struct radeon_state {
struct radeon *radeon;
unsigned refcount;
+ unsigned type;
unsigned id;
+ unsigned nstates;
+ u32 *states;
+ unsigned npm4;
unsigned cpm4;
- u32 states[128];
u32 pm4_crc;
+ u32 *pm4;
+ u32 nimmd;
+ u32 *immd;
unsigned nbo;
struct radeon_bo *bo[4];
- unsigned reloc_pm4_id[4];
+ unsigned nreloc;
+ unsigned reloc_pm4_id[8];
+ unsigned reloc_bo_id[8];
u32 placement[8];
unsigned bo_dirty[4];
};
-struct radeon_state *radeon_state(struct radeon *radeon, u32 id);
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
struct radeon_state *radeon_state_incref(struct radeon_state *state);
struct radeon_state *radeon_state_decref(struct radeon_state *state);
int radeon_state_pm4(struct radeon_state *state);
@@ -139,6 +147,16 @@ int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
int radeon_draw_check(struct radeon_draw *draw);
+struct radeon_ctx *radeon_ctx(struct radeon *radeon);
+struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
+struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_pm4(struct radeon_ctx *ctx);
+int radeon_ctx_submit(struct radeon_ctx *ctx);
+void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+
/*
* radeon context functions
*/
@@ -151,216 +169,261 @@ struct radeon_cs_reloc {
};
#pragma pack()
-struct radeon_ctx_bo {
- struct radeon_bo *bo;
- u32 bo_flushed;
- unsigned state_id;
-};
-
struct radeon_ctx {
int refcount;
struct radeon *radeon;
u32 *pm4;
- int npm4;
+ u32 cpm4;
+ u32 draw_cpm4;
unsigned id;
+ unsigned next_id;
unsigned nreloc;
- unsigned max_reloc;
struct radeon_cs_reloc *reloc;
unsigned nbo;
- struct radeon_ctx_bo *bo;
- unsigned max_bo;
- u32 *state_crc32;
+ struct radeon_bo **bo;
+ unsigned ndraw;
+ struct radeon_draw *cdraw;
+ struct radeon_draw **draw;
+ unsigned nstate;
+ struct radeon_state **state;
};
-struct radeon_ctx *radeon_ctx(struct radeon *radeon);
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
-void radeon_ctx_clear(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-int radeon_ctx_pm4(struct radeon_ctx *ctx);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
-
-
/*
* R600/R700
*/
-#define R600_CONFIG 0
-#define R600_CB_CNTL 1
-#define R600_RASTERIZER 2
-#define R600_VIEWPORT 3
-#define R600_SCISSOR 4
-#define R600_BLEND 5
-#define R600_DSA 6
-#define R600_VGT 7
-#define R600_QUERY_BEGIN 8
-#define R600_QUERY_END 9
-#define R600_VS_SHADER 10
-#define R600_PS_SHADER 11
-#define R600_DB 12
-#define R600_CB0 13
-#define R600_UCP0 21
-#define R600_PS_RESOURCE0 27
-#define R600_VS_RESOURCE0 187
-#define R600_FS_RESOURCE0 347
-#define R600_GS_RESOURCE0 363
-#define R600_PS_CONSTANT0 523
-#define R600_VS_CONSTANT0 779
-#define R600_PS_SAMPLER0 1035
-#define R600_VS_SAMPLER0 1053
-#define R600_GS_SAMPLER0 1071
-#define R600_PS_SAMPLER_BORDER0 1089
-#define R600_VS_SAMPLER_BORDER0 1107
-#define R600_GS_SAMPLER_BORDER0 1125
-#define R600_DRAW_AUTO 1143
-#define R600_DRAW 1144
-#define R600_NSTATE 1145
+
+#define R600_NSTATE 1288
+#define R600_NTYPE 35
+
+#define R600_CONFIG 0
+#define R600_CONFIG_TYPE 0
+#define R600_CB_CNTL 1
+#define R600_CB_CNTL_TYPE 1
+#define R600_RASTERIZER 2
+#define R600_RASTERIZER_TYPE 2
+#define R600_VIEWPORT 3
+#define R600_VIEWPORT_TYPE 3
+#define R600_SCISSOR 4
+#define R600_SCISSOR_TYPE 4
+#define R600_BLEND 5
+#define R600_BLEND_TYPE 5
+#define R600_DSA 6
+#define R600_DSA_TYPE 6
+#define R600_VS_SHADER 7
+#define R600_VS_SHADER_TYPE 7
+#define R600_PS_SHADER 8
+#define R600_PS_SHADER_TYPE 8
+#define R600_PS_CONSTANT 9
+#define R600_PS_CONSTANT_TYPE 9
+#define R600_VS_CONSTANT 265
+#define R600_VS_CONSTANT_TYPE 10
+#define R600_PS_RESOURCE 521
+#define R600_PS_RESOURCE_TYPE 11
+#define R600_VS_RESOURCE 681
+#define R600_VS_RESOURCE_TYPE 12
+#define R600_FS_RESOURCE 841
+#define R600_FS_RESOURCE_TYPE 13
+#define R600_GS_RESOURCE 1001
+#define R600_GS_RESOURCE_TYPE 14
+#define R600_PS_SAMPLER 1161
+#define R600_PS_SAMPLER_TYPE 15
+#define R600_VS_SAMPLER 1179
+#define R600_VS_SAMPLER_TYPE 16
+#define R600_GS_SAMPLER 1197
+#define R600_GS_SAMPLER_TYPE 17
+#define R600_PS_SAMPLER_BORDER 1215
+#define R600_PS_SAMPLER_BORDER_TYPE 18
+#define R600_VS_SAMPLER_BORDER 1233
+#define R600_VS_SAMPLER_BORDER_TYPE 19
+#define R600_GS_SAMPLER_BORDER 1251
+#define R600_GS_SAMPLER_BORDER_TYPE 20
+#define R600_CB0 1269
+#define R600_CB0_TYPE 21
+#define R600_CB1 1270
+#define R600_CB1_TYPE 22
+#define R600_CB2 1271
+#define R600_CB2_TYPE 23
+#define R600_CB3 1272
+#define R600_CB3_TYPE 24
+#define R600_CB4 1273
+#define R600_CB4_TYPE 25
+#define R600_CB5 1274
+#define R600_CB5_TYPE 26
+#define R600_CB6 1275
+#define R600_CB6_TYPE 27
+#define R600_CB7 1276
+#define R600_CB7_TYPE 28
+#define R600_QUERY_BEGIN 1277
+#define R600_QUERY_BEGIN_TYPE 29
+#define R600_QUERY_END 1278
+#define R600_QUERY_END_TYPE 30
+#define R600_DB 1279
+#define R600_DB_TYPE 31
+#define R600_CLIP 1280
+#define R600_CLIP_TYPE 32
+#define R600_VGT 1286
+#define R600_VGT_TYPE 33
+#define R600_DRAW 1287
+#define R600_DRAW_TYPE 34
/* R600_CONFIG */
-#define R600_CONFIG__SQ_CONFIG 0
+#define R600_CONFIG__SQ_CONFIG 0
#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1
#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2
#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3
#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4
#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5
-#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 8
-#define R600_CONFIG__TA_CNTL_AUX 11
-#define R600_CONFIG__VC_ENHANCE 14
-#define R600_CONFIG__DB_DEBUG 17
-#define R600_CONFIG__DB_WATERMARKS 20
-#define R600_CONFIG__SX_MISC 23
-#define R600_CONFIG__SPI_THREAD_GROUPING 26
-#define R600_CONFIG__CB_SHADER_CONTROL 29
-#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 32
-#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 33
-#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 34
-#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 35
-#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 36
-#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 37
-#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 38
-#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 39
-#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 40
-#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 43
-#define R600_CONFIG__VGT_HOS_CNTL 44
-#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 45
-#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 46
-#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 47
-#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 48
-#define R600_CONFIG__VGT_GROUP_FIRST_DECR 49
-#define R600_CONFIG__VGT_GROUP_DECR 50
-#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 51
-#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 52
-#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 53
-#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 54
-#define R600_CONFIG__VGT_GS_MODE 55
-#define R600_CONFIG__PA_SC_MODE_CNTL 58
-#define R600_CONFIG__VGT_STRMOUT_EN 61
-#define R600_CONFIG__VGT_REUSE_OFF 62
-#define R600_CONFIG__VGT_VTX_CNT_EN 63
-#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 66
+#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6
+#define R600_CONFIG__TA_CNTL_AUX 7
+#define R600_CONFIG__VC_ENHANCE 8
+#define R600_CONFIG__DB_DEBUG 9
+#define R600_CONFIG__DB_WATERMARKS 10
+#define R600_CONFIG__SX_MISC 11
+#define R600_CONFIG__SPI_THREAD_GROUPING 12
+#define R600_CONFIG__CB_SHADER_CONTROL 13
+#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14
+#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15
+#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16
+#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17
+#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18
+#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19
+#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20
+#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21
+#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22
+#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23
+#define R600_CONFIG__VGT_HOS_CNTL 24
+#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25
+#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26
+#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27
+#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28
+#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29
+#define R600_CONFIG__VGT_GROUP_DECR 30
+#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31
+#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32
+#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33
+#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34
+#define R600_CONFIG__VGT_GS_MODE 35
+#define R600_CONFIG__PA_SC_MODE_CNTL 36
+#define R600_CONFIG__VGT_STRMOUT_EN 37
+#define R600_CONFIG__VGT_REUSE_OFF 38
+#define R600_CONFIG__VGT_VTX_CNT_EN 39
+#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40
+#define R600_CONFIG_SIZE 41
+#define R600_CONFIG_PM4 128
/* R600_CB_CNTL */
-#define R600_CB_CNTL__CB_CLEAR_RED 0
-#define R600_CB_CNTL__CB_CLEAR_GREEN 1
-#define R600_CB_CNTL__CB_CLEAR_BLUE 2
-#define R600_CB_CNTL__CB_CLEAR_ALPHA 3
-#define R600_CB_CNTL__CB_SHADER_MASK 6
-#define R600_CB_CNTL__CB_TARGET_MASK 7
-#define R600_CB_CNTL__CB_FOG_RED 10
-#define R600_CB_CNTL__CB_FOG_GREEN 11
-#define R600_CB_CNTL__CB_FOG_BLUE 12
-#define R600_CB_CNTL__CB_COLOR_CONTROL 15
-#define R600_CB_CNTL__PA_SC_AA_CONFIG 18
-#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 21
-#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 22
-#define R600_CB_CNTL__CB_CLRCMP_CONTROL 25
-#define R600_CB_CNTL__CB_CLRCMP_SRC 26
-#define R600_CB_CNTL__CB_CLRCMP_DST 27
-#define R600_CB_CNTL__CB_CLRCMP_MSK 28
-#define R600_CB_CNTL__PA_SC_AA_MASK 31
+#define R600_CB_CNTL__CB_CLEAR_RED 0
+#define R600_CB_CNTL__CB_CLEAR_GREEN 1
+#define R600_CB_CNTL__CB_CLEAR_BLUE 2
+#define R600_CB_CNTL__CB_CLEAR_ALPHA 3
+#define R600_CB_CNTL__CB_SHADER_MASK 4
+#define R600_CB_CNTL__CB_TARGET_MASK 5
+#define R600_CB_CNTL__CB_FOG_RED 6
+#define R600_CB_CNTL__CB_FOG_GREEN 7
+#define R600_CB_CNTL__CB_FOG_BLUE 8
+#define R600_CB_CNTL__CB_COLOR_CONTROL 9
+#define R600_CB_CNTL__PA_SC_AA_CONFIG 10
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12
+#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13
+#define R600_CB_CNTL__CB_CLRCMP_SRC 14
+#define R600_CB_CNTL__CB_CLRCMP_DST 15
+#define R600_CB_CNTL__CB_CLRCMP_MSK 16
+#define R600_CB_CNTL__PA_SC_AA_MASK 17
+#define R600_CB_CNTL_SIZE 18
+#define R600_CB_CNTL_PM4 128
/* R600_RASTERIZER */
#define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0
-#define R600_RASTERIZER__PA_CL_CLIP_CNTL 3
-#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 4
-#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 7
-#define R600_RASTERIZER__PA_CL_NANINF_CNTL 8
-#define R600_RASTERIZER__PA_SU_POINT_SIZE 11
-#define R600_RASTERIZER__PA_SU_POINT_MINMAX 12
-#define R600_RASTERIZER__PA_SU_LINE_CNTL 13
-#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 14
-#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 17
-#define R600_RASTERIZER__PA_SC_LINE_CNTL 20
-#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 23
-#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 24
-#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 25
-#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 26
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 29
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 30
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 31
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 32
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 33
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 34
+#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1
+#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2
+#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3
+#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4
+#define R600_RASTERIZER__PA_SU_POINT_SIZE 5
+#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6
+#define R600_RASTERIZER__PA_SU_LINE_CNTL 7
+#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8
+#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9
+#define R600_RASTERIZER__PA_SC_LINE_CNTL 10
+#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11
+#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12
+#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13
+#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20
+#define R600_RASTERIZER_SIZE 21
+#define R600_RASTERIZER_PM4 128
/* R600_VIEWPORT */
#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0
#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1
-#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 4
-#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 7
-#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 10
-#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 13
-#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 16
-#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 19
-#define R600_VIEWPORT__PA_CL_VTE_CNTL 22
+#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2
+#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3
+#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4
+#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5
+#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6
+#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7
+#define R600_VIEWPORT__PA_CL_VTE_CNTL 8
+#define R600_VIEWPORT_SIZE 9
+#define R600_VIEWPORT_PM4 128
/* R600_SCISSOR */
#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0
#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1
-#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 4
-#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 5
-#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 6
-#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 7
-#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 8
-#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 9
-#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 10
-#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 11
-#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 12
-#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 13
-#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 14
-#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 15
-#define R600_SCISSOR__PA_SC_EDGERULE 16
-#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 19
-#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 20
-#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 23
-#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 24
+#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4
+#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13
+#define R600_SCISSOR__PA_SC_EDGERULE 14
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18
+#define R600_SCISSOR_SIZE 19
+#define R600_SCISSOR_PM4 128
/* R600_BLEND */
-#define R600_BLEND__CB_BLEND_RED 0
-#define R600_BLEND__CB_BLEND_GREEN 1
-#define R600_BLEND__CB_BLEND_BLUE 2
-#define R600_BLEND__CB_BLEND_ALPHA 3
-#define R600_BLEND__CB_BLEND0_CONTROL 6
-#define R600_BLEND__CB_BLEND1_CONTROL 7
-#define R600_BLEND__CB_BLEND2_CONTROL 8
-#define R600_BLEND__CB_BLEND3_CONTROL 9
-#define R600_BLEND__CB_BLEND4_CONTROL 10
-#define R600_BLEND__CB_BLEND5_CONTROL 11
-#define R600_BLEND__CB_BLEND6_CONTROL 12
-#define R600_BLEND__CB_BLEND7_CONTROL 13
-#define R600_BLEND__CB_BLEND_CONTROL 16
+#define R600_BLEND__CB_BLEND_RED 0
+#define R600_BLEND__CB_BLEND_GREEN 1
+#define R600_BLEND__CB_BLEND_BLUE 2
+#define R600_BLEND__CB_BLEND_ALPHA 3
+#define R600_BLEND__CB_BLEND0_CONTROL 4
+#define R600_BLEND__CB_BLEND1_CONTROL 5
+#define R600_BLEND__CB_BLEND2_CONTROL 6
+#define R600_BLEND__CB_BLEND3_CONTROL 7
+#define R600_BLEND__CB_BLEND4_CONTROL 8
+#define R600_BLEND__CB_BLEND5_CONTROL 9
+#define R600_BLEND__CB_BLEND6_CONTROL 10
+#define R600_BLEND__CB_BLEND7_CONTROL 11
+#define R600_BLEND__CB_BLEND_CONTROL 12
+#define R600_BLEND_SIZE 13
+#define R600_BLEND_PM4 128
/* R600_DSA */
-#define R600_DSA__DB_STENCIL_CLEAR 0
-#define R600_DSA__DB_DEPTH_CLEAR 1
-#define R600_DSA__SX_ALPHA_TEST_CONTROL 4
-#define R600_DSA__DB_STENCILREFMASK 7
-#define R600_DSA__DB_STENCILREFMASK_BF 8
-#define R600_DSA__SX_ALPHA_REF 9
-#define R600_DSA__SPI_FOG_FUNC_SCALE 12
-#define R600_DSA__SPI_FOG_FUNC_BIAS 13
-#define R600_DSA__SPI_FOG_CNTL 16
-#define R600_DSA__DB_DEPTH_CONTROL 19
-#define R600_DSA__DB_SHADER_CONTROL 22
-#define R600_DSA__DB_RENDER_CONTROL 25
-#define R600_DSA__DB_RENDER_OVERRIDE 26
-#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 29
-#define R600_DSA__DB_PRELOAD_CONTROL 30
-#define R600_DSA__DB_ALPHA_TO_MASK 33
+#define R600_DSA__DB_STENCIL_CLEAR 0
+#define R600_DSA__DB_DEPTH_CLEAR 1
+#define R600_DSA__SX_ALPHA_TEST_CONTROL 2
+#define R600_DSA__DB_STENCILREFMASK 3
+#define R600_DSA__DB_STENCILREFMASK_BF 4
+#define R600_DSA__SX_ALPHA_REF 5
+#define R600_DSA__SPI_FOG_FUNC_SCALE 6
+#define R600_DSA__SPI_FOG_FUNC_BIAS 7
+#define R600_DSA__SPI_FOG_CNTL 8
+#define R600_DSA__DB_DEPTH_CONTROL 9
+#define R600_DSA__DB_SHADER_CONTROL 10
+#define R600_DSA__DB_RENDER_CONTROL 11
+#define R600_DSA__DB_RENDER_OVERRIDE 12
+#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13
+#define R600_DSA__DB_PRELOAD_CONTROL 14
+#define R600_DSA__DB_ALPHA_TO_MASK 15
+#define R600_DSA_SIZE 16
+#define R600_DSA_PM4 128
/* R600_VS_SHADER */
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1
@@ -394,25 +457,25 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31
-#define R600_VS_SHADER__SPI_VS_OUT_ID_0 34
-#define R600_VS_SHADER__SPI_VS_OUT_ID_1 35
-#define R600_VS_SHADER__SPI_VS_OUT_ID_2 36
-#define R600_VS_SHADER__SPI_VS_OUT_ID_3 37
-#define R600_VS_SHADER__SPI_VS_OUT_ID_4 38
-#define R600_VS_SHADER__SPI_VS_OUT_ID_5 39
-#define R600_VS_SHADER__SPI_VS_OUT_ID_6 40
-#define R600_VS_SHADER__SPI_VS_OUT_ID_7 41
-#define R600_VS_SHADER__SPI_VS_OUT_ID_8 42
-#define R600_VS_SHADER__SPI_VS_OUT_ID_9 43
-#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 46
-#define R600_VS_SHADER__SQ_PGM_START_VS 49
-#define R600_VS_SHADER__SQ_PGM_START_VS_BO_ID 51
-#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 54
-#define R600_VS_SHADER__SQ_PGM_START_FS 57
-#define R600_VS_SHADER__SQ_PGM_START_FS_BO_ID 59
-#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 62
-#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 65
-#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 68
+#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32
+#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33
+#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34
+#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35
+#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36
+#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37
+#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38
+#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39
+#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40
+#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41
+#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42
+#define R600_VS_SHADER__SQ_PGM_START_VS 43
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44
+#define R600_VS_SHADER__SQ_PGM_START_FS 45
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48
+#define R600_VS_SHADER_SIZE 49
+#define R600_VS_SHADER_PM4 128
/* R600_PS_SHADER */
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1
@@ -446,104 +509,158 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31
-#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 34
-#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 35
-#define R600_PS_SHADER__SPI_INPUT_Z 38
-#define R600_PS_SHADER__SQ_PGM_START_PS 41
-#define R600_PS_SHADER__SQ_PGM_START_PS_BO_ID 43
-#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 46
-#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 47
-#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 50
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33
+#define R600_PS_SHADER__SPI_INPUT_Z 34
+#define R600_PS_SHADER__SQ_PGM_START_PS 35
+#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36
+#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37
+#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38
+#define R600_PS_SHADER_SIZE 39
+#define R600_PS_SHADER_PM4 128
/* R600_PS_CONSTANT */
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3
+#define R600_PS_CONSTANT_SIZE 4
+#define R600_PS_CONSTANT_PM4 128
/* R600_VS_CONSTANT */
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3
+#define R600_VS_CONSTANT_SIZE 4
+#define R600_VS_CONSTANT_PM4 128
/* R600_PS_RESOURCE */
-#define R600_RESOURCE__RESOURCE_WORD0 0
-#define R600_RESOURCE__RESOURCE_WORD1 1
-#define R600_RESOURCE__RESOURCE_WORD2 2
-#define R600_RESOURCE__RESOURCE_WORD3 3
-#define R600_RESOURCE__RESOURCE_WORD4 4
-#define R600_RESOURCE__RESOURCE_WORD5 5
-#define R600_RESOURCE__RESOURCE_WORD6 6
-#define R600_RESOURCE__RESOURCE_BO0_ID 8
-#define R600_RESOURCE__RESOURCE_BO1_ID 10
+#define R600_PS_RESOURCE__RESOURCE0_WORD0 0
+#define R600_PS_RESOURCE__RESOURCE0_WORD1 1
+#define R600_PS_RESOURCE__RESOURCE0_WORD2 2
+#define R600_PS_RESOURCE__RESOURCE0_WORD3 3
+#define R600_PS_RESOURCE__RESOURCE0_WORD4 4
+#define R600_PS_RESOURCE__RESOURCE0_WORD5 5
+#define R600_PS_RESOURCE__RESOURCE0_WORD6 6
+#define R600_PS_RESOURCE_SIZE 7
+#define R600_PS_RESOURCE_PM4 128
+/* R600_VS_RESOURCE */
+#define R600_VS_RESOURCE__RESOURCE160_WORD0 0
+#define R600_VS_RESOURCE__RESOURCE160_WORD1 1
+#define R600_VS_RESOURCE__RESOURCE160_WORD2 2
+#define R600_VS_RESOURCE__RESOURCE160_WORD3 3
+#define R600_VS_RESOURCE__RESOURCE160_WORD4 4
+#define R600_VS_RESOURCE__RESOURCE160_WORD5 5
+#define R600_VS_RESOURCE__RESOURCE160_WORD6 6
+#define R600_VS_RESOURCE_SIZE 7
+#define R600_VS_RESOURCE_PM4 128
+/* R600_FS_RESOURCE */
+#define R600_FS_RESOURCE__RESOURCE320_WORD0 0
+#define R600_FS_RESOURCE__RESOURCE320_WORD1 1
+#define R600_FS_RESOURCE__RESOURCE320_WORD2 2
+#define R600_FS_RESOURCE__RESOURCE320_WORD3 3
+#define R600_FS_RESOURCE__RESOURCE320_WORD4 4
+#define R600_FS_RESOURCE__RESOURCE320_WORD5 5
+#define R600_FS_RESOURCE__RESOURCE320_WORD6 6
+#define R600_FS_RESOURCE_SIZE 7
+#define R600_FS_RESOURCE_PM4 128
+/* R600_GS_RESOURCE */
+#define R600_GS_RESOURCE__RESOURCE336_WORD0 0
+#define R600_GS_RESOURCE__RESOURCE336_WORD1 1
+#define R600_GS_RESOURCE__RESOURCE336_WORD2 2
+#define R600_GS_RESOURCE__RESOURCE336_WORD3 3
+#define R600_GS_RESOURCE__RESOURCE336_WORD4 4
+#define R600_GS_RESOURCE__RESOURCE336_WORD5 5
+#define R600_GS_RESOURCE__RESOURCE336_WORD6 6
+#define R600_GS_RESOURCE_SIZE 7
+#define R600_GS_RESOURCE_PM4 128
/* R600_PS_SAMPLER */
#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0
#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1
#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2
+#define R600_PS_SAMPLER_SIZE 3
+#define R600_PS_SAMPLER_PM4 128
/* R600_VS_SAMPLER */
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
+#define R600_VS_SAMPLER_SIZE 3
+#define R600_VS_SAMPLER_PM4 128
/* R600_GS_SAMPLER */
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
+#define R600_GS_SAMPLER_SIZE 3
+#define R600_GS_SAMPLER_PM4 128
/* R600_PS_SAMPLER_BORDER */
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
+#define R600_PS_SAMPLER_BORDER_SIZE 4
+#define R600_PS_SAMPLER_BORDER_PM4 128
/* R600_VS_SAMPLER_BORDER */
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
+#define R600_VS_SAMPLER_BORDER_SIZE 4
+#define R600_VS_SAMPLER_BORDER_PM4 128
/* R600_GS_SAMPLER_BORDER */
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
-/* R600_CB */
-#define R600_CB__CB_COLOR0_BASE 0
-#define R600_CB__CB_COLOR0_BASE_BO_ID 2
-#define R600_CB__CB_COLOR0_INFO 5
-#define R600_CB__CB_COLOR0_SIZE 8
-#define R600_CB__CB_COLOR0_VIEW 11
-#define R600_CB__CB_COLOR0_FRAG 14
-#define R600_CB__CB_COLOR0_FRAG_BO_ID 16
-#define R600_CB__CB_COLOR0_TILE 19
-#define R600_CB__CB_COLOR0_TILE_BO_ID 21
-#define R600_CB__CB_COLOR0_MASK 24
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
+#define R600_GS_SAMPLER_BORDER_SIZE 4
+#define R600_GS_SAMPLER_BORDER_PM4 128
+/* R600_CB0 */
+#define R600_CB0__CB_COLOR0_BASE 0
+#define R600_CB0__CB_COLOR0_INFO 1
+#define R600_CB0__CB_COLOR0_SIZE 2
+#define R600_CB0__CB_COLOR0_VIEW 3
+#define R600_CB0__CB_COLOR0_FRAG 4
+#define R600_CB0__CB_COLOR0_TILE 5
+#define R600_CB0__CB_COLOR0_MASK 6
+#define R600_CB0_SIZE 7
+#define R600_CB0_PM4 128
/* R600_DB */
-#define R600_DB__DB_DEPTH_BASE 0
-#define R600_DB__DB_DEPTH_BASE_BO_ID 2
-#define R600_DB__DB_DEPTH_SIZE 5
-#define R600_DB__DB_DEPTH_VIEW 6
-#define R600_DB__DB_DEPTH_INFO 9
-#define R600_DB__DB_HTILE_SURFACE 12
-#define R600_DB__DB_PREFETCH_LIMIT 15
+#define R600_DB__DB_DEPTH_BASE 0
+#define R600_DB__DB_DEPTH_SIZE 1
+#define R600_DB__DB_DEPTH_VIEW 2
+#define R600_DB__DB_DEPTH_INFO 3
+#define R600_DB__DB_HTILE_SURFACE 4
+#define R600_DB__DB_PREFETCH_LIMIT 5
+#define R600_DB_SIZE 6
+#define R600_DB_PM4 128
/* R600_VGT */
-#define R600_VGT__VGT_MAX_VTX_INDX 0
-#define R600_VGT__VGT_MIN_VTX_INDX 1
-#define R600_VGT__VGT_INDX_OFFSET 2
-#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 3
-#define R600_VGT__VGT_PRIMITIVE_TYPE 6
-#define R600_VGT__VGT_DMA_INDEX_TYPE 8
-#define R600_VGT__VGT_DMA_NUM_INSTANCES 10
-/* R600_DRAW_AUTO */
-#define R600_DRAW_AUTO__VGT_NUM_INDICES 0
-#define R600_DRAW_AUTO__VGT_DRAW_INITIATOR 1
+#define R600_VGT__VGT_PRIMITIVE_TYPE 0
+#define R600_VGT__VGT_MAX_VTX_INDX 1
+#define R600_VGT__VGT_MIN_VTX_INDX 2
+#define R600_VGT__VGT_INDX_OFFSET 3
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4
+#define R600_VGT__VGT_DMA_INDEX_TYPE 5
+#define R600_VGT__VGT_PRIMITIVEID_EN 6
+#define R600_VGT__VGT_DMA_NUM_INSTANCES 7
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8
+#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9
+#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10
+#define R600_VGT_SIZE 11
+#define R600_VGT_PM4 128
/* R600_DRAW */
-#define R600_DRAW__VGT_DMA_BASE 0
-#define R600_DRAW__VGT_DMA_BASE_HI 1
-#define R600_DRAW__VGT_NUM_INDICES 2
-#define R600_DRAW__VGT_DRAW_INITIATOR 3
-#define R600_DRAW__INDICES_BO_ID 5
-/* R600_UCP */
-#define R600_UCP__PA_CL_UCP_X_0 0
-#define R600_UCP__PA_CL_UCP_Y_0 1
-#define R600_UCP__PA_CL_UCP_Z_0 2
-#define R600_UCP__PA_CL_UCP_W_0 3
+#define R600_DRAW__VGT_NUM_INDICES 0
+#define R600_DRAW__VGT_DMA_BASE_HI 1
+#define R600_DRAW__VGT_DMA_BASE 2
+#define R600_DRAW__VGT_DRAW_INITIATOR 3
+#define R600_DRAW_SIZE 4
+#define R600_DRAW_PM4 128
+/* R600_CLIP */
+#define R600_CLIP__PA_CL_UCP_X_0 0
+#define R600_CLIP__PA_CL_UCP_Y_0 1
+#define R600_CLIP__PA_CL_UCP_Z_0 2
+#define R600_CLIP__PA_CL_UCP_W_0 3
+#define R600_CLIP_SIZE 4
+#define R600_CLIP_PM4 128
/* R600 QUERY BEGIN/END */
-#define R600_QUERY__OFFSET 0
-#define R600_QUERY__BO_ID 3
+#define R600_QUERY__OFFSET 0
+#define R600_QUERY_SIZE 1
+#define R600_QUERY_PM4 128
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 07:13:25 +0000