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-rw-r--r--src/gallium/winsys/r600/drm/eg_states.h27
-rw-r--r--src/gallium/winsys/r600/drm/r600.c36
-rw-r--r--src/gallium/winsys/r600/drm/r600_drm.c3
-rw-r--r--src/gallium/winsys/r600/drm/r600_priv.h1
-rw-r--r--src/gallium/winsys/r600/drm/r600_state.c14
-rw-r--r--src/gallium/winsys/r600/drm/r600_state2.c3
-rw-r--r--src/gallium/winsys/r600/drm/r600_states.h20
-rw-r--r--src/gallium/winsys/r600/drm/radeon.c36
-rw-r--r--src/gallium/winsys/r600/drm/radeon_bo_pb.c40
-rw-r--r--src/gallium/winsys/r600/drm/radeon_priv.h1
-rw-r--r--src/gallium/winsys/r600/drm/radeon_ws_bo.c11
11 files changed, 139 insertions, 53 deletions
diff --git a/src/gallium/winsys/r600/drm/eg_states.h b/src/gallium/winsys/r600/drm/eg_states.h
index c26ba6c6cd..518e05fefb 100644
--- a/src/gallium/winsys/r600/drm/eg_states.h
+++ b/src/gallium/winsys/r600/drm/eg_states.h
@@ -371,24 +371,27 @@ static const struct radeon_register EG_names_GS_SAMPLER[] = {
};
static const struct radeon_register EG_names_PS_SAMPLER_BORDER[] = {
- {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
- {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
- {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
- {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
+ {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_INDEX"},
+ {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
+ {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
+ {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
+ {0x0000A410, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
};
static const struct radeon_register EG_names_VS_SAMPLER_BORDER[] = {
- {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
- {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
- {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
- {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
+ {0x0000A414, 0, 0, "TD_VS_SAMPLER0_BORDER_INDEX"},
+ {0x0000A418, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
+ {0x0000A41C, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
+ {0x0000A420, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
+ {0x0000A424, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
};
static const struct radeon_register EG_names_GS_SAMPLER_BORDER[] = {
- {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
- {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
- {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
- {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
+ {0x0000A428, 0, 0, "TD_GS_SAMPLER0_BORDER_INDEX"},
+ {0x0000A42C, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
+ {0x0000A430, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
+ {0x0000A434, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
+ {0x0000A438, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
};
static const struct radeon_register EG_names_CB[] = {
diff --git a/src/gallium/winsys/r600/drm/r600.c b/src/gallium/winsys/r600/drm/r600.c
index af9b9187ab..fdcadffc53 100644
--- a/src/gallium/winsys/r600/drm/r600.c
+++ b/src/gallium/winsys/r600/drm/r600.c
@@ -32,6 +32,11 @@ enum radeon_family r600_get_family(struct radeon *r600)
return r600->family;
}
+enum chip_class r600_get_family_class(struct radeon *radeon)
+{
+ return radeon->chip_class;
+}
+
static int r600_get_device(struct radeon *r600)
{
struct drm_radeon_info info;
@@ -117,6 +122,37 @@ struct radeon *r600_new(int fd, unsigned device)
R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device);
break;
}
+
+ /* setup class */
+ switch (r600->family) {
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ r600->chip_class = R600;
+ break;
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ r600->chip_class = R700;
+ break;
+ case CHIP_CEDAR:
+ case CHIP_REDWOOD:
+ case CHIP_JUNIPER:
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ r600->chip_class = EVERGREEN;
+ break;
+ default:
+ R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device);
+ break;
+ }
+
return r600;
}
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index bbf53fcbdc..7a1a762f54 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -29,10 +29,7 @@
#include "util/u_inlines.h"
#include "util/u_debug.h"
#include "radeon_priv.h"
-#include "r600_screen.h"
-#include "r600_resource.h"
#include "r600_drm_public.h"
-#include "state_tracker/drm_driver.h"
struct radeon *r600_drm_winsys_create(int drmfd)
{
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 7a9025ad3c..d02562f17f 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -38,6 +38,7 @@ struct radeon {
int refcount;
unsigned device;
unsigned family;
+ enum chip_class chip_class;
};
struct radeon *r600_new(int fd, unsigned device);
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index b04885a85f..25dd8fe7d8 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -110,7 +110,7 @@ struct radeon_stype_info eg_stypes[] = {
{ R600_STATE_CBUF, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_CBUF), EG_SUB_VS(VS_CBUF) } },
{ R600_STATE_RESOURCE, 176, 0x20, r600_state_pm4_resource, { EG_SUB_PS(PS_RESOURCE), EG_SUB_VS(VS_RESOURCE), EG_SUB_GS(GS_RESOURCE), EG_SUB_FS(FS_RESOURCE)} },
{ R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER), EG_SUB_VS(VS_SAMPLER), EG_SUB_GS(GS_SAMPLER) } },
- { R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER_BORDER), EG_SUB_VS(VS_SAMPLER_BORDER), EG_SUB_GS(GS_SAMPLER_BORDER) } },
+ { R600_STATE_SAMPLER_BORDER, 18, 0, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER_BORDER), EG_SUB_VS(VS_SAMPLER_BORDER), EG_SUB_GS(GS_SAMPLER_BORDER) } },
{ R600_STATE_CB0, 11, 0x3c, r600_state_pm4_generic, EG_SUB_NONE(CB) },
{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, EG_SUB_NONE(VGT_EVENT) },
{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, EG_SUB_NONE(VGT_EVENT) },
@@ -304,6 +304,7 @@ static int r600_state_pm4_generic(struct radeon_state *state)
static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int bufs_are_cbs)
{
unsigned i, j, add, size;
+ uint32_t flags_cb;
state->nreloc = 0;
for (i = 0; i < state->nbo; i++) {
@@ -318,11 +319,12 @@ static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int
}
}
for (i = 0; i < state->nreloc; i++) {
+ flags_cb = flags;
size = (radeon_ws_bo_get_size(state->bo[state->reloc_bo_id[i]]) + 255) >> 8;
state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
if (bufs_are_cbs)
- flags |= S_0085F0_CB0_DEST_BASE_ENA(1 << i);
- state->pm4[state->cpm4++] = flags;
+ flags_cb |= S_0085F0_CB0_DEST_BASE_ENA(1 << i);
+ state->pm4[state->cpm4++] = flags_cb;
state->pm4[state->cpm4++] = size;
state->pm4[state->cpm4++] = 0x00000000;
state->pm4[state->cpm4++] = 0x0000000A;
@@ -335,12 +337,14 @@ static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int
static int r600_state_pm4_cb0(struct radeon_state *state)
{
int r;
-
+ uint32_t sbu;
r = r600_state_pm4_generic(state);
if (r)
return r;
+
+ sbu = (2 << (state->stype->stype - R600_STATE_CB0));
state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
- state->pm4[state->cpm4++] = 0x00000002;
+ state->pm4[state->cpm4++] = sbu;
return 0;
}
diff --git a/src/gallium/winsys/r600/drm/r600_state2.c b/src/gallium/winsys/r600/drm/r600_state2.c
index f6fba0a8dc..b3d618748d 100644
--- a/src/gallium/winsys/r600/drm/r600_state2.c
+++ b/src/gallium/winsys/r600/drm/r600_state2.c
@@ -28,6 +28,7 @@
#include <string.h>
#include <stdlib.h>
#include <assert.h>
+#include "xf86drm.h"
#include "r600.h"
#include "r600d.h"
#include "r600_priv.h"
@@ -983,7 +984,7 @@ void r600_context_dump_bof(struct r600_context *ctx, const char *file)
goto out_err;
device_id = bof_int32(ctx->radeon->device);
if (device_id == NULL)
- return;
+ goto out_err;
if (bof_object_set(root, "device_id", device_id))
goto out_err;
bof_decref(device_id);
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 50b25a9940..76e185ac03 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -31,7 +31,6 @@ static const struct radeon_register R600_names_CONFIG[] = {
{0x00009838, 0, 0, "DB_WATERMARKS"},
{0x00028350, 0, 0, "SX_MISC"},
{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
- {0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
@@ -80,6 +79,7 @@ static const struct radeon_register R600_names_CB_CNTL[] = {
{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
+ {0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
};
static const struct radeon_register R600_names_RASTERIZER[] = {
@@ -401,7 +401,7 @@ static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = {
static const struct radeon_register R600_names_CB0[] = {
{0x00028040, 1, 0, "CB_COLOR0_BASE"},
- {0x000280A0, 0, 0, "CB_COLOR0_INFO"},
+ {0x000280A0, 1, 0, "CB_COLOR0_INFO"},
{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
{0x000280E0, 1, 0, "CB_COLOR0_FRAG"},
@@ -411,7 +411,7 @@ static const struct radeon_register R600_names_CB0[] = {
static const struct radeon_register R600_names_CB1[] = {
{0x00028044, 1, 0, "CB_COLOR1_BASE"},
- {0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+ {0x000280A4, 1, 0, "CB_COLOR1_INFO"},
{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
{0x000280E4, 1, 0, "CB_COLOR1_FRAG"},
@@ -421,7 +421,7 @@ static const struct radeon_register R600_names_CB1[] = {
static const struct radeon_register R600_names_CB2[] = {
{0x00028048, 1, 0, "CB_COLOR2_BASE"},
- {0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+ {0x000280A8, 1, 0, "CB_COLOR2_INFO"},
{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
{0x000280E8, 1, 0, "CB_COLOR2_FRAG"},
@@ -431,7 +431,7 @@ static const struct radeon_register R600_names_CB2[] = {
static const struct radeon_register R600_names_CB3[] = {
{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
- {0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+ {0x000280AC, 1, 0, "CB_COLOR3_INFO"},
{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
{0x000280EC, 1, 0, "CB_COLOR3_FRAG"},
@@ -441,7 +441,7 @@ static const struct radeon_register R600_names_CB3[] = {
static const struct radeon_register R600_names_CB4[] = {
{0x00028050, 1, 0, "CB_COLOR4_BASE"},
- {0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+ {0x000280B0, 1, 0, "CB_COLOR4_INFO"},
{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
{0x000280F0, 1, 0, "CB_COLOR4_FRAG"},
@@ -451,7 +451,7 @@ static const struct radeon_register R600_names_CB4[] = {
static const struct radeon_register R600_names_CB5[] = {
{0x00028054, 1, 0, "CB_COLOR5_BASE"},
- {0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+ {0x000280B4, 1, 0, "CB_COLOR5_INFO"},
{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
{0x000280F4, 1, 0, "CB_COLOR5_FRAG"},
@@ -461,7 +461,7 @@ static const struct radeon_register R600_names_CB5[] = {
static const struct radeon_register R600_names_CB6[] = {
{0x00028058, 1, 0, "CB_COLOR6_BASE"},
- {0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+ {0x000280B8, 1, 0, "CB_COLOR6_INFO"},
{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
{0x000280F8, 1, 0, "CB_COLOR6_FRAG"},
@@ -471,7 +471,7 @@ static const struct radeon_register R600_names_CB6[] = {
static const struct radeon_register R600_names_CB7[] = {
{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
- {0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+ {0x000280BC, 1, 0, "CB_COLOR7_INFO"},
{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
{0x000280FC, 1, 0, "CB_COLOR7_FRAG"},
@@ -483,7 +483,7 @@ static const struct radeon_register R600_names_DB[] = {
{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
- {0x00028010, 0, 0, "DB_DEPTH_INFO"},
+ {0x00028010, 1, 0, "DB_DEPTH_INFO"},
{0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
};
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index f39d020559..c3d345fef9 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -30,6 +30,11 @@ enum radeon_family radeon_get_family(struct radeon *radeon)
return radeon->family;
}
+enum chip_class radeon_get_family_class(struct radeon *radeon)
+{
+ return radeon->chip_class;
+}
+
void radeon_set_mem_constant(struct radeon *radeon, boolean state)
{
radeon->use_mem_constant = state;
@@ -127,6 +132,37 @@ struct radeon *radeon_new(int fd, unsigned device)
break;
}
+ /* setup class */
+ switch (radeon->family) {
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ radeon->chip_class = R600;
+ break;
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ radeon->chip_class = R700;
+ break;
+ case CHIP_CEDAR:
+ case CHIP_REDWOOD:
+ case CHIP_JUNIPER:
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ radeon->chip_class = EVERGREEN;
+ break;
+ default:
+ fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+ __func__, radeon->device);
+ break;
+ }
+
radeon->mman = pb_malloc_bufmgr_create();
if (!radeon->mman)
return NULL;
diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
index 6cc0f93033..897938c2ca 100644
--- a/src/gallium/winsys/r600/drm/radeon_bo_pb.c
+++ b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
@@ -53,28 +53,45 @@ radeon_bo_pb_map_internal(struct pb_buffer *_buf,
unsigned flags, void *ctx)
{
struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
-
- if (flags & PB_USAGE_DONTBLOCK) {
- if (p_atomic_read(&buf->bo->reference.count) > 1)
+ struct pipe_context *pctx = ctx;
+
+ if (flags & PB_USAGE_UNSYNCHRONIZED) {
+ if (!buf->bo->data && radeon_bo_map(buf->mgr->radeon, buf->bo)) {
return NULL;
- }
- if (buf->bo->data != NULL) {
+ }
LIST_DELINIT(&buf->maplist);
return buf->bo->data;
}
+ if (p_atomic_read(&buf->bo->reference.count) > 1) {
+ if (flags & PB_USAGE_DONTBLOCK) {
+ return NULL;
+ }
+ if (ctx) {
+ pctx->flush(pctx, 0, NULL);
+ }
+ }
+
if (flags & PB_USAGE_DONTBLOCK) {
uint32_t domain;
if (radeon_bo_busy(buf->mgr->radeon, buf->bo, &domain))
return NULL;
}
- if (p_atomic_read(&buf->bo->reference.count) > 1 && ctx) {
- r600_flush_ctx(ctx);
- }
- if (radeon_bo_map(buf->mgr->radeon, buf->bo)) {
- return NULL;
+ if (buf->bo->data != NULL) {
+ if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) {
+ return NULL;
+ }
+ } else {
+ if (radeon_bo_map(buf->mgr->radeon, buf->bo)) {
+ return NULL;
+ }
+ if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) {
+ radeon_bo_unmap(buf->mgr->radeon, buf->bo);
+ return NULL;
+ }
}
+
LIST_DELINIT(&buf->maplist);
return buf->bo->data;
}
@@ -218,7 +235,8 @@ struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon)
void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr)
{
struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
- struct radeon_bo_pb *rpb, *t_rpb;
+ struct radeon_bo_pb *rpb = NULL;
+ struct radeon_bo_pb *t_rpb;
LIST_FOR_EACH_ENTRY_SAFE(rpb, t_rpb, &mgr->buffer_map_list, maplist) {
radeon_bo_unmap(mgr->radeon, rpb->bo);
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index c284f6aa7d..85aea89c70 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -83,6 +83,7 @@ struct radeon {
int refcount;
unsigned device;
unsigned family;
+ enum chip_class chip_class;
unsigned nstype;
struct radeon_stype_info *stype;
unsigned max_states;
diff --git a/src/gallium/winsys/r600/drm/radeon_ws_bo.c b/src/gallium/winsys/r600/drm/radeon_ws_bo.c
index 8114526a14..daaf2cbc51 100644
--- a/src/gallium/winsys/r600/drm/radeon_ws_bo.c
+++ b/src/gallium/winsys/r600/drm/radeon_ws_bo.c
@@ -72,17 +72,6 @@ void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
*dst = src;
}
-int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *pb_bo)
-{
- /* TODO */
- struct radeon_bo *bo;
- bo = radeon_bo_pb_get_bo(pb_bo->pb);
- if (!bo)
- return 0;
- radeon_bo_wait(radeon, bo);
- return 0;
-}
-
unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo)
{
struct radeon_bo *bo;
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-17 21:23:37 +0000