diff options
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r-- | src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c | 3 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/r600_state.c | 182 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/r600_states.h | 161 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/r600d.h | 3 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/radeon.c | 70 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/radeon_bo.c | 4 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/radeon_ctx.c | 218 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/radeon_draw.c | 108 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/radeon_priv.h | 37 | ||||
-rw-r--r-- | src/gallium/winsys/r600/drm/radeon_state.c | 145 | ||||
-rw-r--r-- | src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c | 8 |
11 files changed, 449 insertions, 490 deletions
diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c index 660dbd0c33..d4bf124ce6 100644 --- a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c +++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c @@ -19,7 +19,8 @@ nouveau_drm_destroy_winsys(struct pipe_winsys *s) { struct nouveau_winsys *nv_winsys = nouveau_winsys(s); struct nouveau_screen *nv_screen= nouveau_screen(nv_winsys->pscreen); - nouveau_device_close(&nv_screen->device); + if (nv_screen) + nouveau_device_close(&nv_screen->device); FREE(nv_winsys); } diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c index d17d6e7954..71d65f0fea 100644 --- a/src/gallium/winsys/r600/drm/r600_state.c +++ b/src/gallium/winsys/r600/drm/r600_state.c @@ -30,6 +30,8 @@ #include "radeon_priv.h" #include "r600d.h" +#include "util/u_memory.h" + static int r600_state_pm4_resource(struct radeon_state *state); static int r600_state_pm4_cb0(struct radeon_state *state); static int r600_state_pm4_vgt(struct radeon_state *state); @@ -38,24 +40,69 @@ static int r600_state_pm4_shader(struct radeon_state *state); static int r600_state_pm4_draw(struct radeon_state *state); static int r600_state_pm4_config(struct radeon_state *state); static int r600_state_pm4_generic(struct radeon_state *state); +static int r600_state_pm4_query_begin(struct radeon_state *state); +static int r600_state_pm4_query_end(struct radeon_state *state); static int r700_state_pm4_config(struct radeon_state *state); static int r700_state_pm4_cb0(struct radeon_state *state); static int r700_state_pm4_db(struct radeon_state *state); #include "r600_states.h" + +#define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } } +#define SUB_PS(param) { R600_SHADER_PS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } +#define SUB_VS(param) { R600_SHADER_VS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } +#define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } +#define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } + +/* some of these are overriden at runtime for R700 */ +struct radeon_stype_info r600_stypes[] = { + { R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), }, + { R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, SUB_NONE(CB_CNTL) }, + { R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, SUB_NONE(RASTERIZER) }, + { R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, SUB_NONE(VIEWPORT) }, + { R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, SUB_NONE(SCISSOR) }, + { R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, SUB_NONE(BLEND), }, + { R600_STATE_DSA, 1, 0, r600_state_pm4_generic, SUB_NONE(DSA), }, + { R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { SUB_PS(PS_SHADER), SUB_VS(VS_SHADER) } }, + { R600_STATE_CONSTANT, 256, 0x10, r600_state_pm4_generic, { SUB_PS(PS_CONSTANT), SUB_VS(VS_CONSTANT) } }, + { R600_STATE_RESOURCE, 160, 0x1c, r600_state_pm4_resource, { SUB_PS(PS_RESOURCE), SUB_VS(VS_RESOURCE), SUB_GS(GS_RESOURCE), SUB_FS(FS_RESOURCE)} }, + { R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER), SUB_VS(VS_SAMPLER), SUB_GS(GS_SAMPLER) } }, + { R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER_BORDER), SUB_VS(VS_SAMPLER_BORDER), SUB_GS(GS_SAMPLER_BORDER) } }, + { R600_STATE_CB0, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB0) }, + { R600_STATE_CB1, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB1) }, + { R600_STATE_CB2, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB2) }, + { R600_STATE_CB3, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB3) }, + { R600_STATE_CB4, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB4) }, + { R600_STATE_CB5, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB5) }, + { R600_STATE_CB6, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB6) }, + { R600_STATE_CB7, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB7) }, + { R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) }, + { R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) }, + { R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) }, + { R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) }, + { R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) }, + { R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) }, +}; +#define STYPES_SIZE Elements(r600_stypes) + +static const struct radeon_register *get_regs(struct radeon_state *state) +{ + return state->stype->reginfo[state->shader_index].regs; +} + /* * r600/r700 state functions */ static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg) { - const struct radeon_register *regs = state->radeon->type[state->type].regs; + const struct radeon_register *regs = get_regs(state); unsigned i; int r; if (!offset) { fprintf(stderr, "%s invalid register for state %d %d\n", - __func__, state->type, id); + __func__, state->stype->stype, id); return -EINVAL; } if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) { @@ -114,19 +161,18 @@ static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, static int r600_state_pm4_generic(struct radeon_state *state) { - struct radeon *radeon = state->radeon; - unsigned i, offset, nreg, type, coffset, loffset, soffset; + const struct radeon_register *regs = get_regs(state); + unsigned i, offset, nreg, coffset, loffset, soffset; unsigned start; int r; if (!state->nstates) return 0; - type = state->type; - soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride; - offset = loffset = radeon->type[type].regs[0].offset + soffset; + soffset = state->id * state->stype->stride; + offset = loffset = regs[0].offset + soffset; start = 0; for (i = 1, nreg = 1; i < state->nstates; i++) { - coffset = radeon->type[type].regs[i].offset + soffset; + coffset = regs[i].offset + soffset; if (coffset == (loffset + 4)) { nreg++; loffset = coffset; @@ -233,20 +279,54 @@ static int r600_state_pm4_config(struct radeon_state *state) state->pm4[state->cpm4++] = 0x80000000; state->pm4[state->cpm4++] = 0x80000000; state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); - state->pm4[state->cpm4++] = 0x00000016; + state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); state->pm4[state->cpm4++] = 0x00000010; state->pm4[state->cpm4++] = 0x00028000; return r600_state_pm4_generic(state); } +static int r600_state_pm4_query_begin(struct radeon_state *state) +{ + int r; + + state->cpm4 = 0; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2); + state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE; + state->pm4[state->cpm4++] = state->states[0]; + state->pm4[state->cpm4++] = 0x0; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + return 0; +} + +static int r600_state_pm4_query_end(struct radeon_state *state) +{ + int r; + + state->cpm4 = 0; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2); + state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE; + state->pm4[state->cpm4++] = state->states[0]; + state->pm4[state->cpm4++] = 0x0; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + return 0; +} + static int r700_state_pm4_config(struct radeon_state *state) { state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); state->pm4[state->cpm4++] = 0x80000000; state->pm4[state->cpm4++] = 0x80000000; state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); - state->pm4[state->cpm4++] = 0x00000016; + state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); state->pm4[state->cpm4++] = 0x00000010; state->pm4[state->cpm4++] = 0x00028000; @@ -287,7 +367,6 @@ static int r600_state_pm4_vgt(struct radeon_state *state) static int r600_state_pm4_draw(struct radeon_state *state) { - unsigned i; int r; if (state->nbo) { @@ -301,20 +380,13 @@ static int r600_state_pm4_draw(struct radeon_state *state) if (r) return r; state->pm4[state->cpm4++] = state->bo[0]->handle; - } else if (state->nimmd) { - state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1); - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; - for (i = 0; i < state->nimmd; i++) { - state->pm4[state->cpm4++] = state->immd[i]; - } } else { state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; } state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); - state->pm4[state->cpm4++] = 0x00000016; + state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; return 0; } @@ -322,8 +394,9 @@ static int r600_state_pm4_resource(struct radeon_state *state) { u32 flags, type, nbo, offset, soffset; int r; + const struct radeon_register *regs = get_regs(state); - soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride; + soffset = state->id * state->stype->stride; type = G_038018_TYPE(state->states[6]); switch (type) { case 2: @@ -342,7 +415,7 @@ static int r600_state_pm4_resource(struct radeon_state *state) return -EINVAL; } r600_state_pm4_with_flush(state, flags); - offset = state->radeon->type[state->type].regs[0].offset + soffset; + offset = regs[0].offset + soffset; state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7); state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2; state->pm4[state->cpm4++] = state->states[0]; @@ -367,33 +440,62 @@ static int r600_state_pm4_resource(struct radeon_state *state) return 0; } -int r600_init(struct radeon *radeon) + +static void r600_modify_type_array(struct radeon *radeon) { + int i; switch (radeon->family) { - case CHIP_R600: - case CHIP_RV610: - case CHIP_RV630: - case CHIP_RV670: - case CHIP_RV620: - case CHIP_RV635: - case CHIP_RS780: - case CHIP_RS880: - radeon->ntype = R600_NTYPE; - radeon->nstate = R600_NSTATE; - radeon->type = R600_types; - break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: - radeon->ntype = R600_NTYPE; - radeon->nstate = R600_NSTATE; - radeon->type = R700_types; break; default: - fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", - __func__, radeon->device); - return -EINVAL; + return; + } + + /* r700 needs some mods */ + for (i = 0; i < radeon->nstype; i++) { + struct radeon_stype_info *info = &radeon->stype[i]; + + switch(info->stype) { + case R600_STATE_CONFIG: + info->pm4 = r700_state_pm4_config; + break; + case R600_STATE_CB0: + info->pm4 = r700_state_pm4_cb0; + break; + case R600_STATE_DB: + info->pm4 = r700_state_pm4_db; + }; } +} + +static void r600_build_types_array(struct radeon *radeon) +{ + int i, j; + int id = 0; + + for (i = 0; i < STYPES_SIZE; i++) { + r600_stypes[i].base_id = id; + r600_stypes[i].npm4 = 128; + if (r600_stypes[i].reginfo[0].shader_type == 0) { + id += r600_stypes[i].num; + } else { + for (j = 0; j < R600_SHADER_MAX; j++) { + if (r600_stypes[i].reginfo[j].shader_type) + id += r600_stypes[i].num; + } + } + } + radeon->stype = r600_stypes; + radeon->nstype = STYPES_SIZE; + + r600_modify_type_array(radeon); +} + +int r600_init(struct radeon *radeon) +{ + r600_build_types_array(radeon); return 0; } diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h index e40c77d8f6..09d79d498d 100644 --- a/src/gallium/winsys/r600/drm/r600_states.h +++ b/src/gallium/winsys/r600/drm/r600_states.h @@ -17,7 +17,7 @@ #ifndef R600_STATES_H #define R600_STATES_H -static const struct radeon_register R600_CONFIG_names[] = { +static const struct radeon_register R600_names_CONFIG[] = { {0x00008C00, 0, 0, "SQ_CONFIG"}, {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"}, {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"}, @@ -61,7 +61,7 @@ static const struct radeon_register R600_CONFIG_names[] = { {0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"}, }; -static const struct radeon_register R600_CB_CNTL_names[] = { +static const struct radeon_register R600_names_CB_CNTL[] = { {0x00028120, 0, 0, "CB_CLEAR_RED"}, {0x00028124, 0, 0, "CB_CLEAR_GREEN"}, {0x00028128, 0, 0, "CB_CLEAR_BLUE"}, @@ -82,7 +82,7 @@ static const struct radeon_register R600_CB_CNTL_names[] = { {0x00028C48, 0, 0, "PA_SC_AA_MASK"}, }; -static const struct radeon_register R600_RASTERIZER_names[] = { +static const struct radeon_register R600_names_RASTERIZER[] = { {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"}, {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"}, {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"}, @@ -106,7 +106,7 @@ static const struct radeon_register R600_RASTERIZER_names[] = { {0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"}, }; -static const struct radeon_register R600_VIEWPORT_names[] = { +static const struct radeon_register R600_names_VIEWPORT[] = { {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"}, {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"}, {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"}, @@ -118,7 +118,7 @@ static const struct radeon_register R600_VIEWPORT_names[] = { {0x00028818, 0, 0, "PA_CL_VTE_CNTL"}, }; -static const struct radeon_register R600_SCISSOR_names[] = { +static const struct radeon_register R600_names_SCISSOR[] = { {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"}, {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"}, {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"}, @@ -140,7 +140,7 @@ static const struct radeon_register R600_SCISSOR_names[] = { {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"}, }; -static const struct radeon_register R600_BLEND_names[] = { +static const struct radeon_register R600_names_BLEND[] = { {0x00028414, 0, 0, "CB_BLEND_RED"}, {0x00028418, 0, 0, "CB_BLEND_GREEN"}, {0x0002841C, 0, 0, "CB_BLEND_BLUE"}, @@ -156,7 +156,7 @@ static const struct radeon_register R600_BLEND_names[] = { {0x00028804, 0, 0, "CB_BLEND_CONTROL"}, }; -static const struct radeon_register R600_DSA_names[] = { +static const struct radeon_register R600_names_DSA[] = { {0x00028028, 0, 0, "DB_STENCIL_CLEAR"}, {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"}, {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"}, @@ -175,7 +175,7 @@ static const struct radeon_register R600_DSA_names[] = { {0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"}, }; -static const struct radeon_register R600_VS_SHADER_names[] = { +static const struct radeon_register R600_names_VS_SHADER[] = { {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"}, {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"}, {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"}, @@ -227,7 +227,7 @@ static const struct radeon_register R600_VS_SHADER_names[] = { {0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"}, }; -static const struct radeon_register R600_PS_SHADER_names[] = { +static const struct radeon_register R600_names_PS_SHADER[] = { {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"}, {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"}, {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"}, @@ -269,21 +269,48 @@ static const struct radeon_register R600_PS_SHADER_names[] = { {0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"}, }; -static const struct radeon_register R600_PS_CONSTANT_names[] = { +static const struct radeon_register R600_names_PS_CONSTANT[] = { {0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"}, {0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"}, {0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"}, {0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"}, }; -static const struct radeon_register R600_VS_CONSTANT_names[] = { +static const struct radeon_register R600_names_VS_CONSTANT[] = { {0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"}, {0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"}, {0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"}, {0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"}, }; -static const struct radeon_register R600_PS_RESOURCE_names[] = { +static const struct radeon_register R600_names_UCP[] = { + {0x00028E20, 0, 0, "PA_CL_UCP0_X"}, + {0x00028E24, 0, 0, "PA_CL_UCP0_Y"}, + {0x00028E28, 0, 0, "PA_CL_UCP0_Z"}, + {0x00028E2C, 0, 0, "PA_CL_UCP0_W"}, + {0x00028E30, 0, 0, "PA_CL_UCP1_X"}, + {0x00028E34, 0, 0, "PA_CL_UCP1_Y"}, + {0x00028E38, 0, 0, "PA_CL_UCP1_Z"}, + {0x00028E3C, 0, 0, "PA_CL_UCP1_W"}, + {0x00028E40, 0, 0, "PA_CL_UCP2_X"}, + {0x00028E44, 0, 0, "PA_CL_UCP2_Y"}, + {0x00028E48, 0, 0, "PA_CL_UCP2_Z"}, + {0x00028E4C, 0, 0, "PA_CL_UCP2_W"}, + {0x00028E50, 0, 0, "PA_CL_UCP3_X"}, + {0x00028E54, 0, 0, "PA_CL_UCP3_Y"}, + {0x00028E58, 0, 0, "PA_CL_UCP3_Z"}, + {0x00028E5C, 0, 0, "PA_CL_UCP3_W"}, + {0x00028E60, 0, 0, "PA_CL_UCP4_X"}, + {0x00028E64, 0, 0, "PA_CL_UCP4_Y"}, + {0x00028E68, 0, 0, "PA_CL_UCP4_Z"}, + {0x00028E6C, 0, 0, "PA_CL_UCP4_W"}, + {0x00028E70, 0, 0, "PA_CL_UCP5_X"}, + {0x00028E74, 0, 0, "PA_CL_UCP5_Y"}, + {0x00028E78, 0, 0, "PA_CL_UCP5_Z"}, + {0x00028E7C, 0, 0, "PA_CL_UCP5_W"}, +}; + +static const struct radeon_register R600_names_PS_RESOURCE[] = { {0x00038000, 0, 0, "RESOURCE0_WORD0"}, {0x00038004, 0, 0, "RESOURCE0_WORD1"}, {0x00038008, 0, 0, "RESOURCE0_WORD2"}, @@ -293,7 +320,7 @@ static const struct radeon_register R600_PS_RESOURCE_names[] = { {0x00038018, 0, 0, "RESOURCE0_WORD6"}, }; -static const struct radeon_register R600_VS_RESOURCE_names[] = { +static const struct radeon_register R600_names_VS_RESOURCE[] = { {0x00039180, 0, 0, "RESOURCE160_WORD0"}, {0x00039184, 0, 0, "RESOURCE160_WORD1"}, {0x00039188, 0, 0, "RESOURCE160_WORD2"}, @@ -303,7 +330,7 @@ static const struct radeon_register R600_VS_RESOURCE_names[] = { {0x00039198, 0, 0, "RESOURCE160_WORD6"}, }; -static const struct radeon_register R600_FS_RESOURCE_names[] = { +static const struct radeon_register R600_names_FS_RESOURCE[] = { {0x0003A300, 0, 0, "RESOURCE320_WORD0"}, {0x0003A304, 0, 0, "RESOURCE320_WORD1"}, {0x0003A308, 0, 0, "RESOURCE320_WORD2"}, @@ -313,7 +340,7 @@ static const struct radeon_register R600_FS_RESOURCE_names[] = { {0x0003A318, 0, 0, "RESOURCE320_WORD6"}, }; -static const struct radeon_register R600_GS_RESOURCE_names[] = { +static const struct radeon_register R600_names_GS_RESOURCE[] = { {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"}, {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"}, {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"}, @@ -323,46 +350,46 @@ static const struct radeon_register R600_GS_RESOURCE_names[] = { {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"}, }; -static const struct radeon_register R600_PS_SAMPLER_names[] = { +static const struct radeon_register R600_names_PS_SAMPLER[] = { {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"}, {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"}, {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"}, }; -static const struct radeon_register R600_VS_SAMPLER_names[] = { +static const struct radeon_register R600_names_VS_SAMPLER[] = { {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"}, {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"}, {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"}, }; -static const struct radeon_register R600_GS_SAMPLER_names[] = { +static const struct radeon_register R600_names_GS_SAMPLER[] = { {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"}, {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"}, {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"}, }; -static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = { +static const struct radeon_register R600_names_PS_SAMPLER_BORDER[] = { {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"}, {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"}, {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"}, {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"}, }; -static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = { +static const struct radeon_register R600_names_VS_SAMPLER_BORDER[] = { {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"}, {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"}, {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"}, {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"}, }; -static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = { +static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = { {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"}, {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"}, {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"}, {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"}, }; -static const struct radeon_register R600_CB0_names[] = { +static const struct radeon_register R600_names_CB0[] = { {0x00028040, 1, 0, "CB_COLOR0_BASE"}, {0x000280A0, 0, 0, "CB_COLOR0_INFO"}, {0x00028060, 0, 0, "CB_COLOR0_SIZE"}, @@ -372,7 +399,7 @@ static const struct radeon_register R600_CB0_names[] = { {0x00028100, 0, 0, "CB_COLOR0_MASK"}, }; -static const struct radeon_register R600_CB1_names[] = { +static const struct radeon_register R600_names_CB1[] = { {0x00028044, 1, 0, "CB_COLOR1_BASE"}, {0x000280A4, 0, 0, "CB_COLOR1_INFO"}, {0x00028064, 0, 0, "CB_COLOR1_SIZE"}, @@ -382,7 +409,7 @@ static const struct radeon_register R600_CB1_names[] = { {0x00028104, 0, 0, "CB_COLOR1_MASK"}, }; -static const struct radeon_register R600_CB2_names[] = { +static const struct radeon_register R600_names_CB2[] = { {0x00028048, 1, 0, "CB_COLOR2_BASE"}, {0x000280A8, 0, 0, "CB_COLOR2_INFO"}, {0x00028068, 0, 0, "CB_COLOR2_SIZE"}, @@ -392,7 +419,7 @@ static const struct radeon_register R600_CB2_names[] = { {0x00028108, 0, 0, "CB_COLOR2_MASK"}, }; -static const struct radeon_register R600_CB3_names[] = { +static const struct radeon_register R600_names_CB3[] = { {0x0002804C, 1, 0, "CB_COLOR3_BASE"}, {0x000280AC, 0, 0, "CB_COLOR3_INFO"}, {0x0002806C, 0, 0, "CB_COLOR3_SIZE"}, @@ -402,7 +429,7 @@ static const struct radeon_register R600_CB3_names[] = { {0x0002810C, 0, 0, "CB_COLOR3_MASK"}, }; -static const struct radeon_register R600_CB4_names[] = { +static const struct radeon_register R600_names_CB4[] = { {0x00028050, 1, 0, "CB_COLOR4_BASE"}, {0x000280B0, 0, 0, "CB_COLOR4_INFO"}, {0x00028070, 0, 0, "CB_COLOR4_SIZE"}, @@ -412,7 +439,7 @@ static const struct radeon_register R600_CB4_names[] = { {0x00028110, 0, 0, "CB_COLOR4_MASK"}, }; -static const struct radeon_register R600_CB5_names[] = { +static const struct radeon_register R600_names_CB5[] = { {0x00028054, 1, 0, "CB_COLOR5_BASE"}, {0x000280B4, 0, 0, "CB_COLOR5_INFO"}, {0x00028074, 0, 0, "CB_COLOR5_SIZE"}, @@ -422,7 +449,7 @@ static const struct radeon_register R600_CB5_names[] = { {0x00028114, 0, 0, "CB_COLOR5_MASK"}, }; -static const struct radeon_register R600_CB6_names[] = { +static const struct radeon_register R600_names_CB6[] = { {0x00028058, 1, 0, "CB_COLOR6_BASE"}, {0x000280B8, 0, 0, "CB_COLOR6_INFO"}, {0x00028078, 0, 0, "CB_COLOR6_SIZE"}, @@ -432,7 +459,7 @@ static const struct radeon_register R600_CB6_names[] = { {0x00028118, 0, 0, "CB_COLOR6_MASK"}, }; -static const struct radeon_register R600_CB7_names[] = { +static const struct radeon_register R600_names_CB7[] = { {0x0002805C, 1, 0, "CB_COLOR7_BASE"}, {0x000280BC, 0, 0, "CB_COLOR7_INFO"}, {0x0002807C, 0, 0, "CB_COLOR7_SIZE"}, @@ -442,7 +469,7 @@ static const struct radeon_register R600_CB7_names[] = { {0x0002811C, 0, 0, "CB_COLOR7_MASK"}, }; -static const struct radeon_register R600_DB_names[] = { +static const struct radeon_register R600_names_DB[] = { {0x0002800C, 1, 0, "DB_DEPTH_BASE"}, {0x00028000, 0, 0, "DB_DEPTH_SIZE"}, {0x00028004, 0, 0, "DB_DEPTH_VIEW"}, @@ -451,7 +478,7 @@ static const struct radeon_register R600_DB_names[] = { {0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"}, }; -static const struct radeon_register R600_VGT_names[] = { +static const struct radeon_register R600_names_VGT[] = { {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, @@ -465,81 +492,15 @@ static const struct radeon_register R600_VGT_names[] = { {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, }; -static const struct radeon_register R600_DRAW_names[] = { +static const struct radeon_register R600_names_DRAW[] = { {0x00008970, 0, 0, "VGT_NUM_INDICES"}, {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"}, {0x000287E8, 1, 0, "VGT_DMA_BASE"}, {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, }; -static struct radeon_type R600_types[] = { - { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names}, - { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names}, - { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names}, - { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names}, - { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names}, - { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names}, - { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names}, - { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names}, - { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names}, - { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names}, - { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names}, - { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names}, - { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names}, - { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names}, - { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names}, - { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names}, - { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names}, - { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names}, - { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names}, - { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names}, - { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names}, - { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names}, - { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names}, - { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names}, - { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names}, - { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names}, - { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names}, - { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names}, - { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names}, - { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names}, - { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names}, - { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names}, -}; - -static struct radeon_type R700_types[] = { - { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names}, - { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names}, - { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names}, - { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names}, - { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names}, - { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names}, - { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names}, - { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names}, - { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names}, - { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names}, - { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names}, - { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names}, - { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names}, - { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names}, - { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names}, - { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names}, - { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names}, - { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names}, - { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names}, - { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names}, - { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names}, - { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names}, - { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names}, - { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names}, - { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names}, - { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names}, - { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names}, - { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names}, - { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names}, - { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names}, - { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names}, - { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names}, +static const struct radeon_register R600_names_VGT_EVENT[] = { + {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, }; #endif diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h index 5d13378627..e8c2dc0651 100644 --- a/src/gallium/winsys/r600/drm/r600d.h +++ b/src/gallium/winsys/r600/drm/r600d.h @@ -82,6 +82,9 @@ #define PKT3_SET_CTL_CONST 0x6F #define PKT3_SURFACE_BASE_UPDATE 0x73 +#define EVENT_TYPE_ZPASS_DONE 0x15 +#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 + #define PKT_TYPE_S(x) (((x) & 0x3) << 30) #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) #define PKT_TYPE_C 0x3FFFFFFF diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c index 80b0a1d397..e2d813ebac 100644 --- a/src/gallium/winsys/r600/drm/radeon.c +++ b/src/gallium/winsys/r600/drm/radeon.c @@ -42,24 +42,13 @@ static int radeon_get_device(struct radeon *radeon) return r; } -/* symbol missing drove me crazy hack to get symbol exported */ -static void fake(void) -{ - struct radeon_ctx *ctx; - struct radeon_draw *draw; - - ctx = radeon_ctx(NULL); - draw = radeon_draw(NULL); -} - struct radeon *radeon_new(int fd, unsigned device) { struct radeon *radeon; - int r; + int r, i, id; radeon = calloc(1, sizeof(*radeon)); if (radeon == NULL) { - fake(); return NULL; } radeon->fd = fd; @@ -131,6 +120,19 @@ struct radeon *radeon_new(int fd, unsigned device) __func__, radeon->device); break; } + radeon->state_type_id = calloc(radeon->nstype, sizeof(unsigned)); + if (radeon->state_type_id == NULL) { + return radeon_decref(radeon); + } + for (i = 0, id = 0; i < radeon->nstype; i++) { + radeon->state_type_id[i] = id; + for (int j = 0; j < radeon->nstype; j++) { + if (radeon->stype[j].stype != i) + continue; + id += radeon->stype[j].num; + } + } + radeon->nstate_per_shader = id; return radeon; } @@ -153,47 +155,3 @@ struct radeon *radeon_decref(struct radeon *radeon) free(radeon); return NULL; } - -int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id) -{ - unsigned i, j; - - for (i = 0; i < radeon->ntype; i++) { - if (radeon->type[i].range_start) { - if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) { - *typeid = i; - j = offset - radeon->type[i].range_start; - j /= radeon->type[i].stride; - *stateid = radeon->type[i].id + j; - *id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4; - return 0; - } - } else { - for (j = 0; j < radeon->type[i].nstates; j++) { - if (radeon->type[i].regs[j].offset == offset) { - *typeid = i; - *stateid = radeon->type[i].id; - *id = j; - return 0; - } - } - } - } - fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset); - return -EINVAL; -} - -unsigned radeon_type_from_id(struct radeon *radeon, unsigned id) -{ - unsigned i; - - for (i = 0; i < radeon->ntype - 1; i++) { - if (radeon->type[i].id == id) - return i; - if (id > radeon->type[i].id && id < radeon->type[i + 1].id) - return i; - } - if (radeon->type[i].id == id) - return i; - return -1; -} diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c index f259ae7fb5..a1306f6e9d 100644 --- a/src/gallium/winsys/r600/drm/radeon_bo.c +++ b/src/gallium/winsys/r600/drm/radeon_bo.c @@ -145,7 +145,9 @@ struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo) return NULL; } - munmap(bo->data, bo->size); + if (bo->map_count) { + munmap(bo->data, bo->size); + } memset(&args, 0, sizeof(args)); args.handle = bo->handle; drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args); diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c index 45b706bb0f..47fca76136 100644 --- a/src/gallium/winsys/r600/drm/radeon_ctx.c +++ b/src/gallium/winsys/r600/drm/radeon_ctx.c @@ -30,21 +30,16 @@ #include "radeon_drm.h" #include "bof.h" -int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo) +static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo) { - void *ptr; - - ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1)); - if (ptr == NULL) { - return -ENOMEM; - } - ctx->bo = ptr; + if (ctx->nbo >= RADEON_CTX_MAX_PM4) + return -EBUSY; ctx->bo[ctx->nbo] = bo; ctx->nbo++; return 0; } -struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc) +static struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc) { struct radeon_cs_reloc *greloc; unsigned i; @@ -59,7 +54,7 @@ struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc) return NULL; } -void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement) +static void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement) { struct radeon_cs_reloc *greloc; unsigned i; @@ -76,50 +71,57 @@ void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *place } } -struct radeon_ctx *radeon_ctx(struct radeon *radeon) +void radeon_ctx_clear(struct radeon_ctx *ctx) { - struct radeon_ctx *ctx; - - if (radeon == NULL) - return NULL; - ctx = calloc(1, sizeof(*ctx)); - if (ctx == NULL) - return NULL; - ctx->radeon = radeon_incref(radeon); - return ctx; + for (int i = 0; i < ctx->nbo; i++) { + ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]); + } + ctx->ndwords = RADEON_CTX_MAX_PM4; + ctx->cdwords = 0; + ctx->nreloc = 0; + ctx->nbo = 0; } -struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx) +int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon) { - ctx->refcount++; - return ctx; + if (radeon == NULL) + return -EINVAL; + memset(ctx, 0, sizeof(struct radeon_ctx)); + ctx->radeon = radeon_incref(radeon); + radeon_ctx_clear(ctx); + ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4); + if (ctx->pm4 == NULL) { + radeon_ctx_fini(ctx); + return -ENOMEM; + } + ctx->reloc = malloc(sizeof(struct radeon_cs_reloc) * RADEON_CTX_MAX_PM4); + if (ctx->reloc == NULL) { + radeon_ctx_fini(ctx); + return -ENOMEM; + } + ctx->bo = malloc(sizeof(void *) * RADEON_CTX_MAX_PM4); + if (ctx->bo == NULL) { + radeon_ctx_fini(ctx); + return -ENOMEM; + } + return 0; } -struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx) +void radeon_ctx_fini(struct radeon_ctx *ctx) { unsigned i; if (ctx == NULL) - return NULL; - if (--ctx->refcount > 0) { - return NULL; - } + return; - for (i = 0; i < ctx->ndraw; i++) { - ctx->draw[i] = radeon_draw_decref(ctx->draw[i]); - } for (i = 0; i < ctx->nbo; i++) { ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]); } ctx->radeon = radeon_decref(ctx->radeon); - free(ctx->state); - free(ctx->draw); free(ctx->bo); free(ctx->pm4); free(ctx->reloc); - memset(ctx, 0, sizeof(*ctx)); - free(ctx); - return NULL; + memset(ctx, 0, sizeof(struct radeon_ctx)); } static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state) @@ -152,17 +154,17 @@ int radeon_ctx_submit(struct radeon_ctx *ctx) uint64_t chunk_array[2]; int r = 0; - if (!ctx->cpm4) + if (!ctx->cdwords) return 0; #if 0 - for (r = 0; r < ctx->cpm4; r++) { + for (r = 0; r < ctx->cdwords; r++) { fprintf(stderr, "0x%08X\n", ctx->pm4[r]); } #endif drmib.num_chunks = 2; drmib.chunks = (uint64_t)(uintptr_t)chunk_array; chunks[0].chunk_id = RADEON_CHUNK_ID_IB; - chunks[0].length_dw = ctx->cpm4; + chunks[0].length_dw = ctx->cdwords; chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; @@ -180,7 +182,6 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, unsigned id, unsigned *placement) { unsigned i; - struct radeon_cs_reloc *ptr; for (i = 0; i < ctx->nreloc; i++) { if (ctx->reloc[i].handle == bo->handle) { @@ -188,14 +189,13 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, return 0; } } - ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1)); - if (ptr == NULL) - return -ENOMEM; - ctx->reloc = ptr; - ptr[ctx->nreloc].handle = bo->handle; - ptr[ctx->nreloc].read_domain = placement[0] | placement [1]; - ptr[ctx->nreloc].write_domain = placement[0] | placement [1]; - ptr[ctx->nreloc].flags = 0; + if (ctx->nreloc >= RADEON_CTX_MAX_PM4) { + return -EBUSY; + } + ctx->reloc[ctx->nreloc].handle = bo->handle; + ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1]; + ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1]; + ctx->reloc[ctx->nreloc].flags = 0; ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; ctx->nreloc++; return 0; @@ -208,97 +208,80 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state if (state == NULL) return 0; - memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4); + if (state->cpm4 > ctx->ndwords) { + return -EBUSY; + } + memcpy(&ctx->pm4[ctx->cdwords], state->pm4, state->cpm4 * 4); for (i = 0; i < state->nreloc; i++) { rid = state->reloc_pm4_id[i]; bid = state->reloc_bo_id[i]; - cid = ctx->id + rid; + cid = ctx->cdwords + rid; r = radeon_ctx_reloc(ctx, state->bo[bid], cid, &state->placement[bid * 2]); if (r) { - fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type); + fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->stype->stype); return r; } } - ctx->id += state->cpm4; + ctx->cdwords += state->cpm4; + ctx->ndwords -= state->cpm4; return 0; } -int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw) +int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state) { - struct radeon_draw *pdraw = NULL; - struct radeon_draw **ndraw; - struct radeon_state *nstate, *ostate; - unsigned cpm4, i, cstate; - void *tmp; int r = 0; - ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1)); - if (ndraw == NULL) - return -ENOMEM; - ctx->draw = ndraw; - for (i = 0; i < draw->nstate; i++) { - r = radeon_ctx_state_bo(ctx, draw->state[i]); - if (r) - return r; - } - r = radeon_draw_check(draw); + /* !!! ONLY ACCEPT QUERY STATE HERE !!! */ + r = radeon_state_pm4(state); if (r) return r; - if (draw->cpm4 >= RADEON_CTX_MAX_PM4) { - fprintf(stderr, "%s single draw too big %d, max %d\n", - __func__, draw->cpm4, RADEON_CTX_MAX_PM4); + /* BEGIN/END query are balanced in the same cs so account for END + * END query when scheduling BEGIN query + */ + switch (state->stype->stype) { + case R600_STATE_QUERY_BEGIN: + /* is there enough place for begin & end */ + if ((state->cpm4 * 2) > ctx->ndwords) + return -EBUSY; + ctx->ndwords -= state->cpm4; + break; + case R600_STATE_QUERY_END: + ctx->ndwords += state->cpm4; + break; + default: return -EINVAL; } - tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*)); - if (tmp == NULL) - return -ENOMEM; - ctx->state = tmp; - pdraw = ctx->cdraw; - for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) { - nstate = draw->state[i]; - if (nstate) { - if (pdraw && pdraw->state[i]) { - ostate = pdraw->state[i]; - if (ostate->pm4_crc != nstate->pm4_crc) { - ctx->state[cstate++] = nstate; - cpm4 += nstate->cpm4; - } - } else { - ctx->state[cstate++] = nstate; - cpm4 += nstate->cpm4; - } - } - } - /* The last state is the draw state always add it */ - if (draw->state[i] == NULL) { - fprintf(stderr, "%s no draw command\n", __func__); - return -EINVAL; - } - ctx->state[cstate++] = draw->state[i]; - cpm4 += draw->state[i]->cpm4; - if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) { - /* need to flush */ - return -EBUSY; - } - ctx->draw_cpm4 += cpm4; - ctx->nstate = cstate; - ctx->draw[ctx->ndraw++] = draw; - ctx->cdraw = draw; - return 0; + return radeon_ctx_state_schedule(ctx, state); } int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw) { - int r; + unsigned previous_cdwords; + int r = 0; - radeon_draw_incref(draw); - r = radeon_ctx_set_draw_new(ctx, draw); - if (r) - radeon_draw_decref(draw); - return r; + for (int i = 0; i < (ctx->radeon->nstate_per_shader * R600_SHADER_MAX); i++) { + r = radeon_ctx_state_bo(ctx, draw->state[i]); + if (r) + return r; + } + previous_cdwords = ctx->cdwords; + for (int i = 0, id = 0; i < ctx->radeon->nstate_per_shader; i++) { + for (int j = 0; j < R600_SHADER_MAX; j++) { + id = j * ctx->radeon->nstate_per_shader + i; + if (draw->state[id]) { + r = radeon_ctx_state_schedule(ctx, draw->state[id]); + if (r) { + ctx->cdwords = previous_cdwords; + return r; + } + } + } + } + return 0; } +#if 0 int radeon_ctx_pm4(struct radeon_ctx *ctx) { unsigned i; @@ -310,9 +293,6 @@ int radeon_ctx_pm4(struct radeon_ctx *ctx) if (ctx->pm4 == NULL) return -EINVAL; for (i = 0, ctx->id = 0; i < ctx->nstate; i++) { - r = radeon_ctx_state_schedule(ctx, ctx->state[i]); - if (r) - return r; } if (ctx->id != ctx->draw_cpm4) { fprintf(stderr, "%s miss predicted pm4 size %d for %d\n", @@ -322,6 +302,7 @@ int radeon_ctx_pm4(struct radeon_ctx *ctx) ctx->cpm4 = ctx->draw_cpm4; return 0; } +#endif void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file) { @@ -349,8 +330,8 @@ printf("%d relocs\n", ctx->nreloc); bof_decref(blob); blob = NULL; /* dump cs */ -printf("%d pm4\n", ctx->cpm4); - blob = bof_blob(ctx->cpm4 * 4, ctx->pm4); +printf("%d pm4\n", ctx->cdwords); + blob = bof_blob(ctx->cdwords * 4, ctx->pm4); if (blob == NULL) goto out_err; if (bof_object_set(root, "pm4", blob)) @@ -366,7 +347,6 @@ printf("%d pm4\n", ctx->cpm4); if (bo == NULL) goto out_err; size = bof_int32(ctx->bo[i]->size); -printf("[%d] %d bo\n", i, size); if (size == NULL) goto out_err; if (bof_object_set(bo, "size", size)) diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c index 4413ed79fb..b992c4a55d 100644 --- a/src/gallium/winsys/r600/drm/radeon_draw.c +++ b/src/gallium/winsys/r600/drm/radeon_draw.c @@ -31,111 +31,27 @@ /* * draw functions */ -struct radeon_draw *radeon_draw(struct radeon *radeon) +int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon) { - struct radeon_draw *draw; - - draw = calloc(1, sizeof(*draw)); - if (draw == NULL) - return NULL; - draw->nstate = radeon->nstate; draw->radeon = radeon; - draw->refcount = 1; - draw->state = calloc(1, sizeof(void*) * draw->nstate); - if (draw->state == NULL) { - free(draw); - return NULL; - } - return draw; -} - -struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw) -{ - draw->refcount++; - return draw; -} - -struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw) -{ - unsigned i; - - if (draw == NULL) - return NULL; - if (--draw->refcount > 0) - return NULL; - for (i = 0; i < draw->nstate; i++) { - draw->state[i] = radeon_state_decref(draw->state[i]); - } - free(draw->state); - memset(draw, 0, sizeof(*draw)); - free(draw); - return NULL; -} - -int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state) -{ - if (state == NULL) - return 0; - if (state->type >= draw->radeon->ntype) - return -EINVAL; - draw->state[state->id] = radeon_state_decref(draw->state[state->id]); - draw->state[state->id] = state; + draw->state = calloc(radeon->nstate_per_shader * R600_SHADER_MAX, sizeof(void*)); + if (draw->state == NULL) + return -ENOMEM; return 0; } -int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state) +void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state) { if (state == NULL) - return 0; - radeon_state_incref(state); - return radeon_draw_set_new(draw, state); + return; + draw->state[state->state_id] = state; } -int radeon_draw_check(struct radeon_draw *draw) +void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state) { - unsigned i; - int r; - - r = radeon_draw_pm4(draw); - if (r) - return r; - for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) { - if (draw->state[i]) { - draw->cpm4 += draw->state[i]->cpm4; - } - } - return 0; -} - -struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw) -{ - struct radeon_draw *ndraw; - unsigned i; - - if (draw == NULL) - return NULL; - ndraw = radeon_draw(draw->radeon); - if (ndraw == NULL) { - return NULL; - } - for (i = 0; i < draw->nstate; i++) { - if (radeon_draw_set(ndraw, draw->state[i])) { - radeon_draw_decref(ndraw); - return NULL; - } - } - return ndraw; -} - -int radeon_draw_pm4(struct radeon_draw *draw) -{ - unsigned i; - int r; - - for (i = 0; i < draw->nstate; i++) { - r = radeon_state_pm4(draw->state[i]); - if (r) - return r; + if (state == NULL) + return; + if (draw->state[state->state_id] == state) { + draw->state[state->state_id] = NULL; } - return 0; } diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h index 96c0d060f7..84e552ba4d 100644 --- a/src/gallium/winsys/r600/drm/radeon_priv.h +++ b/src/gallium/winsys/r600/drm/radeon_priv.h @@ -37,17 +37,20 @@ struct radeon_register { char name[64]; }; -struct radeon_type { - unsigned npm4; - unsigned id; - unsigned range_start; - unsigned range_end; - unsigned stride; - unsigned immediate; - char name[64]; +struct radeon_sub_type { + int shader_type; + const struct radeon_register *regs; unsigned nstates; +}; + +struct radeon_stype_info { + unsigned stype; + unsigned num; + unsigned stride; radeon_state_pm4_t pm4; - const struct radeon_register *regs; + struct radeon_sub_type reginfo[R600_SHADER_MAX]; + unsigned base_id; + unsigned npm4; }; struct radeon { @@ -55,9 +58,10 @@ struct radeon { int refcount; unsigned device; unsigned family; - unsigned nstate; - unsigned ntype; - const struct radeon_type *type; + unsigned nstype; + unsigned nstate_per_shader; + unsigned *state_type_id; + struct radeon_stype_info *stype; }; extern struct radeon *radeon_new(int fd, unsigned device); @@ -65,15 +69,6 @@ extern struct radeon *radeon_incref(struct radeon *radeon); extern struct radeon *radeon_decref(struct radeon *radeon); extern unsigned radeon_family_from_device(unsigned device); extern int radeon_is_family_compatible(unsigned family1, unsigned family2); -extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id); -extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id); - - -int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo); -struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc); -void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement); -int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw); -int radeon_ctx_draw(struct radeon_ctx *ctx); /* * r600/r700 context functions diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c index 308288557a..ac60485b28 100644 --- a/src/gallium/winsys/r600/drm/radeon_state.c +++ b/src/gallium/winsys/r600/drm/radeon_state.c @@ -32,82 +32,116 @@ /* * state core functions */ -struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id) +int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 stype, u32 id, u32 shader_type) { - struct radeon_state *state; + struct radeon_stype_info *found = NULL; + int i, j, shader_index = -1; - if (type > radeon->ntype) { - fprintf(stderr, "%s invalid type %d\n", __func__, type); - return NULL; + /* traverse the stype array */ + for (i = 0; i < radeon->nstype; i++) { + /* if the type doesn't match, if the shader doesn't match */ + if (stype != radeon->stype[i].stype) + continue; + if (shader_type) { + for (j = 0; j < 4; j++) { + if (radeon->stype[i].reginfo[j].shader_type == shader_type) { + shader_index = j; + break; + } + } + if (shader_index == -1) + continue; + } else { + if (radeon->stype[i].reginfo[0].shader_type) + continue; + else + shader_index = 0; + } + if (id > radeon->stype[i].num) + continue; + + found = &radeon->stype[i]; + break; } - if (id > radeon->nstate) { - fprintf(stderr, "%s invalid state id %d\n", __func__, id); - return NULL; + + if (!found) { + fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type); + return -EINVAL; } - state = calloc(1, sizeof(*state)); - if (state == NULL) - return NULL; + + memset(state, 0, sizeof(struct radeon_state)); + state->state_id = radeon->nstate_per_shader * shader_index + radeon->state_type_id[stype] + id; + state->stype = found; state->radeon = radeon; - state->type = type; state->id = id; + state->shader_index = shader_index; state->refcount = 1; - state->npm4 = radeon->type[type].npm4; - state->nstates = radeon->type[type].nstates; - state->states = calloc(1, state->nstates * 4); - state->pm4 = calloc(1, radeon->type[type].npm4 * 4); - if (state->states == NULL || state->pm4 == NULL) { - radeon_state_decref(state); - return NULL; - } - return state; + state->npm4 = found->npm4; + state->nstates = found->reginfo[shader_index].nstates; + return 0; } -struct radeon_state *radeon_state_duplicate(struct radeon_state *state) +int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type) { - struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id); - unsigned i; + struct radeon_stype_info *found = NULL; + int i, j, shader_index = -1; if (state == NULL) - return NULL; - nstate->cpm4 = state->cpm4; - nstate->nbo = state->nbo; - nstate->nreloc = state->nreloc; - memcpy(nstate->states, state->states, state->nstates * 4); - memcpy(nstate->pm4, state->pm4, state->npm4 * 4); - memcpy(nstate->placement, state->placement, 8 * 4); - memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4); - memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4); - memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4); - for (i = 0; i < state->nbo; i++) { - nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]); + return 0; + /* traverse the stype array */ + for (i = 0; i < state->radeon->nstype; i++) { + /* if the type doesn't match, if the shader doesn't match */ + if (stype != state->radeon->stype[i].stype) + continue; + if (shader_type) { + for (j = 0; j < 4; j++) { + if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) { + shader_index = j; + break; + } + } + if (shader_index == -1) + continue; + } else { + if (state->radeon->stype[i].reginfo[0].shader_type) + continue; + else + shader_index = 0; + } + if (id > state->radeon->stype[i].num) + continue; + + found = &state->radeon->stype[i]; + break; } - return nstate; -} -struct radeon_state *radeon_state_incref(struct radeon_state *state) -{ - state->refcount++; - return state; + if (!found) { + fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type); + return -EINVAL; + } + + if (found->reginfo[shader_index].nstates != state->nstates) { + fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n", + state->stype->stype, state->id, state->shader_index, stype, id, shader_index); + } + + state->stype = found; + state->id = id; + state->shader_index = shader_index; + state->state_id = state->radeon->nstate_per_shader * shader_index + state->radeon->state_type_id[stype] + id; + return radeon_state_pm4(state); } -struct radeon_state *radeon_state_decref(struct radeon_state *state) +void radeon_state_fini(struct radeon_state *state) { unsigned i; if (state == NULL) return NULL; - if (--state->refcount > 0) { - return NULL; - } for (i = 0; i < state->nbo; i++) { state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]); } - free(state->immd); - free(state->states); - free(state->pm4); - memset(state, 0, sizeof(*state)); - free(state); - return NULL; + memset(state, 0, sizeof(struct radeon_state)); } int radeon_state_replace_always(struct radeon_state *ostate, @@ -147,12 +181,13 @@ int radeon_state_pm4(struct radeon_state *state) { int r; - if (state == NULL || state->cpm4) + if (state == NULL) return 0; - r = state->radeon->type[state->type].pm4(state); + state->cpm4 = 0; + r = state->stype->pm4(state); if (r) { fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n", - __func__, state->type, state->id); + __func__, state->stype->stype, state->id); return r; } state->pm4_crc = crc32(state->pm4, state->cpm4 * 4); diff --git a/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c b/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c index b997abda9b..3a76098b65 100644 --- a/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c +++ b/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c @@ -52,6 +52,7 @@ struct wrapper_sw_winsys struct sw_winsys base; struct pipe_screen *screen; struct pipe_context *pipe; + enum pipe_texture_target target; }; struct wrapper_sw_displaytarget @@ -145,7 +146,7 @@ wsw_dt_create(struct sw_winsys *ws, * XXX Why don't we just get the template. */ memset(&templ, 0, sizeof(templ)); - templ.target = PIPE_TEXTURE_2D; + templ.target = wsw->target; templ.width0 = width; templ.height0 = height; templ.format = format; @@ -291,6 +292,11 @@ wrapper_sw_winsys_warp_pipe_screen(struct pipe_screen *screen) if (!wsw->pipe) goto err_free; + if(screen->get_param(screen, PIPE_CAP_NPOT_TEXTURES)) + wsw->target = PIPE_TEXTURE_2D; + else + wsw->target = PIPE_TEXTURE_RECT; + return &wsw->base; err_free: |