summaryrefslogtreecommitdiff
path: root/src/gallium/winsys
diff options
context:
space:
mode:
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/r600/drm/SConscript25
-rw-r--r--src/gallium/winsys/r600/drm/r600_drm.c3
-rw-r--r--src/gallium/winsys/r600/drm/r600_states.h96
-rw-r--r--src/gallium/winsys/r600/drm/radeon.c1
-rw-r--r--src/gallium/winsys/r600/drm/radeon_bo_pb.c186
-rw-r--r--src/gallium/winsys/r600/drm/radeon_ctx.c3
-rw-r--r--src/gallium/winsys/r600/drm/radeon_priv.h30
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm.c36
-rw-r--r--src/gallium/winsys/svga/drm/vmw_screen_dri.c2
9 files changed, 331 insertions, 51 deletions
diff --git a/src/gallium/winsys/r600/drm/SConscript b/src/gallium/winsys/r600/drm/SConscript
new file mode 100644
index 0000000000..2f20d9f895
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/SConscript
@@ -0,0 +1,25 @@
+Import('*')
+
+env = env.Clone()
+
+r600_sources = [
+ 'bof.c',
+ 'r600_state.c',
+ 'radeon_ctx.c',
+ 'radeon_draw.c',
+ 'radeon_state.c',
+ 'radeon_bo.c',
+ 'radeon_pciid.c',
+ 'radeon.c',
+ 'r600_drm.c'
+]
+
+env.ParseConfig('pkg-config --cflags libdrm_radeon')
+env.Append(CPPPATH = '#/src/gallium/drivers/r600')
+
+r600winsys = env.ConvenienceLibrary(
+ target ='r600winsys',
+ source = r600_sources,
+)
+
+Export('r600winsys')
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 9520792f54..c76e7f5fa5 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -31,7 +31,6 @@
#include "radeon_priv.h"
#include "r600_screen.h"
#include "r600_resource.h"
-#include "r600_public.h"
#include "r600_drm_public.h"
#include "state_tracker/drm_driver.h"
@@ -45,7 +44,7 @@ boolean r600_buffer_get_handle(struct radeon *rw,
struct winsys_handle *whandle)
{
struct drm_gem_flink flink;
- struct r600_resource* rbuffer = (struct r600_buffer*)buf;
+ struct r600_resource* rbuffer = (struct r600_resource*)buf;
if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
if (!rbuffer->flink) {
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 5896df21b2..e40c77d8f6 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -372,6 +372,76 @@ static const struct radeon_register R600_CB0_names[] = {
{0x00028100, 0, 0, "CB_COLOR0_MASK"},
};
+static const struct radeon_register R600_CB1_names[] = {
+ {0x00028044, 1, 0, "CB_COLOR1_BASE"},
+ {0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+ {0x00028064, 0, 0, "CB_COLOR1_SIZE"},
+ {0x00028084, 0, 0, "CB_COLOR1_VIEW"},
+ {0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
+ {0x000280C4, 1, 2, "CB_COLOR1_TILE"},
+ {0x00028104, 0, 0, "CB_COLOR1_MASK"},
+};
+
+static const struct radeon_register R600_CB2_names[] = {
+ {0x00028048, 1, 0, "CB_COLOR2_BASE"},
+ {0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+ {0x00028068, 0, 0, "CB_COLOR2_SIZE"},
+ {0x00028088, 0, 0, "CB_COLOR2_VIEW"},
+ {0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
+ {0x000280C8, 1, 2, "CB_COLOR2_TILE"},
+ {0x00028108, 0, 0, "CB_COLOR2_MASK"},
+};
+
+static const struct radeon_register R600_CB3_names[] = {
+ {0x0002804C, 1, 0, "CB_COLOR3_BASE"},
+ {0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+ {0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
+ {0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
+ {0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
+ {0x000280CC, 1, 2, "CB_COLOR3_TILE"},
+ {0x0002810C, 0, 0, "CB_COLOR3_MASK"},
+};
+
+static const struct radeon_register R600_CB4_names[] = {
+ {0x00028050, 1, 0, "CB_COLOR4_BASE"},
+ {0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+ {0x00028070, 0, 0, "CB_COLOR4_SIZE"},
+ {0x00028090, 0, 0, "CB_COLOR4_VIEW"},
+ {0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
+ {0x000280D0, 1, 2, "CB_COLOR4_TILE"},
+ {0x00028110, 0, 0, "CB_COLOR4_MASK"},
+};
+
+static const struct radeon_register R600_CB5_names[] = {
+ {0x00028054, 1, 0, "CB_COLOR5_BASE"},
+ {0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+ {0x00028074, 0, 0, "CB_COLOR5_SIZE"},
+ {0x00028094, 0, 0, "CB_COLOR5_VIEW"},
+ {0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
+ {0x000280D4, 1, 2, "CB_COLOR5_TILE"},
+ {0x00028114, 0, 0, "CB_COLOR5_MASK"},
+};
+
+static const struct radeon_register R600_CB6_names[] = {
+ {0x00028058, 1, 0, "CB_COLOR6_BASE"},
+ {0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+ {0x00028078, 0, 0, "CB_COLOR6_SIZE"},
+ {0x00028098, 0, 0, "CB_COLOR6_VIEW"},
+ {0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
+ {0x000280D8, 1, 2, "CB_COLOR6_TILE"},
+ {0x00028118, 0, 0, "CB_COLOR6_MASK"},
+};
+
+static const struct radeon_register R600_CB7_names[] = {
+ {0x0002805C, 1, 0, "CB_COLOR7_BASE"},
+ {0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+ {0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
+ {0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
+ {0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
+ {0x000280DC, 1, 2, "CB_COLOR7_TILE"},
+ {0x0002811C, 0, 0, "CB_COLOR7_MASK"},
+};
+
static const struct radeon_register R600_DB_names[] = {
{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
@@ -425,9 +495,16 @@ static struct radeon_type R600_types[] = {
{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
- { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
- { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
- { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+ { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+ { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+ { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+ { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+ { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+ { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+ { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+ { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+ { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+ { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
};
static struct radeon_type R700_types[] = {
@@ -453,9 +530,16 @@ static struct radeon_type R700_types[] = {
{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
- { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
- { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
- { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+ { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+ { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+ { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+ { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+ { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+ { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+ { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+ { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+ { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+ { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
};
#endif
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 7e65669806..80b0a1d397 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -23,7 +23,6 @@
#include "xf86drm.h"
#include "radeon_priv.h"
#include "radeon_drm.h"
-#include "r600d.h"
enum radeon_family radeon_get_family(struct radeon *radeon)
{
diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
new file mode 100644
index 0000000000..e8e53a971f
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
@@ -0,0 +1,186 @@
+#include "radeon_priv.h"
+
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include "util/u_double_list.h"
+#include "pipebuffer/pb_buffer.h"
+#include "pipebuffer/pb_bufmgr.h"
+
+struct radeon_bo_pb {
+ struct pb_buffer b;
+ struct radeon_bo *bo;
+
+ struct radeon_bo_pbmgr *mgr;
+ struct list_head maplist;
+};
+
+extern const struct pb_vtbl radeon_bo_pb_vtbl;
+
+static INLINE struct radeon_bo_pb *radeon_bo_pb(struct pb_buffer *buf)
+{
+ assert(buf);
+ assert(buf->vtbl == &radeon_bo_pb_vtbl);
+ return (struct radeon_bo_pb *)buf;
+}
+
+struct radeon_bo_pbmgr {
+ struct pb_manager b;
+ struct radeon *radeon;
+ struct list_head buffer_map_list;
+};
+
+static INLINE struct radeon_bo_pbmgr *radeon_bo_pbmgr(struct pb_manager *mgr)
+{
+ assert(mgr);
+ return (struct radeon_bo_pbmgr *)mgr;
+}
+
+static void radeon_bo_pb_destroy(struct pb_buffer *_buf)
+{
+ struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
+
+ if (buf->bo->data != NULL) {
+ LIST_DEL(&buf->maplist);
+ radeon_bo_unmap(buf->mgr->radeon, buf->bo);
+ }
+ radeon_bo_decref(buf->mgr->radeon, buf->bo);
+ FREE(buf);
+}
+
+static void *
+radeon_bo_pb_map_internal(struct pb_buffer *_buf,
+ unsigned flags)
+{
+ struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
+
+ if (buf->bo->data != NULL)
+ return buf->bo->data;
+
+ if (flags & PB_USAGE_DONTBLOCK) {
+ uint32_t domain;
+ if (radeon_bo_busy(buf->mgr->radeon, buf->bo, &domain))
+ return NULL;
+ }
+
+ if (radeon_bo_map(buf->mgr->radeon, buf->bo)) {
+ return NULL;
+ }
+ LIST_ADDTAIL(&buf->maplist, &buf->mgr->buffer_map_list);
+ return buf->bo->data;
+}
+
+static void radeon_bo_pb_unmap_internal(struct pb_buffer *_buf)
+{
+ (void)_buf;
+}
+
+static void
+radeon_bo_pb_get_base_buffer(struct pb_buffer *buf,
+ struct pb_buffer **base_buf,
+ unsigned *offset)
+{
+ *base_buf = buf;
+ *offset = 0;
+}
+
+static enum pipe_error
+radeon_bo_pb_validate(struct pb_buffer *_buf,
+ struct pb_validate *vl,
+ unsigned flags)
+{
+ /* Always pinned */
+ return PIPE_OK;
+}
+
+static void
+radeon_bo_pb_fence(struct pb_buffer *buf,
+ struct pipe_fence_handle *fence)
+{
+}
+
+const struct pb_vtbl radeon_bo_pb_vtbl = {
+ radeon_bo_pb_destroy,
+ radeon_bo_pb_map_internal,
+ radeon_bo_pb_unmap_internal,
+ radeon_bo_pb_validate,
+ radeon_bo_pb_fence,
+ radeon_bo_pb_get_base_buffer,
+};
+
+static struct pb_buffer *
+radeon_bo_pb_create_buffer(struct pb_manager *_mgr,
+ pb_size size,
+ const struct pb_desc *desc)
+{
+ struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+ struct radeon *radeon = mgr->radeon;
+ struct radeon_bo_pb *bo;
+ uint32_t domain;
+
+ bo = CALLOC_STRUCT(radeon_bo_pb);
+ if (!bo)
+ goto error1;
+
+ pipe_reference_init(&bo->b.base.reference, 1);
+ bo->b.base.alignment = desc->alignment;
+ bo->b.base.usage = desc->usage;
+ bo->b.base.size = size;
+ bo->b.vtbl = &radeon_bo_pb_vtbl;
+ bo->mgr = mgr;
+
+ LIST_INITHEAD(&bo->maplist);
+
+ bo->bo = radeon_bo(radeon, 0, size,
+ desc->alignment, NULL);
+ if (bo->bo == NULL)
+ goto error2;
+ return &bo->b;
+
+error2:
+ FREE(bo);
+error1:
+ return NULL;
+}
+
+static void
+radeon_bo_pbmgr_flush(struct pb_manager *mgr)
+{
+ /* NOP */
+}
+
+static void
+radeon_bo_pbmgr_destroy(struct pb_manager *_mgr)
+{
+ struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+ FREE(mgr);
+}
+
+struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon)
+{
+ struct radeon_bo_pbmgr *mgr;
+
+ mgr = CALLOC_STRUCT(radeon_bo_pbmgr);
+ if (!mgr)
+ return NULL;
+
+ mgr->b.destroy = radeon_bo_pbmgr_destroy;
+ mgr->b.create_buffer = radeon_bo_pb_create_buffer;
+ mgr->b.flush = radeon_bo_pbmgr_flush;
+
+ mgr->radeon = radeon;
+ LIST_INITHEAD(&mgr->buffer_map_list);
+ return &mgr->b;
+}
+
+void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr)
+{
+ struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+ struct radeon_bo_pb *rpb, *t_rpb;
+
+ LIST_FOR_EACH_ENTRY_SAFE(rpb, t_rpb, &mgr->buffer_map_list, maplist) {
+ radeon_bo_unmap(mgr->radeon, rpb->bo);
+ LIST_DEL(&rpb->maplist);
+ }
+
+ LIST_INITHEAD(&mgr->buffer_map_list);
+}
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 6b0eba0b28..45b706bb0f 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -112,6 +112,7 @@ struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
}
ctx->radeon = radeon_decref(ctx->radeon);
+ free(ctx->state);
free(ctx->draw);
free(ctx->bo);
free(ctx->pm4);
@@ -151,6 +152,8 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
uint64_t chunk_array[2];
int r = 0;
+ if (!ctx->cpm4)
+ return 0;
#if 0
for (r = 0; r < ctx->cpm4; r++) {
fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index b91421f438..96c0d060f7 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -68,36 +68,6 @@ extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
-/*
- * radeon context functions
- */
-#pragma pack(1)
-struct radeon_cs_reloc {
- uint32_t handle;
- uint32_t read_domain;
- uint32_t write_domain;
- uint32_t flags;
-};
-#pragma pack()
-
-struct radeon_ctx {
- int refcount;
- struct radeon *radeon;
- u32 *pm4;
- u32 cpm4;
- u32 draw_cpm4;
- unsigned id;
- unsigned next_id;
- unsigned nreloc;
- struct radeon_cs_reloc *reloc;
- unsigned nbo;
- struct radeon_bo **bo;
- unsigned ndraw;
- struct radeon_draw *cdraw;
- struct radeon_draw **draw;
- unsigned nstate;
- struct radeon_state **state;
-};
int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm.c b/src/gallium/winsys/radeon/drm/radeon_drm.c
index ecaf096dea..86d4f94969 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm.c
@@ -39,7 +39,6 @@
#include "util/u_memory.h"
#include "xf86drm.h"
-#include <sys/ioctl.h>
static struct radeon_libdrm_winsys *
radeon_winsys_create(int fd)
@@ -55,6 +54,31 @@ radeon_winsys_create(int fd)
return rws;
}
+/* Enable/disable Hyper-Z access. Return TRUE on success. */
+static boolean radeon_set_hyperz_access(int fd, boolean enable)
+{
+#ifndef RADEON_INFO_WANT_HYPERZ
+#define RADEON_INFO_WANT_HYPERZ 7
+#endif
+
+ struct drm_radeon_info info = {0};
+ unsigned value = enable ? 1 : 0;
+
+ if (!debug_get_bool_option("RADEON_HYPERZ", FALSE))
+ return FALSE;
+
+ info.value = (unsigned long)&value;
+ info.request = RADEON_INFO_WANT_HYPERZ;
+
+ if (drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)) != 0)
+ return FALSE;
+
+ if (enable && !value)
+ return FALSE;
+
+ return TRUE;
+}
+
/* Helper function to do the ioctls needed for setup and init. */
static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys)
{
@@ -134,15 +158,7 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys)
}
winsys->z_pipes = target;
- winsys->hyperz = FALSE;
-#ifndef RADEON_INFO_WANT_HYPERZ
-#define RADEON_INFO_WANT_HYPERZ 7
-#endif
- info.request = RADEON_INFO_WANT_HYPERZ;
- retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
- if (!retval && target == 1) {
- winsys->hyperz = TRUE;
- }
+ winsys->hyperz = radeon_set_hyperz_access(fd, TRUE);
retval = drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
diff --git a/src/gallium/winsys/svga/drm/vmw_screen_dri.c b/src/gallium/winsys/svga/drm/vmw_screen_dri.c
index 1b0d10f60d..7bd4407e9f 100644
--- a/src/gallium/winsys/svga/drm/vmw_screen_dri.c
+++ b/src/gallium/winsys/svga/drm/vmw_screen_dri.c
@@ -32,8 +32,6 @@
#include "vmw_screen.h"
#include "vmw_surface.h"
-#include "vmw_fence.h"
-#include "vmw_context.h"
#include "svga_drm_public.h"
#include "state_tracker/drm_driver.h"
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-13 01:02:48 +0000