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-rw-r--r--src/mesa/drivers/dri/i915/Makefile5
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.c2
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.h2
-rw-r--r--src/mesa/drivers/dri/i915/i830_state.c4
-rw-r--r--src/mesa/drivers/dri/i915/i830_texblend.c1
-rw-r--r--src/mesa/drivers/dri/i915/i830_texstate.c43
-rw-r--r--src/mesa/drivers/dri/i915/i830_vtbl.c81
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.c5
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.h3
-rw-r--r--src/mesa/drivers/dri/i915/i915_debug.c1
-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c4
-rw-r--r--src/mesa/drivers/dri/i915/i915_program.c2
-rw-r--r--src/mesa/drivers/dri/i915/i915_reg.h6
-rw-r--r--src/mesa/drivers/dri/i915/i915_state.c36
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c76
-rw-r--r--src/mesa/drivers/dri/i915/i915_vtbl.c80
-rw-r--r--src/mesa/drivers/dri/i915/intel_render.c4
l---------src/mesa/drivers/dri/i915/intel_swapbuffers.c1
-rw-r--r--src/mesa/drivers/dri/i915/intel_tris.c98
19 files changed, 188 insertions, 266 deletions
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 393312e732..cf32476f40 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -34,7 +34,6 @@ DRIVER_SOURCES = \
intel_pixel_read.c \
intel_buffers.c \
intel_blit.c \
- intel_swapbuffers.c \
i915_tex_layout.c \
i915_texstate.c \
i915_context.c \
@@ -64,7 +63,8 @@ DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \
$(shell pkg-config libdrm --atleast-version=2.3.1 \
&& echo "-DDRM_VBLANK_FLIP=DRM_VBLANK_FLIP")
-DRI_LIB_DEPS += -ldrm_intel
+INCLUDES += $(INTEL_CFLAGS)
+DRI_LIB_DEPS += $(INTEL_LIBS)
include ../Makefile.template
@@ -72,4 +72,3 @@ intel_decode.o: ../intel/intel_decode.c
intel_tex_layout.o: ../intel/intel_tex_layout.c
-symlinks:
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index 840946f908..4cb6305988 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -53,7 +53,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[];
GLboolean
i830CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h
index f73cbbf88b..592ae53976 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -178,7 +178,7 @@ i830_state_draw_region(struct intel_context *intel,
*/
extern GLboolean
i830CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate);
/* i830_tex.c, i830_texstate.c
diff --git a/src/mesa/drivers/dri/i915/i830_state.c b/src/mesa/drivers/dri/i915/i830_state.c
index 645ebe3057..acda7e70de 100644
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -620,7 +620,7 @@ i830LineWidth(GLcontext * ctx, GLfloat widthf)
DBG("%s\n", __FUNCTION__);
width = (int) (widthf * 2);
- CLAMP_SELF(width, 1, 15);
+ width = CLAMP(width, 1, 15);
state5 = i830->state.Ctx[I830_CTXREG_STATE5] & ~FIXED_LINE_WIDTH_MASK;
state5 |= (ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(width));
@@ -639,7 +639,7 @@ i830PointSize(GLcontext * ctx, GLfloat size)
DBG("%s\n", __FUNCTION__);
- CLAMP_SELF(point_size, 1, 256);
+ point_size = CLAMP(point_size, 1, 256);
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
i830->state.Ctx[I830_CTXREG_STATE5] &= ~FIXED_POINT_WIDTH_MASK;
i830->state.Ctx[I830_CTXREG_STATE5] |= (ENABLE_FIXED_POINT_WIDTH |
diff --git a/src/mesa/drivers/dri/i915/i830_texblend.c b/src/mesa/drivers/dri/i915/i830_texblend.c
index 09f7f37e76..3f64be8c96 100644
--- a/src/mesa/drivers/dri/i915/i830_texblend.c
+++ b/src/mesa/drivers/dri/i915/i830_texblend.c
@@ -30,7 +30,6 @@
#include "main/mtypes.h"
#include "main/simple_list.h"
#include "main/enums.h"
-#include "main/texformat.h"
#include "main/texstore.h"
#include "main/mm.h"
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index 6f998fa6f7..7525f9f2e0 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -27,7 +27,7 @@
#include "main/mtypes.h"
#include "main/enums.h"
-#include "main/texformat.h"
+#include "main/colormac.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
@@ -56,10 +56,9 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format)
case MESA_FORMAT_ARGB4444:
return MAPSURF_16BIT | MT_16BIT_ARGB4444;
case MESA_FORMAT_ARGB8888:
- if (internal_format == GL_RGB)
- return MAPSURF_32BIT | MT_32BIT_XRGB8888;
- else
- return MAPSURF_32BIT | MT_32BIT_ARGB8888;
+ return MAPSURF_32BIT | MT_32BIT_ARGB8888;
+ case MESA_FORMAT_XRGB8888:
+ return MAPSURF_32BIT | MT_32BIT_XRGB8888;
case MESA_FORMAT_YCBCR_REV:
return (MAPSURF_422 | MT_422_YCRCB_NORMAL);
case MESA_FORMAT_YCBCR:
@@ -160,13 +159,20 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
pitch = intelObj->pitchOverride;
} else {
+ GLuint dst_x, dst_y;
+
+ intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0,
+ &dst_x, &dst_y);
+
dri_bo_reference(intelObj->mt->region->buffer);
i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
- i830->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt,
- 0, intelObj->
- firstLevel);
+ /* XXX: This calculation is probably broken for tiled images with
+ * a non-page-aligned offset.
+ */
+ i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) *
+ intelObj->mt->cpp;
- format = translate_texture_format(firstImage->TexFormat->MesaFormat,
+ format = translate_texture_format(firstImage->TexFormat,
firstImage->InternalFormat);
pitch = intelObj->mt->pitch * intelObj->mt->cpp;
}
@@ -298,16 +304,15 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]);
-
- state[I830_TEXREG_TM0S4] = INTEL_PACKCOLOR8888(border[0],
- border[1],
- border[2],
- border[3]);
-
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
+
+ state[I830_TEXREG_TM0S4] = PACK_COLOR_8888(border[3],
+ border[0],
+ border[1],
+ border[2]);
I830_ACTIVESTATE(i830, I830_UPLOAD_TEX(unit), GL_TRUE);
/* memcmp was already disabled, but definitely won't work as the
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 983f6724c9..4471ca2bbb 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -26,7 +26,6 @@
**************************************************************************/
#include "glapi/glapi.h"
-#include "main/texformat.h"
#include "i830_context.h"
#include "i830_reg.h"
@@ -127,7 +126,7 @@ i830_render_start(struct intel_context *intel)
for (i = 0; i < I830_TEX_UNITS; i++) {
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
- GLuint sz = VB->TexCoordPtr[i]->size;
+ GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
GLuint emit;
GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
~TEXCOORDTYPE_MASK);
@@ -299,7 +298,7 @@ i830_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(29, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(29);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
@@ -367,7 +366,7 @@ i830_emit_invarient_state(struct intel_context *intel)
#define emit( intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
+ intel_batchbuffer_data(intel->batch, state, size )
static GLuint
get_dirty(struct i830_hw_state *state)
@@ -430,13 +429,9 @@ i830_emit_state(struct intel_context *intel)
* It might be better to talk about explicit places where
* scheduling is allowed, rather than assume that it is whenever a
* batchbuffer fills up.
- *
- * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
- * will be emitted under.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- LOOP_CLIPRECTS);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
aper_count = 0;
@@ -492,17 +487,14 @@ i830_emit_state(struct intel_context *intel)
}
if (dirty & I830_UPLOAD_BUFFERS) {
- GLuint count = 9;
+ GLuint count = 15;
DBG("I830_UPLOAD_BUFFERS:\n");
if (state->depth_region)
count += 3;
- if (intel->constant_cliprect)
- count += 6;
-
- BEGIN_BATCH(count, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
@@ -524,15 +516,13 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
- if (intel->constant_cliprect) {
- assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
- }
+ assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
ADVANCE_BATCH();
}
@@ -545,7 +535,7 @@ i830_emit_state(struct intel_context *intel)
if ((dirty & I830_UPLOAD_TEX(i))) {
DBG("I830_UPLOAD_TEX(%d):\n", i);
- BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
if (state->tex_buffer[i]) {
@@ -646,8 +636,9 @@ i830_state_draw_region(struct intel_context *intel,
DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
if (irb != NULL) {
- switch (irb->texformat->MesaFormat) {
+ switch (irb->Base.Format) {
case MESA_FORMAT_ARGB8888:
+ case MESA_FORMAT_XRGB8888:
value |= DV_PF_8888;
break;
case MESA_FORMAT_RGB565:
@@ -661,7 +652,7 @@ i830_state_draw_region(struct intel_context *intel,
break;
default:
_mesa_problem(ctx, "Bad renderbuffer format: %d\n",
- irb->texformat->MesaFormat);
+ irb->Base.Format);
}
}
@@ -673,23 +664,14 @@ i830_state_draw_region(struct intel_context *intel,
}
state->Buffer[I830_DESTREG_DV1] = value;
- if (intel->constant_cliprect) {
- state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
- state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
- state->Buffer[I830_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
- } else {
- state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
- }
+ state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
+ state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
+ state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I830_DESTREG_DRAWRECT3] =
+ (ctx->DrawBuffer->Width & 0xffff) |
+ (ctx->DrawBuffer->Height << 16);
+ state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
+ state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
@@ -714,20 +696,8 @@ i830_new_batch(struct intel_context *intel)
{
struct i830_context *i830 = i830_context(&intel->ctx);
i830->state.emitted = 0;
-
- /* Check that we didn't just wrap our batchbuffer at a bad time. */
- assert(!intel->no_batch_wrap);
-}
-
-
-
-static GLuint
-i830_flush_cmd(void)
-{
- return MI_FLUSH | FLUSH_MAP_CACHE;
}
-
static void
i830_assert_not_dirty( struct intel_context *intel )
{
@@ -753,7 +723,6 @@ i830InitVtbl(struct i830_context *i830)
i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
i830->intel.vtbl.set_draw_region = i830_set_draw_region;
i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
- i830->intel.vtbl.flush_cmd = i830_flush_cmd;
i830->intel.vtbl.render_start = i830_render_start;
i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 7d4c7cfbab..7c7711da09 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -100,7 +100,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[];
GLboolean
i915CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
@@ -143,6 +143,9 @@ i915CreateContext(const __GLcontextModes * mesaVis,
ctx->Const.MaxTextureImageUnits = I915_TEX_UNITS;
ctx->Const.MaxTextureCoordUnits = I915_TEX_UNITS;
ctx->Const.MaxVarying = I915_TEX_UNITS;
+ ctx->Const.MaxCombinedTextureImageUnits =
+ ctx->Const.MaxVertexTextureImageUnits +
+ ctx->Const.MaxTextureImageUnits;
/* Advertise the full hardware capabilities. The new memory
* manager should cope much better with overload situations:
diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h
index 082d614442..f55b551139 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -39,6 +39,7 @@
#define I915_FALLBACK_LOGICOP 0x20000
#define I915_FALLBACK_POLYGON_SMOOTH 0x40000
#define I915_FALLBACK_POINT_SMOOTH 0x80000
+#define I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN 0x100000
#define I915_UPLOAD_CTX 0x1
#define I915_UPLOAD_BUFFERS 0x2
@@ -317,7 +318,7 @@ do { \
* i915_context.c
*/
extern GLboolean i915CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate);
diff --git a/src/mesa/drivers/dri/i915/i915_debug.c b/src/mesa/drivers/dri/i915/i915_debug.c
index f7bb7ea44c..fecfac3033 100644
--- a/src/mesa/drivers/dri/i915/i915_debug.c
+++ b/src/mesa/drivers/dri/i915/i915_debug.c
@@ -806,6 +806,7 @@ static GLboolean i915_debug_packet( struct debug_stream *stream )
default:
return debug(stream, "", 0);
}
+ break;
default:
assert(0);
return 0;
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index d9c61446f5..a273bd28ea 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -663,7 +663,7 @@ upload_program(struct i915_fragment_program *p)
A0_MOV,
get_result_vector(p, inst),
get_result_flags(inst), 0,
- swizzle(src0, ZERO, ZERO, ZERO, ZERO), 0, 0);
+ swizzle(tmp, ZERO, ZERO, ZERO, ZERO), 0, 0);
case OPCODE_POW:
src0 = src_vector(p, &inst->SrcReg[0], program);
@@ -1301,7 +1301,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
if (inputsRead & FRAG_BIT_TEX(i)) {
- int sz = VB->TexCoordPtr[i]->size;
+ int sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(sz));
diff --git a/src/mesa/drivers/dri/i915/i915_program.c b/src/mesa/drivers/dri/i915/i915_program.c
index e7908bd48f..3902c69097 100644
--- a/src/mesa/drivers/dri/i915/i915_program.c
+++ b/src/mesa/drivers/dri/i915/i915_program.c
@@ -245,7 +245,7 @@ GLuint i915_emit_texld( struct i915_fragment_program *p,
}
else {
assert(GET_UREG_TYPE(dest) != REG_TYPE_CONST);
- assert(dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)));
+ assert(dest == UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)));
/* Can't use unsaved temps for coords, as the phase boundary would result
* in the contents becoming undefined.
*/
diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index b5fa7fddb9..7f31ff674f 100644
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -626,9 +626,9 @@
#define MT_32BIT_AWVU2101010 (0xA<<3)
#define MT_32BIT_GR1616 (0xB<<3)
#define MT_32BIT_VU1616 (0xC<<3)
-#define MT_32BIT_xI824 (0xD<<3)
-#define MT_32BIT_xA824 (0xE<<3)
-#define MT_32BIT_xL824 (0xF<<3)
+#define MT_32BIT_x8I24 (0xD<<3)
+#define MT_32BIT_x8L24 (0xE<<3)
+#define MT_32BIT_x8A24 (0xF<<3)
#define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */
#define MT_422_YCRCB_NORMAL (1<<3)
#define MT_422_YCRCB_SWAPUV (2<<3)
diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c
index b60efea75b..9d7a9e1dfe 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -571,7 +571,7 @@ i915LineWidth(GLcontext * ctx, GLfloat widthf)
DBG("%s\n", __FUNCTION__);
width = (int) (widthf * 2);
- CLAMP_SELF(width, 1, 0xf);
+ width = CLAMP(width, 1, 0xf);
lis4 |= width << S4_LINE_WIDTH_SHIFT;
if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
@@ -585,11 +585,11 @@ i915PointSize(GLcontext * ctx, GLfloat size)
{
struct i915_context *i915 = I915_CONTEXT(ctx);
int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_POINT_WIDTH_MASK;
- GLint point_size = (int) size;
+ GLint point_size = (int) round(size);
DBG("%s\n", __FUNCTION__);
- CLAMP_SELF(point_size, 1, 255);
+ point_size = CLAMP(point_size, 1, 255);
lis4 |= point_size << S4_POINT_WIDTH_SHIFT;
if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
@@ -599,6 +599,24 @@ i915PointSize(GLcontext * ctx, GLfloat size)
}
+static void
+i915PointParameterfv(GLcontext * ctx, GLenum pname, const GLfloat *params)
+{
+ struct i915_context *i915 = I915_CONTEXT(ctx);
+
+ switch (pname) {
+ case GL_POINT_SPRITE_COORD_ORIGIN:
+ /* This could be supported, but it would require modifying the fragment
+ * program to invert the y component of the texture coordinate by
+ * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
+ */
+ FALLBACK(&i915->intel, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN,
+ (params[0] != GL_UPPER_LEFT));
+ break;
+ }
+}
+
+
/* =============================================================
* Color masks
*/
@@ -939,6 +957,17 @@ i915Enable(GLcontext * ctx, GLenum cap, GLboolean state)
case GL_POLYGON_SMOOTH:
break;
+ case GL_POINT_SPRITE:
+ /* This state change is handled in i915_reduced_primitive_state because
+ * the hardware bit should only be set when rendering points.
+ */
+ I915_STATECHANGE(i915, I915_UPLOAD_CTX);
+ if (state)
+ i915->state.Ctx[I915_CTXREG_LIS4] |= S4_SPRITE_POINT_ENABLE;
+ else
+ i915->state.Ctx[I915_CTXREG_LIS4] &= ~S4_SPRITE_POINT_ENABLE;
+ break;
+
case GL_POINT_SMOOTH:
break;
@@ -1108,6 +1137,7 @@ i915InitStateFunctions(struct dd_function_table *functions)
functions->LineWidth = i915LineWidth;
functions->LogicOpcode = i915LogicOp;
functions->PointSize = i915PointSize;
+ functions->PointParameterfv = i915PointParameterfv;
functions->PolygonStipple = i915PolygonStipple;
functions->Scissor = i915Scissor;
functions->ShadeModel = i915ShadeModel;
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 32d4b30cf9..3ee4c8653a 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -27,7 +27,8 @@
#include "main/mtypes.h"
#include "main/enums.h"
-#include "main/texformat.h"
+#include "main/macros.h"
+#include "main/colormac.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
@@ -37,7 +38,7 @@
static GLuint
-translate_texture_format(GLuint mesa_format, GLuint internal_format,
+translate_texture_format(gl_format mesa_format, GLuint internal_format,
GLenum DepthMode)
{
switch (mesa_format) {
@@ -56,10 +57,9 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format,
case MESA_FORMAT_ARGB4444:
return MAPSURF_16BIT | MT_16BIT_ARGB4444;
case MESA_FORMAT_ARGB8888:
- if (internal_format == GL_RGB)
- return MAPSURF_32BIT | MT_32BIT_XRGB8888;
- else
- return MAPSURF_32BIT | MT_32BIT_ARGB8888;
+ return MAPSURF_32BIT | MT_32BIT_ARGB8888;
+ case MESA_FORMAT_XRGB8888:
+ return MAPSURF_32BIT | MT_32BIT_XRGB8888;
case MESA_FORMAT_YCBCR_REV:
return (MAPSURF_422 | MT_422_YCRCB_NORMAL);
case MESA_FORMAT_YCBCR:
@@ -82,7 +82,12 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format,
case MESA_FORMAT_RGBA_DXT5:
return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT4_5);
case MESA_FORMAT_S8_Z24:
- return (MAPSURF_32BIT | MT_32BIT_xI824);
+ if (DepthMode == GL_ALPHA)
+ return (MAPSURF_32BIT | MT_32BIT_x8A24);
+ else if (DepthMode == GL_INTENSITY)
+ return (MAPSURF_32BIT | MT_32BIT_x8I24);
+ else
+ return (MAPSURF_32BIT | MT_32BIT_x8L24);
default:
fprintf(stderr, "%s: bad image format %x\n", __FUNCTION__, mesa_format);
abort();
@@ -134,6 +139,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
GLuint *state = i915->state.Tex[unit], format, pitch;
GLint lodbias, aniso = 0;
GLubyte border[4];
+ GLfloat maxlod;
memset(state, 0, sizeof(state));
@@ -173,11 +179,9 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
} else {
dri_bo_reference(intelObj->mt->region->buffer);
i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
- i915->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt,
- 0, intelObj->
- firstLevel);
+ i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */
- format = translate_texture_format(firstImage->TexFormat->MesaFormat,
+ format = translate_texture_format(firstImage->TexFormat,
firstImage->InternalFormat,
tObj->DepthMode);
pitch = intelObj->mt->pitch * intelObj->mt->cpp;
@@ -193,11 +197,16 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
state[I915_TEXREG_MS3] |= MS3_TILE_WALK;
}
+ /* We get one field with fraction bits for the maximum addressable
+ * (lowest resolution) LOD. Use it to cover both MAX_LEVEL and
+ * MAX_LOD.
+ */
+ maxlod = MIN2(tObj->MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
state[I915_TEXREG_MS4] =
- ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK |
- ((((intelObj->lastLevel - intelObj->firstLevel) * 4)) <<
- MS4_MAX_LOD_SHIFT) | ((firstImage->Depth - 1) <<
- MS4_VOLUME_DEPTH_SHIFT));
+ ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) |
+ MS4_CUBE_FACE_ENA_MASK |
+ (U_FIXED(CLAMP(maxlod, 0.0, 11.0), 2) << MS4_MAX_LOD_SHIFT) |
+ ((firstImage->Depth - 1) << MS4_VOLUME_DEPTH_SHIFT));
{
@@ -263,8 +272,8 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
/* YUV conversion:
*/
- if (firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR ||
- firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR_REV)
+ if (firstImage->TexFormat == MESA_FORMAT_YCBCR ||
+ firstImage->TexFormat == MESA_FORMAT_YCBCR_REV)
state[I915_TEXREG_SS2] |= SS2_COLORSPACE_CONVERSION;
/* Shadow:
@@ -293,6 +302,12 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
GLenum wt = tObj->WrapT;
GLenum wr = tObj->WrapR;
+ /* We program 1D textures as 2D textures, so the 2D texcoord could
+ * result in sampling border values if we don't set the T wrap to
+ * repeat.
+ */
+ if (tObj->Target == GL_TEXTURE_1D)
+ wt = GL_REPEAT;
/* 3D textures don't seem to respect the border color.
* Fallback if there's ever a danger that they might refer to
@@ -327,28 +342,31 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
(translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT));
state[I915_TEXREG_SS3] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT);
+ state[I915_TEXREG_SS3] |= (U_FIXED(CLAMP(tObj->MinLod, 0.0, 11.0), 4) <<
+ SS3_MIN_LOD_SHIFT);
+
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]);
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
/* GL specs that border color for depth textures is taken from the
* R channel, while the hardware uses A. Spam R into all the channels
* for safety.
*/
- state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(border[0],
- border[0],
- border[0],
- border[0]);
+ state[I915_TEXREG_SS4] = PACK_COLOR_8888(border[0],
+ border[0],
+ border[0],
+ border[0]);
} else {
- state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(border[0],
- border[1],
- border[2],
- border[3]);
+ state[I915_TEXREG_SS4] = PACK_COLOR_8888(border[3],
+ border[0],
+ border[1],
+ border[2]);
}
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 9e2523932f..266e6848c3 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -32,7 +32,6 @@
#include "main/imports.h"
#include "main/macros.h"
#include "main/colormac.h"
-#include "main/texformat.h"
#include "tnl/t_context.h"
#include "tnl/t_vertex.h"
@@ -175,7 +174,7 @@ i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(17, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(17);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
@@ -221,7 +220,7 @@ i915_emit_invarient_state(struct intel_context *intel)
#define emit(intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
+ intel_batchbuffer_data(intel->batch, state, size)
static GLuint
get_dirty(struct i915_hw_state *state)
@@ -302,13 +301,9 @@ i915_emit_state(struct intel_context *intel)
* It might be better to talk about explicit places where
* scheduling is allowed, rather than assume that it is whenever a
* batchbuffer fills up.
- *
- * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
- * will be emitted under.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- LOOP_CLIPRECTS);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
aper_count = 0;
@@ -374,7 +369,7 @@ i915_emit_state(struct intel_context *intel)
}
if (dirty & I915_UPLOAD_BUFFERS) {
- GLuint count = 9;
+ GLuint count = 15;
if (INTEL_DEBUG & DEBUG_STATE)
fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
@@ -382,10 +377,7 @@ i915_emit_state(struct intel_context *intel)
if (state->depth_region)
count += 3;
- if (intel->constant_cliprect)
- count += 6;
-
- BEGIN_BATCH(count, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
@@ -407,15 +399,13 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
- if (intel->constant_cliprect) {
- assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
- }
+ assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
ADVANCE_BATCH();
}
@@ -442,7 +432,7 @@ i915_emit_state(struct intel_context *intel)
if (dirty & I915_UPLOAD_TEX(i))
nr++;
- BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2 + nr * 3);
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -466,7 +456,7 @@ i915_emit_state(struct intel_context *intel)
}
ADVANCE_BATCH();
- BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2 + nr * 3);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -588,8 +578,9 @@ i915_state_draw_region(struct intel_context *intel,
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
if (irb != NULL) {
- switch (irb->texformat->MesaFormat) {
+ switch (irb->Base.Format) {
case MESA_FORMAT_ARGB8888:
+ case MESA_FORMAT_XRGB8888:
value |= DV_PF_8888;
break;
case MESA_FORMAT_RGB565:
@@ -603,7 +594,7 @@ i915_state_draw_region(struct intel_context *intel,
break;
default:
_mesa_problem(ctx, "Bad renderbuffer format: %d\n",
- irb->texformat->MesaFormat);
+ irb->Base.Format);
}
}
@@ -611,7 +602,7 @@ i915_state_draw_region(struct intel_context *intel,
* the value of this bit, the pipeline needs to be MI_FLUSHed. And it
* can only be set when a depth buffer is already defined.
*/
- if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
+ if (intel->is_945 && intel->use_early_z &&
depth_region->tiling != I915_TILING_NONE)
value |= CLASSIC_EARLY_DEPTH;
@@ -623,23 +614,14 @@ i915_state_draw_region(struct intel_context *intel,
}
state->Buffer[I915_DESTREG_DV1] = value;
- if (intel->constant_cliprect) {
- state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
- state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
- state->Buffer[I915_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
- } else {
- state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
- }
+ state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
+ state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
+ state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I915_DESTREG_DRAWRECT3] =
+ (ctx->DrawBuffer->Width & 0xffff) |
+ (ctx->DrawBuffer->Height << 16);
+ state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
+ state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
}
@@ -667,15 +649,6 @@ i915_new_batch(struct intel_context *intel)
* difficulties associated with them (physical address requirements).
*/
i915->state.emitted = 0;
-
- /* Check that we didn't just wrap our batchbuffer at a bad time. */
- assert(!intel->no_batch_wrap);
-}
-
-static GLuint
-i915_flush_cmd(void)
-{
- return MI_FLUSH | FLUSH_MAP_CACHE;
}
static void
@@ -699,7 +672,6 @@ i915InitVtbl(struct i915_context *i915)
i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
i915->intel.vtbl.set_draw_region = i915_set_draw_region;
i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
- i915->intel.vtbl.flush_cmd = i915_flush_cmd;
i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
i915->intel.vtbl.finish_batch = intel_finish_vb;
}
diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c
index 410052b3c2..ec209391ab 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -117,7 +117,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim)
intel_set_prim(intel, hw_prim[prim]);
}
-static inline GLuint intel_get_vb_max(struct intel_context *intel)
+static INLINE GLuint intel_get_vb_max(struct intel_context *intel)
{
GLuint ret;
@@ -129,7 +129,7 @@ static inline GLuint intel_get_vb_max(struct intel_context *intel)
return ret;
}
-static inline GLuint intel_get_current_max(struct intel_context *intel)
+static INLINE GLuint intel_get_current_max(struct intel_context *intel)
{
if (intel->intelScreen->no_vbo)
diff --git a/src/mesa/drivers/dri/i915/intel_swapbuffers.c b/src/mesa/drivers/dri/i915/intel_swapbuffers.c
deleted file mode 120000
index 148d5215aa..0000000000
--- a/src/mesa/drivers/dri/i915/intel_swapbuffers.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_swapbuffers.c \ No newline at end of file
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 0641e6df9d..e99baf8e0e 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -89,7 +89,6 @@ intel_flush_inline_primitive(struct intel_context *intel)
static void intel_start_inline(struct intel_context *intel, uint32_t prim)
{
- uint32_t batch_flags = LOOP_CLIPRECTS;
BATCH_LOCALS;
intel->vtbl.emit_state(intel);
@@ -101,7 +100,7 @@ static void intel_start_inline(struct intel_context *intel, uint32_t prim)
/* Emit a slot which will be filled with the inline primitive
* command later.
*/
- BEGIN_BATCH(2, batch_flags);
+ BEGIN_BATCH(2);
OUT_BATCH(0);
assert((intel->batch->dirty_state & (1<<1)) == 0);
@@ -221,7 +220,7 @@ void intel_flush_prim(struct intel_context *intel)
intel->prim.count = 0;
offset = intel->prim.start_offset;
intel->prim.start_offset = intel->prim.current_offset;
- if (!IS_9XX(intel->intelScreen->deviceID))
+ if (!intel->gen >= 3)
intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128);
intel->prim.flush = NULL;
@@ -251,8 +250,8 @@ void intel_flush_prim(struct intel_context *intel)
intel->vertex_size * 4);
#endif
- if (IS_9XX(intel->intelScreen->deviceID)) {
- BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ if (intel->gen >= 3) {
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
assert((offset & !S0_VB_OFFSET_MASK) == 0);
@@ -270,7 +269,7 @@ void intel_flush_prim(struct intel_context *intel)
} else {
struct i830_context *i830 = i830_context(&intel->ctx);
- BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(2) | 1);
/* S0 */
@@ -1088,6 +1087,7 @@ intelRenderStart(GLcontext * ctx)
{
struct intel_context *intel = intel_context(ctx);
+ intel_check_front_buffer_rendering(intel);
intel->vtbl.render_start(intel_context(ctx));
intel->vtbl.emit_state(intel);
}
@@ -1196,12 +1196,16 @@ getFallbackString(GLuint bit)
+/**
+ * Enable/disable a fallback flag.
+ * \param bit one of INTEL_FALLBACK_x flags.
+ */
void
-intelFallback(struct intel_context *intel, GLuint bit, GLboolean mode)
+intelFallback(struct intel_context *intel, GLbitfield bit, GLboolean mode)
{
GLcontext *ctx = &intel->ctx;
TNLcontext *tnl = TNL_CONTEXT(ctx);
- GLuint oldfallback = intel->Fallback;
+ const GLbitfield oldfallback = intel->Fallback;
if (mode) {
intel->Fallback |= bit;
@@ -1245,81 +1249,6 @@ union fi
GLint i;
};
-
-/**********************************************************************/
-/* Used only with the metaops callbacks. */
-/**********************************************************************/
-static void
-intel_meta_draw_poly(struct intel_context *intel,
- GLuint n,
- GLfloat xy[][2],
- GLfloat z, GLuint color, GLfloat tex[][2])
-{
- union fi *vb;
- GLint i;
- unsigned int saved_vertex_size = intel->vertex_size;
-
- LOCK_HARDWARE(intel);
-
- intel->vertex_size = 6;
-
- /* All 3d primitives should be emitted with LOOP_CLIPRECTS,
- * otherwise the drawing origin (DR4) might not be set correctly.
- */
- intel_set_prim(intel, PRIM3D_TRIFAN);
- vb = (union fi *) intel_get_prim_space(intel, n);
-
- for (i = 0; i < n; i++) {
- vb[0].f = xy[i][0];
- vb[1].f = xy[i][1];
- vb[2].f = z;
- vb[3].i = color;
- vb[4].f = tex[i][0];
- vb[5].f = tex[i][1];
- vb += 6;
- }
-
- INTEL_FIREVERTICES(intel);
-
- intel->vertex_size = saved_vertex_size;
-
- UNLOCK_HARDWARE(intel);
-}
-
-static void
-intel_meta_draw_quad(struct intel_context *intel,
- GLfloat x0, GLfloat x1,
- GLfloat y0, GLfloat y1,
- GLfloat z,
- GLuint color,
- GLfloat s0, GLfloat s1, GLfloat t0, GLfloat t1)
-{
- GLfloat xy[4][2];
- GLfloat tex[4][2];
-
- xy[0][0] = x0;
- xy[0][1] = y0;
- xy[1][0] = x1;
- xy[1][1] = y0;
- xy[2][0] = x1;
- xy[2][1] = y1;
- xy[3][0] = x0;
- xy[3][1] = y1;
-
- tex[0][0] = s0;
- tex[0][1] = t0;
- tex[1][0] = s1;
- tex[1][1] = t0;
- tex[2][0] = s1;
- tex[2][1] = t1;
- tex[3][0] = s0;
- tex[3][1] = t1;
-
- intel_meta_draw_poly(intel, 4, xy, z, color, tex);
-}
-
-
-
/**********************************************************************/
/* Initialization. */
/**********************************************************************/
@@ -1328,7 +1257,6 @@ intel_meta_draw_quad(struct intel_context *intel,
void
intelInitTriFuncs(GLcontext * ctx)
{
- struct intel_context *intel = intel_context(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
static int firsttime = 1;
@@ -1345,6 +1273,4 @@ intelInitTriFuncs(GLcontext * ctx)
tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
-
- intel->vtbl.meta_draw_quad = intel_meta_draw_quad;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 07:44:32 +0000