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-rw-r--r--src/mesa/drivers/dri/i915/Makefile4
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.c2
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.h2
-rw-r--r--src/mesa/drivers/dri/i915/i830_state.c4
-rw-r--r--src/mesa/drivers/dri/i915/i830_texstate.c20
-rw-r--r--src/mesa/drivers/dri/i915/i830_vtbl.c67
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.c5
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.h2
-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c4
-rw-r--r--src/mesa/drivers/dri/i915/i915_state.c4
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c25
-rw-r--r--src/mesa/drivers/dri/i915/i915_vtbl.c69
l---------src/mesa/drivers/dri/i915/intel_swapbuffers.c1
-rw-r--r--src/mesa/drivers/dri/i915/intel_tris.c89
14 files changed, 88 insertions, 210 deletions
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 37f15aa767..cf32476f40 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -34,7 +34,6 @@ DRIVER_SOURCES = \
intel_pixel_read.c \
intel_buffers.c \
intel_blit.c \
- intel_swapbuffers.c \
i915_tex_layout.c \
i915_texstate.c \
i915_context.c \
@@ -64,7 +63,8 @@ DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \
$(shell pkg-config libdrm --atleast-version=2.3.1 \
&& echo "-DDRM_VBLANK_FLIP=DRM_VBLANK_FLIP")
-DRI_LIB_DEPS += -ldrm_intel
+INCLUDES += $(INTEL_CFLAGS)
+DRI_LIB_DEPS += $(INTEL_LIBS)
include ../Makefile.template
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index 7be18cb65a..947330b2f1 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -50,7 +50,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[];
GLboolean
i830CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h
index f73cbbf88b..592ae53976 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -178,7 +178,7 @@ i830_state_draw_region(struct intel_context *intel,
*/
extern GLboolean
i830CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate);
/* i830_tex.c, i830_texstate.c
diff --git a/src/mesa/drivers/dri/i915/i830_state.c b/src/mesa/drivers/dri/i915/i830_state.c
index 645ebe3057..acda7e70de 100644
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -620,7 +620,7 @@ i830LineWidth(GLcontext * ctx, GLfloat widthf)
DBG("%s\n", __FUNCTION__);
width = (int) (widthf * 2);
- CLAMP_SELF(width, 1, 15);
+ width = CLAMP(width, 1, 15);
state5 = i830->state.Ctx[I830_CTXREG_STATE5] & ~FIXED_LINE_WIDTH_MASK;
state5 |= (ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(width));
@@ -639,7 +639,7 @@ i830PointSize(GLcontext * ctx, GLfloat size)
DBG("%s\n", __FUNCTION__);
- CLAMP_SELF(point_size, 1, 256);
+ point_size = CLAMP(point_size, 1, 256);
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
i830->state.Ctx[I830_CTXREG_STATE5] &= ~FIXED_POINT_WIDTH_MASK;
i830->state.Ctx[I830_CTXREG_STATE5] |= (ENABLE_FIXED_POINT_WIDTH |
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index ce409b3a60..7525f9f2e0 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -27,6 +27,7 @@
#include "main/mtypes.h"
#include "main/enums.h"
+#include "main/colormac.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
@@ -303,16 +304,15 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]);
-
- state[I830_TEXREG_TM0S4] = INTEL_PACKCOLOR8888(border[0],
- border[1],
- border[2],
- border[3]);
-
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
+
+ state[I830_TEXREG_TM0S4] = PACK_COLOR_8888(border[3],
+ border[0],
+ border[1],
+ border[2]);
I830_ACTIVESTATE(i830, I830_UPLOAD_TEX(unit), GL_TRUE);
/* memcmp was already disabled, but definitely won't work as the
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index e8c8d5a048..3767712d19 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -25,8 +25,6 @@
*
**************************************************************************/
-#include "glapi/glapi.h"
-
#include "i830_context.h"
#include "i830_reg.h"
#include "intel_batchbuffer.h"
@@ -126,7 +124,7 @@ i830_render_start(struct intel_context *intel)
for (i = 0; i < I830_TEX_UNITS; i++) {
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
- GLuint sz = VB->TexCoordPtr[i]->size;
+ GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
GLuint emit;
GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
~TEXCOORDTYPE_MASK);
@@ -298,7 +296,7 @@ i830_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(29, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(29);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
@@ -366,7 +364,7 @@ i830_emit_invarient_state(struct intel_context *intel)
#define emit( intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
+ intel_batchbuffer_data(intel->batch, state, size )
static GLuint
get_dirty(struct i830_hw_state *state)
@@ -429,13 +427,9 @@ i830_emit_state(struct intel_context *intel)
* It might be better to talk about explicit places where
* scheduling is allowed, rather than assume that it is whenever a
* batchbuffer fills up.
- *
- * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
- * will be emitted under.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- LOOP_CLIPRECTS);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
aper_count = 0;
@@ -491,17 +485,14 @@ i830_emit_state(struct intel_context *intel)
}
if (dirty & I830_UPLOAD_BUFFERS) {
- GLuint count = 9;
+ GLuint count = 15;
DBG("I830_UPLOAD_BUFFERS:\n");
if (state->depth_region)
count += 3;
- if (intel->constant_cliprect)
- count += 6;
-
- BEGIN_BATCH(count, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
@@ -523,15 +514,13 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
- if (intel->constant_cliprect) {
- assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
- }
+ assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
ADVANCE_BATCH();
}
@@ -544,7 +533,7 @@ i830_emit_state(struct intel_context *intel)
if ((dirty & I830_UPLOAD_TEX(i))) {
DBG("I830_UPLOAD_TEX(%d):\n", i);
- BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
if (state->tex_buffer[i]) {
@@ -673,23 +662,14 @@ i830_state_draw_region(struct intel_context *intel,
}
state->Buffer[I830_DESTREG_DV1] = value;
- if (intel->constant_cliprect) {
- state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
- state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
- state->Buffer[I830_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
- } else {
- state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
- }
+ state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
+ state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
+ state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I830_DESTREG_DRAWRECT3] =
+ (ctx->DrawBuffer->Width & 0xffff) |
+ (ctx->DrawBuffer->Height << 16);
+ state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
+ state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
@@ -714,9 +694,6 @@ i830_new_batch(struct intel_context *intel)
{
struct i830_context *i830 = i830_context(&intel->ctx);
i830->state.emitted = 0;
-
- /* Check that we didn't just wrap our batchbuffer at a bad time. */
- assert(!intel->no_batch_wrap);
}
static void
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 4767016487..8477e2f9a4 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -95,7 +95,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[];
GLboolean
i915CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
@@ -138,6 +138,9 @@ i915CreateContext(const __GLcontextModes * mesaVis,
ctx->Const.MaxTextureImageUnits = I915_TEX_UNITS;
ctx->Const.MaxTextureCoordUnits = I915_TEX_UNITS;
ctx->Const.MaxVarying = I915_TEX_UNITS;
+ ctx->Const.MaxCombinedTextureImageUnits =
+ ctx->Const.MaxVertexTextureImageUnits +
+ ctx->Const.MaxTextureImageUnits;
/* Advertise the full hardware capabilities. The new memory
* manager should cope much better with overload situations:
diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h
index 25418d5f7a..f55b551139 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -318,7 +318,7 @@ do { \
* i915_context.c
*/
extern GLboolean i915CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate);
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index d9c61446f5..a273bd28ea 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -663,7 +663,7 @@ upload_program(struct i915_fragment_program *p)
A0_MOV,
get_result_vector(p, inst),
get_result_flags(inst), 0,
- swizzle(src0, ZERO, ZERO, ZERO, ZERO), 0, 0);
+ swizzle(tmp, ZERO, ZERO, ZERO, ZERO), 0, 0);
case OPCODE_POW:
src0 = src_vector(p, &inst->SrcReg[0], program);
@@ -1301,7 +1301,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
if (inputsRead & FRAG_BIT_TEX(i)) {
- int sz = VB->TexCoordPtr[i]->size;
+ int sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(sz));
diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c
index cc98d125db..9d7a9e1dfe 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -571,7 +571,7 @@ i915LineWidth(GLcontext * ctx, GLfloat widthf)
DBG("%s\n", __FUNCTION__);
width = (int) (widthf * 2);
- CLAMP_SELF(width, 1, 0xf);
+ width = CLAMP(width, 1, 0xf);
lis4 |= width << S4_LINE_WIDTH_SHIFT;
if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
@@ -589,7 +589,7 @@ i915PointSize(GLcontext * ctx, GLfloat size)
DBG("%s\n", __FUNCTION__);
- CLAMP_SELF(point_size, 1, 255);
+ point_size = CLAMP(point_size, 1, 255);
lis4 |= point_size << S4_POINT_WIDTH_SHIFT;
if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 825f1dbbe3..3ee4c8653a 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -28,6 +28,7 @@
#include "main/mtypes.h"
#include "main/enums.h"
#include "main/macros.h"
+#include "main/colormac.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
@@ -347,25 +348,25 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]);
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
/* GL specs that border color for depth textures is taken from the
* R channel, while the hardware uses A. Spam R into all the channels
* for safety.
*/
- state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(border[0],
- border[0],
- border[0],
- border[0]);
+ state[I915_TEXREG_SS4] = PACK_COLOR_8888(border[0],
+ border[0],
+ border[0],
+ border[0]);
} else {
- state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(border[0],
- border[1],
- border[2],
- border[3]);
+ state[I915_TEXREG_SS4] = PACK_COLOR_8888(border[3],
+ border[0],
+ border[1],
+ border[2]);
}
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 668e02ef70..933a565f02 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -45,8 +45,6 @@
#include "i915_reg.h"
#include "i915_context.h"
-#include "glapi/glapi.h"
-
static void
i915_render_prevalidate(struct intel_context *intel)
{
@@ -173,7 +171,7 @@ i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(17, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(17);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
@@ -219,7 +217,7 @@ i915_emit_invarient_state(struct intel_context *intel)
#define emit(intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
+ intel_batchbuffer_data(intel->batch, state, size)
static GLuint
get_dirty(struct i915_hw_state *state)
@@ -300,13 +298,9 @@ i915_emit_state(struct intel_context *intel)
* It might be better to talk about explicit places where
* scheduling is allowed, rather than assume that it is whenever a
* batchbuffer fills up.
- *
- * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
- * will be emitted under.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- LOOP_CLIPRECTS);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
aper_count = 0;
@@ -372,7 +366,7 @@ i915_emit_state(struct intel_context *intel)
}
if (dirty & I915_UPLOAD_BUFFERS) {
- GLuint count = 9;
+ GLuint count = 15;
if (INTEL_DEBUG & DEBUG_STATE)
fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
@@ -380,10 +374,7 @@ i915_emit_state(struct intel_context *intel)
if (state->depth_region)
count += 3;
- if (intel->constant_cliprect)
- count += 6;
-
- BEGIN_BATCH(count, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
@@ -405,15 +396,13 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
- if (intel->constant_cliprect) {
- assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
- }
+ assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
ADVANCE_BATCH();
}
@@ -440,7 +429,7 @@ i915_emit_state(struct intel_context *intel)
if (dirty & I915_UPLOAD_TEX(i))
nr++;
- BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2 + nr * 3);
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -464,7 +453,7 @@ i915_emit_state(struct intel_context *intel)
}
ADVANCE_BATCH();
- BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2 + nr * 3);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -610,7 +599,7 @@ i915_state_draw_region(struct intel_context *intel,
* the value of this bit, the pipeline needs to be MI_FLUSHed. And it
* can only be set when a depth buffer is already defined.
*/
- if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
+ if (intel->is_945 && intel->use_early_z &&
depth_region->tiling != I915_TILING_NONE)
value |= CLASSIC_EARLY_DEPTH;
@@ -622,23 +611,14 @@ i915_state_draw_region(struct intel_context *intel,
}
state->Buffer[I915_DESTREG_DV1] = value;
- if (intel->constant_cliprect) {
- state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
- state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
- state->Buffer[I915_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
- } else {
- state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
- }
+ state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
+ state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
+ state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I915_DESTREG_DRAWRECT3] =
+ (ctx->DrawBuffer->Width & 0xffff) |
+ (ctx->DrawBuffer->Height << 16);
+ state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
+ state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
}
@@ -666,9 +646,6 @@ i915_new_batch(struct intel_context *intel)
* difficulties associated with them (physical address requirements).
*/
i915->state.emitted = 0;
-
- /* Check that we didn't just wrap our batchbuffer at a bad time. */
- assert(!intel->no_batch_wrap);
}
static void
diff --git a/src/mesa/drivers/dri/i915/intel_swapbuffers.c b/src/mesa/drivers/dri/i915/intel_swapbuffers.c
deleted file mode 120000
index 148d5215aa..0000000000
--- a/src/mesa/drivers/dri/i915/intel_swapbuffers.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_swapbuffers.c \ No newline at end of file
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 65db947aee..763c1a0ae7 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -88,7 +88,6 @@ intel_flush_inline_primitive(struct intel_context *intel)
static void intel_start_inline(struct intel_context *intel, uint32_t prim)
{
- uint32_t batch_flags = LOOP_CLIPRECTS;
BATCH_LOCALS;
intel->vtbl.emit_state(intel);
@@ -100,7 +99,7 @@ static void intel_start_inline(struct intel_context *intel, uint32_t prim)
/* Emit a slot which will be filled with the inline primitive
* command later.
*/
- BEGIN_BATCH(2, batch_flags);
+ BEGIN_BATCH(2);
OUT_BATCH(0);
assert((intel->batch->dirty_state & (1<<1)) == 0);
@@ -220,7 +219,7 @@ void intel_flush_prim(struct intel_context *intel)
intel->prim.count = 0;
offset = intel->prim.start_offset;
intel->prim.start_offset = intel->prim.current_offset;
- if (!IS_9XX(intel->intelScreen->deviceID))
+ if (!intel->gen >= 3)
intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128);
intel->prim.flush = NULL;
@@ -250,8 +249,8 @@ void intel_flush_prim(struct intel_context *intel)
intel->vertex_size * 4);
#endif
- if (IS_9XX(intel->intelScreen->deviceID)) {
- BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ if (intel->gen >= 3) {
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
assert((offset & !S0_VB_OFFSET_MASK) == 0);
@@ -269,7 +268,7 @@ void intel_flush_prim(struct intel_context *intel)
} else {
struct i830_context *i830 = i830_context(&intel->ctx);
- BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(2) | 1);
/* S0 */
@@ -1249,81 +1248,6 @@ union fi
GLint i;
};
-
-/**********************************************************************/
-/* Used only with the metaops callbacks. */
-/**********************************************************************/
-static void
-intel_meta_draw_poly(struct intel_context *intel,
- GLuint n,
- GLfloat xy[][2],
- GLfloat z, GLuint color, GLfloat tex[][2])
-{
- union fi *vb;
- GLint i;
- unsigned int saved_vertex_size = intel->vertex_size;
-
- LOCK_HARDWARE(intel);
-
- intel->vertex_size = 6;
-
- /* All 3d primitives should be emitted with LOOP_CLIPRECTS,
- * otherwise the drawing origin (DR4) might not be set correctly.
- */
- intel_set_prim(intel, PRIM3D_TRIFAN);
- vb = (union fi *) intel_get_prim_space(intel, n);
-
- for (i = 0; i < n; i++) {
- vb[0].f = xy[i][0];
- vb[1].f = xy[i][1];
- vb[2].f = z;
- vb[3].i = color;
- vb[4].f = tex[i][0];
- vb[5].f = tex[i][1];
- vb += 6;
- }
-
- INTEL_FIREVERTICES(intel);
-
- intel->vertex_size = saved_vertex_size;
-
- UNLOCK_HARDWARE(intel);
-}
-
-static void
-intel_meta_draw_quad(struct intel_context *intel,
- GLfloat x0, GLfloat x1,
- GLfloat y0, GLfloat y1,
- GLfloat z,
- GLuint color,
- GLfloat s0, GLfloat s1, GLfloat t0, GLfloat t1)
-{
- GLfloat xy[4][2];
- GLfloat tex[4][2];
-
- xy[0][0] = x0;
- xy[0][1] = y0;
- xy[1][0] = x1;
- xy[1][1] = y0;
- xy[2][0] = x1;
- xy[2][1] = y1;
- xy[3][0] = x0;
- xy[3][1] = y1;
-
- tex[0][0] = s0;
- tex[0][1] = t0;
- tex[1][0] = s1;
- tex[1][1] = t0;
- tex[2][0] = s1;
- tex[2][1] = t1;
- tex[3][0] = s0;
- tex[3][1] = t1;
-
- intel_meta_draw_poly(intel, 4, xy, z, color, tex);
-}
-
-
-
/**********************************************************************/
/* Initialization. */
/**********************************************************************/
@@ -1332,7 +1256,6 @@ intel_meta_draw_quad(struct intel_context *intel,
void
intelInitTriFuncs(GLcontext * ctx)
{
- struct intel_context *intel = intel_context(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
static int firsttime = 1;
@@ -1349,6 +1272,4 @@ intelInitTriFuncs(GLcontext * ctx)
tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
-
- intel->vtbl.meta_draw_quad = intel_meta_draw_quad;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-29 14:57:32 +0000