diff options
Diffstat (limited to 'src/mesa/drivers/dri/i915tex')
23 files changed, 276 insertions, 256 deletions
diff --git a/src/mesa/drivers/dri/i915tex/i830_reg.h b/src/mesa/drivers/dri/i915tex/i830_reg.h index 24ac524500..41280bca7c 100644 --- a/src/mesa/drivers/dri/i915tex/i830_reg.h +++ b/src/mesa/drivers/dri/i915tex/i830_reg.h @@ -575,6 +575,7 @@ #define MT_16BIT_DIB_RGB565_8888 (7<<3) #define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */ #define MT_32BIT_ABGR8888 (1<<3) +#define MT_32BIT_XRGB8888 (2<<3) /* XXX: Guess from i915_reg.h */ #define MT_32BIT_BUMP_XLDVDU_8888 (6<<3) #define MT_32BIT_DIB_8888 (7<<3) #define MT_411_YUV411 (0<<3) /* SURFACE_411 */ diff --git a/src/mesa/drivers/dri/i915tex/i830_state.c b/src/mesa/drivers/dri/i915tex/i830_state.c index 812daa6524..3c149e6905 100644 --- a/src/mesa/drivers/dri/i915tex/i830_state.c +++ b/src/mesa/drivers/dri/i915tex/i830_state.c @@ -34,6 +34,8 @@ #include "texmem.h" +#include "drivers/common/driverfuncs.h" + #include "intel_screen.h" #include "intel_batchbuffer.h" #include "intel_fbo.h" @@ -1101,7 +1103,7 @@ i830InitState(struct i830_context *i830) i830_init_packets(i830); - intelInitState(ctx); + _mesa_init_driver_state(ctx); memcpy(&i830->initial, &i830->state, sizeof(i830->state)); diff --git a/src/mesa/drivers/dri/i915tex/i830_texstate.c b/src/mesa/drivers/dri/i915tex/i830_texstate.c index e3f34e3944..0d3f053226 100644 --- a/src/mesa/drivers/dri/i915tex/i830_texstate.c +++ b/src/mesa/drivers/dri/i915tex/i830_texstate.c @@ -117,7 +117,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); struct gl_texture_image *firstImage; - GLuint *state = i830->state.Tex[unit]; + GLuint *state = i830->state.Tex[unit], format, pitch; memset(state, 0, sizeof(state)); @@ -128,7 +128,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) i830->state.tex_buffer[unit] = NULL; } - if (!intel_finalize_mipmap_tree(intel, unit)) + if (!intelObj->imageOverride && !intel_finalize_mipmap_tree(intel, unit)) return GL_FALSE; /* Get first image here, since intelObj->firstLevel will get set in @@ -136,11 +136,34 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) */ firstImage = tObj->Image[0][intelObj->firstLevel]; - i830->state.tex_buffer[unit] = driBOReference(intelObj->mt->region->buffer); - i830->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, 0, - intelObj-> - firstLevel); + if (intelObj->imageOverride) { + i830->state.tex_buffer[unit] = NULL; + i830->state.tex_offset[unit] = intelObj->textureOffset; + switch (intelObj->depthOverride) { + case 32: + format = MAPSURF_32BIT | MT_32BIT_ARGB8888; + break; + case 24: + default: + format = MAPSURF_32BIT | MT_32BIT_XRGB8888; + break; + case 16: + format = MAPSURF_16BIT | MT_16BIT_RGB565; + break; + } + + pitch = intelObj->pitchOverride; + } else { + i830->state.tex_buffer[unit] = driBOReference(intelObj->mt->region-> + buffer); + i830->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, + 0, intelObj-> + firstLevel); + + format = translate_texture_format(firstImage->TexFormat->MesaFormat); + pitch = intelObj->mt->pitch * intelObj->mt->cpp; + } state[I830_TEXREG_TM0LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_2 | (LOAD_TEXTURE_MAP0 << unit) | 4); @@ -151,12 +174,10 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) state[I830_TEXREG_TM0S1] = (((firstImage->Height - 1) << TM0S1_HEIGHT_SHIFT) | - ((firstImage->Width - 1) << TM0S1_WIDTH_SHIFT) | - translate_texture_format(firstImage->TexFormat->MesaFormat)); + ((firstImage->Width - 1) << TM0S1_WIDTH_SHIFT) | format); state[I830_TEXREG_TM0S2] = - (((((intelObj->mt->pitch * intelObj->mt->cpp) / 4) - - 1) << TM0S2_PITCH_SHIFT) | TM0S2_CUBE_FACE_ENA_MASK); + ((((pitch / 4) - 1) << TM0S2_PITCH_SHIFT) | TM0S2_CUBE_FACE_ENA_MASK); { if (tObj->Target == GL_TEXTURE_CUBE_MAP) diff --git a/src/mesa/drivers/dri/i915tex/i830_vtbl.c b/src/mesa/drivers/dri/i915tex/i830_vtbl.c index dd0670dec3..e432648ada 100644 --- a/src/mesa/drivers/dri/i915tex/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915tex/i830_vtbl.c @@ -490,11 +490,13 @@ i830_emit_state(struct intel_context *intel) DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, state->tex_offset[i] | TM0S0_USE_FENCE); } - else { - assert(i == 0); - assert(state == &i830->meta); - OUT_BATCH(0); - } + else if (state == &i830->meta) { + assert(i == 0); + OUT_BATCH(0); + } + else { + OUT_BATCH(state->tex_offset[i]); + } OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]); diff --git a/src/mesa/drivers/dri/i915tex/i915_fragprog.c b/src/mesa/drivers/dri/i915tex/i915_fragprog.c index cbea6092a8..a4b22a0c32 100644 --- a/src/mesa/drivers/dri/i915tex/i915_fragprog.c +++ b/src/mesa/drivers/dri/i915tex/i915_fragprog.c @@ -849,11 +849,6 @@ i915BindProgram(GLcontext * ctx, GLenum target, struct gl_program *prog) assert(p->on_hardware == 0); assert(p->params_uptodate == 0); - /* Hack: make sure fog is correctly enabled according to this - * fragment program's fog options. - */ - ctx->Driver.Enable(ctx, GL_FRAGMENT_PROGRAM_ARB, - ctx->FragmentProgram.Enabled); } } @@ -926,9 +921,6 @@ i915ProgramStringNotify(GLcontext * ctx, /* Hack: make sure fog is correctly enabled according to this * fragment program's fog options. */ - ctx->Driver.Enable(ctx, GL_FRAGMENT_PROGRAM_ARB, - ctx->FragmentProgram.Enabled); - if (p->FragProg.FogOption) { /* add extra instructions to do fog, then turn off FogOption field */ _mesa_append_fog_code(ctx, &p->FragProg); diff --git a/src/mesa/drivers/dri/i915tex/i915_state.c b/src/mesa/drivers/dri/i915tex/i915_state.c index 1fafadced0..e5d8d27993 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state.c +++ b/src/mesa/drivers/dri/i915tex/i915_state.c @@ -36,6 +36,8 @@ #include "texmem.h" +#include "drivers/common/driverfuncs.h" + #include "intel_fbo.h" #include "intel_screen.h" #include "intel_batchbuffer.h" @@ -563,7 +565,6 @@ i915_update_fog(GLcontext * ctx) if (ctx->FragmentProgram._Active) { /* Pull in static fog state from program */ - mode = ctx->FragmentProgram._Current->FogOption; enabled = (mode != GL_NONE); try_pixel_fog = 0; @@ -571,15 +572,19 @@ i915_update_fog(GLcontext * ctx) else { enabled = ctx->Fog.Enabled; mode = ctx->Fog.Mode; - - try_pixel_fog = (ctx->Fog.FogCoordinateSource == GL_FRAGMENT_DEPTH_EXT && ctx->Hint.Fog == GL_NICEST && 0); /* XXX - DISABLE -- Need ortho fallback */ +#if 0 + /* XXX - DISABLED -- Need ortho fallback */ + try_pixel_fog = (ctx->Fog.FogCoordinateSource == GL_FRAGMENT_DEPTH_EXT + && ctx->Hint.Fog == GL_NICEST); +#else + try_pixel_fog = 0; +#endif } if (!enabled) { i915->vertex_fog = I915_FOG_NONE; } else if (try_pixel_fog) { - I915_STATECHANGE(i915, I915_UPLOAD_FOG); i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_FOGFUNC_MASK; i915->vertex_fog = I915_FOG_PIXEL; @@ -591,12 +596,13 @@ i915_update_fog(GLcontext * ctx) * either fallback or append fog instructions to end of * program in the case of linear fog. */ + printf("vertex fog!\n"); i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_VERTEX; i915->vertex_fog = I915_FOG_VERTEX; } else { - GLfloat c1 = ctx->Fog.End / (ctx->Fog.End - ctx->Fog.Start); GLfloat c2 = 1.0 / (ctx->Fog.End - ctx->Fog.Start); + GLfloat c1 = ctx->Fog.End * c2; i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_C1_MASK; i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_LINEAR; @@ -604,15 +610,11 @@ i915_update_fog(GLcontext * ctx) ((GLuint) (c1 * FMC1_C1_ONE)) & FMC1_C1_MASK; if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) { - i915->state.Fog[I915_FOGREG_MODE2] = - (GLuint) (c2 * FMC2_C2_ONE); + i915->state.Fog[I915_FOGREG_MODE2] + = (GLuint) (c2 * FMC2_C2_ONE); } else { - union - { - float f; - int i; - } fi; + fi_type fi; fi.f = c2; i915->state.Fog[I915_FOGREG_MODE2] = fi.i; } @@ -628,26 +630,22 @@ i915_update_fog(GLcontext * ctx) break; } } - else { /* if (i915->vertex_fog != I915_FOG_VERTEX) */ - + else { /* if (i915->vertex_fog != I915_FOG_VERTEX) */ I915_STATECHANGE(i915, I915_UPLOAD_FOG); i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_FOGFUNC_MASK; i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_VERTEX; i915->vertex_fog = I915_FOG_VERTEX; } - { - I915_STATECHANGE(i915, I915_UPLOAD_CTX); - I915_ACTIVESTATE(i915, I915_UPLOAD_FOG, enabled); - if (enabled) - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_FOG_ENABLE; - else - i915->state.Ctx[I915_CTXREG_LIS5] &= ~S5_FOG_ENABLE; - } + I915_STATECHANGE(i915, I915_UPLOAD_CTX); + I915_ACTIVESTATE(i915, I915_UPLOAD_FOG, enabled); + if (enabled) + i915->state.Ctx[I915_CTXREG_LIS5] |= S5_FOG_ENABLE; + else + i915->state.Ctx[I915_CTXREG_LIS5] &= ~S5_FOG_ENABLE; - /* always enbale pixel fog - * vertex fog use precaculted fog coord will conflict with appended - * fog program + /* Always enable pixel fog. Vertex fog using fog coord will conflict + * with fog code appended onto fragment program. */ _tnl_allow_vertex_fog( ctx, 0 ); _tnl_allow_pixel_fog( ctx, 1 ); @@ -669,15 +667,11 @@ i915Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) I915_STATECHANGE(i915, I915_UPLOAD_FOG); if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) { - i915->state.Fog[I915_FOGREG_MODE3] = (GLuint) (ctx->Fog.Density * - FMC3_D_ONE); + i915->state.Fog[I915_FOGREG_MODE3] = + (GLuint) (ctx->Fog.Density * FMC3_D_ONE); } else { - union - { - float f; - int i; - } fi; + fi_type fi; fi.f = ctx->Fog.Density; i915->state.Fog[I915_FOGREG_MODE3] = fi.i; } @@ -1013,7 +1007,7 @@ i915InitState(struct i915_context *i915) i915_init_packets(i915); - intelInitState(ctx); + _mesa_init_driver_state(ctx); memcpy(&i915->initial, &i915->state, sizeof(i915->state)); i915->current = &i915->state; diff --git a/src/mesa/drivers/dri/i915tex/i915_tex_layout.c b/src/mesa/drivers/dri/i915tex/i915_tex_layout.c index 2e1600cfdf..7b761a7b22 100644 --- a/src/mesa/drivers/dri/i915tex/i915_tex_layout.c +++ b/src/mesa/drivers/dri/i915tex/i915_tex_layout.c @@ -113,7 +113,7 @@ i915_miptree_layout(struct intel_mipmap_tree * mt) */ for (level = mt->first_level; level <= MAX2(8, mt->last_level); level++) { - intel_miptree_set_level_info(mt, level, 1, 0, mt->total_height, + intel_miptree_set_level_info(mt, level, depth, 0, mt->total_height, width, height, depth); @@ -161,11 +161,9 @@ i915_miptree_layout(struct intel_mipmap_tree * mt) if (mt->compressed) img_height = MAX2(1, height / 4); else - img_height = MAX2(2, height); + img_height = (MAX2(2, height) + 1) & ~1; mt->total_height += img_height; - mt->total_height += 1; - mt->total_height &= ~1; width = minify(width); height = minify(height); diff --git a/src/mesa/drivers/dri/i915tex/i915_texstate.c b/src/mesa/drivers/dri/i915tex/i915_texstate.c index e0ecdfde24..3d68187cf8 100644 --- a/src/mesa/drivers/dri/i915tex/i915_texstate.c +++ b/src/mesa/drivers/dri/i915tex/i915_texstate.c @@ -122,7 +122,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); struct gl_texture_image *firstImage; - GLuint *state = i915->state.Tex[unit]; + GLuint *state = i915->state.Tex[unit], format, pitch; memset(state, 0, sizeof(state)); @@ -133,7 +133,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) i915->state.tex_buffer[unit] = NULL; } - if (!intel_finalize_mipmap_tree(intel, unit)) + if (!intelObj->imageOverride && !intel_finalize_mipmap_tree(intel, unit)) return GL_FALSE; /* Get first image here, since intelObj->firstLevel will get set in @@ -141,24 +141,45 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) */ firstImage = tObj->Image[0][intelObj->firstLevel]; - i915->state.tex_buffer[unit] = driBOReference(intelObj->mt->region->buffer); - i915->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, 0, - intelObj-> - firstLevel); + if (intelObj->imageOverride) { + i915->state.tex_buffer[unit] = NULL; + i915->state.tex_offset[unit] = intelObj->textureOffset; + + switch (intelObj->depthOverride) { + case 32: + format = MAPSURF_32BIT | MT_32BIT_ARGB8888; + break; + case 24: + default: + format = MAPSURF_32BIT | MT_32BIT_XRGB8888; + break; + case 16: + format = MAPSURF_16BIT | MT_16BIT_RGB565; + break; + } + + pitch = intelObj->pitchOverride; + } else { + i915->state.tex_buffer[unit] = driBOReference(intelObj->mt->region-> + buffer); + i915->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, + 0, intelObj-> + firstLevel); + + format = translate_texture_format(firstImage->TexFormat->MesaFormat); + pitch = intelObj->mt->pitch * intelObj->mt->cpp; + } state[I915_TEXREG_MS3] = (((firstImage->Height - 1) << MS3_HEIGHT_SHIFT) | - ((firstImage->Width - 1) << MS3_WIDTH_SHIFT) | - translate_texture_format(firstImage->TexFormat->MesaFormat) | + ((firstImage->Width - 1) << MS3_WIDTH_SHIFT) | format | MS3_USE_FENCE_REGS); state[I915_TEXREG_MS4] = - (((((intelObj->mt->pitch * intelObj->mt->cpp) / 4) - - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK | - ((((intelObj->lastLevel - - intelObj->firstLevel) * - 4)) << MS4_MAX_LOD_SHIFT) | ((firstImage->Depth - - 1) << MS4_VOLUME_DEPTH_SHIFT)); + ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK | + ((((intelObj->lastLevel - intelObj->firstLevel) * 4)) << + MS4_MAX_LOD_SHIFT) | ((firstImage->Depth - 1) << + MS4_VOLUME_DEPTH_SHIFT)); { diff --git a/src/mesa/drivers/dri/i915tex/i915_vtbl.c b/src/mesa/drivers/dri/i915tex/i915_vtbl.c index 52db9a95e6..f80e8d6327 100644 --- a/src/mesa/drivers/dri/i915tex/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915tex/i915_vtbl.c @@ -381,11 +381,13 @@ i915_emit_state(struct intel_context *intel) DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, state->tex_offset[i]); } - else { + else if (state == &i915->meta) { assert(i == 0); - assert(state == &i915->meta); OUT_BATCH(0); } + else { + OUT_BATCH(state->tex_offset[i]); + } OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]); OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]); diff --git a/src/mesa/drivers/dri/i915tex/intel_batchpool.c b/src/mesa/drivers/dri/i915tex/intel_batchpool.c index 3c17c50204..2503b8a62a 100644 --- a/src/mesa/drivers/dri/i915tex/intel_batchpool.c +++ b/src/mesa/drivers/dri/i915tex/intel_batchpool.c @@ -96,7 +96,7 @@ createBPool(int fd, unsigned long bufSize, unsigned numBufs, unsigned flags, _glthread_INIT_MUTEX(p->mutex); if (drmBOCreate(fd, 0, numBufs * bufSize, 0, NULL, drm_bo_type_dc, - flags, 0, &p->kernelBO)) { + flags, DRM_BO_HINT_DONT_FENCE, &p->kernelBO)) { free(p->bufs); free(p); return NULL; diff --git a/src/mesa/drivers/dri/i915tex/intel_buffer_objects.c b/src/mesa/drivers/dri/i915tex/intel_buffer_objects.c index ba3c7f0c1f..91c45ad95b 100644 --- a/src/mesa/drivers/dri/i915tex/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i915tex/intel_buffer_objects.c @@ -76,7 +76,9 @@ intel_bufferobj_release_region(struct intel_context *intel, */ driGenBuffers(intel->intelScreen->regionPool, "buffer object", 1, &intel_obj->buffer, 64, 0, 0); + LOCK_HARDWARE(intel); driBOData(intel_obj->buffer, intel_obj->Base.Size, NULL, 0); + UNLOCK_HARDWARE(intel); } /* Break the COW tie to the region. Both the pbo and the region end @@ -137,7 +139,9 @@ intel_bufferobj_data(GLcontext * ctx, if (intel_obj->region) intel_bufferobj_release_region(intel, intel_obj); + LOCK_HARDWARE(intel); driBOData(intel_obj->buffer, size, data, 0); + UNLOCK_HARDWARE(intel); } diff --git a/src/mesa/drivers/dri/i915tex/intel_context.c b/src/mesa/drivers/dri/i915tex/intel_context.c index 6a3456e154..c927dca8e5 100644 --- a/src/mesa/drivers/dri/i915tex/intel_context.c +++ b/src/mesa/drivers/dri/i915tex/intel_context.c @@ -130,6 +130,18 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_I945_GM: chipset = "Intel(R) 945GM"; break; + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; + break; + case PCI_CHIP_G33_G: + chipset = "Intel(R) G33"; + break; + case PCI_CHIP_Q35_G: + chipset = "Intel(R) Q35"; + break; + case PCI_CHIP_Q33_G: + chipset = "Intel(R) Q33"; + break; default: chipset = "Unknown Intel Chipset"; break; @@ -209,7 +221,6 @@ static const struct tnl_pipeline_stage *intel_pipeline[] = { &_tnl_texgen_stage, &_tnl_texture_transform_stage, &_tnl_point_attenuation_stage, - &_tnl_arb_vertex_program_stage, &_tnl_vertex_program_stage, #if 1 &_intel_render_stage, /* ADD: unclipped rastersetup-to-dma */ @@ -347,7 +358,15 @@ intelInitContext(struct intel_context *intel, drmI830Sarea *saPriv = (drmI830Sarea *) (((GLubyte *) sPriv->pSAREA) + intelScreen->sarea_priv_offset); int fthrottle_mode; + GLboolean havePools; + + DRM_LIGHT_LOCK(sPriv->fd, &sPriv->pSAREA->lock, driContextPriv->hHWContext); + havePools = intelCreatePools(intelScreen); + DRM_UNLOCK(sPriv->fd, &sPriv->pSAREA->lock, driContextPriv->hHWContext); + if (!havePools) + return GL_FALSE; + if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx, functions, (void *) intel)) diff --git a/src/mesa/drivers/dri/i915tex/intel_context.h b/src/mesa/drivers/dri/i915tex/intel_context.h index 44c20af7f8..9d060eb866 100644 --- a/src/mesa/drivers/dri/i915tex/intel_context.h +++ b/src/mesa/drivers/dri/i915tex/intel_context.h @@ -92,6 +92,10 @@ struct intel_texture_object * regions will be copied to this region and the old storage freed. */ struct intel_mipmap_tree *mt; + + GLboolean imageOverride; + GLint depthOverride; + GLuint pitchOverride; }; @@ -381,6 +385,10 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I915_GM 0x2592 #define PCI_CHIP_I945_G 0x2772 #define PCI_CHIP_I945_GM 0x27A2 +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q33_G 0x29D2 /* ================================================================ @@ -395,7 +403,6 @@ extern GLboolean intelInitContext(struct intel_context *intel, extern void intelGetLock(struct intel_context *intel, GLuint flags); -extern void intelInitState(GLcontext * ctx); extern void intelFinish(GLcontext * ctx); extern void intelFlush(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c index 8e83028b26..843a78eb82 100644 --- a/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c @@ -79,6 +79,10 @@ intel_miptree_create(struct intel_context *intel, switch (intel->intelScreen->deviceID) { case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q33_G: + case PCI_CHIP_Q35_G: ok = i945_miptree_layout(mt); break; case PCI_CHIP_I915_G: diff --git a/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c b/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c index 10a079896a..77c67c821e 100644 --- a/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c @@ -363,5 +363,20 @@ intelDrawPixels(GLcontext * ctx, if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s: fallback to swrast\n", __FUNCTION__); - _swrast_DrawPixels(ctx, x, y, width, height, format, type, unpack, pixels); + if (ctx->FragmentProgram._Current == ctx->FragmentProgram._TexEnvProgram) { + /* + * We don't want the i915 texenv program to be applied to DrawPixels. + * This is really just a performance optimization (mesa will other- + * wise happily run the fragment program on each pixel in the image). + */ + struct gl_fragment_program *fpSave = ctx->FragmentProgram._Current; + ctx->FragmentProgram._Current = NULL; + _swrast_DrawPixels( ctx, x, y, width, height, format, type, + unpack, pixels ); + ctx->FragmentProgram._Current = fpSave; + } + else { + _swrast_DrawPixels( ctx, x, y, width, height, format, type, + unpack, pixels ); + } } diff --git a/src/mesa/drivers/dri/i915tex/intel_regions.c b/src/mesa/drivers/dri/i915tex/intel_regions.c index a114bdf896..7d19bd07d3 100644 --- a/src/mesa/drivers/dri/i915tex/intel_regions.c +++ b/src/mesa/drivers/dri/i915tex/intel_regions.c @@ -90,6 +90,7 @@ intel_region_alloc(intelScreenPrivate *intelScreen, GLuint cpp, GLuint pitch, GLuint height) { struct intel_region *region = calloc(sizeof(*region), 1); + struct intel_context *intel = intelScreenContext(intelScreen); DBG("%s\n", __FUNCTION__); @@ -107,7 +108,9 @@ intel_region_alloc(intelScreenPrivate *intelScreen, 0, #endif 0); + LOCK_HARDWARE(intel); driBOData(region->buffer, pitch * cpp * height, NULL, 0); + UNLOCK_HARDWARE(intel); return region; } @@ -392,6 +395,8 @@ void intel_region_release_pbo(intelScreenPrivate *intelScreen, struct intel_region *region) { + struct intel_context *intel = intelScreenContext(intelScreen); + assert(region->buffer == region->pbo->buffer); region->pbo->region = NULL; region->pbo = NULL; @@ -400,8 +405,11 @@ intel_region_release_pbo(intelScreenPrivate *intelScreen, driGenBuffers(intelScreen->regionPool, "region", 1, ®ion->buffer, 64, 0, 0); + + LOCK_HARDWARE(intel); driBOData(region->buffer, region->cpp * region->pitch * region->height, NULL, 0); + UNLOCK_HARDWARE(intel); } /* Break the COW tie to the pbo. Both the pbo and the region end up diff --git a/src/mesa/drivers/dri/i915tex/intel_screen.c b/src/mesa/drivers/dri/i915tex/intel_screen.c index 9034ee1b22..2acdead63d 100644 --- a/src/mesa/drivers/dri/i915tex/intel_screen.c +++ b/src/mesa/drivers/dri/i915tex/intel_screen.c @@ -386,6 +386,45 @@ intelUpdateScreenFromSAREA(intelScreenPrivate * intelScreen, intelPrintSAREA(sarea); } +GLboolean +intelCreatePools(intelScreenPrivate *intelScreen) +{ + unsigned batchPoolSize = 1024*1024; + __DRIscreenPrivate * sPriv = intelScreen->driScrnPriv; + + if (intelScreen->havePools) + return GL_TRUE; + + batchPoolSize /= intelScreen->maxBatchSize; + intelScreen->regionPool = driDRMPoolInit(sPriv->fd); + + if (!intelScreen->regionPool) + return GL_FALSE; + + intelScreen->staticPool = driDRMStaticPoolInit(sPriv->fd); + + if (!intelScreen->staticPool) + return GL_FALSE; + + intelScreen->texPool = intelScreen->regionPool; + + intelScreen->batchPool = driBatchPoolInit(sPriv->fd, + DRM_BO_FLAG_EXE | + DRM_BO_FLAG_MEM_TT | + DRM_BO_FLAG_MEM_LOCAL, + intelScreen->maxBatchSize, + batchPoolSize, 5); + if (!intelScreen->batchPool) { + fprintf(stderr, "Failed to initialize batch pool - possible incorrect agpgart installed\n"); + return GL_FALSE; + } + + intel_recreate_static_regions(intelScreen); + intelScreen->havePools = GL_TRUE; + + return GL_TRUE; +} + static GLboolean intelInitDriver(__DRIscreenPrivate * sPriv) @@ -393,7 +432,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv) intelScreenPrivate *intelScreen; I830DRIPtr gDRIPriv = (I830DRIPtr) sPriv->pDevPriv; drmI830Sarea *sarea; - unsigned batchPoolSize = 1024*1024; PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension = (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface-> @@ -426,7 +464,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv) intelScreen->deviceID = gDRIPriv->deviceID; if (intelScreen->deviceID == PCI_CHIP_I865_G) intelScreen->maxBatchSize = 4096; - batchPoolSize /= intelScreen->maxBatchSize; intelScreen->mem = gDRIPriv->mem; intelScreen->cpp = gDRIPriv->cpp; @@ -517,31 +554,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv) (*glx_enable_extension) (psc, "GLX_SGI_make_current_read"); } - intelScreen->regionPool = driDRMPoolInit(sPriv->fd); - - if (!intelScreen->regionPool) - return GL_FALSE; - - intelScreen->staticPool = driDRMStaticPoolInit(sPriv->fd); - - if (!intelScreen->staticPool) - return GL_FALSE; - - intelScreen->texPool = intelScreen->regionPool; - - intelScreen->batchPool = driBatchPoolInit(sPriv->fd, - DRM_BO_FLAG_EXE | - DRM_BO_FLAG_MEM_TT | - DRM_BO_FLAG_MEM_LOCAL, - intelScreen->maxBatchSize, - batchPoolSize, 5); - if (!intelScreen->batchPool) { - fprintf(stderr, "Failed to initialize batch pool - possible incorrect agpgart installed\n"); - return GL_FALSE; - } - - intel_recreate_static_regions(intelScreen); - return GL_TRUE; } @@ -553,9 +565,11 @@ intelDestroyScreen(__DRIscreenPrivate * sPriv) intelUnmapScreenRegions(intelScreen); - driPoolTakeDown(intelScreen->regionPool); - driPoolTakeDown(intelScreen->staticPool); - driPoolTakeDown(intelScreen->batchPool); + if (intelScreen->havePools) { + driPoolTakeDown(intelScreen->regionPool); + driPoolTakeDown(intelScreen->staticPool); + driPoolTakeDown(intelScreen->batchPool); + } FREE(intelScreen); sPriv->private = NULL; } @@ -738,6 +752,10 @@ intelCreateContext(const __GLcontextModes * mesaVis, case PCI_CHIP_I915_GM: case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate); default: @@ -762,7 +780,8 @@ static const struct __DriverAPIRec intelAPI = { .WaitForMSC = driWaitForMSC32, .WaitForSBC = NULL, .SwapBuffersMSC = NULL, - .CopySubBuffer = intelCopySubBuffer + .CopySubBuffer = intelCopySubBuffer, + .setTexOffset = intelSetTexOffset, }; @@ -892,6 +911,7 @@ __driCreateNewScreen_20050727(__DRInativeDisplay * dpy, int scrn, ddx_version, dri_version, drm_version, frame_buffer, pSAREA, fd, internal_api_version, &intelAPI); + if (psp != NULL) { I830DRIPtr dri_priv = (I830DRIPtr) psp->pDevPriv; *driver_modes = intelFillInModes(dri_priv->cpp * 8, diff --git a/src/mesa/drivers/dri/i915tex/intel_screen.h b/src/mesa/drivers/dri/i915tex/intel_screen.h index 05e2f1f2ea..bac43aaddd 100644 --- a/src/mesa/drivers/dri/i915tex/intel_screen.h +++ b/src/mesa/drivers/dri/i915tex/intel_screen.h @@ -95,6 +95,7 @@ typedef struct struct _DriBufferPool *regionPool; struct _DriBufferPool *staticPool; unsigned int maxBatchSize; + GLboolean havePools; } intelScreenPrivate; @@ -130,5 +131,7 @@ extern struct intel_context *intelScreenContext(intelScreenPrivate *intelScreen) extern void intelUpdateScreenRotation(__DRIscreenPrivate * sPriv, drmI830Sarea * sarea); +extern GLboolean +intelCreatePools(intelScreenPrivate *intelScreen); #endif diff --git a/src/mesa/drivers/dri/i915tex/intel_state.c b/src/mesa/drivers/dri/i915tex/intel_state.c index f85d8ef835..271511037e 100644 --- a/src/mesa/drivers/dri/i915tex/intel_state.c +++ b/src/mesa/drivers/dri/i915tex/intel_state.c @@ -267,97 +267,3 @@ intelInitStateFuncs(struct dd_function_table *functions) functions->DepthRange = intelDepthRange; functions->ClearColor = intelClearColor; } - - - - -void -intelInitState(GLcontext * ctx) -{ - /* Mesa should do this for us: - */ - ctx->Driver.AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef); - - ctx->Driver.BlendColor(ctx, ctx->Color.BlendColor); - - ctx->Driver.BlendEquationSeparate(ctx, - ctx->Color.BlendEquationRGB, - ctx->Color.BlendEquationA); - - ctx->Driver.BlendFuncSeparate(ctx, - ctx->Color.BlendSrcRGB, - ctx->Color.BlendDstRGB, - ctx->Color.BlendSrcA, ctx->Color.BlendDstA); - - ctx->Driver.ColorMask(ctx, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); - - ctx->Driver.CullFace(ctx, ctx->Polygon.CullFaceMode); - ctx->Driver.DepthFunc(ctx, ctx->Depth.Func); - ctx->Driver.DepthMask(ctx, ctx->Depth.Mask); - - ctx->Driver.Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled); - ctx->Driver.Enable(ctx, GL_BLEND, ctx->Color.BlendEnabled); - ctx->Driver.Enable(ctx, GL_COLOR_LOGIC_OP, ctx->Color.ColorLogicOpEnabled); - ctx->Driver.Enable(ctx, GL_COLOR_SUM, ctx->Fog.ColorSumEnabled); - ctx->Driver.Enable(ctx, GL_CULL_FACE, ctx->Polygon.CullFlag); - ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); - ctx->Driver.Enable(ctx, GL_DITHER, ctx->Color.DitherFlag); - ctx->Driver.Enable(ctx, GL_FOG, ctx->Fog.Enabled); - ctx->Driver.Enable(ctx, GL_LIGHTING, ctx->Light.Enabled); - ctx->Driver.Enable(ctx, GL_LINE_SMOOTH, ctx->Line.SmoothFlag); - ctx->Driver.Enable(ctx, GL_POLYGON_STIPPLE, ctx->Polygon.StippleFlag); - ctx->Driver.Enable(ctx, GL_SCISSOR_TEST, ctx->Scissor.Enabled); - ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); - ctx->Driver.Enable(ctx, GL_TEXTURE_1D, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_2D, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_RECTANGLE_NV, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_3D, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_CUBE_MAP, GL_FALSE); - - ctx->Driver.Fogfv(ctx, GL_FOG_COLOR, ctx->Fog.Color); - ctx->Driver.Fogfv(ctx, GL_FOG_MODE, 0); - ctx->Driver.Fogfv(ctx, GL_FOG_DENSITY, &ctx->Fog.Density); - ctx->Driver.Fogfv(ctx, GL_FOG_START, &ctx->Fog.Start); - ctx->Driver.Fogfv(ctx, GL_FOG_END, &ctx->Fog.End); - - ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); - - { - GLfloat f = (GLfloat) ctx->Light.Model.ColorControl; - ctx->Driver.LightModelfv(ctx, GL_LIGHT_MODEL_COLOR_CONTROL, &f); - } - - ctx->Driver.LineWidth(ctx, ctx->Line.Width); - ctx->Driver.LogicOpcode(ctx, ctx->Color.LogicOp); - ctx->Driver.PointSize(ctx, ctx->Point.Size); - ctx->Driver.PolygonStipple(ctx, (const GLubyte *) ctx->PolygonStipple); - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - ctx->Driver.ShadeModel(ctx, ctx->Light.ShadeModel); - ctx->Driver.StencilFuncSeparate(ctx, GL_FRONT, - ctx->Stencil.Function[0], - ctx->Stencil.Ref[0], - ctx->Stencil.ValueMask[0]); - ctx->Driver.StencilFuncSeparate(ctx, GL_BACK, - ctx->Stencil.Function[1], - ctx->Stencil.Ref[1], - ctx->Stencil.ValueMask[1]); - ctx->Driver.StencilMaskSeparate(ctx, GL_FRONT, ctx->Stencil.WriteMask[0]); - ctx->Driver.StencilMaskSeparate(ctx, GL_BACK, ctx->Stencil.WriteMask[1]); - ctx->Driver.StencilOpSeparate(ctx, GL_FRONT, - ctx->Stencil.FailFunc[0], - ctx->Stencil.ZFailFunc[0], - ctx->Stencil.ZPassFunc[0]); - ctx->Driver.StencilOpSeparate(ctx, GL_BACK, - ctx->Stencil.FailFunc[1], - ctx->Stencil.ZFailFunc[1], - ctx->Stencil.ZPassFunc[1]); - - - /* XXX this isn't really needed */ - ctx->Driver.DrawBuffer(ctx, ctx->Color.DrawBuffer[0]); -} diff --git a/src/mesa/drivers/dri/i915tex/intel_tex.h b/src/mesa/drivers/dri/i915tex/intel_tex.h index 6e9938fe53..b77d7a1d8a 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tex.h +++ b/src/mesa/drivers/dri/i915tex/intel_tex.h @@ -135,6 +135,9 @@ void intelGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level, const struct gl_texture_object *texObj, const struct gl_texture_image *texImage); +void intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, GLuint pitch); + GLuint intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit); void intel_tex_map_images(struct intel_context *intel, diff --git a/src/mesa/drivers/dri/i915tex/intel_tex_image.c b/src/mesa/drivers/dri/i915tex/intel_tex_image.c index 42679ef9db..f790b1e6f7 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tex_image.c +++ b/src/mesa/drivers/dri/i915tex/intel_tex_image.c @@ -385,7 +385,6 @@ intelTexImage(GLcontext * ctx, } } - assert(!intelImage->mt); if (intelObj->mt && @@ -667,3 +666,26 @@ intelGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level, texObj, texImage, 1); } + +void +intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, GLuint pitch) +{ + struct intel_context *intel = (struct intel_context*) + ((__DRIcontextPrivate*)pDRICtx->private)->driverPrivate; + struct gl_texture_object *tObj = _mesa_lookup_texture(&intel->ctx, texname); + struct intel_texture_object *intelObj = intel_texture_object(tObj); + + if (!intelObj) + return; + + if (intelObj->mt) + intel_miptree_release(intel, &intelObj->mt); + + intelObj->imageOverride = GL_TRUE; + intelObj->depthOverride = depth; + intelObj->pitchOverride = pitch; + + if (offset) + intelObj->textureOffset = offset; +} diff --git a/src/mesa/drivers/dri/i915tex/intel_tex_validate.c b/src/mesa/drivers/dri/i915tex/intel_tex_validate.c index 79d587a174..af18c26d55 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i915tex/intel_tex_validate.c @@ -105,6 +105,8 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) { struct gl_texture_object *tObj = intel->ctx.Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); + int comp_byte = 0; + int cpp; GLuint face, i; GLuint nr_faces = 0; @@ -114,7 +116,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* We know/require this is true by now: */ - assert(intelObj->base.Complete); + assert(intelObj->base._Complete); /* What levels must the tree include at a minimum? */ @@ -148,6 +150,12 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) intel_miptree_reference(&intelObj->mt, firstImage->mt); } + if (firstImage->base.IsCompressed) { + comp_byte = intel_compressed_num_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = comp_byte; + } + else cpp = firstImage->base.TexFormat->TexelBytes; + /* Check tree can hold all active levels. Check tree matches * target, imageFormat, etc. * @@ -165,7 +173,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) intelObj->mt->width0 != firstImage->base.Width || intelObj->mt->height0 != firstImage->base.Height || intelObj->mt->depth0 != firstImage->base.Depth || - intelObj->mt->cpp != firstImage->base.TexFormat->TexelBytes || + intelObj->mt->cpp != cpp || intelObj->mt->compressed != firstImage->base.IsCompressed)) { intel_miptree_release(intel, &intelObj->mt); } @@ -174,10 +182,6 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* May need to create a new tree: */ if (!intelObj->mt) { - int comp_byte = 0; - - if (firstImage->base.IsCompressed) - comp_byte = intel_compressed_num_bytes(firstImage->base.TexFormat->MesaFormat); intelObj->mt = intel_miptree_create(intel, intelObj->base.Target, firstImage->base.InternalFormat, @@ -186,8 +190,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) firstImage->base.Width, firstImage->base.Height, firstImage->base.Depth, - firstImage->base.TexFormat-> - TexelBytes, + cpp, comp_byte); } diff --git a/src/mesa/drivers/dri/i915tex/server/intel_dri.c b/src/mesa/drivers/dri/i915tex/server/intel_dri.c index 4d1ac09f64..e49c4214ad 100644 --- a/src/mesa/drivers/dri/i915tex/server/intel_dri.c +++ b/src/mesa/drivers/dri/i915tex/server/intel_dri.c @@ -483,12 +483,14 @@ static unsigned long AllocFromAGP(const DRIDriverContext *ctx, I830Rec *pI830, l } unsigned long -I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *result, I830MemPool *pool, long size, unsigned long alignment, int flags) +I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830, + I830MemRange *result, I830MemPool *pool, long size, + unsigned long alignment, int flags) { - int ret; + unsigned long ret; - if (!result) - return 0; + if (!result) + return 0; /* Make sure these are initialised. */ result->Size = 0; @@ -498,16 +500,15 @@ I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *resul return 0; } - if (pool->Free.Size < size) - return AllocFromAGP(ctx, pI830, size, alignment, result); - else - { - ret = AllocFromPool(ctx, pI830, result, pool, size, alignment, flags); - - if (ret==0) - return AllocFromAGP(ctx, pI830, size, alignment, result); - return ret; + if (pool->Free.Size < size) { + ret = AllocFromAGP(ctx, pI830, size, alignment, result); } + else { + ret = AllocFromPool(ctx, pI830, result, pool, size, alignment, flags); + if (ret == 0) + ret = AllocFromAGP(ctx, pI830, size, alignment, result); + } + return ret; } static Bool BindAgpRange(const DRIDriverContext *ctx, I830MemRange *mem) @@ -895,31 +896,6 @@ I830DRIUnmapScreenRegions(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sa } } -#if 0 -static void -I830InitTextureHeap(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) -{ - /* Start up the simple memory manager for agp space */ - drmI830MemInitHeap drmHeap; - drmHeap.region = I830_MEM_REGION_AGP; - drmHeap.start = 0; - drmHeap.size = sarea->tex_size; - - if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT_HEAP, - &drmHeap, sizeof(drmHeap))) { - fprintf(stderr, - "[drm] Failed to initialized agp heap manager\n"); - } else { - fprintf(stderr, - "[drm] Initialized kernel agp heap manager, %d\n", - sarea->tex_size); - - I830SetParam(ctx, I830_SETPARAM_TEX_LRU_LOG_GRANULARITY, - sarea->log_tex_granularity); - } -} -#endif - static Bool I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) { @@ -943,9 +919,6 @@ I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) I830DRIMapScreenRegions(ctx, pI830, sarea); SetupDRIMM(ctx, pI830); -#if 0 - I830InitTextureHeap(ctx, pI830, sarea); -#endif if (ctx->pciDevice != PCI_CHIP_845_G && ctx->pciDevice != PCI_CHIP_I830_M) { I830SetParam(ctx, I830_SETPARAM_USE_MI_BATCHBUFFER_START, 1 ); |