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path: root/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_surface_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c19
1 files changed, 8 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index afb36b7bd7..357c8c90de 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -256,8 +256,7 @@ brw_create_texture_surface( struct brw_context *brw,
bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
key, sizeof(*key),
&key->bo, key->bo ? 1 : 0,
- &surf, sizeof(surf),
- NULL, NULL);
+ &surf, sizeof(surf));
if (key->bo) {
/* Emit relocation to surface contents */
@@ -351,8 +350,7 @@ brw_create_constant_surface( struct brw_context *brw,
bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
key, sizeof(*key),
&key->bo, key->bo ? 1 : 0,
- &surf, sizeof(surf),
- NULL, NULL);
+ &surf, sizeof(surf));
if (key->bo) {
/* Emit relocation to surface contents. Section 5.1.1 of the gen4
@@ -511,7 +509,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct gl_renderbuffer *rb,
unsigned int unit)
{
- GLcontext *ctx = &brw->intel.ctx;
+ struct intel_context *intel = &brw->intel;;
+ GLcontext *ctx = &intel->ctx;
dri_bo *region_bo = NULL;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_region *region = irb ? irb->region : NULL;
@@ -578,7 +577,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
key.draw_y = 0;
}
/* _NEW_COLOR */
- memcpy(key.color_mask, ctx->Color.ColorMask,
+ memcpy(key.color_mask, ctx->Color.ColorMask[0],
sizeof(key.color_mask));
/* As mentioned above, disable writes to the alpha component when the
@@ -622,7 +621,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
tile_base = ((key.draw_y / 32) * (32 * pitch));
tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
}
- assert(BRW_IS_G4X(brw) || (tile_x == 0 && tile_y == 0));
+ assert(intel->is_g4x || (tile_x == 0 && tile_y == 0));
assert(tile_x % 4 == 0);
assert(tile_y % 2 == 0);
/* Note that the low bits of these fields are missing, so
@@ -652,8 +651,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
BRW_SS_SURFACE,
&key, sizeof(key),
&region_bo, 1,
- &surf, sizeof(surf),
- NULL, NULL);
+ &surf, sizeof(surf));
if (region_bo != NULL) {
/* We might sample from it, and we might render to it, so flag
* them both. We might be able to figure out from other state
@@ -700,8 +698,7 @@ brw_wm_get_binding_table(struct brw_context *brw)
bind_bo = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
NULL, 0,
brw->wm.surf_bo, brw->wm.nr_surfaces,
- data, data_size,
- NULL, NULL);
+ data, data_size);
/* Emit binding table relocations to surface state */
for (i = 0; i < BRW_WM_MAX_SURF; i++) {