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-rw-r--r--src/mesa/drivers/dri/i965/Makefile2
-rw-r--r--src/mesa/drivers/dri/i965/brw_cc.c11
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_state.c11
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_curbe.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h64
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c14
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs_state.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c55
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf_state.c20
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_cache.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_state.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_sampler_state.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c32
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c131
l---------src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c1
17 files changed, 141 insertions, 247 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index c561b744d1..8fa205e79f 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -9,7 +9,6 @@ DRIVER_SOURCES = \
intel_blit.c \
intel_buffer_objects.c \
intel_buffers.c \
- intel_bufmgr_ttm.c \
intel_context.c \
intel_decode.c \
intel_depthstencil.c \
@@ -85,7 +84,6 @@ DRIVER_SOURCES = \
C_SOURCES = \
$(COMMON_SOURCES) \
- $(COMMON_BM_SOURCES) \
$(MINIGLX_SOURCES) \
$(DRIVER_SOURCES)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 9d8984f05c..49a80d3e4a 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -256,11 +256,12 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
NULL, NULL);
/* Emit CC viewport relocation */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- 0,
- offsetof(struct brw_cc_unit_state, cc4),
- brw->cc.vp_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ 0,
+ 0,
+ offsetof(struct brw_cc_unit_state, cc4),
+ brw->cc.vp_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 2d0b24c5ca..974cb77cb8 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -119,11 +119,12 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- clip.thread0.grf_reg_count << 1,
- offsetof(struct brw_clip_unit_state, thread0),
- brw->clip.prog_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ 0,
+ clip.thread0.grf_reg_count << 1,
+ offsetof(struct brw_clip_unit_state, thread0),
+ brw->clip.prog_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 1c7ad5c9c8..b4e2619929 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -134,7 +134,6 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = (1<<11);
- ctx->Const.MaxTextureUnits = BRW_MAX_TEX_UNIT;
/* ctx->Const.MaxNativeVertexProgramTemps = 32; */
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 5ff4e2964e..b603be8fc1 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -306,10 +306,7 @@ static int prepare_constant_buffer(struct brw_context *brw)
* They're generally around 64b.
*/
brw->curbe.curbe_bo = dri_bo_alloc(brw->intel.bufmgr, "CURBE",
- 4096, 1 << 6,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ 4096, 1 << 6);
brw->curbe.curbe_next_offset = 0;
}
@@ -353,7 +350,8 @@ static void emit_constant_buffer(struct brw_context *brw)
OUT_BATCH(0);
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
- OUT_RELOC(brw->curbe.curbe_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ OUT_RELOC(brw->curbe.curbe_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
(sz - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 92c058ade8..0593e8d5f5 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -33,69 +33,6 @@
#ifndef BRW_DEFINES_H
#define BRW_DEFINES_H
-/*
- */
-#define MI_NOOP 0x00
-#define MI_USER_INTERRUPT 0x02
-#define MI_WAIT_FOR_EVENT 0x03
-#define MI_FLUSH 0x04
-#define MI_REPORT_HEAD 0x07
-#define MI_ARB_ON_OFF 0x08
-#define MI_BATCH_BUFFER_END 0x0A
-#define MI_OVERLAY_FLIP 0x11
-#define MI_LOAD_SCAN_LINES_INCL 0x12
-#define MI_LOAD_SCAN_LINES_EXCL 0x13
-#define MI_DISPLAY_BUFFER_INFO 0x14
-#define MI_SET_CONTEXT 0x18
-#define MI_STORE_DATA_IMM 0x20
-#define MI_STORE_DATA_INDEX 0x21
-#define MI_LOAD_REGISTER_IMM 0x22
-#define MI_STORE_REGISTER_MEM 0x24
-#define MI_BATCH_BUFFER_START 0x31
-
-#define MI_SYNCHRONOUS_FLIP 0x0
-#define MI_ASYNCHRONOUS_FLIP 0x1
-
-#define MI_BUFFER_SECURE 0x0
-#define MI_BUFFER_NONSECURE 0x1
-
-#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0
-#define MI_ARBITRATE_BETWEEN_INSTS 0x1
-#define MI_NO_ARBITRATION 0x3
-
-#define MI_CONDITION_CODE_WAIT_DISABLED 0x0
-#define MI_CONDITION_CODE_WAIT_0 0x1
-#define MI_CONDITION_CODE_WAIT_1 0x2
-#define MI_CONDITION_CODE_WAIT_2 0x3
-#define MI_CONDITION_CODE_WAIT_3 0x4
-#define MI_CONDITION_CODE_WAIT_4 0x5
-
-#define MI_DISPLAY_PIPE_A 0x0
-#define MI_DISPLAY_PIPE_B 0x1
-
-#define MI_DISPLAY_PLANE_A 0x0
-#define MI_DISPLAY_PLANE_B 0x1
-#define MI_DISPLAY_PLANE_C 0x2
-
-#define MI_STANDARD_FLIP 0x0
-#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1
-#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2
-#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3
-
-#define MI_PHYSICAL_ADDRESS 0x0
-#define MI_VIRTUAL_ADDRESS 0x1
-
-#define MI_BUFFER_MEMORY_MAIN 0x0
-#define MI_BUFFER_MEMORY_GTT 0x2
-#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3
-
-#define MI_FLIP_CONTINUE 0x0
-#define MI_FLIP_ON 0x1
-#define MI_FLIP_OFF 0x2
-
-#define MI_UNTRUSTED_REGISTER_SPACE 0x0
-#define MI_TRUSTED_REGISTER_SPACE 0x1
-
/* 3D state:
*/
#define _3DOP_3DSTATE_PIPELINED 0x0
@@ -119,7 +56,6 @@
#define _3DSTATE_LINE_STIPPLE 0x08
#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09
#define _3DCONTROL 0x00
-#define _3DPRIMITIVE 0x00
#define PIPE_CONTROL_NOWRITE 0x00
#define PIPE_CONTROL_WRITEIMMEDIATE 0x01
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 2d99238ddc..0181b06764 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -247,10 +247,7 @@ static void wrap_buffers( struct brw_context *brw,
if (brw->vb.upload.bo != NULL)
dri_bo_unreference(brw->vb.upload.bo);
brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO",
- size, 1,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ size, 1);
/* Set the internal VBO\ to no-backing-store. We only use them as a
* temporary within a brw_try_draw_prims while the lock is held.
@@ -470,7 +467,7 @@ void brw_emit_vertices( struct brw_context *brw,
BRW_VB0_ACCESS_VERTEXDATA |
(input->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(input->bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ I915_GEM_DOMAIN_VERTEX, 0,
input->offset);
OUT_BATCH(max_index);
OUT_BATCH(0); /* Instance data step rate */
@@ -591,8 +588,11 @@ void brw_emit_indices(struct brw_context *brw,
BEGIN_BATCH(4, IGNORE_CLIPRECTS);
OUT_BATCH( ib.header.dword );
- OUT_RELOC( bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, offset);
- OUT_RELOC( bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ OUT_RELOC( bo,
+ I915_GEM_DOMAIN_VERTEX, 0,
+ offset);
+ OUT_RELOC( bo,
+ I915_GEM_DOMAIN_VERTEX, 0,
offset + ib_size);
OUT_BATCH( 0 );
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index f1f9e018f1..ae6b48a517 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -106,11 +106,11 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- gs.thread0.grf_reg_count << 1,
- offsetof(struct brw_gs_unit_state, thread0),
- brw->gs.prog_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ gs.thread0.grf_reg_count << 1,
+ offsetof(struct brw_gs_unit_state, thread0),
+ brw->gs.prog_bo);
}
return bo;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 62df2590f3..653695cdf5 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -88,7 +88,9 @@ static void upload_binding_table_pointers(struct brw_context *brw)
OUT_BATCH(0); /* gs */
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
- OUT_RELOC(brw->wm.bind_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(brw->wm.bind_bo,
+ I915_GEM_DOMAIN_SAMPLER, 0,
+ 0);
ADVANCE_BATCH();
}
@@ -114,18 +116,18 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
BEGIN_BATCH(7, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->vs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
if (brw->gs.prog_active)
- OUT_RELOC(brw->gs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
+ OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
if (!brw->metaops.active)
- OUT_RELOC(brw->clip.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
+ OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->sf.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
- OUT_RELOC(brw->wm.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
- OUT_RELOC(brw->cc.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
@@ -230,10 +232,11 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
- (region->tiled << 27) |
+ ((region->tiling != I915_TILING_NONE) << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
((region->height - 1) << 19));
@@ -380,40 +383,6 @@ const struct brw_tracked_state brw_line_stipple = {
};
-
-/***********************************************************************
- * Misc constant state packets
- */
-
-static void upload_pipe_control(struct brw_context *brw)
-{
- struct brw_pipe_control pc;
-
- return;
-
- memset(&pc, 0, sizeof(pc));
-
- pc.header.opcode = CMD_PIPE_CONTROL;
- pc.header.length = sizeof(pc)/4 - 2;
- pc.header.post_sync_operation = PIPE_CONTROL_NOWRITE;
-
- pc.header.instruction_state_cache_flush_enable = 1;
-
- pc.bits1.dest_addr_type = PIPE_CONTROL_GTTWRITE_GLOBAL;
-
- BRW_BATCH_STRUCT(brw, &pc);
-}
-
-const struct brw_tracked_state brw_pipe_control = {
- .dirty = {
- .mesa = 0,
- .brw = BRW_NEW_BATCH,
- .cache = 0
- },
- .emit = upload_pipe_control
-};
-
-
/***********************************************************************
* Misc invarient state packets
*/
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 24388b79a5..cbed301d31 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -253,18 +253,18 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
NULL, NULL);
/* Emit SF program relocation */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- sf.thread0.grf_reg_count << 1,
- offsetof(struct brw_sf_unit_state, thread0),
- brw->sf.prog_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ sf.thread0.grf_reg_count << 1,
+ offsetof(struct brw_sf_unit_state, thread0),
+ brw->sf.prog_bo);
/* Emit SF viewport relocation */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
- offsetof(struct brw_sf_unit_state, sf5),
- brw->sf.vp_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
+ offsetof(struct brw_sf_unit_state, sf5),
+ brw->sf.vp_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index d617650fad..fc0c3bd9ff 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -214,10 +214,7 @@ brw_upload_cache( struct brw_cache *cache,
/* Create the buffer object to contain the data */
bo = dri_bo_alloc(cache->brw->intel.bufmgr,
- cache->name[cache_id], data_size, 1 << 6,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ cache->name[cache_id], data_size, 1 << 6);
/* Set up the memory containing the key, aux_data, and reloc_bufs */
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 3b2ccd48c3..b8dfcf5b03 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -80,7 +80,6 @@ const struct brw_tracked_state *atoms[] =
*/
&brw_invarient_state,
&brw_state_base_address,
- &brw_pipe_control,
&brw_binding_table_pointers,
&brw_blend_constant_color,
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 2a64f3df33..e18cd42f4e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -115,11 +115,11 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
NULL, NULL);
/* Emit VS program relocation */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- vs.thread0.grf_reg_count << 1,
- offsetof(struct brw_vs_unit_state, thread0),
- brw->vs.prog_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ vs.thread0.grf_reg_count << 1,
+ offsetof(struct brw_vs_unit_state, thread0),
+ brw->vs.prog_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index d40332e9ae..461f977aac 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -305,12 +305,12 @@ static int upload_wm_samplers( struct brw_context *brw )
continue;
ret |= dri_bufmgr_check_aperture_space(brw->wm.sdc_bo[i]);
- dri_emit_reloc(brw->wm.sampler_bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- 0,
- i * sizeof(struct brw_sampler_state) +
- offsetof(struct brw_sampler_state, ss2),
- brw->wm.sdc_bo[i]);
+ intel_bo_emit_reloc(brw->wm.sampler_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0,
+ i * sizeof(struct brw_sampler_state) +
+ offsetof(struct brw_sampler_state, ss2),
+ brw->wm.sdc_bo[i]);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f4da0f279e..6fe30f0a9a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -199,28 +199,28 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
NULL, NULL);
/* Emit WM program relocation */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- wm.thread0.grf_reg_count << 1,
- offsetof(struct brw_wm_unit_state, thread0),
- brw->wm.prog_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ wm.thread0.grf_reg_count << 1,
+ offsetof(struct brw_wm_unit_state, thread0),
+ brw->wm.prog_bo);
/* Emit scratch space relocation */
if (key->total_scratch != 0) {
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
- wm.thread2.per_thread_scratch_space,
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.scratch_buffer);
+ intel_bo_emit_reloc(bo,
+ 0, 0,
+ wm.thread2.per_thread_scratch_space,
+ offsetof(struct brw_wm_unit_state, thread2),
+ brw->wm.scratch_buffer);
}
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
- offsetof(struct brw_wm_unit_state, wm4),
- brw->wm.sampler_bo);
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
+ offsetof(struct brw_wm_unit_state, wm4),
+ brw->wm.sampler_bo);
}
return bo;
@@ -251,7 +251,7 @@ static int upload_wm_unit( struct brw_context *brw )
brw->wm.scratch_buffer = dri_bo_alloc(intel->bufmgr,
"wm scratch",
total,
- 4096, DRM_BO_FLAG_MEM_TT);
+ 4096);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 2ba3eb4de8..761a5df33f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -154,10 +154,28 @@ struct brw_wm_surface_key {
GLint first_level, last_level;
GLint width, height, depth;
GLint pitch, cpp;
- GLboolean tiled;
- GLuint offset;
+ uint32_t tiling;
};
+static void
+brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
+{
+ switch (tiling) {
+ case I915_TILING_NONE:
+ surf->ss3.tiled_surface = 0;
+ surf->ss3.tile_walk = 0;
+ break;
+ case I915_TILING_X:
+ surf->ss3.tiled_surface = 1;
+ surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
+ break;
+ case I915_TILING_Y:
+ surf->ss3.tiled_surface = 1;
+ surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
+ break;
+ }
+}
+
static dri_bo *
brw_create_texture_surface( struct brw_context *brw,
struct brw_wm_surface_key *key )
@@ -169,32 +187,18 @@ brw_create_texture_surface( struct brw_context *brw,
surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
surf.ss0.surface_type = translate_tex_target(key->target);
-
- if (key->bo)
- surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode);
- else {
- switch(key->depth) {
- case 32: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break;
- default:
- case 24: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; break;
- case 16: surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; break;
- }
- }
+ surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode);
/* This is ok for all textures with channel width 8bit or less:
*/
/* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
- if (key->bo)
- surf.ss1.base_addr = key->bo->offset; /* reloc */
- else
- surf.ss1.base_addr = key->offset;
+
+ surf.ss1.base_addr = key->bo->offset; /* reloc */
surf.ss2.mip_count = key->last_level - key->first_level;
surf.ss2.width = key->width - 1;
surf.ss2.height = key->height - 1;
-
- surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
- surf.ss3.tiled_surface = key->tiled;
+ brw_set_surface_tiling(&surf, key->tiling);
surf.ss3.pitch = (key->pitch * key->cpp) - 1;
surf.ss3.depth = key->depth - 1;
@@ -211,17 +215,17 @@ brw_create_texture_surface( struct brw_context *brw,
bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
key, sizeof(*key),
- &key->bo, key->bo ? 1 : 0,
+ &key->bo, 1,
&surf, sizeof(surf),
NULL, NULL);
- if (key->bo) {
- /* Emit relocation to surface contents */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- 0,
- offsetof(struct brw_surface_state, ss1),
- key->bo);
- }
+
+ /* Emit relocation to surface contents */
+ intel_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_SAMPLER, 0,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ key->bo);
+
return bo;
}
@@ -236,35 +240,26 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
int ret = 0;
memset(&key, 0, sizeof(key));
-
- if (intelObj->imageOverride) {
- key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
- key.depth = intelObj->depthOverride;
- key.bo = NULL;
- key.offset = intelObj->textureOffset;
- } else {
- key.format = firstImage->TexFormat->MesaFormat;
- key.pitch = intelObj->mt->pitch;
- key.depth = firstImage->Depth;
- key.bo = intelObj->mt->region->buffer;
- key.offset = 0;
- ret |= dri_bufmgr_check_aperture_space(key.bo);
- }
-
key.target = tObj->Target;
key.depthmode = tObj->DepthMode;
+ key.format = firstImage->TexFormat->MesaFormat;
+ key.bo = intelObj->mt->region->buffer;
key.first_level = intelObj->firstLevel;
key.last_level = intelObj->lastLevel;
key.width = firstImage->Width;
key.height = firstImage->Height;
+ key.pitch = intelObj->mt->pitch;
key.cpp = intelObj->mt->cpp;
- key.tiled = intelObj->mt->region->tiled;
+ key.depth = firstImage->Depth;
+ key.tiling = intelObj->mt->region->tiling;
+
+ ret |= dri_bufmgr_check_aperture_space(key.bo);
dri_bo_unreference(brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS]);
brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
- &key, sizeof(key),
- &key.bo, key.bo ? 1 : 0,
- NULL);
+ &key, sizeof(key),
+ &key.bo, 1,
+ NULL);
if (brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] == NULL) {
brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_create_texture_surface(brw, &key);
}
@@ -289,7 +284,8 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
unsigned int surface_format;
unsigned int width, height, cpp;
GLubyte color_mask[4];
- GLboolean tiled, color_blend;
+ GLboolean color_blend;
+ uint32_t tiling;
} key;
memset(&key, 0, sizeof(key));
@@ -302,7 +298,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
else
key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
- key.tiled = region->tiled;
+ key.tiling = region->tiling;
key.width = region->pitch; /* XXX: not really! */
key.height = region->height;
key.cpp = region->cpp;
@@ -311,7 +307,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
} else {
key.surface_type = BRW_SURFACE_NULL;
key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
- key.tiled = 0;
+ key.tiling = 0;
key.width = 1;
key.height = 1;
key.cpp = 4;
@@ -341,8 +337,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
surf.ss2.width = key.width - 1;
surf.ss2.height = key.height - 1;
- surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
- surf.ss3.tiled_surface = key.tiled;
+ brw_set_surface_tiling(&surf, key.tiling);
surf.ss3.pitch = (key.width * key.cpp) - 1;
/* _NEW_COLOR */
@@ -359,13 +354,17 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
&surf, sizeof(surf),
NULL, NULL);
if (region_bo != NULL) {
- dri_emit_reloc(brw->wm.surf_bo[unit],
- DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_READ |
- DRM_BO_FLAG_WRITE,
- 0,
- offsetof(struct brw_surface_state, ss1),
- region_bo);
+ /* We might sample from it, and we might render to it, so flag
+ * them both. We might be able to figure out from other state
+ * a more restrictive relocation to emit.
+ */
+ intel_bo_emit_reloc(brw->wm.surf_bo[unit],
+ I915_GEM_DOMAIN_RENDER |
+ I915_GEM_DOMAIN_SAMPLER,
+ I915_GEM_DOMAIN_RENDER,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ region_bo);
}
}
@@ -409,13 +408,11 @@ brw_wm_get_binding_table(struct brw_context *brw)
/* Emit binding table relocations to surface state */
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
- dri_emit_reloc(bind_bo,
- DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_READ |
- DRM_BO_FLAG_WRITE,
- 0,
- i * sizeof(GLuint),
- brw->wm.surf_bo[i]);
+ intel_bo_emit_reloc(bind_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0,
+ i * sizeof(GLuint),
+ brw->wm.surf_bo[i]);
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c b/src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c
deleted file mode 120000
index e9df5c6279..0000000000
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_ttm.c \ No newline at end of file
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-18 23:16:58 +0000