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-rw-r--r--src/mesa/drivers/dri/i965/Makefile3
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h23
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c3
-rw-r--r--src/mesa/drivers/dri/i965/gen6_vs_state.c75
5 files changed, 101 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 7ce794d3aa..d21c921db3 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -86,7 +86,8 @@ DRIVER_SOURCES = \
brw_wm_state.c \
brw_wm_surface_state.c \
gen6_cc.c \
- gen6_depthstencil.c
+ gen6_depthstencil.c \
+ gen6_vs_state.c
C_SOURCES = \
$(COMMON_SOURCES) \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 5d3b0a8b7a..7a7bcc4e79 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -807,10 +807,29 @@
# define BRW_VE1_COMPONENT_3_SHIFT 16
# define BRW_VE1_DST_OFFSET_SHIFT 0
-#define CMD_3D_CC_STATE_POINTERS 0x780e /* GEN6+ */
#define CMD_INDEX_BUFFER 0x780a
-#define CMD_VF_STATISTICS_965 0x780b
+#define CMD_VF_STATISTICS_965 0x780b
#define CMD_VF_STATISTICS_GM45 0x680b
+#define CMD_3D_CC_STATE_POINTERS 0x780e /* GEN6+ */
+
+#define CMD_3D_VS_STATE 0x7810 /* GEN6+ */
+# define GEN6_VS_SPF_MODE (1 << 31)
+# define GEN6_VS_VECTOR_MASK_ENABLE (1 << 30)
+# define GEN6_VS_SAMPLER_COUNT_SHIFT 27
+# define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
+# define GEN6_VS_DISPATCH_START_GRF_SHIFT 20
+# define GEN6_VS_URB_READ_LENGTH_SHIFT 11
+# define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 0
+# define GEN6_VS_MAX_THREADS_SHIFT 25
+# define GEN6_VS_STATISTICS_ENABLE (1 << 10)
+# define GEN6_VS_CACHE_DISABLE (1 << 1)
+# define GEN6_VS_ENABLE (1 << 0)
+
+#define CMD_3D_CONSTANT_VS_STATE 0x7815 /* GEN6+ */
+# define GEN6_VS_BUFFER_3_ENABLE (1 << 15)
+# define GEN6_VS_BUFFER_2_ENABLE (1 << 14)
+# define GEN6_VS_BUFFER_1_ENABLE (1 << 13)
+# define GEN6_VS_BUFFER_0_ENABLE (1 << 12)
#define CMD_DRAW_RECT 0x7900
#define CMD_BLEND_CONSTANT_COLOR 0x7901
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 5112cd8016..5066fe151b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -95,6 +95,7 @@ const struct brw_tracked_state gen6_blend_state;
const struct brw_tracked_state gen6_cc_state_pointers;
const struct brw_tracked_state gen6_color_calc_state;
const struct brw_tracked_state gen6_depth_stencil_state;
+const struct brw_tracked_state gen6_vs_state;
/**
* Use same key for WM and VS surfaces.
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index ed9e18f33c..b4b086dec4 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -132,13 +132,14 @@ const struct brw_tracked_state *gen6_atoms[] =
&brw_vs_surfaces, /* must do before unit */
&brw_wm_constant_surface, /* must do before wm surfaces/bind bo */
&brw_wm_surfaces, /* must do before samplers and unit */
+
+ &gen6_vs_state,
#if 0
&brw_wm_samplers,
&brw_wm_unit,
&brw_sf_vp,
&brw_sf_unit,
- &brw_vs_unit, /* always required, enabled or not */
&brw_clip_unit,
&brw_gs_unit,
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
new file mode 100644
index 0000000000..4caabf32b0
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_vs_state(struct brw_context *brw)
+{
+ struct intel_context *intel = &brw->intel;
+
+ BEGIN_BATCH(6);
+ OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
+ OUT_BATCH(0); /* prog_bo */
+ /* OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */
+ OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
+ (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+ OUT_BATCH(0); /* scratch space base offset */
+ OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+ (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+ (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+ OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
+ GEN6_VS_STATISTICS_ENABLE);
+ ADVANCE_BATCH();
+
+ /* Disable all the constant buffers. */
+ BEGIN_BATCH(5);
+ OUT_BATCH(CMD_3D_CONSTANT_VS_STATE | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_vs_state = {
+ .dirty = {
+ .mesa = _NEW_TRANSFORM,
+ .brw = (BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_NR_VS_SURFACES |
+ BRW_NEW_URB_FENCE |
+ BRW_NEW_CONTEXT),
+ .cache = CACHE_NEW_VS_PROG
+ },
+ .emit = upload_vs_state,
+};