diff options
Diffstat (limited to 'src/mesa/drivers/dri/intel')
33 files changed, 694 insertions, 2158 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index ae0f8a16f9..9768b0deee 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -104,7 +104,8 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used) batch->map = NULL; batch->ptr = NULL; - dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16)); + if (!intel->no_hw) + dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16)); if (INTEL_DEBUG & DEBUG_BATCH) { dri_bo_map(batch->buf, GL_FALSE); @@ -158,9 +159,10 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, } /* Mark the end of the buffer. */ - *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */ + *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; batch->ptr += 4; used = batch->ptr - batch->map; + assert (used <= batch->buf->size); /* Workaround for recursive batchbuffer flushing: If the window is * moved, we can get into a case where we try to flush during a @@ -208,9 +210,11 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, { int ret; + assert(delta < buffer->size); + if (batch->ptr - batch->map > batch->buf->size) - _mesa_printf ("bad relocation ptr %p map %p offset %d size %d\n", - batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size); + printf ("bad relocation ptr %p map %p offset %d size %lu\n", + batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size); ret = dri_bo_emit_reloc(batch->buf, read_domains, write_domain, delta, batch->ptr - batch->map, buffer); @@ -224,6 +228,33 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, return GL_TRUE; } +GLboolean +intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch, + drm_intel_bo *buffer, + uint32_t read_domains, uint32_t write_domain, + uint32_t delta) +{ + int ret; + + assert(delta < buffer->size); + + if (batch->ptr - batch->map > batch->buf->size) + printf ("bad relocation ptr %p map %p offset %d size %lu\n", + batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size); + ret = drm_intel_bo_emit_reloc_fence(batch->buf, batch->ptr - batch->map, + buffer, delta, + read_domains, write_domain); + + /* + * Using the old buffer offset, write in what the right data would + * be, in case the buffer doesn't move and we can short-circuit the + * relocation processing in the kernel + */ + intel_batchbuffer_emit_dword (batch, buffer->offset + delta); + + return GL_TRUE; +} + void intel_batchbuffer_data(struct intel_batchbuffer *batch, const void *data, GLuint bytes) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index b052b724d8..e5ad2617ab 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -24,11 +24,13 @@ struct intel_batchbuffer GLuint size; +#ifdef DEBUG /** Tracking of BEGIN_BATCH()/OUT_BATCH()/ADVANCE_BATCH() debugging */ struct { GLuint total; GLubyte *start_ptr; } emit; +#endif GLuint dirty_state; GLuint reserved_space; @@ -64,8 +66,24 @@ GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, uint32_t read_domains, uint32_t write_domain, uint32_t offset); +GLboolean intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch, + drm_intel_bo *buffer, + uint32_t read_domains, + uint32_t write_domain, + uint32_t offset); void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch); +static INLINE uint32_t float_as_int(float f) +{ + union { + float f; + uint32_t d; + } fi; + + fi.f = f; + return fi.d; +} + /* Inline functions - might actually be better off with these * non-inlined. Certainly better off switching all command packets to * be passed as structs rather than dwords, but that's a little bit of @@ -81,49 +99,73 @@ intel_batchbuffer_space(struct intel_batchbuffer *batch) static INLINE void intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword) { - assert(batch->map); +#ifdef DEBUG assert(intel_batchbuffer_space(batch) >= 4); +#endif *(GLuint *) (batch->ptr) = dword; batch->ptr += 4; } static INLINE void +intel_batchbuffer_emit_float(struct intel_batchbuffer *batch, float f) +{ + intel_batchbuffer_emit_dword(batch, float_as_int(f)); +} + +static INLINE void intel_batchbuffer_require_space(struct intel_batchbuffer *batch, GLuint sz) { +#ifdef DEBUG assert(sz < batch->size - 8); +#endif if (intel_batchbuffer_space(batch) < sz) intel_batchbuffer_flush(batch); } +static INLINE void +intel_batchbuffer_begin(struct intel_batchbuffer *batch, int n) +{ + intel_batchbuffer_require_space(batch, n * 4); +#ifdef DEBUG + assert(batch->map); + assert(batch->emit.start_ptr == NULL); + batch->emit.total = n * 4; + batch->emit.start_ptr = batch->ptr; +#endif +} + +static INLINE void +intel_batchbuffer_advance(struct intel_batchbuffer *batch) +{ +#ifdef DEBUG + unsigned int _n = batch->ptr - batch->emit.start_ptr; + assert(batch->emit.start_ptr != NULL); + if (_n != batch->emit.total) { + fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n", + _n, batch->emit.total); + abort(); + } + batch->emit.start_ptr = NULL; +#endif +} + /* Here are the crusty old macros, to be removed: */ #define BATCH_LOCALS -#define BEGIN_BATCH(n) do { \ - intel_batchbuffer_require_space(intel->batch, (n)*4); \ - assert(intel->batch->emit.start_ptr == NULL); \ - intel->batch->emit.total = (n) * 4; \ - intel->batch->emit.start_ptr = intel->batch->ptr; \ -} while (0) - +#define BEGIN_BATCH(n) intel_batchbuffer_begin(intel->batch, n) #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d) - +#define OUT_BATCH_F(f) intel_batchbuffer_emit_float(intel->batch,f) #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ - assert((unsigned) (delta) < buf->size); \ intel_batchbuffer_emit_reloc(intel->batch, buf, \ read_domains, write_domain, delta); \ } while (0) +#define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \ + intel_batchbuffer_emit_reloc_fenced(intel->batch, buf, \ + read_domains, write_domain, delta); \ +} while (0) -#define ADVANCE_BATCH() do { \ - unsigned int _n = intel->batch->ptr - intel->batch->emit.start_ptr; \ - assert(intel->batch->emit.start_ptr != NULL); \ - if (_n != intel->batch->emit.total) { \ - fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n", \ - _n, intel->batch->emit.total); \ - abort(); \ - } \ - intel->batch->emit.start_ptr = NULL; \ -} while(0) +#define ADVANCE_BATCH() intel_batchbuffer_advance(intel->batch); #endif diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 1fd07e8b82..f2769aa3e8 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -89,6 +89,10 @@ intelEmitCopyBlit(struct intel_context *intel, dri_bo *aper_array[3]; BATCH_LOCALS; + /* Blits are in a different ringbuffer so we don't use them. */ + if (intel->gen >= 6) + return GL_FALSE; + if (dst_tiling != I915_TILING_NONE) { if (dst_offset & 4095) return GL_FALSE; @@ -115,22 +119,23 @@ intelEmitCopyBlit(struct intel_context *intel, break; } while (pass < 2); + intel_prepare_render(intel); + if (pass >= 2) { - dri_bo_map(dst_buffer, GL_TRUE); - dri_bo_map(src_buffer, GL_FALSE); - _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, - cpp, - dst_pitch, - dst_x, dst_y, - w, h, - (GLubyte *)src_buffer->virtual + src_offset, - src_pitch, - src_x, src_y); - - dri_bo_unmap(src_buffer); - dri_bo_unmap(dst_buffer); - - return GL_TRUE; + drm_intel_gem_bo_map_gtt(dst_buffer); + drm_intel_gem_bo_map_gtt(src_buffer); + _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, + cpp, + dst_pitch, + dst_x, dst_y, + w, h, + (GLubyte *)src_buffer->virtual + src_offset, + src_pitch, + src_x, src_y); + drm_intel_gem_bo_unmap_gtt(src_buffer); + drm_intel_gem_bo_unmap_gtt(dst_buffer); + + return GL_TRUE; } intel_batchbuffer_require_space(intel->batch, 8 * 4); @@ -183,14 +188,14 @@ intelEmitCopyBlit(struct intel_context *intel, OUT_BATCH(BR13 | (uint16_t)dst_pitch); OUT_BATCH((dst_y << 16) | dst_x); OUT_BATCH((dst_y2 << 16) | dst_x2); - OUT_RELOC(dst_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - dst_offset); + OUT_RELOC_FENCED(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); OUT_BATCH((src_y << 16) | src_x); OUT_BATCH((uint16_t)src_pitch); - OUT_RELOC(src_buffer, - I915_GEM_DOMAIN_RENDER, 0, - src_offset); + OUT_RELOC_FENCED(src_buffer, + I915_GEM_DOMAIN_RENDER, 0, + src_offset); ADVANCE_BATCH(); intel_batchbuffer_emit_mi_flush(intel->batch); @@ -216,6 +221,9 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) GLint cx, cy, cw, ch; BATCH_LOCALS; + /* Blits are in a different ringbuffer so we don't use them. */ + assert(intel->gen < 6); + /* * Compute values for clearing the buffers. */ @@ -241,6 +249,8 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) GLuint buf; all = (cw == fb->Width && ch == fb->Height); + intel_prepare_render(intel); + /* Loop over all renderbuffers */ for (buf = 0; buf < BUFFER_COUNT && mask; buf++) { const GLbitfield bufBit = 1 << buf; @@ -355,9 +365,9 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) OUT_BATCH(BR13); OUT_BATCH((y1 << 16) | x1); OUT_BATCH((y2 << 16) | x2); - OUT_RELOC(write_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - 0); + OUT_RELOC_FENCED(write_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); OUT_BATCH(clear_val); ADVANCE_BATCH(); @@ -384,6 +394,10 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; + /* Blits are in a different ringbuffer so we don't use them. */ + if (intel->gen >= 6) + return GL_FALSE; + if (dst_tiling != I915_TILING_NONE) { if (dst_offset & 4095) return GL_FALSE; @@ -434,9 +448,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ - OUT_RELOC(dst_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - dst_offset); + OUT_RELOC_FENCED(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ @@ -469,6 +483,9 @@ intel_emit_linear_blit(struct intel_context *intel, { GLuint pitch, height; + /* Blits are in a different ringbuffer so we don't use them. */ + assert(intel->gen < 6); + /* The pitch is a signed value. */ pitch = MIN2(size, (1 << 15) - 1); height = size / pitch; diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c index 3b7015b5ad..103aaf2b95 100644 --- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c @@ -31,10 +31,12 @@ #include "main/macros.h" #include "main/bufferobj.h" -#include "intel_context.h" #include "intel_blit.h" #include "intel_buffer_objects.h" #include "intel_batchbuffer.h" +#include "intel_context.h" +#include "intel_fbo.h" +#include "intel_mipmap_tree.h" #include "intel_regions.h" static GLboolean @@ -113,7 +115,7 @@ intel_bufferobj_free(GLcontext * ctx, struct gl_buffer_object *obj) if (obj->Pointer) intel_bufferobj_unmap(ctx, 0, obj); - _mesa_free(intel_obj->sys_buffer); + free(intel_obj->sys_buffer); if (intel_obj->region) { intel_bufferobj_release_region(intel, intel_obj); } @@ -121,7 +123,7 @@ intel_bufferobj_free(GLcontext * ctx, struct gl_buffer_object *obj) dri_bo_unreference(intel_obj->buffer); } - _mesa_free(intel_obj); + free(intel_obj); } @@ -155,7 +157,7 @@ intel_bufferobj_data(GLcontext * ctx, dri_bo_unreference(intel_obj->buffer); intel_obj->buffer = NULL; } - _mesa_free(intel_obj->sys_buffer); + free(intel_obj->sys_buffer); intel_obj->sys_buffer = NULL; if (size != 0) { @@ -164,7 +166,7 @@ intel_bufferobj_data(GLcontext * ctx, * with their contents anyway. */ if (target == GL_ARRAY_BUFFER || target == GL_ELEMENT_ARRAY_BUFFER) { - intel_obj->sys_buffer = _mesa_malloc(size); + intel_obj->sys_buffer = malloc(size); if (intel_obj->sys_buffer != NULL) { if (data != NULL) memcpy(intel_obj->sys_buffer, data, size); @@ -285,7 +287,7 @@ intel_bufferobj_map(GLcontext * ctx, return NULL; } - if (write_only && intel->intelScreen->kernel_exec_fencing) { + if (write_only) { drm_intel_gem_bo_map_gtt(intel_obj->buffer); intel_obj->mapped_gtt = GL_TRUE; } else { @@ -373,14 +375,13 @@ intel_bufferobj_map_range(GLcontext * ctx, if ((access & GL_MAP_INVALIDATE_RANGE_BIT) && drm_intel_bo_busy(intel_obj->buffer)) { if (access & GL_MAP_FLUSH_EXPLICIT_BIT) { - intel_obj->range_map_buffer = _mesa_malloc(length); + intel_obj->range_map_buffer = malloc(length); obj->Pointer = intel_obj->range_map_buffer; } else { intel_obj->range_map_bo = drm_intel_bo_alloc(intel->bufmgr, "range map", length, 64); - if (!(access & GL_MAP_READ_BIT) && - intel->intelScreen->kernel_exec_fencing) { + if (!(access & GL_MAP_READ_BIT)) { drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo); intel_obj->mapped_gtt = GL_TRUE; } else { @@ -393,8 +394,7 @@ intel_bufferobj_map_range(GLcontext * ctx, return obj->Pointer; } - if (!(access & GL_MAP_READ_BIT) && - intel->intelScreen->kernel_exec_fencing) { + if (!(access & GL_MAP_READ_BIT)) { drm_intel_gem_bo_map_gtt(intel_obj->buffer); intel_obj->mapped_gtt = GL_TRUE; } else { @@ -523,7 +523,7 @@ intel_bufferobj_buffer(struct intel_context *intel, intel_obj->Base.Size, sys_buffer, &intel_obj->Base); - _mesa_free(sys_buffer); + free(sys_buffer); intel_obj->sys_buffer = NULL; } @@ -588,6 +588,126 @@ intel_bufferobj_copy_subdata(GLcontext *ctx, intel_batchbuffer_emit_mi_flush(intel->batch); } +#if FEATURE_APPLE_object_purgeable +static GLenum +intel_buffer_purgeable(GLcontext * ctx, + drm_intel_bo *buffer, + GLenum option) +{ + int retained = 0; + + if (buffer != NULL) + retained = drm_intel_bo_madvise (buffer, I915_MADV_DONTNEED); + + return retained ? GL_VOLATILE_APPLE : GL_RELEASED_APPLE; +} + +static GLenum +intel_buffer_object_purgeable(GLcontext * ctx, + struct gl_buffer_object *obj, + GLenum option) +{ + struct intel_buffer_object *intel; + + intel = intel_buffer_object (obj); + if (intel->buffer != NULL) + return intel_buffer_purgeable (ctx, intel->buffer, option); + + if (option == GL_RELEASED_APPLE) { + if (intel->sys_buffer != NULL) { + free(intel->sys_buffer); + intel->sys_buffer = NULL; + } + + return GL_RELEASED_APPLE; + } else { + /* XXX Create the buffer and madvise(MADV_DONTNEED)? */ + return intel_buffer_purgeable (ctx, + intel_bufferobj_buffer(intel_context(ctx), + intel, INTEL_READ), + option); + } +} + +static GLenum +intel_texture_object_purgeable(GLcontext * ctx, + struct gl_texture_object *obj, + GLenum option) +{ + struct intel_texture_object *intel; + + intel = intel_texture_object(obj); + if (intel->mt == NULL || intel->mt->region == NULL) + return GL_RELEASED_APPLE; + + return intel_buffer_purgeable (ctx, intel->mt->region->buffer, option); +} + +static GLenum +intel_render_object_purgeable(GLcontext * ctx, + struct gl_renderbuffer *obj, + GLenum option) +{ + struct intel_renderbuffer *intel; + + intel = intel_renderbuffer(obj); + if (intel->region == NULL) + return GL_RELEASED_APPLE; + + return intel_buffer_purgeable (ctx, intel->region->buffer, option); +} + +static GLenum +intel_buffer_unpurgeable(GLcontext * ctx, + drm_intel_bo *buffer, + GLenum option) +{ + int retained; + + retained = 0; + if (buffer != NULL) + retained = drm_intel_bo_madvise (buffer, I915_MADV_WILLNEED); + + return retained ? GL_RETAINED_APPLE : GL_UNDEFINED_APPLE; +} + +static GLenum +intel_buffer_object_unpurgeable(GLcontext * ctx, + struct gl_buffer_object *obj, + GLenum option) +{ + return intel_buffer_unpurgeable (ctx, intel_buffer_object (obj)->buffer, option); +} + +static GLenum +intel_texture_object_unpurgeable(GLcontext * ctx, + struct gl_texture_object *obj, + GLenum option) +{ + struct intel_texture_object *intel; + + intel = intel_texture_object(obj); + if (intel->mt == NULL || intel->mt->region == NULL) + return GL_UNDEFINED_APPLE; + + return intel_buffer_unpurgeable (ctx, intel->mt->region->buffer, option); +} + +static GLenum +intel_render_object_unpurgeable(GLcontext * ctx, + struct gl_renderbuffer *obj, + GLenum option) +{ + struct intel_renderbuffer *intel; + + intel = intel_renderbuffer(obj); + if (intel->region == NULL) + return GL_UNDEFINED_APPLE; + + return intel_buffer_unpurgeable (ctx, intel->region->buffer, option); +} +#endif + void intelInitBufferObjectFuncs(struct dd_function_table *functions) { @@ -601,4 +721,14 @@ intelInitBufferObjectFuncs(struct dd_function_table *functions) functions->FlushMappedBufferRange = intel_bufferobj_flush_mapped_range; functions->UnmapBuffer = intel_bufferobj_unmap; functions->CopyBufferSubData = intel_bufferobj_copy_subdata; + +#if FEATURE_APPLE_object_purgeable + functions->BufferObjectPurgeable = intel_buffer_object_purgeable; + functions->TextureObjectPurgeable = intel_texture_object_purgeable; + functions->RenderObjectPurgeable = intel_render_object_purgeable; + + functions->BufferObjectUnpurgeable = intel_buffer_object_unpurgeable; + functions->TextureObjectUnpurgeable = intel_texture_object_unpurgeable; + functions->RenderObjectUnpurgeable = intel_render_object_unpurgeable; +#endif } diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 2f03e45005..b10693050a 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -271,13 +271,12 @@ intelDrawBuffer(GLcontext * ctx, GLenum mode) intel->is_front_buffer_rendering = (mode == GL_FRONT_LEFT) || (mode == GL_FRONT); - /* If we weren't front-buffer rendering before but we are now, make sure - * that the front-buffer has actually been allocated. + /* If we weren't front-buffer rendering before but we are now, + * invalidate our DRI drawable so we'll ask for new buffers + * (including the fake front) before we start rendering again. */ - if (!was_front_buffer_rendering && intel->is_front_buffer_rendering) { - intel_update_renderbuffers(intel->driContext, - intel->driContext->driDrawablePriv); - } + if (!was_front_buffer_rendering && intel->is_front_buffer_rendering) + dri2InvalidateDrawable(intel->driContext->driDrawablePriv); } intel_draw_buffer(ctx, ctx->DrawBuffer); @@ -295,13 +294,12 @@ intelReadBuffer(GLcontext * ctx, GLenum mode) intel->is_front_buffer_reading = (mode == GL_FRONT_LEFT) || (mode == GL_FRONT); - /* If we weren't front-buffer reading before but we are now, make sure - * that the front-buffer has actually been allocated. + /* If we weren't front-buffer reading before but we are now, + * invalidate our DRI drawable so we'll ask for new buffers + * (including the fake front) before we start reading again. */ - if (!was_front_buffer_reading && intel->is_front_buffer_reading) { - intel_update_renderbuffers(intel->driContext, - intel->driContext->driDrawablePriv); - } + if (!was_front_buffer_reading && intel->is_front_buffer_reading) + dri2InvalidateDrawable(intel->driContext->driReadablePriv); } if (ctx->ReadBuffer == ctx->DrawBuffer) { diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 3dc8653a73..a0b2266925 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -1,4 +1,4 @@ -/* + /* * Copyright © 2007 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,6 +71,8 @@ #define PCI_CHIP_ILD_G 0x0042 #define PCI_CHIP_ILM_G 0x0046 +#define PCI_CHIP_SANDYBRIDGE 0x0102 + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ devid == PCI_CHIP_I945_GM || \ @@ -104,14 +106,20 @@ devid == PCI_CHIP_Q33_G || \ devid == PCI_CHIP_Q35_G || IS_IGD(devid)) -#define IS_965(devid) (devid == PCI_CHIP_I965_G || \ +#define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \ devid == PCI_CHIP_I965_Q || \ devid == PCI_CHIP_I965_G_1 || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_I946_GZ || \ + IS_G4X(devid)) + +#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE) + +#define IS_965(devid) (IS_GEN4(devid) || \ IS_G4X(devid) || \ - IS_IGDNG(devid)) + IS_IGDNG(devid) || \ + IS_GEN6(devid)) #define IS_9XX(devid) (IS_915(devid) || \ IS_945(devid) || \ diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c index ca78681538..03b24e2b51 100644 --- a/src/mesa/drivers/dri/intel/intel_clear.c +++ b/src/mesa/drivers/dri/intel/intel_clear.c @@ -133,6 +133,12 @@ intelClear(GLcontext *ctx, GLbitfield mask) } } + if (intel->gen >= 6) { + /* Blits are in a different ringbuffer so we don't use them. */ + tri_mask |= blit_mask; + blit_mask = 0; + } + /* SW fallback clearing */ swrast_mask = mask & ~tri_mask & ~blit_mask; diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index fa2168b6ef..d6a1ba6952 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -197,6 +197,20 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) unsigned int attachments[10]; const char *region_name; + /* If we're rendering to the fake front buffer, make sure all the + * pending drawing has landed on the real front buffer. Otherwise + * when we eventually get to DRI2GetBuffersWithFormat the stale + * real front buffer contents will get copied to the new fake front + * buffer. + */ + if (intel->is_front_buffer_rendering) + intel_flush(&intel->ctx, GL_FALSE); + + /* Set this up front, so that in case our buffers get invalidated + * while we're getting new buffers, we don't clobber the stamp and + * thus ignore the invalidate. */ + drawable->lastStamp = drawable->dri2.stamp; + if (INTEL_DEBUG & DEBUG_DRI) fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); @@ -366,41 +380,44 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) } } - drawable->validBuffers = GL_TRUE; driUpdateFramebufferSize(&intel->ctx, drawable); } void +intel_prepare_render(struct intel_context *intel) +{ + __DRIcontext *driContext = intel->driContext; + __DRIdrawable *drawable; + + drawable = intel->driDrawable; + if (drawable->dri2.stamp != driContext->dri2.draw_stamp) { + if (drawable->lastStamp != drawable->dri2.stamp) + intel_update_renderbuffers(driContext, drawable); + intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer); + driContext->dri2.draw_stamp = drawable->dri2.stamp; + } + + drawable = intel->driReadDrawable; + if (drawable->dri2.stamp != driContext->dri2.read_stamp) { + if (drawable->lastStamp != drawable->dri2.stamp) + intel_update_renderbuffers(driContext, drawable); + driContext->dri2.read_stamp = drawable->dri2.stamp; + } +} + +void intel_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) { struct intel_context *intel = intel_context(ctx); __DRIcontext *driContext = intel->driContext; - void (*old_viewport)(GLcontext *ctx, GLint x, GLint y, - GLsizei w, GLsizei h); - - if (!intel->meta.internal_viewport_call && ctx->DrawBuffer->Name == 0) { - /* If we're rendering to the fake front buffer, make sure all the pending - * drawing has landed on the real front buffer. Otherwise when we - * eventually get to DRI2GetBuffersWithFormat the stale real front - * buffer contents will get copied to the new fake front buffer. - */ - if (intel->is_front_buffer_rendering) { - intel_flush(ctx, GL_FALSE); - } - intel_update_renderbuffers(driContext, driContext->driDrawablePriv); - if (driContext->driDrawablePriv != driContext->driReadablePriv) - intel_update_renderbuffers(driContext, driContext->driReadablePriv); + if (!intel->using_dri2_swapbuffers && + !intel->meta.internal_viewport_call && ctx->DrawBuffer->Name == 0) { + dri2InvalidateDrawable(driContext->driDrawablePriv); + dri2InvalidateDrawable(driContext->driReadablePriv); } - - old_viewport = ctx->Driver.Viewport; - ctx->Driver.Viewport = NULL; - intel->driDrawable = driContext->driDrawablePriv; - intel_draw_buffer(ctx, intel->ctx.DrawBuffer); - ctx->Driver.Viewport = old_viewport; } - static const struct dri_debug_control debug_control[] = { { "tex", DEBUG_TEXTURE}, { "state", DEBUG_STATE}, @@ -577,9 +594,13 @@ intelInitContext(struct intel_context *intel, struct intel_screen *intelScreen = sPriv->private; int bo_reuse_mode; + /* we can't do anything without a connection to the device */ + if (intelScreen->bufmgr == NULL) + return GL_FALSE; + if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx, functions, (void *) intel)) { - _mesa_printf("%s: failed to init mesa context\n", __FUNCTION__); + printf("%s: failed to init mesa context\n", __FUNCTION__); return GL_FALSE; } @@ -589,7 +610,11 @@ intelInitContext(struct intel_context *intel, intel->driContext = driContextPriv; intel->driFd = sPriv->fd; - if (IS_965(intel->intelScreen->deviceID)) { + if (IS_GEN6(intel->intelScreen->deviceID)) { + intel->gen = 6; + intel->needs_ff_sync = GL_TRUE; + intel->has_luminance_srgb = GL_TRUE; + } else if (IS_965(intel->intelScreen->deviceID)) { intel->gen = 4; } else if (IS_9XX(intel->intelScreen->deviceID)) { intel->gen = 3; @@ -730,12 +755,6 @@ intelInitContext(struct intel_context *intel, } intel->use_texture_tiling = driQueryOptionb(&intel->optionCache, "texture_tiling"); - if (intel->use_texture_tiling && - !intel->intelScreen->kernel_exec_fencing) { - fprintf(stderr, "No kernel support for execution fencing, " - "disabling texture tiling\n"); - intel->use_texture_tiling = GL_FALSE; - } intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z"); intel->prim.primitive = ~0; @@ -860,22 +879,13 @@ intelMakeCurrent(__DRIcontext * driContextPriv, if (driContextPriv) { struct gl_framebuffer *fb = driDrawPriv->driverPrivate; struct gl_framebuffer *readFb = driReadPriv->driverPrivate; - - intel_update_renderbuffers(driContextPriv, driDrawPriv); - if (driDrawPriv != driReadPriv) - intel_update_renderbuffers(driContextPriv, driReadPriv); - - /* set GLframebuffer size to match window, if needed */ - driUpdateFramebufferSize(&intel->ctx, driDrawPriv); - - if (driReadPriv != driDrawPriv) { - driUpdateFramebufferSize(&intel->ctx, driReadPriv); - } _mesa_make_current(&intel->ctx, fb, readFb); intel->driReadDrawable = driReadPriv; intel->driDrawable = driDrawPriv; - intel_draw_buffer(&intel->ctx, fb); + driContextPriv->dri2.draw_stamp = driDrawPriv->dri2.stamp - 1; + driContextPriv->dri2.read_stamp = driReadPriv->dri2.stamp - 1; + intel_prepare_render(intel); } else { _mesa_make_current(NULL, NULL, NULL); diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 0f0a194b3f..22736a9327 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -345,7 +345,7 @@ extern int INTEL_DEBUG; #define DBG(...) do { \ if (INTEL_DEBUG & FILE_DEBUG_FLAG) \ - _mesa_printf(__VA_ARGS__); \ + printf(__VA_ARGS__); \ } while(0) #define PCI_CHIP_845_G 0x2562 @@ -454,6 +454,7 @@ void intel_viewport(GLcontext * ctx, GLint x, GLint y, void intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); +void intel_prepare_render(struct intel_context *intel); void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region, uint32_t buffer_id); @@ -474,25 +475,4 @@ is_power_of_two(uint32_t value) return (value & (value - 1)) == 0; } -static INLINE void -intel_bo_map_gtt_preferred(struct intel_context *intel, - drm_intel_bo *bo, - GLboolean write) -{ - if (intel->intelScreen->kernel_exec_fencing) - drm_intel_gem_bo_map_gtt(bo); - else - drm_intel_bo_map(bo, write); -} - -static INLINE void -intel_bo_unmap_gtt_preferred(struct intel_context *intel, - drm_intel_bo *bo) -{ - if (intel->intelScreen->kernel_exec_fencing) - drm_intel_gem_bo_unmap_gtt(bo); - else - drm_intel_bo_unmap(bo); -} - #endif diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c index a9dfe281cb..5293482b35 100644 --- a/src/mesa/drivers/dri/intel/intel_decode.c +++ b/src/mesa/drivers/dri/intel/intel_decode.c @@ -1437,6 +1437,12 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) { 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, { 0x790a, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" }, { 0x7b00, 6, 6, "3DPRIMITIVE" }, + { 0x780e, 4, 4, "3DSTATE_CC_STATE_POINTERS" }, + { 0x7810, 6, 6, "3DSTATE_VS_STATE" }, + { 0x7811, 6, 6, "3DSTATE_GS_STATE" }, + { 0x7812, 4, 4, "3DSTATE_CLIP_STATE" }, + { 0x7815, 5, 5, "3DSTATE_CONSTANT_VS_STATE" }, + { 0x7816, 5, 5, "3DSTATE_CONSTANT_GS_STATE" }, }; len = (data[0] & 0x0000ffff) + 2; @@ -1592,7 +1598,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) return len; case 0x7905: - if (len != 5 && len != 6) + if (len < 5 || len > 7) fprintf(out, "Bad count in 3DSTATE_DEPTH_BUFFER\n"); if (count < len) BUFFER_FAIL(count, len, "3DSTATE_DEPTH_BUFFER"); @@ -1611,6 +1617,8 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) instr_out(data, hw_offset, 4, "volume depth\n"); if (len == 6) instr_out(data, hw_offset, 5, "\n"); + if (len == 7) + instr_out(data, hw_offset, 6, "render target view extent\n"); return len; diff --git a/src/mesa/drivers/dri/intel/intel_depthtmp.h b/src/mesa/drivers/dri/intel/intel_depthtmp.h deleted file mode 100644 index a9c75d44cf..0000000000 --- a/src/mesa/drivers/dri/intel/intel_depthtmp.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright © 2009 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Eric Anholt <eric@anholt.net> - * - */ - -/** - * Wrapper around the depthtmp.h macrofest to generate spans code for - * all the tiling styles. - */ - -#define VALUE_TYPE INTEL_VALUE_TYPE -#define WRITE_DEPTH(_x, _y, d) \ - (*(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual + \ - NO_TILE(_x, _y)) = d) -#define READ_DEPTH(d, _x, _y) \ - d = *(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual + \ - NO_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel_gttmap_##x) -#include "depthtmp.h" - -#define VALUE_TYPE INTEL_VALUE_TYPE -#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(NO_TILE(_x, _y), d) -#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(NO_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel##x) -#include "depthtmp.h" - -#define VALUE_TYPE INTEL_VALUE_TYPE -#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(X_TILE(_x, _y), d) -#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(X_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel_XTile_##x) -#include "depthtmp.h" - -#define VALUE_TYPE INTEL_VALUE_TYPE -#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(Y_TILE(_x, _y), d) -#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(Y_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel_YTile_##x) -#include "depthtmp.h" - -#undef INTEL_VALUE_TYPE -#undef INTEL_WRITE_DEPTH -#undef INTEL_READ_DEPTH -#undef INTEL_TAG diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 84c8d013e3..a1aac699c9 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -58,6 +58,7 @@ #define need_GL_EXT_secondary_color #define need_GL_EXT_stencil_two_side #define need_GL_APPLE_vertex_array_object +#define need_GL_APPLE_object_purgeable #define need_GL_ATI_separate_stencil #define need_GL_ATI_envmap_bumpmap #define need_GL_NV_point_sprite @@ -121,6 +122,7 @@ static const struct dri_extension card_extensions[] = { { "GL_EXT_texture_lod_bias", NULL }, { "GL_3DFX_texture_compression_FXT1", NULL }, { "GL_APPLE_client_storage", NULL }, + { "GL_APPLE_object_purgeable", GL_APPLE_object_purgeable_functions }, { "GL_APPLE_vertex_array_object", GL_APPLE_vertex_array_object_functions}, { "GL_MESA_pack_invert", NULL }, { "GL_MESA_ycbcr_texture", NULL }, @@ -151,6 +153,7 @@ static const struct dri_extension i915_extensions[] = { static const struct dri_extension brw_extensions[] = { { "GL_ARB_depth_clamp", NULL }, { "GL_ARB_depth_texture", NULL }, + { "GL_ARB_fragment_coord_conventions", NULL }, { "GL_ARB_fragment_program", NULL }, { "GL_ARB_fragment_program_shadow", NULL }, { "GL_ARB_fragment_shader", NULL }, @@ -181,6 +184,7 @@ static const struct dri_extension arb_oq_extensions[] = { { NULL, NULL } }; + static const struct dri_extension fragment_shader_extensions[] = { { "GL_ARB_fragment_shader", NULL }, { NULL, NULL } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index d58ffd95fa..a429f8d003 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -70,14 +70,11 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb) ASSERT(irb); - if (irb->span_cache != NULL) - _mesa_free(irb->span_cache); - if (intel && irb->region) { intel_region_release(&irb->region); } - _mesa_free(irb); + free(irb); } @@ -200,6 +197,38 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, } +#if FEATURE_OES_EGL_image +static void +intel_image_target_renderbuffer_storage(GLcontext *ctx, + struct gl_renderbuffer *rb, + void *image_handle) +{ + struct intel_context *intel = intel_context(ctx); + struct intel_renderbuffer *irb; + __DRIscreen *screen; + __DRIimage *image; + + screen = intel->intelScreen->driScrnPriv; + image = screen->dri2.image->lookupEGLImage(intel->driContext, image_handle, + intel->driContext->loaderPrivate); + if (image == NULL) + return; + + irb = intel_renderbuffer(rb); + if (irb->region) + intel_region_release(&irb->region); + intel_region_reference(&irb->region, image->region); + + rb->InternalFormat = image->internal_format; + rb->Width = image->region->width; + rb->Height = image->region->height; + rb->Format = image->format; + rb->DataType = image->data_type; + rb->_BaseFormat = _mesa_base_fbo_format(&intel->ctx, + image->internal_format); +} +#endif + /** * Called for each hardware renderbuffer when a _window_ is resized. * Just update fields. @@ -316,7 +345,7 @@ intel_create_renderbuffer(gl_format format) default: _mesa_problem(NULL, "Unexpected intFormat in intel_create_renderbuffer"); - _mesa_free(irb); + free(irb); return NULL; } @@ -468,7 +497,7 @@ intel_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage) irb->Base.ClassID = INTEL_RB_CLASS; if (!intel_update_wrapper(ctx, irb, texImage)) { - _mesa_free(irb); + free(irb); return NULL; } @@ -525,7 +554,7 @@ intel_render_texture(GLcontext * ctx, return; } - DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", + DBG("Begin render texture tid %lx tex=%u w=%d h=%d refcount=%d\n", _glthread_GetID(), att->Texture->Name, newImage->Width, newImage->Height, irb->Base.RefCount); @@ -651,4 +680,9 @@ intel_fbo_init(struct intel_context *intel) intel->ctx.Driver.ResizeBuffers = intel_resize_buffers; intel->ctx.Driver.ValidateFramebuffer = intel_validate_framebuffer; intel->ctx.Driver.BlitFramebuffer = _mesa_meta_BlitFramebuffer; + +#if FEATURE_OES_EGL_image + intel->ctx.Driver.EGLImageTargetRenderbufferStorage = + intel_image_target_renderbuffer_storage; +#endif } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 586dbbbb25..72413f7369 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -40,9 +40,6 @@ struct intel_renderbuffer { struct gl_renderbuffer Base; struct intel_region *region; - - uint8_t *span_cache; - unsigned long span_cache_offset; }; diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index cb5a341050..4f14946ec7 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -119,8 +119,7 @@ intel_miptree_create(struct intel_context *intel, struct intel_mipmap_tree *mt; uint32_t tiling; - if (intel->use_texture_tiling && compress_byte == 0 && - intel->intelScreen->kernel_exec_fencing) { + if (intel->use_texture_tiling && compress_byte == 0) { if (intel->gen >= 4 && (base_format == GL_DEPTH_COMPONENT || base_format == GL_DEPTH_STENCIL_EXT)) @@ -238,11 +237,11 @@ int intel_miptree_pitch_align (struct intel_context *intel, pitch = ALIGN(pitch * mt->cpp, pitch_align); #ifdef I915 - /* XXX: At least the i915 seems very upset when the pitch is a multiple - * of 1024 and sometimes 512 bytes - performance can drop by several - * times. Go to the next multiple of the required alignment for now. + /* Do a little adjustment to linear allocations so that we avoid + * hitting the same channel of memory for 2 different pages when + * reading a 2x2 subspan or doing bilinear filtering. */ - if (!(pitch & 511) && + if (tiling == I915_TILING_NONE && !(pitch & 511) && (pitch + pitch_align) < (1 << ctx->Const.MaxTextureLevels)) pitch += pitch_align; #endif diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index 1e517650b7..076fee89bd 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -123,7 +123,7 @@ static GLuint get_bitmap_rect(GLsizei width, GLsizei height, GLuint count = 0; if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s %d,%d %dx%d bitmap %dx%d skip %d src_offset %d mask %d\n", + printf("%s %d,%d %dx%d bitmap %dx%d skip %d src_offset %d mask %d\n", __FUNCTION__, x,y,w,h,width,height,unpack->SkipPixels, src_offset, mask); if (invert) { @@ -234,6 +234,8 @@ do_blit_bitmap( GLcontext *ctx, if (!intel_check_blit_fragment_ops(ctx, tmpColor[3] == 1.0F)) return GL_FALSE; + intel_prepare_render(intel); + /* Clip to buffer bounds and scissor. */ if (!_mesa_clip_to_region(fb->_Xmin, fb->_Ymin, fb->_Xmax, fb->_Ymax, @@ -393,7 +395,7 @@ intel_texture_bitmap(GLcontext * ctx, } /* Convert the A1 bitmap to an A8 format suitable for glTexImage */ - a8_bitmap = _mesa_calloc(width * height); + a8_bitmap = calloc(1, width * height); _mesa_expand_bitmap(width, height, unpack, bitmap, a8_bitmap, width, 0xff); if (_mesa_is_bufferobj(unpack->BufferObj)) { @@ -428,7 +430,7 @@ intel_texture_bitmap(GLcontext * ctx, _mesa_PixelStorei(GL_UNPACK_ALIGNMENT, 1); _mesa_TexImage2D(GL_TEXTURE_2D, 0, GL_ALPHA, width, height, 0, GL_ALPHA, GL_UNSIGNED_BYTE, a8_bitmap); - _mesa_free(a8_bitmap); + free(a8_bitmap); meta_set_fragment_program(&intel->meta, &intel->meta.bitmap_fp, fp); _mesa_ProgramLocalParameter4fvARB(GL_FRAGMENT_PROGRAM_ARB, 0, @@ -514,7 +516,7 @@ intelBitmap(GLcontext * ctx, return; if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s: fallback to swrast\n", __FUNCTION__); + printf("%s: fallback to swrast\n", __FUNCTION__); _swrast_Bitmap(ctx, x, y, width, height, unpack, pixels); } diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c index 87c293d8b0..f4f3fd6d88 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c @@ -138,6 +138,8 @@ do_blit_copypixels(GLcontext * ctx, intelFlush(&intel->ctx); + intel_prepare_render(intel); + /* XXX: We fail to handle different inversion between read and draw framebuffer. */ /* Clip to destination buffer. */ diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c index 10177228bd..bd1dd13fb7 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c @@ -147,7 +147,7 @@ intel_stencil_drawpixels(GLcontext * ctx, /* Unpack the supplied stencil values into a ubyte buffer. */ assert(sizeof(GLstencil) == sizeof(GLubyte)); - stencil_pixels = _mesa_malloc(width * height * sizeof(GLstencil)); + stencil_pixels = malloc(width * height * sizeof(GLstencil)); for (row = 0; row < height; row++) { GLvoid *source = _mesa_image_address2d(unpack, pixels, width, height, @@ -201,7 +201,7 @@ intel_stencil_drawpixels(GLcontext * ctx, _mesa_TexImage2D(GL_TEXTURE_2D, 0, GL_INTENSITY, width, height, 0, GL_RED, GL_UNSIGNED_BYTE, stencil_pixels); ctx->Unpack = old_unpack; - _mesa_free(stencil_pixels); + free(stencil_pixels); meta_set_passthrough_transform(&intel->meta); diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c index a98e8e16c2..2ac3da7f42 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_read.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c @@ -80,7 +80,7 @@ do_blit_readpixels(GLcontext * ctx, GLint dst_x, dst_y; if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s\n", __FUNCTION__); + printf("%s\n", __FUNCTION__); if (!src) return GL_FALSE; @@ -89,7 +89,7 @@ do_blit_readpixels(GLcontext * ctx, /* PBO only for now: */ if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s - not PBO\n", __FUNCTION__); + printf("%s - not PBO\n", __FUNCTION__); return GL_FALSE; } @@ -97,13 +97,13 @@ do_blit_readpixels(GLcontext * ctx, if (ctx->_ImageTransferState || !intel_check_blit_format(src, format, type)) { if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s - bad format for blit\n", __FUNCTION__); + printf("%s - bad format for blit\n", __FUNCTION__); return GL_FALSE; } if (pack->Alignment != 1 || pack->SwapBytes || pack->LsbFirst) { if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s: bad packing params\n", __FUNCTION__); + printf("%s: bad packing params\n", __FUNCTION__); return GL_FALSE; } @@ -114,7 +114,7 @@ do_blit_readpixels(GLcontext * ctx, if (pack->Invert) { if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s: MESA_PACK_INVERT not done yet\n", __FUNCTION__); + printf("%s: MESA_PACK_INVERT not done yet\n", __FUNCTION__); return GL_FALSE; } else { @@ -132,6 +132,8 @@ do_blit_readpixels(GLcontext * ctx, return GL_TRUE; } + intel_prepare_render(intel); + all = (width * height * src->cpp == dst->Base.Size && x == 0 && dst_offset == 0); @@ -157,7 +159,7 @@ do_blit_readpixels(GLcontext * ctx, } if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s - DONE\n", __FUNCTION__); + printf("%s - DONE\n", __FUNCTION__); return GL_TRUE; } @@ -172,13 +174,14 @@ intelReadPixels(GLcontext * ctx, fprintf(stderr, "%s\n", __FUNCTION__); intelFlush(ctx); + intel_prepare_render(intel_context(ctx)); if (do_blit_readpixels (ctx, x, y, width, height, format, type, pack, pixels)) return; if (INTEL_DEBUG & DEBUG_PIXEL) - _mesa_printf("%s: fallback to swrast\n", __FUNCTION__); + printf("%s: fallback to swrast\n", __FUNCTION__); /* Update Mesa state before calling down into _swrast_ReadPixels, as * the spans code requires the computed buffer states to be up to date, diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 881653ff01..f042bcbc28 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -42,7 +42,7 @@ #include <sys/ioctl.h> #include <errno.h> -#include <main/hash.h> +#include "main/hash.h" #include "intel_context.h" #include "intel_regions.h" #include "intel_blit.h" @@ -118,8 +118,7 @@ intel_region_map(struct intel_context *intel, struct intel_region *region) if (region->pbo) intel_region_cow(intel, region); - if (region->tiling != I915_TILING_NONE && - intel->intelScreen->kernel_exec_fencing) + if (region->tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(region->buffer); else dri_bo_map(region->buffer, GL_TRUE); @@ -134,8 +133,7 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region) { _DBG("%s %p\n", __FUNCTION__, region); if (!--region->map_refcount) { - if (region->tiling != I915_TILING_NONE && - intel->intelScreen->kernel_exec_fencing) + if (region->tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(region->buffer); else dri_bo_unmap(region->buffer); @@ -180,36 +178,19 @@ intel_region_alloc(struct intel_context *intel, { dri_bo *buffer; struct intel_region *region; + unsigned long flags = 0; + unsigned long aligned_pitch; - /* If we're tiled, our allocations are in 8 or 32-row blocks, so - * failure to align our height means that we won't allocate enough pages. - * - * If we're untiled, we still have to align to 2 rows high because the - * data port accesses 2x2 blocks even if the bottom row isn't to be - * rendered, so failure to align means we could walk off the end of the - * GTT and fault. - */ - if (tiling == I915_TILING_X) - height = ALIGN(height, 8); - else if (tiling == I915_TILING_Y) - height = ALIGN(height, 32); - else - height = ALIGN(height, 2); - - /* If we're untiled, we have to align to 2 rows high because the - * data port accesses 2x2 blocks even if the bottom row isn't to be - * rendered, so failure to align means we could walk off the end of the - * GTT and fault. + if (expect_accelerated_upload) + flags |= BO_ALLOC_FOR_RENDER; + + buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "region", + width, height, cpp, + &tiling, &aligned_pitch, flags); + /* We've already chosen a pitch as part of miptree layout. It had + * better be the same. */ - height = ALIGN(height, 2); - - if (expect_accelerated_upload) { - buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", - pitch * cpp * height, 64); - } else { - buffer = drm_intel_bo_alloc(intel->bufmgr, "region", - pitch * cpp * height, 64); - } + assert(aligned_pitch == pitch * cpp); region = intel_region_alloc_internal(intel, cpp, width, height, pitch, buffer); @@ -378,6 +359,8 @@ intel_region_data(struct intel_context *intel, intel_region_cow(intel, dst); } + intel_prepare_render(intel); + _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset, dst->cpp, dst->pitch, @@ -500,6 +483,7 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region) /* Now blit from the texture buffer to the new buffer: */ + intel_prepare_render(intel); ok = intelEmitCopyBlit(intel, region->cpp, region->pitch, pbo->buffer, 0, region->tiling, diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h index 6d36f3d88a..7ee6a988ea 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.h +++ b/src/mesa/drivers/dri/intel/intel_regions.h @@ -148,4 +148,12 @@ void _mesa_copy_rect(GLubyte * dst, const GLubyte * src, GLuint src_pitch, GLuint src_x, GLuint src_y); +struct __DRIimageRec { + struct intel_region *region; + GLenum internal_format; + GLuint format; + GLenum data_type; + void *data; +}; + #endif diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index f7ce87e063..6e4bb64365 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -30,6 +30,7 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/hash.h" +#include "main/fbobject.h" #include "utils.h" #include "xmlpool.h" @@ -41,13 +42,11 @@ #include "intel_fbo.h" #include "intel_screen.h" #include "intel_tex.h" +#include "intel_regions.h" #include "i915_drm.h" #define DRI_CONF_TEXTURE_TILING(def) \ - DRI_CONF_OPT_BEGIN(texture_tiling, bool, def) \ - DRI_CONF_DESC(en, "Enable texture tiling") \ - DRI_CONF_OPT_END \ PUBLIC const char __driConfigOptions[] = DRI_CONF_BEGIN @@ -63,11 +62,9 @@ PUBLIC const char __driConfigOptions[] = DRI_CONF_DESC_END DRI_CONF_OPT_END -#ifdef I915 - DRI_CONF_TEXTURE_TILING(false) -#else - DRI_CONF_TEXTURE_TILING(true) -#endif + DRI_CONF_OPT_BEGIN(texture_tiling, bool, true) + DRI_CONF_DESC(en, "Enable texture tiling") + DRI_CONF_OPT_END DRI_CONF_OPT_BEGIN(early_z, bool, false) DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).") @@ -99,11 +96,6 @@ const GLuint __driNConfigOptions = 11; static PFNGLXCREATECONTEXTMODES create_context_modes = NULL; #endif /*USE_NEW_INTERFACE */ -static const __DRItexOffsetExtension intelTexOffsetExtension = { - { __DRI_TEX_OFFSET }, - intelSetTexOffset, -}; - static const __DRItexBufferExtension intelTexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, intelSetTexBuffer, @@ -123,29 +115,116 @@ intelDRI2Flush(__DRIdrawable *drawable) } static void -intelDRI2FlushInvalidate(__DRIdrawable *drawable) +intelDRI2Invalidate(__DRIdrawable *drawable) { struct intel_context *intel = drawable->driContextPriv->driverPrivate; intel->using_dri2_swapbuffers = GL_TRUE; - - intelDRI2Flush(drawable); - drawable->validBuffers = GL_FALSE; - - intel_update_renderbuffers(intel->driContext, drawable); + dri2InvalidateDrawable(drawable); } static const struct __DRI2flushExtensionRec intelFlushExtension = { { __DRI2_FLUSH, __DRI2_FLUSH_VERSION }, intelDRI2Flush, - intelDRI2FlushInvalidate, + intelDRI2Invalidate, +}; + +static __DRIimage * +intel_create_image_from_name(__DRIcontext *context, + int width, int height, int format, + int name, int pitch, void *loaderPrivate) +{ + __DRIimage *image; + struct intel_context *intel = context->driverPrivate; + int cpp; + + image = CALLOC(sizeof *image); + if (image == NULL) + return NULL; + + switch (format) { + case __DRI_IMAGE_FORMAT_RGB565: + image->format = MESA_FORMAT_RGB565; + image->internal_format = GL_RGB; + image->data_type = GL_UNSIGNED_BYTE; + break; + case __DRI_IMAGE_FORMAT_XRGB8888: + image->format = MESA_FORMAT_XRGB8888; + image->internal_format = GL_RGB; + image->data_type = GL_UNSIGNED_BYTE; + break; + case __DRI_IMAGE_FORMAT_ARGB8888: + image->format = MESA_FORMAT_ARGB8888; + image->internal_format = GL_RGBA; + image->data_type = GL_UNSIGNED_BYTE; + break; + default: + free(image); + return NULL; + } + + image->data = loaderPrivate; + cpp = _mesa_get_format_bytes(image->format); + + image->region = intel_region_alloc_for_handle(intel, cpp, width, height, + pitch, name, "image"); + if (image->region == NULL) { + FREE(image); + return NULL; + } + + return image; +} + +static __DRIimage * +intel_create_image_from_renderbuffer(__DRIcontext *context, + int renderbuffer, void *loaderPrivate) +{ + __DRIimage *image; + struct intel_context *intel = context->driverPrivate; + struct gl_renderbuffer *rb; + struct intel_renderbuffer *irb; + + rb = _mesa_lookup_renderbuffer(&intel->ctx, renderbuffer); + if (!rb) { + _mesa_error(&intel->ctx, + GL_INVALID_OPERATION, "glRenderbufferExternalMESA"); + return NULL; + } + + irb = intel_renderbuffer(rb); + image = CALLOC(sizeof *image); + if (image == NULL) + return NULL; + + image->internal_format = rb->InternalFormat; + image->format = rb->Format; + image->data_type = rb->DataType; + image->data = loaderPrivate; + intel_region_reference(&image->region, irb->region); + + return image; +} + +static void +intel_destroy_image(__DRIimage *image) +{ + intel_region_release(&image->region); + FREE(image); +} + +static struct __DRIimageExtensionRec intelImageExtension = { + { __DRI_IMAGE, __DRI_IMAGE_VERSION }, + intel_create_image_from_name, + intel_create_image_from_renderbuffer, + intel_destroy_image, }; static const __DRIextension *intelScreenExtensions[] = { &driReadDrawableExtension, - &intelTexOffsetExtension.base, &intelTexBufferExtension.base, &intelFlushExtension.base, + &intelImageExtension.base, NULL }; @@ -331,10 +410,13 @@ intel_init_bufmgr(struct intel_screen *intelScreen) return GL_FALSE; } - if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences)) - intelScreen->kernel_exec_fencing = !!num_fences; - else - intelScreen->kernel_exec_fencing = GL_FALSE; + if (!intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences) || + num_fences == 0) { + fprintf(stderr, "[%s: %u] Kernel 2.6.29 required.\n", __func__, __LINE__); + return GL_FALSE; + } + + drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr); intelScreen->named_regions = _mesa_NewHashTable(); diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index 1ce476daca..5863093f00 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -46,7 +46,6 @@ struct intel_screen GLboolean no_vbo; dri_bufmgr *bufmgr; - GLboolean kernel_exec_fencing; struct _mesa_HashTable *named_regions; /** diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index d925cb9997..fb5c01bc4d 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -43,218 +43,6 @@ static void intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb); -#define SPAN_CACHE_SIZE 4096 - -static void -get_span_cache(struct intel_renderbuffer *irb, uint32_t offset) -{ - if (irb->span_cache == NULL) { - irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE); - irb->span_cache_offset = -1; - } - - if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) { - irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1); - dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset, - SPAN_CACHE_SIZE, irb->span_cache); - } -} - -static void -clear_span_cache(struct intel_renderbuffer *irb) -{ - irb->span_cache_offset = -1; -} - -static uint32_t -pread_32(struct intel_renderbuffer *irb, uint32_t offset) -{ - get_span_cache(irb, offset); - - return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))); -} - -static uint32_t -pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset) -{ - get_span_cache(irb, offset); - - return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) | - 0xff000000; -} - -static uint16_t -pread_16(struct intel_renderbuffer *irb, uint32_t offset) -{ - get_span_cache(irb, offset); - - return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))); -} - -static uint8_t -pread_8(struct intel_renderbuffer *irb, uint32_t offset) -{ - get_span_cache(irb, offset); - - return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))); -} - -static void -pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val) -{ - clear_span_cache(irb); - - dri_bo_subdata(irb->region->buffer, offset, 4, &val); -} - -static void -pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val) -{ - clear_span_cache(irb); - - dri_bo_subdata(irb->region->buffer, offset, 3, &val); -} - -static void -pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val) -{ - clear_span_cache(irb); - - dri_bo_subdata(irb->region->buffer, offset, 2, &val); -} - -static void -pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val) -{ - clear_span_cache(irb); - - dri_bo_subdata(irb->region->buffer, offset, 1, &val); -} - -static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb, - int x, int y) -{ - return (y * irb->region->pitch + x) * irb->region->cpp; -} - -/* - * Deal with tiled surfaces - */ - -static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb, - int x, int y) -{ - int tile_stride; - int xbyte; - int x_tile_off, y_tile_off; - int x_tile_number, y_tile_number; - int tile_off, tile_base; - - x += irb->region->draw_x; - y += irb->region->draw_y; - - tile_stride = (irb->region->pitch * irb->region->cpp) << 3; - - xbyte = x * irb->region->cpp; - - x_tile_off = xbyte & 0x1ff; - y_tile_off = y & 7; - - x_tile_number = xbyte >> 9; - y_tile_number = y >> 3; - - tile_off = (y_tile_off << 9) + x_tile_off; - - switch (irb->region->bit_6_swizzle) { - case I915_BIT_6_SWIZZLE_NONE: - break; - case I915_BIT_6_SWIZZLE_9: - tile_off ^= ((tile_off >> 3) & 64); - break; - case I915_BIT_6_SWIZZLE_9_10: - tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64); - break; - case I915_BIT_6_SWIZZLE_9_11: - tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64); - break; - case I915_BIT_6_SWIZZLE_9_10_11: - tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^ - ((tile_off >> 5) & 64); - break; - default: - fprintf(stderr, "Unknown tile swizzling mode %d\n", - irb->region->bit_6_swizzle); - exit(1); - } - - tile_base = (x_tile_number << 12) + y_tile_number * tile_stride; - -#if 0 - printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n", - x, y, tile_off, tile_base, - tile_off + tile_base, - irb->region->pitch, tile_stride); -#endif - - return tile_base + tile_off; -} - -static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, - int x, int y) -{ - int tile_stride; - int xbyte; - int x_tile_off, y_tile_off; - int x_tile_number, y_tile_number; - int tile_off, tile_base; - - x += irb->region->draw_x; - y += irb->region->draw_y; - - tile_stride = (irb->region->pitch * irb->region->cpp) << 5; - - xbyte = x * irb->region->cpp; - - x_tile_off = xbyte & 0x7f; - y_tile_off = y & 0x1f; - - x_tile_number = xbyte >> 7; - y_tile_number = y >> 5; - - tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + - (x_tile_off & 0xf); - - switch (irb->region->bit_6_swizzle) { - case I915_BIT_6_SWIZZLE_NONE: - break; - case I915_BIT_6_SWIZZLE_9: - tile_off ^= ((tile_off >> 3) & 64); - break; - case I915_BIT_6_SWIZZLE_9_10: - tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64); - break; - case I915_BIT_6_SWIZZLE_9_11: - tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64); - break; - case I915_BIT_6_SWIZZLE_9_10_11: - tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^ - ((tile_off >> 5) & 64); - break; - default: - fprintf(stderr, "Unknown tile swizzling mode %d\n", - irb->region->bit_6_swizzle); - exit(1); - } - - tile_base = (x_tile_number << 12) + y_tile_number * tile_stride; - - return tile_base + tile_off; -} - -/* - break intelWriteRGBASpan_ARGB8888 -*/ - #undef DBG #define DBG 0 @@ -280,50 +68,43 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, #define HW_UNLOCK() -/* Convenience macros to avoid typing the swizzle argument over and over */ -#define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X), (_Y)) -#define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X), (_Y)) -#define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X), (_Y)) +/* Convenience macros to avoid typing the address argument over and over */ +#define NO_TILE(_X, _Y) (((_Y) * irb->region->pitch + (_X)) * irb->region->cpp) /* r5g6b5 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_RGB -#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 -#define INTEL_READ_VALUE(offset) pread_16(irb, offset) -#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v) -#define INTEL_TAG(x) x##_RGB565 -#include "intel_spantmp.h" +#define SPANTMP_PIXEL_FMT GL_RGB +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 +#define TAG(x) intel_##x##_RGB565 +#define TAG2(x,y) intel_##x##y_RGB565 +#include "spantmp2.h" /* a4r4g4b4 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_BGRA -#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV -#define INTEL_READ_VALUE(offset) pread_16(irb, offset) -#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v) -#define INTEL_TAG(x) x##_ARGB4444 -#include "intel_spantmp.h" +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV +#define TAG(x) intel_##x##_ARGB4444 +#define TAG2(x,y) intel_##x##y_ARGB4444 +#include "spantmp2.h" /* a1r5g5b5 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_BGRA -#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV -#define INTEL_READ_VALUE(offset) pread_16(irb, offset) -#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v) -#define INTEL_TAG(x) x##_ARGB1555 -#include "intel_spantmp.h" +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV +#define TAG(x) intel_##x##_ARGB1555 +#define TAG2(x,y) intel_##x##y##_ARGB1555 +#include "spantmp2.h" /* a8r8g8b8 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_BGRA -#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV -#define INTEL_READ_VALUE(offset) pread_32(irb, offset) -#define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v) -#define INTEL_TAG(x) x##_ARGB8888 -#include "intel_spantmp.h" +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV +#define TAG(x) intel_##x##_ARGB8888 +#define TAG2(x,y) intel_##x##y##_ARGB8888 +#include "spantmp2.h" /* x8r8g8b8 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_BGR -#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV -#define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset) -#define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v) -#define INTEL_TAG(x) x##_xRGB8888 -#include "intel_spantmp.h" +#define SPANTMP_PIXEL_FMT GL_BGR +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV +#define TAG(x) intel_##x##_xRGB8888 +#define TAG2(x,y) intel_##x##y##_xRGB8888 +#include "spantmp2.h" #define LOCAL_DEPTH_VARS \ struct intel_renderbuffer *irb = intel_renderbuffer(rb); \ @@ -339,52 +120,22 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS /* z16 depthbuffer functions. */ -#define INTEL_VALUE_TYPE GLushort -#define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d) -#define INTEL_READ_DEPTH(offset) pread_16(irb, offset) -#define INTEL_TAG(name) name##_z16 -#include "intel_depthtmp.h" - -/* z24x8 depthbuffer functions. */ -#define INTEL_VALUE_TYPE GLuint -#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d) -#define INTEL_READ_DEPTH(offset) pread_32(irb, offset) -#define INTEL_TAG(name) name##_z24_x8 -#include "intel_depthtmp.h" - - -/** - ** 8-bit stencil function (XXX FBO: This is obsolete) - **/ -/* XXX */ -#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d) -#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3); -#define TAG(x) intel_gttmap_##x##_z24_s8 -#include "stenciltmp.h" - -/** - ** 8-bit stencil function (XXX FBO: This is obsolete) - **/ -#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d) -#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3); -#define TAG(x) intel##x##_z24_s8 -#include "stenciltmp.h" - -/** - ** 8-bit x-tile stencil function (XXX FBO: This is obsolete) - **/ -#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d) -#define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3); -#define TAG(x) intel_XTile_##x##_z24_s8 -#include "stenciltmp.h" - -/** - ** 8-bit y-tile stencil function (XXX FBO: This is obsolete) - **/ -#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d) -#define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3) -#define TAG(x) intel_YTile_##x##_z24_s8 -#include "stenciltmp.h" +#define VALUE_TYPE GLushort +#define WRITE_DEPTH(_x, _y, d) \ + (*(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d) +#define READ_DEPTH(d, _x, _y) \ + d = *(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) +#define TAG(x) intel_##x##_z16 +#include "depthtmp.h" + +/* z24_s8 and z24_x8 depthbuffer functions. */ +#define VALUE_TYPE GLuint +#define WRITE_DEPTH(_x, _y, d) \ + (*(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d) +#define READ_DEPTH(d, _x, _y) \ + d = *(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) +#define TAG(x) intel_##x##_z24_x8 +#include "depthtmp.h" void intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb) @@ -394,8 +145,7 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb) if (irb == NULL || irb->region == NULL) return; - if (intel->intelScreen->kernel_exec_fencing) - drm_intel_gem_bo_map_gtt(irb->region->buffer); + drm_intel_gem_bo_map_gtt(irb->region->buffer); intel_set_span_functions(intel, rb); } @@ -409,10 +159,7 @@ intel_renderbuffer_unmap(struct intel_context *intel, if (irb == NULL || irb->region == NULL) return; - if (intel->intelScreen->kernel_exec_fencing) - drm_intel_gem_bo_unmap_gtt(irb->region->buffer); - else - clear_span_cache(irb); + drm_intel_gem_bo_unmap_gtt(irb->region->buffer); rb->GetRow = NULL; rb->PutRow = NULL; @@ -498,6 +245,7 @@ intelSpanRenderStart(GLcontext * ctx) GLuint i; intelFlush(&intel->ctx); + intel_prepare_render(intel); for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { @@ -591,182 +339,34 @@ intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb) { struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; - uint32_t tiling = irb->region->tiling; - - if (intel->intelScreen->kernel_exec_fencing) { - switch (irb->Base.Format) { - case MESA_FORMAT_RGB565: - intel_gttmap_InitPointers_RGB565(rb); - break; - case MESA_FORMAT_ARGB4444: - intel_gttmap_InitPointers_ARGB4444(rb); - break; - case MESA_FORMAT_ARGB1555: - intel_gttmap_InitPointers_ARGB1555(rb); - break; - case MESA_FORMAT_XRGB8888: - intel_gttmap_InitPointers_xRGB8888(rb); - break; - case MESA_FORMAT_ARGB8888: - intel_gttmap_InitPointers_ARGB8888(rb); - break; - case MESA_FORMAT_Z16: - intel_gttmap_InitDepthPointers_z16(rb); - break; - case MESA_FORMAT_X8_Z24: - intel_gttmap_InitDepthPointers_z24_x8(rb); - break; - case MESA_FORMAT_S8_Z24: - /* There are a few different ways SW asks us to access the S8Z24 data: - * Z24 depth-only depth reads - * S8Z24 depth reads - * S8Z24 stencil reads. - */ - if (rb->Format == MESA_FORMAT_S8_Z24) { - intel_gttmap_InitDepthPointers_z24_x8(rb); - } else if (rb->Format == MESA_FORMAT_S8) { - intel_gttmap_InitStencilPointers_z24_s8(rb); - } - break; - default: - _mesa_problem(NULL, - "Unexpected MesaFormat %d in intelSetSpanFunctions", - irb->Base.Format); - break; - } - return; - } - /* If in GEM mode, we need to do the tile address swizzling ourselves, - * instead of the fence registers handling it. - */ switch (irb->Base.Format) { case MESA_FORMAT_RGB565: - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_RGB565(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_RGB565(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_RGB565(rb); - break; - } + intel_InitPointers_RGB565(rb); break; case MESA_FORMAT_ARGB4444: - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_ARGB4444(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_ARGB4444(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_ARGB4444(rb); - break; - } + intel_InitPointers_ARGB4444(rb); break; case MESA_FORMAT_ARGB1555: - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_ARGB1555(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_ARGB1555(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_ARGB1555(rb); - break; - } + intel_InitPointers_ARGB1555(rb); break; case MESA_FORMAT_XRGB8888: - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_xRGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_xRGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_xRGB8888(rb); - break; - } + intel_InitPointers_xRGB8888(rb); break; case MESA_FORMAT_ARGB8888: - /* 8888 RGBA */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_ARGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_ARGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_ARGB8888(rb); - break; - } + intel_InitPointers_ARGB8888(rb); break; case MESA_FORMAT_Z16: - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitDepthPointers_z16(rb); - break; - case I915_TILING_X: - intel_XTile_InitDepthPointers_z16(rb); - break; - case I915_TILING_Y: - intel_YTile_InitDepthPointers_z16(rb); - break; - } + intel_InitDepthPointers_z16(rb); break; case MESA_FORMAT_X8_Z24: case MESA_FORMAT_S8_Z24: - /* There are a few different ways SW asks us to access the S8Z24 data: - * Z24 depth-only depth reads - * S8Z24 depth reads - * S8Z24 stencil reads. - */ - if (rb->Format == MESA_FORMAT_S8_Z24) { - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitDepthPointers_z24_x8(rb); - break; - case I915_TILING_X: - intel_XTile_InitDepthPointers_z24_x8(rb); - break; - case I915_TILING_Y: - intel_YTile_InitDepthPointers_z24_x8(rb); - break; - } - } else if (rb->Format == MESA_FORMAT_S8) { - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitStencilPointers_z24_s8(rb); - break; - case I915_TILING_X: - intel_XTile_InitStencilPointers_z24_s8(rb); - break; - case I915_TILING_Y: - intel_YTile_InitStencilPointers_z24_s8(rb); - break; - } - } else { - _mesa_problem(NULL, - "Unexpected ActualFormat in intelSetSpanFunctions"); - } + intel_InitDepthPointers_z24_x8(rb); break; default: _mesa_problem(NULL, - "Unexpected MesaFormat in intelSetSpanFunctions"); + "Unexpected MesaFormat %d in intelSetSpanFunctions", + irb->Base.Format); break; } } diff --git a/src/mesa/drivers/dri/intel/intel_spantmp.h b/src/mesa/drivers/dri/intel/intel_spantmp.h deleted file mode 100644 index bad03398f6..0000000000 --- a/src/mesa/drivers/dri/intel/intel_spantmp.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright © 2009 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Eric Anholt <eric@anholt.net> - * - */ - -/** - * Wrapper around the spantmp.h macrofest to generate spans code for - * all the tiling styles. - */ - -#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT -#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE -#define TAG(x) INTEL_TAG(intel_gttmap_##x) -#define TAG2(x, y) INTEL_TAG(intel_gttmap_##x##y) -#include "spantmp2.h" - -#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT -#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE -#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(NO_TILE(_x, _y), v) -#define GET_VALUE(_x, _y) INTEL_READ_VALUE(NO_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel##x) -#define TAG2(x, y) INTEL_TAG(intel##x)##y -#include "spantmp2.h" - -#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT -#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE -#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(X_TILE(_x, _y), v) -#define GET_VALUE(_x, _y) INTEL_READ_VALUE(X_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel_XTile_##x) -#define TAG2(x, y) INTEL_TAG(intel_XTile_##x)##y -#include "spantmp2.h" - -#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT -#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE -#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(Y_TILE(_x, _y), v) -#define GET_VALUE(_x, _y) INTEL_READ_VALUE(Y_TILE(_x, _y)) -#define TAG(x) INTEL_TAG(intel_YTile_##x) -#define TAG2(x, y) INTEL_TAG(intel_YTile_##x)##y -#include "spantmp2.h" - -#undef INTEL_PIXEL_FMT -#undef INTEL_PIXEL_TYPE -#undef INTEL_WRITE_VALUE -#undef INTEL_READ_VALUE -#undef INTEL_TAG diff --git a/src/mesa/drivers/dri/intel/intel_syncobj.c b/src/mesa/drivers/dri/intel/intel_syncobj.c index 0d7889d3c2..d67f0cb4a6 100644 --- a/src/mesa/drivers/dri/intel/intel_syncobj.c +++ b/src/mesa/drivers/dri/intel/intel_syncobj.c @@ -50,7 +50,7 @@ intel_new_sync_object(GLcontext *ctx, GLuint id) { struct intel_sync_object *sync; - sync = _mesa_calloc(sizeof(struct intel_sync_object)); + sync = calloc(1, sizeof(struct intel_sync_object)); return &sync->Base; } @@ -61,7 +61,7 @@ intel_delete_sync_object(GLcontext *ctx, struct gl_sync_object *s) struct intel_sync_object *sync = (struct intel_sync_object *)s; drm_intel_bo_unreference(sync->bo); - _mesa_free(sync); + free(sync); } static void diff --git a/src/mesa/drivers/dri/intel/intel_tex.c b/src/mesa/drivers/dri/intel/intel_tex.c index 215a534a5c..8bb6ae99fb 100644 --- a/src/mesa/drivers/dri/intel/intel_tex.c +++ b/src/mesa/drivers/dri/intel/intel_tex.c @@ -146,7 +146,7 @@ timed_memcpy(void *dest, const void *src, size_t n) double rate; if ((((unsigned) src) & 63) || (((unsigned) dest) & 63)) - _mesa_printf("Warning - non-aligned texture copy!\n"); + printf("Warning - non-aligned texture copy!\n"); t1 = fastrdtsc(); ret = do_memcpy(dest, src, n); @@ -154,7 +154,7 @@ timed_memcpy(void *dest, const void *src, size_t n) rate = time_diff(t1, t2); rate /= (double) n; - _mesa_printf("timed_memcpy: %u %u --> %f clocks/byte\n", t1, t2, rate); + printf("timed_memcpy: %u %u --> %f clocks/byte\n", t1, t2, rate); return ret; } #endif /* DO_DEBUG */ diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src/mesa/drivers/dri/intel/intel_tex.h index f3cc0fff5c..4bb012dc65 100644 --- a/src/mesa/drivers/dri/intel/intel_tex.h +++ b/src/mesa/drivers/dri/intel/intel_tex.h @@ -45,8 +45,6 @@ void intelInitTextureCopyImageFuncs(struct dd_function_table *functions); gl_format intelChooseTextureFormat(GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type); -void intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, GLuint pitch); void intelSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *pDraw); void intelSetTexBuffer2(__DRIcontext *pDRICtx, diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index d67451cf8e..13b8bcfa86 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -109,6 +109,7 @@ do_copy_texsubimage(struct intel_context *intel, } /* intelFlush(ctx); */ + intel_prepare_render(intel); { drm_intel_bo *dst_bo = intel_region_buffer(intel, intelImage->mt->region, diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index d63292edd3..bac36eeb56 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -240,6 +240,7 @@ try_pbo_upload(struct intel_context *intel, if (drm_intel_bo_references(intel->batch->buf, dst_buffer)) intelFlush(&intel->ctx); + intel_prepare_render(intel); { dri_bo *src_buffer = intel_bufferobj_buffer(intel, pbo, INTEL_READ); @@ -472,6 +473,8 @@ intelTexImage(GLcontext * ctx, pixels, unpack, "glTexImage"); } + intel_prepare_render(intel); + if (intelImage->mt) { if (pixels != NULL) { /* Flush any queued rendering with the texture before mapping. */ @@ -703,29 +706,6 @@ intelGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level, texObj, texImage, GL_TRUE); } - -void -intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, GLuint pitch) -{ - struct intel_context *intel = pDRICtx->driverPrivate; - struct gl_texture_object *tObj = _mesa_lookup_texture(&intel->ctx, texname); - struct intel_texture_object *intelObj = intel_texture_object(tObj); - - if (!intelObj) - return; - - if (intelObj->mt) - intel_miptree_release(intel, &intelObj->mt); - - intelObj->imageOverride = GL_TRUE; - intelObj->depthOverride = depth; - intelObj->pitchOverride = pitch; - - if (offset) - intelObj->textureOffset = offset; -} - void intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format, @@ -748,7 +728,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, if (!intelObj) return; - if (!dPriv->validBuffers) + if (dPriv->lastStamp != dPriv->dri2.stamp) intel_update_renderbuffers(pDRICtx, dPriv); rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT); @@ -811,6 +791,54 @@ intelSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) intelSetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv); } +#if FEATURE_OES_EGL_image +static void +intel_image_target_texture_2d(GLcontext *ctx, GLenum target, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + GLeglImageOES image_handle) +{ + struct intel_context *intel = intel_context(ctx); + struct intel_texture_object *intelObj = intel_texture_object(texObj); + struct intel_texture_image *intelImage = intel_texture_image(texImage); + struct intel_mipmap_tree *mt; + __DRIscreen *screen; + __DRIimage *image; + + screen = intel->intelScreen->driScrnPriv; + image = screen->dri2.image->lookupEGLImage(intel->driContext, image_handle, + intel->driContext->loaderPrivate); + if (image == NULL) + return; + + mt = intel_miptree_create_for_region(intel, target, + image->internal_format, + 0, 0, image->region, 1, 0); + if (mt == NULL) + return; + + if (intelImage->mt) { + intel_miptree_release(intel, &intelImage->mt); + assert(!texImage->Data); + } + if (intelObj->mt) + intel_miptree_release(intel, &intelObj->mt); + + intelObj->mt = mt; + _mesa_init_teximage_fields(&intel->ctx, target, texImage, + image->region->width, image->region->height, 1, + 0, image->internal_format); + + intelImage->face = target_to_face(target); + intelImage->level = 0; + texImage->TexFormat = image->format; + texImage->RowStride = image->region->pitch; + intel_miptree_reference(&intelImage->mt, intelObj->mt); + + if (!intel_miptree_match_image(intelObj->mt, &intelImage->base)) + fprintf(stderr, "miptree doesn't match image\n"); +} +#endif void intelInitTextureImageFuncs(struct dd_function_table *functions) @@ -822,4 +850,8 @@ intelInitTextureImageFuncs(struct dd_function_table *functions) functions->CompressedTexImage2D = intelCompressedTexImage2D; functions->GetCompressedTexImage = intelGetCompressedTexImage; + +#if FEATURE_OES_EGL_image + functions->EGLImageTargetTexture2D = intel_image_target_texture_2d; +#endif } diff --git a/src/mesa/drivers/dri/intel/intel_tex_obj.h b/src/mesa/drivers/dri/intel/intel_tex_obj.h index 3ad10d3d23..5f60e0ea4f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_obj.h +++ b/src/mesa/drivers/dri/intel/intel_tex_obj.h @@ -46,10 +46,6 @@ struct intel_texture_object * regions will be copied to this region and the old storage freed. */ struct intel_mipmap_tree *mt; - - GLboolean imageOverride; - GLint depthOverride; - GLuint pitchOverride; }; struct intel_texture_image diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index 7f1dc89022..c35d2e8757 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -72,6 +72,8 @@ intelTexSubimage(GLcontext * ctx, if (!pixels) return; + intel_prepare_render(intel); + /* Map buffer if necessary. Need to lock to prevent other contexts * from uploading the buffer under us. */ diff --git a/src/mesa/drivers/dri/intel/server/intel_dri.c b/src/mesa/drivers/dri/intel/server/intel_dri.c deleted file mode 100644 index e49c4214ad..0000000000 --- a/src/mesa/drivers/dri/intel/server/intel_dri.c +++ /dev/null @@ -1,1306 +0,0 @@ -/** - * \file server/intel_dri.c - * \brief File to perform the device-specific initialization tasks typically - * done in the X server. - * - * Here they are converted to run in the client (or perhaps a standalone - * process), and to work with the frame buffer device rather than the X - * server infrastructure. - * - * Copyright (C) 2006 Dave Airlie (airlied@linux.ie) - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sub license, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice (including the - next paragraph) shall be included in all copies or substantial portions - of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - IN NO EVENT SHALL THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR - ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <errno.h> -#include <unistd.h> - -#include "driver.h" -#include "drm.h" - -#include "intel.h" -#include "i830_dri.h" - -#include "memops.h" -#include "pciaccess.h" - -static size_t drm_page_size; -static int nextTile = 0; -#define xf86DrvMsg(...) do {} while(0) - -static const int pitches[] = { - 128 * 8, - 128 * 16, - 128 * 32, - 128 * 64, - 0 -}; - -static Bool I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea); - -static unsigned long -GetBestTileAlignment(unsigned long size) -{ - unsigned long i; - - for (i = KB(512); i < size; i <<= 1) - ; - - if (i > MB(64)) - i = MB(64); - - return i; -} - -static void SetFenceRegs(const DRIDriverContext *ctx, I830Rec *pI830) -{ - int i; - unsigned char *MMIO = ctx->MMIOAddress; - - for (i = 0; i < 8; i++) { - OUTREG(FENCE + i * 4, pI830->Fence[i]); - // if (I810_DEBUG & DEBUG_VERBOSE_VGA) - fprintf(stderr,"Fence Register : %x\n", pI830->Fence[i]); - } -} - -/* Tiled memory is good... really, really good... - * - * Need to make it less likely that we miss out on this - probably - * need to move the frontbuffer away from the 'guarenteed' alignment - * of the first memory segment, or perhaps allocate a discontigous - * framebuffer to get more alignment 'sweet spots'. - */ -static void -SetFence(const DRIDriverContext *ctx, I830Rec *pI830, - int nr, unsigned int start, unsigned int pitch, - unsigned int size) -{ - unsigned int val; - unsigned int fence_mask = 0; - unsigned int fence_pitch; - - if (nr < 0 || nr > 7) { - fprintf(stderr, - "SetFence: fence %d out of range\n",nr); - return; - } - - pI830->Fence[nr] = 0; - - if (IS_I9XX(pI830)) - fence_mask = ~I915G_FENCE_START_MASK; - else - fence_mask = ~I830_FENCE_START_MASK; - - if (start & fence_mask) { - fprintf(stderr, - "SetFence: %d: start (0x%08x) is not %s aligned\n", - nr, start, (IS_I9XX(pI830)) ? "1MB" : "512k"); - return; - } - - if (start % size) { - fprintf(stderr, - "SetFence: %d: start (0x%08x) is not size (%dk) aligned\n", - nr, start, size / 1024); - return; - } - - if (pitch & 127) { - fprintf(stderr, - "SetFence: %d: pitch (%d) not a multiple of 128 bytes\n", - nr, pitch); - return; - } - - val = (start | FENCE_X_MAJOR | FENCE_VALID); - - if (IS_I9XX(pI830)) { - switch (size) { - case MB(1): - val |= I915G_FENCE_SIZE_1M; - break; - case MB(2): - val |= I915G_FENCE_SIZE_2M; - break; - case MB(4): - val |= I915G_FENCE_SIZE_4M; - break; - case MB(8): - val |= I915G_FENCE_SIZE_8M; - break; - case MB(16): - val |= I915G_FENCE_SIZE_16M; - break; - case MB(32): - val |= I915G_FENCE_SIZE_32M; - break; - case MB(64): - val |= I915G_FENCE_SIZE_64M; - break; - default: - fprintf(stderr, - "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024); - return; - } - } else { - switch (size) { - case KB(512): - val |= FENCE_SIZE_512K; - break; - case MB(1): - val |= FENCE_SIZE_1M; - break; - case MB(2): - val |= FENCE_SIZE_2M; - break; - case MB(4): - val |= FENCE_SIZE_4M; - break; - case MB(8): - val |= FENCE_SIZE_8M; - break; - case MB(16): - val |= FENCE_SIZE_16M; - break; - case MB(32): - val |= FENCE_SIZE_32M; - break; - case MB(64): - val |= FENCE_SIZE_64M; - break; - default: - fprintf(stderr, - "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024); - return; - } - } - - if (IS_I9XX(pI830)) - fence_pitch = pitch / 512; - else - fence_pitch = pitch / 128; - - switch (fence_pitch) { - case 1: - val |= FENCE_PITCH_1; - break; - case 2: - val |= FENCE_PITCH_2; - break; - case 4: - val |= FENCE_PITCH_4; - break; - case 8: - val |= FENCE_PITCH_8; - break; - case 16: - val |= FENCE_PITCH_16; - break; - case 32: - val |= FENCE_PITCH_32; - break; - case 64: - val |= FENCE_PITCH_64; - break; - default: - fprintf(stderr, - "SetFence: %d: illegal pitch (%d)\n", nr, pitch); - return; - } - - pI830->Fence[nr] = val; -} - -static Bool -MakeTiles(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *pMem) -{ - int pitch, ntiles, i; - - pitch = pMem->Pitch * ctx->cpp; - /* - * Simply try to break the region up into at most four pieces of size - * equal to the alignment. - */ - ntiles = ROUND_TO(pMem->Size, pMem->Alignment) / pMem->Alignment; - if (ntiles >= 4) { - return FALSE; - } - - for (i = 0; i < ntiles; i++, nextTile++) { - SetFence(ctx, pI830, nextTile, pMem->Start + i * pMem->Alignment, - pitch, pMem->Alignment); - } - return TRUE; -} - -static void I830SetupMemoryTiling(const DRIDriverContext *ctx, I830Rec *pI830) -{ - int i; - - /* Clear out */ - for (i = 0; i < 8; i++) - pI830->Fence[i] = 0; - - nextTile = 0; - - if (pI830->BackBuffer.Alignment >= KB(512)) { - if (MakeTiles(ctx, pI830, &(pI830->BackBuffer))) { - fprintf(stderr, - "Activating tiled memory for the back buffer.\n"); - } else { - fprintf(stderr, - "MakeTiles failed for the back buffer.\n"); - pI830->allowPageFlip = FALSE; - } - } - - if (pI830->DepthBuffer.Alignment >= KB(512)) { - if (MakeTiles(ctx, pI830, &(pI830->DepthBuffer))) { - fprintf(stderr, - "Activating tiled memory for the depth buffer.\n"); - } else { - fprintf(stderr, - "MakeTiles failed for the depth buffer.\n"); - } - } - - return; -} - -static int I830DetectMemory(const DRIDriverContext *ctx, I830Rec *pI830) -{ - struct pci_device host_bridge, ig_dev; - uint32_t gmch_ctrl; - int memsize = 0; - int range; - uint32_t aper_size; - uint32_t membase2 = 0; - - memset(&host_bridge, 0, sizeof(host_bridge)); - memset(&ig_dev, 0, sizeof(ig_dev)); - - ig_dev.dev = 2; - - pci_device_cfg_read_u32(&host_bridge, &gmch_ctrl, I830_GMCH_CTRL); - - if (IS_I830(pI830) || IS_845G(pI830)) { - if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { - aper_size = 0x80000000; - } else { - aper_size = 0x40000000; - } - } else { - if (IS_I9XX(pI830)) { - int ret; - ret = pci_device_cfg_read_u32(&ig_dev, &membase2, 0x18); - if (membase2 & 0x08000000) - aper_size = 0x8000000; - else - aper_size = 0x10000000; - - fprintf(stderr,"aper size is %08X %08x %d\n", aper_size, membase2, ret); - } else - aper_size = 0x8000000; - } - - pI830->aper_size = aper_size; - - - /* We need to reduce the stolen size, by the GTT and the popup. - * The GTT varying according the the FbMapSize and the popup is 4KB */ - range = (ctx->shared.fbSize / (1024*1024)) + 4; - - if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) { - switch (gmch_ctrl & I830_GMCH_GMS_MASK) { - case I855_GMCH_GMS_STOLEN_1M: - memsize = MB(1) - KB(range); - break; - case I855_GMCH_GMS_STOLEN_4M: - memsize = MB(4) - KB(range); - break; - case I855_GMCH_GMS_STOLEN_8M: - memsize = MB(8) - KB(range); - break; - case I855_GMCH_GMS_STOLEN_16M: - memsize = MB(16) - KB(range); - break; - case I855_GMCH_GMS_STOLEN_32M: - memsize = MB(32) - KB(range); - break; - case I915G_GMCH_GMS_STOLEN_48M: - if (IS_I9XX(pI830)) - memsize = MB(48) - KB(range); - break; - case I915G_GMCH_GMS_STOLEN_64M: - if (IS_I9XX(pI830)) - memsize = MB(64) - KB(range); - break; - } - } else { - switch (gmch_ctrl & I830_GMCH_GMS_MASK) { - case I830_GMCH_GMS_STOLEN_512: - memsize = KB(512) - KB(range); - break; - case I830_GMCH_GMS_STOLEN_1024: - memsize = MB(1) - KB(range); - break; - case I830_GMCH_GMS_STOLEN_8192: - memsize = MB(8) - KB(range); - break; - case I830_GMCH_GMS_LOCAL: - memsize = 0; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Local memory found, but won't be used.\n"); - break; - } - } - if (memsize > 0) { - fprintf(stderr, - "detected %d kB stolen memory.\n", memsize / 1024); - } else { - fprintf(stderr, - "no video memory detected.\n"); - } - return memsize; -} - -static int AgpInit(const DRIDriverContext *ctx, I830Rec *info) -{ - unsigned long mode = 0x4; - - if (drmAgpAcquire(ctx->drmFD) < 0) { - fprintf(stderr, "[gart] AGP not available\n"); - return 0; - } - - if (drmAgpEnable(ctx->drmFD, mode) < 0) { - fprintf(stderr, "[gart] AGP not enabled\n"); - drmAgpRelease(ctx->drmFD); - return 0; - } - else - fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode); - - return 1; -} - -/* - * Allocate memory from the given pool. Grow the pool if needed and if - * possible. - */ -static unsigned long -AllocFromPool(const DRIDriverContext *ctx, I830Rec *pI830, - I830MemRange *result, I830MemPool *pool, - long size, unsigned long alignment, int flags) -{ - long needed, start, end; - - if (!result || !pool || !size) - return 0; - - /* Calculate how much space is needed. */ - if (alignment <= GTT_PAGE_SIZE) - needed = size; - else { - start = ROUND_TO(pool->Free.Start, alignment); - end = ROUND_TO(start + size, alignment); - needed = end - pool->Free.Start; - } - if (needed > pool->Free.Size) { - return 0; - } - - result->Start = ROUND_TO(pool->Free.Start, alignment); - pool->Free.Start += needed; - result->End = pool->Free.Start; - - pool->Free.Size = pool->Free.End - pool->Free.Start; - result->Size = result->End - result->Start; - result->Pool = pool; - result->Alignment = alignment; - return needed; -} - -static unsigned long AllocFromAGP(const DRIDriverContext *ctx, I830Rec *pI830, long size, unsigned long alignment, I830MemRange *result) -{ - unsigned long start, end; - unsigned long newApStart, newApEnd; - int ret; - if (!result || !size) - return 0; - - if (!alignment) - alignment = 4; - - start = ROUND_TO(pI830->MemoryAperture.Start, alignment); - end = ROUND_TO(start + size, alignment); - newApStart = end; - newApEnd = pI830->MemoryAperture.End; - - ret=drmAgpAlloc(ctx->drmFD, size, 0, &(result->Physical), (drm_handle_t *)&(result->Key)); - - if (ret) - { - fprintf(stderr,"drmAgpAlloc failed %d\n", ret); - return 0; - } - pI830->allocatedMemory += size; - pI830->MemoryAperture.Start = newApStart; - pI830->MemoryAperture.End = newApEnd; - pI830->MemoryAperture.Size = newApEnd - newApStart; - // pI830->FreeMemory -= size; - result->Start = start; - result->End = start + size; - result->Size = size; - result->Offset = start; - result->Alignment = alignment; - result->Pool = NULL; - - return size; -} - -unsigned long -I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830, - I830MemRange *result, I830MemPool *pool, long size, - unsigned long alignment, int flags) -{ - unsigned long ret; - - if (!result) - return 0; - - /* Make sure these are initialised. */ - result->Size = 0; - result->Key = -1; - - if (!size) { - return 0; - } - - if (pool->Free.Size < size) { - ret = AllocFromAGP(ctx, pI830, size, alignment, result); - } - else { - ret = AllocFromPool(ctx, pI830, result, pool, size, alignment, flags); - if (ret == 0) - ret = AllocFromAGP(ctx, pI830, size, alignment, result); - } - return ret; -} - -static Bool BindAgpRange(const DRIDriverContext *ctx, I830MemRange *mem) -{ - if (!mem) - return FALSE; - - if (mem->Key == -1) - return TRUE; - - return !drmAgpBind(ctx->drmFD, mem->Key, mem->Offset); -} - -/* simple memory allocation routines needed */ -/* put ring buffer in low memory */ -/* need to allocate front, back, depth buffers aligned correctly, - allocate ring buffer, -*/ - -/* */ -static Bool -I830AllocateMemory(const DRIDriverContext *ctx, I830Rec *pI830) -{ - unsigned long size, ret; - unsigned long lines, lineSize, align; - - /* allocate ring buffer */ - memset(pI830->LpRing, 0, sizeof(I830RingBuffer)); - pI830->LpRing->mem.Key = -1; - - size = PRIMARY_RINGBUFFER_SIZE; - - ret = I830AllocVidMem(ctx, pI830, &pI830->LpRing->mem, &pI830->StolenPool, size, 0x1000, 0); - - if (ret != size) - { - fprintf(stderr,"unable to allocate ring buffer %ld\n", ret); - return FALSE; - } - - pI830->LpRing->tail_mask = pI830->LpRing->mem.Size - 1; - - - /* allocate front buffer */ - memset(&(pI830->FrontBuffer), 0, sizeof(pI830->FrontBuffer)); - pI830->FrontBuffer.Key = -1; - pI830->FrontBuffer.Pitch = ctx->shared.virtualWidth; - - align = KB(512); - - lineSize = ctx->shared.virtualWidth * ctx->cpp; - lines = (ctx->shared.virtualHeight + 15) / 16 * 16; - size = lineSize * lines; - size = ROUND_TO_PAGE(size); - - align = GetBestTileAlignment(size); - - ret = I830AllocVidMem(ctx, pI830, &pI830->FrontBuffer, &pI830->StolenPool, size, align, 0); - if (ret < size) - { - fprintf(stderr,"unable to allocate front buffer %ld\n", ret); - return FALSE; - } - - memset(&(pI830->BackBuffer), 0, sizeof(pI830->BackBuffer)); - pI830->BackBuffer.Key = -1; - pI830->BackBuffer.Pitch = ctx->shared.virtualWidth; - - ret = I830AllocVidMem(ctx, pI830, &pI830->BackBuffer, &pI830->StolenPool, size, align, 0); - if (ret < size) - { - fprintf(stderr,"unable to allocate back buffer %ld\n", ret); - return FALSE; - } - - memset(&(pI830->DepthBuffer), 0, sizeof(pI830->DepthBuffer)); - pI830->DepthBuffer.Key = -1; - pI830->DepthBuffer.Pitch = ctx->shared.virtualWidth; - - ret = I830AllocVidMem(ctx, pI830, &pI830->DepthBuffer, &pI830->StolenPool, size, align, 0); - if (ret < size) - { - fprintf(stderr,"unable to allocate depth buffer %ld\n", ret); - return FALSE; - } - - memset(&(pI830->ContextMem), 0, sizeof(pI830->ContextMem)); - pI830->ContextMem.Key = -1; - size = KB(32); - - ret = I830AllocVidMem(ctx, pI830, &pI830->ContextMem, &pI830->StolenPool, size, align, 0); - if (ret < size) - { - fprintf(stderr,"unable to allocate context buffer %ld\n", ret); - return FALSE; - } - -#if 0 - memset(&(pI830->TexMem), 0, sizeof(pI830->TexMem)); - pI830->TexMem.Key = -1; - - size = 32768 * 1024; - ret = AllocFromAGP(ctx, pI830, size, align, &pI830->TexMem); - if (ret < size) - { - fprintf(stderr,"unable to allocate texture memory %ld\n", ret); - return FALSE; - } -#endif - - return TRUE; -} - -static Bool -I830BindMemory(const DRIDriverContext *ctx, I830Rec *pI830) -{ - if (!BindAgpRange(ctx, &pI830->LpRing->mem)) - return FALSE; - if (!BindAgpRange(ctx, &pI830->FrontBuffer)) - return FALSE; - if (!BindAgpRange(ctx, &pI830->BackBuffer)) - return FALSE; - if (!BindAgpRange(ctx, &pI830->DepthBuffer)) - return FALSE; - if (!BindAgpRange(ctx, &pI830->ContextMem)) - return FALSE; -#if 0 - if (!BindAgpRange(ctx, &pI830->TexMem)) - return FALSE; -#endif - return TRUE; -} - -static void SetupDRIMM(const DRIDriverContext *ctx, I830Rec *pI830) -{ - unsigned long aperEnd = ROUND_DOWN_TO(pI830->aper_size, GTT_PAGE_SIZE) / GTT_PAGE_SIZE; - unsigned long aperStart = ROUND_TO(pI830->aper_size - KB(32768), GTT_PAGE_SIZE) / GTT_PAGE_SIZE; - - fprintf(stderr, "aper size is %08X\n", ctx->shared.fbSize); - if (drmMMInit(ctx->drmFD, aperStart, aperEnd - aperStart, DRM_BO_MEM_TT)) { - fprintf(stderr, - "DRM MM Initialization Failed\n"); - } else { - fprintf(stderr, - "DRM MM Initialized at offset 0x%lx length %d page\n", aperStart, aperEnd-aperStart); - } - -} - -static Bool -I830CleanupDma(const DRIDriverContext *ctx) -{ - drmI830Init info; - - memset(&info, 0, sizeof(drmI830Init)); - info.func = I830_CLEANUP_DMA; - - if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT, - &info, sizeof(drmI830Init))) { - fprintf(stderr, "I830 Dma Cleanup Failed\n"); - return FALSE; - } - - return TRUE; -} - -static Bool -I830InitDma(const DRIDriverContext *ctx, I830Rec *pI830) -{ - I830RingBuffer *ring = pI830->LpRing; - drmI830Init info; - - memset(&info, 0, sizeof(drmI830Init)); - info.func = I830_INIT_DMA; - - info.ring_start = ring->mem.Start + pI830->LinearAddr; - info.ring_end = ring->mem.End + pI830->LinearAddr; - info.ring_size = ring->mem.Size; - - info.mmio_offset = (unsigned int)ctx->MMIOStart; - - info.sarea_priv_offset = sizeof(drm_sarea_t); - - info.front_offset = pI830->FrontBuffer.Start; - info.back_offset = pI830->BackBuffer.Start; - info.depth_offset = pI830->DepthBuffer.Start; - info.w = ctx->shared.virtualWidth; - info.h = ctx->shared.virtualHeight; - info.pitch = ctx->shared.virtualWidth; - info.back_pitch = pI830->BackBuffer.Pitch; - info.depth_pitch = pI830->DepthBuffer.Pitch; - info.cpp = ctx->cpp; - - if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT, - &info, sizeof(drmI830Init))) { - fprintf(stderr, - "I830 Dma Initialization Failed\n"); - return FALSE; - } - - return TRUE; -} - -static int I830CheckDRMVersion( const DRIDriverContext *ctx, - I830Rec *pI830 ) -{ - drmVersionPtr version; - - version = drmGetVersion(ctx->drmFD); - - if (version) { - int req_minor, req_patch; - - req_minor = 4; - req_patch = 0; - - if (version->version_major != 1 || - version->version_minor < req_minor || - (version->version_minor == req_minor && - version->version_patchlevel < req_patch)) { - /* Incompatible drm version */ - fprintf(stderr, - "[dri] I830DRIScreenInit failed because of a version " - "mismatch.\n" - "[dri] i915.o kernel module version is %d.%d.%d " - "but version 1.%d.%d or newer is needed.\n" - "[dri] Disabling DRI.\n", - version->version_major, - version->version_minor, - version->version_patchlevel, - req_minor, - req_patch); - drmFreeVersion(version); - return 0; - } - - pI830->drmMinor = version->version_minor; - drmFreeVersion(version); - } - return 1; -} - -static void -I830SetRingRegs(const DRIDriverContext *ctx, I830Rec *pI830) -{ - unsigned int itemp; - unsigned char *MMIO = ctx->MMIOAddress; - - OUTREG(LP_RING + RING_LEN, 0); - OUTREG(LP_RING + RING_TAIL, 0); - OUTREG(LP_RING + RING_HEAD, 0); - - if ((long)(pI830->LpRing->mem.Start & I830_RING_START_MASK) != - pI830->LpRing->mem.Start) { - fprintf(stderr, - "I830SetRingRegs: Ring buffer start (%lx) violates its " - "mask (%x)\n", pI830->LpRing->mem.Start, I830_RING_START_MASK); - } - /* Don't care about the old value. Reserved bits must be zero anyway. */ - itemp = pI830->LpRing->mem.Start & I830_RING_START_MASK; - OUTREG(LP_RING + RING_START, itemp); - - if (((pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES) != - pI830->LpRing->mem.Size - 4096) { - fprintf(stderr, - "I830SetRingRegs: Ring buffer size - 4096 (%lx) violates its " - "mask (%x)\n", pI830->LpRing->mem.Size - 4096, - I830_RING_NR_PAGES); - } - /* Don't care about the old value. Reserved bits must be zero anyway. */ - itemp = (pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES; - itemp |= (RING_NO_REPORT | RING_VALID); - OUTREG(LP_RING + RING_LEN, itemp); - - pI830->LpRing->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK; - pI830->LpRing->tail = INREG(LP_RING + RING_TAIL); - pI830->LpRing->space = pI830->LpRing->head - (pI830->LpRing->tail + 8); - if (pI830->LpRing->space < 0) - pI830->LpRing->space += pI830->LpRing->mem.Size; - - SetFenceRegs(ctx, pI830); - - /* RESET THE DISPLAY PIPE TO POINT TO THE FRONTBUFFER - hacky - hacky hacky */ - OUTREG(DSPABASE, pI830->FrontBuffer.Start + pI830->LinearAddr); - -} - -static Bool -I830SetParam(const DRIDriverContext *ctx, int param, int value) -{ - drmI830SetParam sp; - - memset(&sp, 0, sizeof(sp)); - sp.param = param; - sp.value = value; - - if (drmCommandWrite(ctx->drmFD, DRM_I830_SETPARAM, &sp, sizeof(sp))) { - fprintf(stderr, "I830 SetParam Failed\n"); - return FALSE; - } - - return TRUE; -} - -static Bool -I830DRIMapScreenRegions(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) -{ - fprintf(stderr, - "[drm] Mapping front buffer\n"); - - if (drmAddMap(ctx->drmFD, - (drm_handle_t)(sarea->front_offset + pI830->LinearAddr), - sarea->front_size, - DRM_FRAME_BUFFER, /*DRM_AGP,*/ - 0, - &sarea->front_handle) < 0) { - fprintf(stderr, - "[drm] drmAddMap(front_handle) failed. Disabling DRI\n"); - return FALSE; - } - ctx->shared.hFrameBuffer = sarea->front_handle; - ctx->shared.fbSize = sarea->front_size; - fprintf(stderr, "[drm] Front Buffer = 0x%08x\n", - sarea->front_handle); - - if (drmAddMap(ctx->drmFD, - (drm_handle_t)(sarea->back_offset), - sarea->back_size, DRM_AGP, 0, - &sarea->back_handle) < 0) { - fprintf(stderr, - "[drm] drmAddMap(back_handle) failed. Disabling DRI\n"); - return FALSE; - } - fprintf(stderr, "[drm] Back Buffer = 0x%08x\n", - sarea->back_handle); - - if (drmAddMap(ctx->drmFD, - (drm_handle_t)sarea->depth_offset, - sarea->depth_size, DRM_AGP, 0, - &sarea->depth_handle) < 0) { - fprintf(stderr, - "[drm] drmAddMap(depth_handle) failed. Disabling DRI\n"); - return FALSE; - } - fprintf(stderr, "[drm] Depth Buffer = 0x%08x\n", - sarea->depth_handle); - -#if 0 - if (drmAddMap(ctx->drmFD, - (drm_handle_t)sarea->tex_offset, - sarea->tex_size, DRM_AGP, 0, - &sarea->tex_handle) < 0) { - fprintf(stderr, - "[drm] drmAddMap(tex_handle) failed. Disabling DRI\n"); - return FALSE; - } - fprintf(stderr, "[drm] textures = 0x%08x\n", - sarea->tex_handle); -#endif - return TRUE; -} - - -static void -I830DRIUnmapScreenRegions(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) -{ -#if 1 - if (sarea->front_handle) { - drmRmMap(ctx->drmFD, sarea->front_handle); - sarea->front_handle = 0; - } -#endif - if (sarea->back_handle) { - drmRmMap(ctx->drmFD, sarea->back_handle); - sarea->back_handle = 0; - } - if (sarea->depth_handle) { - drmRmMap(ctx->drmFD, sarea->depth_handle); - sarea->depth_handle = 0; - } - if (sarea->tex_handle) { - drmRmMap(ctx->drmFD, sarea->tex_handle); - sarea->tex_handle = 0; - } -} - -static Bool -I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) -{ - if (drmAddMap(ctx->drmFD, - (drm_handle_t)pI830->LpRing->mem.Start, - pI830->LpRing->mem.Size, DRM_AGP, 0, - &pI830->ring_map) < 0) { - fprintf(stderr, - "[drm] drmAddMap(ring_map) failed. Disabling DRI\n"); - return FALSE; - } - fprintf(stderr, "[drm] ring buffer = 0x%08x\n", - pI830->ring_map); - - if (I830InitDma(ctx, pI830) == FALSE) { - return FALSE; - } - - /* init to zero to be safe */ - - I830DRIMapScreenRegions(ctx, pI830, sarea); - SetupDRIMM(ctx, pI830); - - if (ctx->pciDevice != PCI_CHIP_845_G && - ctx->pciDevice != PCI_CHIP_I830_M) { - I830SetParam(ctx, I830_SETPARAM_USE_MI_BATCHBUFFER_START, 1 ); - } - - /* Okay now initialize the dma engine */ - { - pI830->irq = drmGetInterruptFromBusID(ctx->drmFD, - ctx->pciBus, - ctx->pciDevice, - ctx->pciFunc); - - if (drmCtlInstHandler(ctx->drmFD, pI830->irq)) { - fprintf(stderr, - "[drm] failure adding irq handler\n"); - pI830->irq = 0; - return FALSE; - } - else - fprintf(stderr, - "[drm] dma control initialized, using IRQ %d\n", - pI830->irq); - } - - fprintf(stderr, "[dri] visual configs initialized\n"); - - return TRUE; -} - -static Bool -I830ClearScreen(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea) -{ - /* need to drmMap front and back buffers and zero them */ - drmAddress map_addr; - int ret; - - ret = drmMap(ctx->drmFD, - sarea->front_handle, - sarea->front_size, - &map_addr); - - if (ret) - { - fprintf(stderr, "Unable to map front buffer\n"); - return FALSE; - } - - drimemsetio((char *)map_addr, - 0, - sarea->front_size); - drmUnmap(map_addr, sarea->front_size); - - - ret = drmMap(ctx->drmFD, - sarea->back_handle, - sarea->back_size, - &map_addr); - - if (ret) - { - fprintf(stderr, "Unable to map back buffer\n"); - return FALSE; - } - - drimemsetio((char *)map_addr, - 0, - sarea->back_size); - drmUnmap(map_addr, sarea->back_size); - - return TRUE; -} - -static Bool -I830ScreenInit(DRIDriverContext *ctx, I830Rec *pI830) - -{ - I830DRIPtr pI830DRI; - drmI830Sarea *pSAREAPriv; - int err; - - drm_page_size = getpagesize(); - - pI830->registerSize = ctx->MMIOSize; - /* This is a hack for now. We have to have more than a 4k page here - * because of the size of the state. However, the state should be - * in a per-context mapping. This will be added in the Mesa 3.5 port - * of the I830 driver. - */ - ctx->shared.SAREASize = SAREA_MAX; - - /* Note that drmOpen will try to load the kernel module, if needed. */ - ctx->drmFD = drmOpen("i915", NULL ); - if (ctx->drmFD < 0) { - fprintf(stderr, "[drm] drmOpen failed\n"); - return 0; - } - - if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) { - fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n", - ctx->drmFD, ctx->pciBusID, strerror(-err)); - return 0; - } - - if (drmAddMap( ctx->drmFD, - 0, - ctx->shared.SAREASize, - DRM_SHM, - DRM_CONTAINS_LOCK, - &ctx->shared.hSAREA) < 0) - { - fprintf(stderr, "[drm] drmAddMap failed\n"); - return 0; - } - - fprintf(stderr, "[drm] added %d byte SAREA at 0x%08x\n", - ctx->shared.SAREASize, ctx->shared.hSAREA); - - if (drmMap( ctx->drmFD, - ctx->shared.hSAREA, - ctx->shared.SAREASize, - (drmAddressPtr)(&ctx->pSAREA)) < 0) - { - fprintf(stderr, "[drm] drmMap failed\n"); - return 0; - - } - - memset(ctx->pSAREA, 0, ctx->shared.SAREASize); - fprintf(stderr, "[drm] mapped SAREA 0x%08x to %p, size %d\n", - ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize); - - - if (drmAddMap(ctx->drmFD, - ctx->MMIOStart, - ctx->MMIOSize, - DRM_REGISTERS, - DRM_READ_ONLY, - &pI830->registerHandle) < 0) { - fprintf(stderr, "[drm] drmAddMap mmio failed\n"); - return 0; - } - fprintf(stderr, - "[drm] register handle = 0x%08x\n", pI830->registerHandle); - - - if (!I830CheckDRMVersion(ctx, pI830)) { - return FALSE; - } - - /* Create a 'server' context so we can grab the lock for - * initialization ioctls. - */ - if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) { - fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err); - return 0; - } - - DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); - - /* Initialize the SAREA private data structure */ - pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + - sizeof(drm_sarea_t)); - memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); - - pI830->StolenMemory.Size = I830DetectMemory(ctx, pI830); - pI830->StolenMemory.Start = 0; - pI830->StolenMemory.End = pI830->StolenMemory.Size; - - pI830->MemoryAperture.Start = pI830->StolenMemory.End; - pI830->MemoryAperture.End = KB(40000); - pI830->MemoryAperture.Size = pI830->MemoryAperture.End - pI830->MemoryAperture.Start; - - pI830->StolenPool.Fixed = pI830->StolenMemory; - pI830->StolenPool.Total = pI830->StolenMemory; - pI830->StolenPool.Free = pI830->StolenPool.Total; - pI830->FreeMemory = pI830->StolenPool.Total.Size; - - if (!AgpInit(ctx, pI830)) - return FALSE; - - if (I830AllocateMemory(ctx, pI830) == FALSE) - { - return FALSE; - } - - if (I830BindMemory(ctx, pI830) == FALSE) - { - return FALSE; - } - - pSAREAPriv->rotated_offset = -1; - pSAREAPriv->rotated_size = 0; - pSAREAPriv->rotated_pitch = ctx->shared.virtualWidth; - - pSAREAPriv->front_offset = pI830->FrontBuffer.Start; - pSAREAPriv->front_size = pI830->FrontBuffer.Size; - pSAREAPriv->width = ctx->shared.virtualWidth; - pSAREAPriv->height = ctx->shared.virtualHeight; - pSAREAPriv->pitch = ctx->shared.virtualWidth; - pSAREAPriv->virtualX = ctx->shared.virtualWidth; - pSAREAPriv->virtualY = ctx->shared.virtualHeight; - pSAREAPriv->back_offset = pI830->BackBuffer.Start; - pSAREAPriv->back_size = pI830->BackBuffer.Size; - pSAREAPriv->depth_offset = pI830->DepthBuffer.Start; - pSAREAPriv->depth_size = pI830->DepthBuffer.Size; -#if 0 - pSAREAPriv->tex_offset = pI830->TexMem.Start; - pSAREAPriv->tex_size = pI830->TexMem.Size; -#endif - pSAREAPriv->log_tex_granularity = pI830->TexGranularity; - - ctx->driverClientMsg = malloc(sizeof(I830DRIRec)); - ctx->driverClientMsgSize = sizeof(I830DRIRec); - pI830DRI = (I830DRIPtr)ctx->driverClientMsg; - pI830DRI->deviceID = pI830->Chipset; - pI830DRI->regsSize = I830_REG_SIZE; - pI830DRI->width = ctx->shared.virtualWidth; - pI830DRI->height = ctx->shared.virtualHeight; - pI830DRI->mem = ctx->shared.fbSize; - pI830DRI->cpp = ctx->cpp; - - pI830DRI->bitsPerPixel = ctx->bpp; - pI830DRI->sarea_priv_offset = sizeof(drm_sarea_t); - - err = I830DRIDoMappings(ctx, pI830, pSAREAPriv); - if (err == FALSE) - return FALSE; - - I830SetupMemoryTiling(ctx, pI830); - - /* Quick hack to clear the front & back buffers. Could also use - * the clear ioctl to do this, but would need to setup hw state - * first. - */ - I830ClearScreen(ctx, pI830, pSAREAPriv); - - I830SetRingRegs(ctx, pI830); - - return TRUE; -} - - -/** - * \brief Validate the fbdev mode. - * - * \param ctx display handle. - * - * \return one on success, or zero on failure. - * - * Saves some registers and returns 1. - * - * \sa radeonValidateMode(). - */ -static int i830ValidateMode( const DRIDriverContext *ctx ) -{ - return 1; -} - -/** - * \brief Examine mode returned by fbdev. - * - * \param ctx display handle. - * - * \return one on success, or zero on failure. - * - * Restores registers that fbdev has clobbered and returns 1. - * - * \sa i810ValidateMode(). - */ -static int i830PostValidateMode( const DRIDriverContext *ctx ) -{ - I830Rec *pI830 = ctx->driverPrivate; - - I830SetRingRegs(ctx, pI830); - return 1; -} - - -/** - * \brief Initialize the framebuffer device mode - * - * \param ctx display handle. - * - * \return one on success, or zero on failure. - * - * Fills in \p info with some default values and some information from \p ctx - * and then calls I810ScreenInit() for the screen initialization. - * - * Before exiting clears the framebuffer memory accessing it directly. - */ -static int i830InitFBDev( DRIDriverContext *ctx ) -{ - I830Rec *pI830 = calloc(1, sizeof(I830Rec)); - int i; - - { - int dummy = ctx->shared.virtualWidth; - - switch (ctx->bpp / 8) { - case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break; - case 2: dummy = (ctx->shared.virtualWidth + 31) & ~31; break; - case 3: - case 4: dummy = (ctx->shared.virtualWidth + 15) & ~15; break; - } - - ctx->shared.virtualWidth = dummy; - ctx->shared.Width = ctx->shared.virtualWidth; - } - - - for (i = 0; pitches[i] != 0; i++) { - if (pitches[i] >= ctx->shared.virtualWidth) { - ctx->shared.virtualWidth = pitches[i]; - break; - } - } - - ctx->driverPrivate = (void *)pI830; - - pI830->LpRing = calloc(1, sizeof(I830RingBuffer)); - pI830->Chipset = ctx->chipset; - pI830->LinearAddr = ctx->FBStart; - - if (!I830ScreenInit( ctx, pI830 )) - return 0; - - - return 1; -} - - -/** - * \brief The screen is being closed, so clean up any state and free any - * resources used by the DRI. - * - * \param ctx display handle. - * - * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver - * private data. - */ -static void i830HaltFBDev( DRIDriverContext *ctx ) -{ - drmI830Sarea *pSAREAPriv; - I830Rec *pI830 = ctx->driverPrivate; - - if (pI830->irq) { - drmCtlUninstHandler(ctx->drmFD); - pI830->irq = 0; } - - I830CleanupDma(ctx); - - pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + - sizeof(drm_sarea_t)); - - I830DRIUnmapScreenRegions(ctx, pI830, pSAREAPriv); - drmUnmap( ctx->pSAREA, ctx->shared.SAREASize ); - drmClose(ctx->drmFD); - - if (ctx->driverPrivate) { - free(ctx->driverPrivate); - ctx->driverPrivate = 0; - } -} - - -extern void i810NotifyFocus( int ); - -/** - * \brief Exported driver interface for Mini GLX. - * - * \sa DRIDriverRec. - */ -const struct DRIDriverRec __driDriver = { - i830ValidateMode, - i830PostValidateMode, - i830InitFBDev, - i830HaltFBDev, - NULL,//I830EngineShutdown, - NULL, //I830EngineRestore, -#ifndef _EMBEDDED - 0, -#else - i810NotifyFocus, -#endif -}; |