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-rw-r--r--src/mesa/drivers/dri/r200/r200_maos_arrays.c2
-rw-r--r--src/mesa/drivers/dri/r200/r200_state_init.c2
-rw-r--r--src/mesa/drivers/dri/r200/r200_swtcl.c4
-rw-r--r--src/mesa/drivers/dri/r200/r200_tcl.c15
-rw-r--r--src/mesa/drivers/dri/r200/r200_tex.c21
-rw-r--r--src/mesa/drivers/dri/r200/r200_texstate.c21
6 files changed, 26 insertions, 39 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
index 383a0c4b0d..249c0bbc11 100644
--- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c
+++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
@@ -90,12 +90,14 @@ static void r200_emit_vecfog(GLcontext *ctx, struct radeon_aos *aos,
aos->components = size;
aos->count = count;
+ radeon_bo_map(aos->bo, 1);
out = (uint32_t*)((char*)aos->bo->ptr + aos->offset);
for (i = 0; i < count; i++) {
out[0] = r200ComputeFogBlendFactor( ctx, *(GLfloat *)data );
out++;
data += stride;
}
+ radeon_bo_unmap(aos->bo);
}
/* Emit any changed arrays to new GART memory, re-emit a packet to
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 68bfeea701..e53fd72290 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -640,7 +640,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
OUT_BATCH_TABLE(atom->cmd, 10);
if (t && t->mt && !t->image_override) {
- OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!t) {
/* workaround for old CS mechanism */
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index 240fb45078..4596912ddc 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -168,7 +168,7 @@ static void r200SetVertexFormat( GLcontext *ctx )
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
- GLuint sz = VB->TexCoordPtr[i]->size;
+ GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
fmt_1 |= sz << (3 * i);
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_1F + sz - 1, 0 );
@@ -297,7 +297,7 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
radeonEmitState(&rmesa->radeon);
r200EmitVertexAOS( rmesa,
rmesa->radeon.swtcl.vertex_size,
- first_elem(&rmesa->radeon.dma.reserved)->bo,
+ rmesa->radeon.swtcl.bo,
current_offset);
diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c
index c702910ef2..e7d48a7f29 100644
--- a/src/mesa/drivers/dri/r200/r200_tcl.c
+++ b/src/mesa/drivers/dri/r200/r200_tcl.c
@@ -509,25 +509,26 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx,
prog to a not enabled output however, so just don't mess with it.
We only need to change compsel. */
GLuint out_compsel = 0;
- GLuint vp_out = rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten;
+ const GLbitfield64 vp_out =
+ rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten;
vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0];
- assert(vp_out & (1 << VERT_RESULT_HPOS));
+ assert(vp_out & BITFIELD64_BIT(VERT_RESULT_HPOS));
out_compsel = R200_OUTPUT_XYZW;
- if (vp_out & (1 << VERT_RESULT_COL0)) {
+ if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL0)) {
out_compsel |= R200_OUTPUT_COLOR_0;
}
- if (vp_out & (1 << VERT_RESULT_COL1)) {
+ if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL1)) {
out_compsel |= R200_OUTPUT_COLOR_1;
}
- if (vp_out & (1 << VERT_RESULT_FOGC)) {
+ if (vp_out & BITFIELD64_BIT(VERT_RESULT_FOGC)) {
out_compsel |= R200_OUTPUT_DISCRETE_FOG;
}
- if (vp_out & (1 << VERT_RESULT_PSIZ)) {
+ if (vp_out & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
out_compsel |= R200_OUTPUT_PT_SIZE;
}
for (i = VERT_RESULT_TEX0; i < VERT_RESULT_TEX6; i++) {
- if (vp_out & (1 << i)) {
+ if (vp_out & BITFIELD64_BIT(i)) {
out_compsel |= R200_OUTPUT_TEX_0 << (i - VERT_RESULT_TEX0);
}
}
diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c
index 5a21a8b9c5..a417721553 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.c
+++ b/src/mesa/drivers/dri/r200/r200_tex.c
@@ -385,16 +385,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target,
case GL_TEXTURE_MAX_LEVEL:
case GL_TEXTURE_MIN_LOD:
case GL_TEXTURE_MAX_LOD:
- /* This isn't the most efficient solution but there doesn't appear to
- * be a nice alternative. Since there's no LOD clamping,
- * we just have to rely on loading the right subset of mipmap levels
- * to simulate a clamped LOD.
- */
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = 0;
- t->validated = GL_FALSE;
- }
+ t->validated = GL_FALSE;
break;
default:
@@ -413,7 +404,7 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
(void *)texObj,
_mesa_lookup_enum_by_nr(texObj->Target));
}
-
+
if (rmesa) {
int i;
radeon_firevertices(&rmesa->radeon);
@@ -425,11 +416,9 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
}
}
}
-
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = 0;
- }
+
+ radeon_miptree_unreference(&t->mt);
+
_mesa_delete_texture_object(ctx, texObj);
}
diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index 7d0afa1add..7782404a79 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -824,14 +824,10 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
radeon_bo_unref(rImage->bo);
rImage->bo = NULL;
}
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = NULL;
- }
- if (rImage->mt) {
- radeon_miptree_unreference(rImage->mt);
- rImage->mt = NULL;
- }
+
+ radeon_miptree_unreference(&t->mt);
+ radeon_miptree_unreference(&rImage->mt);
+
_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
texImage->RowStride = rb->pitch / rb->cpp;
@@ -1423,10 +1419,9 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d )
*/
static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t)
{
- int firstlevel = t->mt ? t->mt->firstLevel : 0;
- const struct gl_texture_image *firstImage = t->base.Image[0][firstlevel];
+ const struct gl_texture_image *firstImage = t->base.Image[0][t->minLod];
GLint log2Width, log2Height, log2Depth, texelBytes;
-
+
if ( t->bo ) {
return;
}
@@ -1454,9 +1449,9 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t)
return;
}
}
-
+
t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK;
- t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << R200_MAX_MIP_LEVEL_SHIFT;
+ t->pp_txfilter |= (t->maxLod - t->minLod) << R200_MAX_MIP_LEVEL_SHIFT;
t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK |
R200_TXFORMAT_HEIGHT_MASK |