3 files changed, 40 insertions, 24 deletions

diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index d49f4fabe7..5d0f367b38 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -107,31 +107,37 @@ void r200SetUpAtomList( r200ContextPtr rmesa )
 
 void r200EmitScissor(r200ContextPtr rmesa)
 {
+    unsigned x1, y1, x2, y2;
+    struct radeon_renderbuffer *rrb;
     BATCH_LOCALS(&rmesa->radeon);
     if (!rmesa->radeon.radeonScreen->kernel_mm) {
        return;
     }
+    rrb = radeon_get_colorbuffer(&rmesa->radeon);
+    if (!rrb || !rrb->bo)
+	return;
+
     if (rmesa->radeon.state.scissor.enabled) {
-        BEGIN_BATCH(8);
-        OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0));
-        OUT_BATCH(R200_SCISSOR_ENABLE | rmesa->hw.set.cmd[SET_RE_CNTL]);
-        OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0));
-        OUT_BATCH(R200_SCISSOR_ENABLE_0);
-        OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_TL_0, 0));
-        OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
-                  rmesa->radeon.state.scissor.rect.x1);
-        OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_BR_0, 0));
-        OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) |
-                  (rmesa->radeon.state.scissor.rect.x2 - 1));
-        END_BATCH();
+	x1 = rmesa->radeon.state.scissor.rect.x1;
+	y1 = rmesa->radeon.state.scissor.rect.y1;
+	x2 = rmesa->radeon.state.scissor.rect.x2 - 1;
+	y2 = rmesa->radeon.state.scissor.rect.y2 - 1;
     } else {
-        BEGIN_BATCH(4);
-        OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0));
-        OUT_BATCH(rmesa->hw.set.cmd[SET_RE_CNTL] & ~R200_SCISSOR_ENABLE);
-        OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0));
-        OUT_BATCH(0);
-        END_BATCH();
+        x1 = 0;
+        y1 = 0;
+        x2 = rrb->base.Width - 1;
+        y2 = rrb->base.Height - 1;
     }
+    BEGIN_BATCH(8);
+    OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0));
+    OUT_BATCH(R200_SCISSOR_ENABLE | rmesa->hw.set.cmd[SET_RE_CNTL]);
+    OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0));
+    OUT_BATCH(0);
+    OUT_BATCH(CP_PACKET0(R200_RE_TOP_LEFT, 0));
+    OUT_BATCH((y1 << 16) | x1);
+    OUT_BATCH(CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0));
+    OUT_BATCH((y2 << 16) | x2);
+    END_BATCH();
 }
 
 /* Fire a section of the retained (indexed_verts) buffer as a regular
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index 9a92a32079..8cb287de26 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -500,3 +500,15 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
 }
 
 
+void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
+{
+	int i;
+	r200ContextPtr rmesa = (r200ContextPtr)driContextPriv->driverPrivate;
+	if (rmesa)
+	{
+		for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
+			_math_matrix_dtr( &rmesa->TexGenMatrix[i] );
+		}
+	}
+	radeonDestroyContext(driContextPriv);
+}
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index bc871d9904..78ad5baebb 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -515,7 +515,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    if (drb)
      dwords += 6;
    if (rrb)
-     dwords += 6;
+     dwords += 8;
    if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
      dwords += 4;
 
@@ -546,7 +546,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
      OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
-     OUT_BATCH(cbpitch);
+     OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
    }
 
    if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
@@ -563,7 +563,6 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    uint32_t dwords = atom->cmd_size;
    int i = atom->idx;
    radeonTexObj *t = r200->state.texture.unit[i].texobj;
-   radeon_mipmap_level *lvl;
 
    if (t && t->mt && !t->image_override)
      dwords += 2;
@@ -591,7 +590,6 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    uint32_t dwords = atom->cmd_size;
    int i = atom->idx;
    radeonTexObj *t = r200->state.texture.unit[i].texobj;
-   radeon_mipmap_level *lvl;
    int hastexture = 1;
 
    if (!r200->state.texture.unit[i].unitneeded)
@@ -774,7 +772,7 @@ void r200InitState( r200ContextPtr rmesa )
       ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
    }
 
-   for (i = 0; i < 5; i++)
+   for (i = 0; i < 6; i++)
       if (rmesa->radeon.radeonScreen->kernel_mm)
           rmesa->hw.tex[i].emit = tex_emit_cs;
       else
@@ -786,7 +784,7 @@ void r200InitState( r200ContextPtr rmesa )
       ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
       ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
       ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
-      for (i = 0; i < 5; i++)
+      for (i = 0; i < 6; i++)
           if (rmesa->radeon.radeonScreen->kernel_mm)
               rmesa->hw.cube[i].emit = cube_emit_cs;
           else