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-rw-r--r--src/mesa/drivers/dri/r200/r200_cmdbuf.c28
-rw-r--r--src/mesa/drivers/dri/r200/r200_ioctl.c6
-rw-r--r--src/mesa/drivers/dri/r200/r200_ioctl.h27
-rw-r--r--src/mesa/drivers/dri/r200/r200_maos_arrays.c18
-rw-r--r--src/mesa/drivers/dri/r200/r200_state_init.c62
-rw-r--r--src/mesa/drivers/dri/r200/r200_tcl.c2
6 files changed, 83 insertions, 60 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index f107ff5624..6d421f5d5e 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -47,17 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_sanity.h"
#include "radeon_reg.h"
-static void print_state_atom( struct radeon_state_atom *state )
-{
- int i;
-
- fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
-
- if (0 & R200_DEBUG & DEBUG_VERBOSE)
- for (i = 0 ; i < state->cmd_size ; i++)
- fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
-
-}
+#define DEBUG_CMDBUF 0
/* The state atoms will be emitted in the order they appear in the atom list,
* so this step is important.
@@ -141,7 +131,7 @@ static void r200SaveHwState( r200ContextPtr rmesa )
rmesa->backup_store.cmd_used += size;
}
if (R200_DEBUG & DEBUG_STATE)
- print_state_atom( atom );
+ radeon_print_state_atom( atom );
}
}
@@ -161,9 +151,9 @@ static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty)
if ((atom->dirty || r200->hw.all_dirty) == dirty) {
dwords = (*atom->check) (r200->radeon.glCtx, atom);
if (dwords) {
- // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
- // r300PrintStateAtom(r300, atom);
- // }
+ if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
+ radeon_print_state_atom(atom);
+ }
if (atom->emit) {
(*atom->emit)(r200->radeon.glCtx, atom);
} else {
@@ -173,10 +163,10 @@ static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty)
}
atom->dirty = GL_FALSE;
} else {
- // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
- // fprintf(stderr, " skip state %s\n",
- // atom->name);
- // }
+ if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
+ fprintf(stderr, " skip state %s\n",
+ atom->name);
+ }
}
}
}
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index 1bb97c5002..1fbbbfbb56 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -41,7 +41,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "main/context.h"
#include "swrast/swrast.h"
+#include "radeon_cs.h"
#include "r200_context.h"
+
#include "common_cmdbuf.h"
#include "r200_state.h"
#include "r200_ioctl.h"
@@ -525,8 +527,8 @@ void r200Flush( GLcontext *ctx )
rmesa->dma.flush( ctx );
r200EmitState( rmesa );
-
- if (rmesa->store.cmd_used)
+
+ if (rmesa->radeon.cmdbuf.cs->cdw)
rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
}
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h
index f36a6fd90f..1ae0dd114b 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.h
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.h
@@ -201,40 +201,31 @@ static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa,
}
#endif
-static inline uint32_t cmdpacket3_clip(int cmd_type)
+static inline uint32_t cmdpacket3(int cmd_type)
{
drm_radeon_cmd_header_t cmd;
cmd.i = 0;
- cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP;
+ cmd.header.cmd_type = cmd_type;
return (uint32_t)cmd.i;
}
-#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \
+
+#define OUT_BATCH_PACKET3(packet, num_extra) do { \
if (!b_l_rmesa->radeonScreen->kernel_mm) { \
- OUT_BATCH(cmdpacket3_clip(0)); \
- OUT_BATCH(packet); \
+ OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3)); \
+ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
} else { \
OUT_BATCH(CP_PACKET2); \
OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
} \
} while(0)
-static inline uint32_t cmdpacket3(int cmd_type)
-{
- drm_radeon_cmd_header_t cmd;
-
- cmd.i = 0;
- cmd.header.cmd_type = RADEON_CMD_PACKET3;
-
- return (uint32_t)cmd.i;
-
-}
-#define OUT_BATCH_PACKET3(packet, num_extra) do { \
+#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \
if (!b_l_rmesa->radeonScreen->kernel_mm) { \
- OUT_BATCH(cmdpacket3(0)); \
- OUT_BATCH(packet); \
+ OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP)); \
+ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
} else { \
OUT_BATCH(CP_PACKET2); \
OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
index c3c2b973b5..7f7ae2ba79 100644
--- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c
+++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
@@ -223,6 +223,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
GLuint count = VB->Count;
GLuint i, emitsize;
+ fprintf(stderr,"emit arrays\n");
for ( i = 0; i < 15; i++ ) {
GLubyte attrib = vimap_rev[i];
if (attrib != 255) {
@@ -257,14 +258,14 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
if (!rmesa->tcl.vertex_data[i].buf) {
if (ctx->VertexProgram._Enabled)
rcommon_emit_vector( ctx,
- &(rmesa->tcl.aos[i]),
+ &(rmesa->tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
1,
VB->AttribPtr[attrib]->stride,
count);
else
r200_emit_vecfog( ctx,
- &(rmesa->tcl.aos[i]),
+ &(rmesa->tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
VB->AttribPtr[attrib]->stride,
count);
@@ -313,7 +314,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
}
if (!rmesa->tcl.vertex_data[i].buf) {
rcommon_emit_vector( ctx,
- &(rmesa->tcl.aos[i]),
+ &(rmesa->tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
emitsize,
VB->AttribPtr[attrib]->stride,
@@ -321,6 +322,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
}
after_emit:
assert(nr < 12);
+ nr++;
// component[nr++] = &rmesa->tcl.vertex_data[i];
}
}
@@ -339,12 +341,10 @@ after_emit:
void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs )
{
r200ContextPtr rmesa = R200_CONTEXT( ctx );
-
- /* only do it for changed inputs ? */
int i;
- for (i = 0; i < 15; i++) {
- // if (newinputs & (1 << i))
- // r200ReleaseDmaRegion( rmesa,
- // &rmesa->tcl.vertex_data[i], __FUNCTION__ );
+ for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
+ if (rmesa->tcl.aos[i].bo) {
+ rmesa->tcl.aos[i].bo = radeon_bo_unref(rmesa->tcl.aos[i].bo);
+ }
}
}
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index f46b01b56a..3b56fec78a 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -43,6 +43,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "tnl/t_pipeline.h"
#include "swrast_setup/swrast_setup.h"
+#include "radeon_buffer.h"
+#include "radeon_cs.h"
+#include "common_context.h"
+#include "common_cmdbuf.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
@@ -288,32 +292,66 @@ VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions >
VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
-#if 0
-static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
struct radeon_renderbuffer *rrb;
uint32_t cbpitch;
+ uint32_t zbpitch;
+ uint32_t dwords = atom->cmd_size;
GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
-
+
+ /* output the first 7 bytes of context */
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
+ OUT_BATCH_TABLE(atom->cmd, 5);
+
+ rrb = r200->radeon.state.depth.rrb;
+ if (!rrb) {
+ OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]);
+ OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]);
+ } else {
+ zbpitch = (rrb->pitch / rrb->cpp);
+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+ OUT_BATCH(zbpitch);
+ }
+
+ OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
+ OUT_BATCH(atom->cmd[CTX_CMD_1]);
+ OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
+ OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
+
rrb = r200->radeon.state.color.rrb;
if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
}
if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
+ OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
+ } else {
+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
}
- cbpitch = (rrb->pitch / rrb->cpp);
- if (rrb->cpp == 4)
- ;
- else
- ;
+ OUT_BATCH(atom->cmd[CTX_CMD_2]);
+
+ if (!rrb || !rrb->bo) {
+ OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
+ } else {
+ cbpitch = (rrb->pitch / rrb->cpp);
+ if (rrb->cpp == 4)
+ ;
+ else
+ ;
+ if (r200->radeon.sarea->tiling_enabled)
+ cbpitch |= R200_COLOR_TILE_ENABLE;
+ OUT_BATCH(cbpitch);
+ }
+
+ if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
+ OUT_BATCH_TABLE((atom->cmd + 14), 4);
+
+ END_BATCH();
}
-#endif
static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
{
@@ -410,7 +448,7 @@ void r200InitState( r200ContextPtr rmesa )
else
ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
- // rmesa->hw.ctx.emit = ctx_emit;
+ rmesa->hw.ctx.emit = ctx_emit;
ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c
index 4a31578c89..226bf1620c 100644
--- a/src/mesa/drivers/dri/r200/r200_tcl.c
+++ b/src/mesa/drivers/dri/r200/r200_tcl.c
@@ -142,6 +142,7 @@ static GLboolean discrete_prim[0x10] = {
static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
{
+ fprintf(stderr,"alloc elts\n");
if (rmesa->dma.flush == r200FlushElts &&
rmesa->store.cmd_used + nr*2 < R200_CMD_BUF_SZ) {
@@ -187,6 +188,7 @@ static void r200EmitPrim( GLcontext *ctx,
r200ContextPtr rmesa = R200_CONTEXT( ctx );
r200TclPrimitive( ctx, prim, hwprim );
+ fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components);
rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + VBUF_BUFSZ );