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Diffstat (limited to 'src/mesa/drivers/dri/r300/r300_blit.c')
-rw-r--r--src/mesa/drivers/dri/r300/r300_blit.c47
1 files changed, 28 insertions, 19 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_blit.c b/src/mesa/drivers/dri/r300/r300_blit.c
index 54ac2510e7..fa60628a5e 100644
--- a/src/mesa/drivers/dri/r300/r300_blit.c
+++ b/src/mesa/drivers/dri/r300/r300_blit.c
@@ -97,6 +97,7 @@ static void create_fragment_program(struct r300_context *r300)
struct r300_fragment_program_compiler compiler;
struct rc_instruction *inst;
+ memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler));
rc_init(&compiler.Base);
inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
@@ -125,7 +126,8 @@ static void create_fragment_program(struct r300_context *r300)
void r300_blit_init(struct r300_context *r300)
{
- create_vertex_program(r300);
+ if (r300->options.hw_tcl_enabled)
+ create_vertex_program(r300);
create_fragment_program(r300);
}
@@ -340,8 +342,14 @@ static void emit_pvs_setup(struct r300_context *r300,
static void emit_vap_setup(struct r300_context *r300)
{
+ int tex_offset;
BATCH_LOCALS(&r300->radeon);
+ if (r300->options.hw_tcl_enabled)
+ tex_offset = 1;
+ else
+ tex_offset = 6;
+
BEGIN_BATCH(12);
OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT);
@@ -350,7 +358,7 @@ static void emit_vap_setup(struct r300_context *r300)
OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) |
- (((1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
+ (((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
@@ -373,15 +381,16 @@ static GLboolean validate_buffers(struct r300_context *r300,
struct radeon_bo *dst_bo)
{
int ret;
- radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
- src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
- radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
- dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
+
+ ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
+ src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+ if (ret)
+ return GL_FALSE;
ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
- first_elem(&r300->radeon.dma.reserved)->bo,
- RADEON_GEM_DOMAIN_GTT, 0);
+ dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
if (ret)
return GL_FALSE;
@@ -445,7 +454,7 @@ static void other_stuff(struct r300_context *r300)
{
BATCH_LOCALS(&r300->radeon);
- BEGIN_BATCH(15);
+ BEGIN_BATCH(13);
OUT_BATCH_REGVAL(R300_GA_POLY_MODE,
R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI);
OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW);
@@ -454,9 +463,13 @@ static void other_stuff(struct r300_context *r300)
OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
- OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
OUT_BATCH_REGVAL(R300_ZB_CNTL, 0);
END_BATCH();
+ if (r300->options.hw_tcl_enabled) {
+ BEGIN_BATCH(2);
+ OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ END_BATCH();
+ }
}
static void emit_cb_setup(struct r300_context *r300,
@@ -494,7 +507,7 @@ static void emit_cb_setup(struct r300_context *r300,
END_BATCH();
}
-static unsigned is_blit_supported(gl_format dst_format)
+unsigned r300_check_blit(gl_format dst_format)
{
switch (dst_format) {
case MESA_FORMAT_RGB565:
@@ -562,19 +575,13 @@ unsigned r300_blit(GLcontext *ctx,
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
- if (!is_blit_supported(dst_mesaformat))
+ if (!r300_check_blit(dst_mesaformat))
return 0;
/* Make sure that colorbuffer has even width - hw limitation */
if (dst_pitch % 2 > 0)
++dst_pitch;
- /* Rendering to small buffer doesn't work.
- * Looks like a hw limitation.
- */
- if (dst_pitch < 32)
- return 0;
-
/* Need to clamp the region size to make sure
* we don't read outside of the source buffer
* or write outside of the destination buffer.
@@ -629,7 +636,9 @@ unsigned r300_blit(GLcontext *ctx,
r300_emit_rs_setup(r300);
}
- emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
+ if (r300->options.hw_tcl_enabled)
+ emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
+
emit_vap_setup(r300);
emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);