diff options
Diffstat (limited to 'src/mesa/drivers/dri/r300')
| -rw-r--r-- | src/mesa/drivers/dri/r300/Makefile | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r200_context.h | 822 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r200_ioctl.h | 204 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r200_reg.h | 1423 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r200_state.h | 58 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_context.c | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_context.h | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_fragprog.c | 1111 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_fragprog.h | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_fragprog_swz.c | 1328 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_render.c | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_state.c | 35 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_vertexprog.c | 41 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/radeon_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/radeon_vtxfmt_a.c | 304 |
15 files changed, 891 insertions, 4499 deletions
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 5abb91d987..2ee2328934 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -90,9 +90,11 @@ COMMON_SYMLINKS = \ include ../Makefile.template -$(SYMLINKS): +server: mkdir -p server - for i in $(SYMLINKS) ; do rm -f $$i && test -f ../radeon/$$i && ln -s ../../radeon/$$i $$i ; done + +$(SYMLINKS): server + @[ -e $@ ] || ln -sf ../../radeon/$@ server/ $(COMMON_SYMLINKS): @[ -e $@ ] || ln -sf ../radeon/$@ ./ diff --git a/src/mesa/drivers/dri/r300/r200_context.h b/src/mesa/drivers/dri/r300/r200_context.h deleted file mode 100644 index a06d7152d7..0000000000 --- a/src/mesa/drivers/dri/r300/r200_context.h +++ /dev/null @@ -1,822 +0,0 @@ -/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_context.h,v 1.2 2002/12/16 16:18:54 dawes Exp $ */ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keith@tungstengraphics.com> - */ - -#ifndef __R200_CONTEXT_H__ -#define __R200_CONTEXT_H__ - -#ifdef GLX_DIRECT_RENDERING - -#include "tnl/t_vertex.h" -#include "drm.h" -#include "radeon_drm.h" -#include "dri_util.h" -#include "texmem.h" - -#include "macros.h" -#include "mtypes.h" -#include "colormac.h" -#include "r200_reg.h" -#include "radeon_context.h" - -#define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */ - -struct r200_context; -typedef struct r200_context r200ContextRec; -typedef struct r200_context *r200ContextPtr; - -#include "mm.h" - -/* The blit width for texture uploads - */ -#define BLIT_WIDTH_BYTES 1024 - -/* Use the templated vertex format: - */ -#define COLOR_IS_RGBA -#define TAG(x) r200##x -#include "tnl_dd/t_dd_vertex.h" -#undef TAG - -typedef void (*r200_tri_func) (r200ContextPtr, - r200Vertex *, r200Vertex *, r200Vertex *); - -typedef void (*r200_line_func) (r200ContextPtr, r200Vertex *, r200Vertex *); - -typedef void (*r200_point_func) (r200ContextPtr, r200Vertex *); - -struct r200_depthbuffer_state { - GLfloat scale; -}; - -struct r200_stencilbuffer_state { - GLboolean hwBuffer; - GLuint clear; /* rb3d_stencilrefmask value */ -}; - -struct r200_stipple_state { - GLuint mask[32]; -}; - -typedef struct r200_tex_obj r200TexObj, *r200TexObjPtr; - -/* Texture object in locally shared texture space. - */ -struct r200_tex_obj { - driTextureObject base; - - GLuint bufAddr; /* Offset to start of locally - shared texture block */ - - GLuint dirty_state; /* Flags (1 per texunit) for - whether or not this texobj - has dirty hardware state - (pp_*) that needs to be - brought into the - texunit. */ - - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; - /* Six, for the cube faces */ - - GLuint pp_txfilter; /* hardware register values */ - GLuint pp_txformat; - GLuint pp_txformat_x; - GLuint pp_txoffset; /* Image location in texmem. - All cube faces follow. */ - GLuint pp_txsize; /* npot only */ - GLuint pp_txpitch; /* npot only */ - GLuint pp_border_color; - GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ - - GLboolean border_fallback; -}; - -struct r200_texture_env_state { - r200TexObjPtr texobj; - GLenum format; - GLenum envMode; -}; - -#define R200_MAX_TEXTURE_UNITS 6 - -struct r200_texture_state { - struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; -}; - -struct r200_state_atom { - struct r200_state_atom *next, *prev; - const char *name; /* for debug */ - int cmd_size; /* size in bytes */ - GLuint idx; - int *cmd; /* one or more cmd's */ - int *lastcmd; /* one or more cmd's */ - int *savedcmd; /* one or more cmd's */ - GLboolean dirty; - GLboolean(*check) (GLcontext *, int); /* is this state active? */ -}; - -/* Trying to keep these relatively short as the variables are becoming - * extravagently long. Drop the driver name prefix off the front of - * everything - I think we know which driver we're in by now, and keep the - * prefix to 3 letters unless absolutely impossible. - */ - -#define CTX_CMD_0 0 -#define CTX_PP_MISC 1 -#define CTX_PP_FOG_COLOR 2 -#define CTX_RE_SOLID_COLOR 3 -#define CTX_RB3D_BLENDCNTL 4 -#define CTX_RB3D_DEPTHOFFSET 5 -#define CTX_RB3D_DEPTHPITCH 6 -#define CTX_RB3D_ZSTENCILCNTL 7 -#define CTX_CMD_1 8 -#define CTX_PP_CNTL 9 -#define CTX_RB3D_CNTL 10 -#define CTX_RB3D_COLOROFFSET 11 -#define CTX_CMD_2 12 /* why */ -#define CTX_RB3D_COLORPITCH 13 /* why */ -#define CTX_STATE_SIZE_OLDDRM 14 -#define CTX_CMD_3 14 -#define CTX_RB3D_BLENDCOLOR 15 -#define CTX_RB3D_ABLENDCNTL 16 -#define CTX_RB3D_CBLENDCNTL 17 -#define CTX_STATE_SIZE_NEWDRM 18 - -#define SET_CMD_0 0 -#define SET_SE_CNTL 1 -#define SET_RE_CNTL 2 /* replace se_coord_fmt */ -#define SET_STATE_SIZE 3 - -#define VTE_CMD_0 0 -#define VTE_SE_VTE_CNTL 1 -#define VTE_STATE_SIZE 2 - -#define LIN_CMD_0 0 -#define LIN_RE_LINE_PATTERN 1 -#define LIN_RE_LINE_STATE 2 -#define LIN_CMD_1 3 -#define LIN_SE_LINE_WIDTH 4 -#define LIN_STATE_SIZE 5 - -#define MSK_CMD_0 0 -#define MSK_RB3D_STENCILREFMASK 1 -#define MSK_RB3D_ROPCNTL 2 -#define MSK_RB3D_PLANEMASK 3 -#define MSK_STATE_SIZE 4 - -#define VPT_CMD_0 0 -#define VPT_SE_VPORT_XSCALE 1 -#define VPT_SE_VPORT_XOFFSET 2 -#define VPT_SE_VPORT_YSCALE 3 -#define VPT_SE_VPORT_YOFFSET 4 -#define VPT_SE_VPORT_ZSCALE 5 -#define VPT_SE_VPORT_ZOFFSET 6 -#define VPT_STATE_SIZE 7 - -#define ZBS_CMD_0 0 -#define ZBS_SE_ZBIAS_FACTOR 1 -#define ZBS_SE_ZBIAS_CONSTANT 2 -#define ZBS_STATE_SIZE 3 - -#define MSC_CMD_0 0 -#define MSC_RE_MISC 1 -#define MSC_STATE_SIZE 2 - -#define TAM_CMD_0 0 -#define TAM_DEBUG3 1 -#define TAM_STATE_SIZE 2 - -#define TEX_CMD_0 0 -#define TEX_PP_TXFILTER 1 /*2c00 */ -#define TEX_PP_TXFORMAT 2 /*2c04 */ -#define TEX_PP_TXFORMAT_X 3 /*2c08 */ -#define TEX_PP_TXSIZE 4 /*2c0c */ -#define TEX_PP_TXPITCH 5 /*2c10 */ -#define TEX_PP_BORDER_COLOR 6 /*2c14 */ -#define TEX_CMD_1 7 -#define TEX_PP_TXOFFSET 8 /*2d00 */ -#define TEX_STATE_SIZE 9 - -#define CUBE_CMD_0 0 /* 1 register follows */ -#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ -#define CUBE_CMD_1 2 /* 5 registers follow */ -#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ -#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ -#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ -#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ -#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ -#define CUBE_STATE_SIZE 8 - -#define PIX_CMD_0 0 -#define PIX_PP_TXCBLEND 1 -#define PIX_PP_TXCBLEND2 2 -#define PIX_PP_TXABLEND 3 -#define PIX_PP_TXABLEND2 4 -#define PIX_STATE_SIZE 5 - -#define TF_CMD_0 0 -#define TF_TFACTOR_0 1 -#define TF_TFACTOR_1 2 -#define TF_TFACTOR_2 3 -#define TF_TFACTOR_3 4 -#define TF_TFACTOR_4 5 -#define TF_TFACTOR_5 6 -#define TF_STATE_SIZE 7 - -#define TCL_CMD_0 0 -#define TCL_LIGHT_MODEL_CTL_0 1 -#define TCL_LIGHT_MODEL_CTL_1 2 -#define TCL_PER_LIGHT_CTL_0 3 -#define TCL_PER_LIGHT_CTL_1 4 -#define TCL_PER_LIGHT_CTL_2 5 -#define TCL_PER_LIGHT_CTL_3 6 -#define TCL_CMD_1 7 -#define TCL_UCP_VERT_BLEND_CTL 8 -#define TCL_STATE_SIZE 9 - -#define MSL_CMD_0 0 -#define MSL_MATRIX_SELECT_0 1 -#define MSL_MATRIX_SELECT_1 2 -#define MSL_MATRIX_SELECT_2 3 -#define MSL_MATRIX_SELECT_3 4 -#define MSL_MATRIX_SELECT_4 5 -#define MSL_STATE_SIZE 6 - -#define TCG_CMD_0 0 -#define TCG_TEX_PROC_CTL_2 1 -#define TCG_TEX_PROC_CTL_3 2 -#define TCG_TEX_PROC_CTL_0 3 -#define TCG_TEX_PROC_CTL_1 4 -#define TCG_TEX_CYL_WRAP_CTL 5 -#define TCG_STATE_SIZE 6 - -#define MTL_CMD_0 0 -#define MTL_EMMISSIVE_RED 1 -#define MTL_EMMISSIVE_GREEN 2 -#define MTL_EMMISSIVE_BLUE 3 -#define MTL_EMMISSIVE_ALPHA 4 -#define MTL_AMBIENT_RED 5 -#define MTL_AMBIENT_GREEN 6 -#define MTL_AMBIENT_BLUE 7 -#define MTL_AMBIENT_ALPHA 8 -#define MTL_DIFFUSE_RED 9 -#define MTL_DIFFUSE_GREEN 10 -#define MTL_DIFFUSE_BLUE 11 -#define MTL_DIFFUSE_ALPHA 12 -#define MTL_SPECULAR_RED 13 -#define MTL_SPECULAR_GREEN 14 -#define MTL_SPECULAR_BLUE 15 -#define MTL_SPECULAR_ALPHA 16 -#define MTL_CMD_1 17 -#define MTL_SHININESS 18 -#define MTL_STATE_SIZE 19 - -#define VAP_CMD_0 0 -#define VAP_SE_VAP_CNTL 1 -#define VAP_STATE_SIZE 2 - -/* Replaces a lot of packet info from radeon - */ -#define VTX_CMD_0 0 -#define VTX_VTXFMT_0 1 -#define VTX_VTXFMT_1 2 -#define VTX_TCL_OUTPUT_VTXFMT_0 3 -#define VTX_TCL_OUTPUT_VTXFMT_1 4 -#define VTX_CMD_1 5 -#define VTX_TCL_OUTPUT_COMPSEL 6 -#define VTX_CMD_2 7 -#define VTX_STATE_CNTL 8 -#define VTX_STATE_SIZE 9 - -#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ - R200_VTX_COLOR_MASK) - -/** - * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine - * how many components are in texture coordinate \c n. - */ -#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) - -#define MAT_CMD_0 0 -#define MAT_ELT_0 1 -#define MAT_STATE_SIZE 17 - -#define GRD_CMD_0 0 -#define GRD_VERT_GUARD_CLIP_ADJ 1 -#define GRD_VERT_GUARD_DISCARD_ADJ 2 -#define GRD_HORZ_GUARD_CLIP_ADJ 3 -#define GRD_HORZ_GUARD_DISCARD_ADJ 4 -#define GRD_STATE_SIZE 5 - -/* position changes frequently when lighting in modelpos - separate - * out to new state item? - */ -#define LIT_CMD_0 0 -#define LIT_AMBIENT_RED 1 -#define LIT_AMBIENT_GREEN 2 -#define LIT_AMBIENT_BLUE 3 -#define LIT_AMBIENT_ALPHA 4 -#define LIT_DIFFUSE_RED 5 -#define LIT_DIFFUSE_GREEN 6 -#define LIT_DIFFUSE_BLUE 7 -#define LIT_DIFFUSE_ALPHA 8 -#define LIT_SPECULAR_RED 9 -#define LIT_SPECULAR_GREEN 10 -#define LIT_SPECULAR_BLUE 11 -#define LIT_SPECULAR_ALPHA 12 -#define LIT_POSITION_X 13 -#define LIT_POSITION_Y 14 -#define LIT_POSITION_Z 15 -#define LIT_POSITION_W 16 -#define LIT_DIRECTION_X 17 -#define LIT_DIRECTION_Y 18 -#define LIT_DIRECTION_Z 19 -#define LIT_DIRECTION_W 20 -#define LIT_ATTEN_QUADRATIC 21 -#define LIT_ATTEN_LINEAR 22 -#define LIT_ATTEN_CONST 23 -#define LIT_ATTEN_XXX 24 -#define LIT_CMD_1 25 -#define LIT_SPOT_DCD 26 -#define LIT_SPOT_DCM 27 -#define LIT_SPOT_EXPONENT 28 -#define LIT_SPOT_CUTOFF 29 -#define LIT_SPECULAR_THRESH 30 -#define LIT_RANGE_CUTOFF 31 /* ? */ -#define LIT_ATTEN_CONST_INV 32 -#define LIT_STATE_SIZE 33 - -/* Fog - */ -#define FOG_CMD_0 0 -#define FOG_R 1 -#define FOG_C 2 -#define FOG_D 3 -#define FOG_PAD 4 -#define FOG_STATE_SIZE 5 - -/* UCP - */ -#define UCP_CMD_0 0 -#define UCP_X 1 -#define UCP_Y 2 -#define UCP_Z 3 -#define UCP_W 4 -#define UCP_STATE_SIZE 5 - -/* GLT - Global ambient - */ -#define GLT_CMD_0 0 -#define GLT_RED 1 -#define GLT_GREEN 2 -#define GLT_BLUE 3 -#define GLT_ALPHA 4 -#define GLT_STATE_SIZE 5 - -/* EYE - */ -#define EYE_CMD_0 0 -#define EYE_X 1 -#define EYE_Y 2 -#define EYE_Z 3 -#define EYE_RESCALE_FACTOR 4 -#define EYE_STATE_SIZE 5 - -/* CST - constant state - */ -#define CST_CMD_0 0 -#define CST_PP_CNTL_X 1 -#define CST_CMD_1 2 -#define CST_RB3D_DEPTHXY_OFFSET 3 -#define CST_CMD_2 4 -#define CST_RE_AUX_SCISSOR_CNTL 5 -#define CST_CMD_3 6 -#define CST_RE_SCISSOR_TL_0 7 -#define CST_RE_SCISSOR_BR_0 8 -#define CST_CMD_4 9 -#define CST_SE_VAP_CNTL_STATUS 10 -#define CST_CMD_5 11 -#define CST_RE_POINTSIZE 12 -#define CST_CMD_6 13 -#define CST_SE_TCL_INPUT_VTX_0 14 -#define CST_SE_TCL_INPUT_VTX_1 15 -#define CST_SE_TCL_INPUT_VTX_2 16 -#define CST_SE_TCL_INPUT_VTX_3 17 -#define CST_STATE_SIZE 18 - -struct r200_hw_state { - /* Head of the linked list of state atoms. */ - struct r200_state_atom atomlist; - - /* Hardware state, stored as cmdbuf commands: - * -- Need to doublebuffer for - * - reviving state after loss of context - * - eliding noop statechange loops? (except line stipple count) - */ - struct r200_state_atom ctx; - struct r200_state_atom set; - struct r200_state_atom vte; - struct r200_state_atom lin; - struct r200_state_atom msk; - struct r200_state_atom vpt; - struct r200_state_atom vap; - struct r200_state_atom vtx; - struct r200_state_atom tcl; - struct r200_state_atom msl; - struct r200_state_atom tcg; - struct r200_state_atom msc; - struct r200_state_atom cst; - struct r200_state_atom tam; - struct r200_state_atom tf; - struct r200_state_atom tex[6]; - struct r200_state_atom cube[6]; - struct r200_state_atom zbs; - struct r200_state_atom mtl[2]; - struct r200_state_atom mat[9]; - struct r200_state_atom lit[8]; /* includes vec, scl commands */ - struct r200_state_atom ucp[6]; - struct r200_state_atom pix[6]; /* pixshader stages */ - struct r200_state_atom eye; /* eye pos */ - struct r200_state_atom grd; /* guard band clipping */ - struct r200_state_atom fog; - struct r200_state_atom glt; - - int max_state_size; /* Number of bytes necessary for a full state emit. */ - GLboolean is_dirty, all_dirty; -}; - -struct r200_colorbuffer_state { - int roundEnable; -}; - -struct r200_state { - /* Derived state for internal purposes: - */ - struct r200_colorbuffer_state color; - struct r200_depthbuffer_state depth; - struct r200_stencilbuffer_state stencil; - struct r200_stipple_state stipple; - struct r200_texture_state texture; -}; - -/* Need refcounting on dma buffers: - */ -struct r200_dma_buffer { - int refcount; /* the number of retained regions in buf */ - drmBufPtr buf; -}; - -#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ - (rvb)->address - rmesa->dma.buf0_address + \ - (rvb)->start) - -/* A retained region, eg vertices for indexed vertices. - */ -struct r200_dma_region { - struct r200_dma_buffer *buf; - char *address; /* == buf->address */ - int start, end, ptr; /* offsets from start of buf */ - int aos_start; - int aos_stride; - int aos_size; -}; - -struct r200_dma { - /* Active dma region. Allocations for vertices and retained - * regions come from here. Also used for emitting random vertices, - * these may be flushed by calling flush_current(); - */ - struct r200_dma_region current; - - void (*flush) (r200ContextPtr); - - char *buf0_address; /* start of buf[0], for index calcs */ - GLuint nr_released_bufs; /* flush after so many buffers released */ -}; - -#define R200_CMD_BUF_SZ (8*1024) - -struct r200_store { - GLuint statenr; - GLuint primnr; - char cmd_buf[R200_CMD_BUF_SZ]; - int cmd_used; - int elts_start; -}; - -/* r200_tcl.c - */ -struct r200_tcl_info { - GLuint vertex_format; - GLint last_offset; - GLuint hw_primitive; - - struct r200_dma_region *aos_components[8]; - GLuint nr_aos_components; - - GLuint *Elts; - - struct r200_dma_region indexed_verts; - struct r200_dma_region obj; - struct r200_dma_region rgba; - struct r200_dma_region spec; - struct r200_dma_region fog; - struct r200_dma_region tex[R200_MAX_TEXTURE_UNITS]; - struct r200_dma_region norm; -}; - -/* r200_swtcl.c - */ -struct r200_swtcl_info { - GLuint RenderIndex; - - /** - * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is - * installed in the Mesa state vector. - */ - GLuint vertex_size; - - /** - * Attributes instructing the Mesa TCL pipeline where / how to put vertex - * data in the hardware buffer. - */ - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - - /** - * Number of elements of \c ::vertex_attrs that are actually used. - */ - GLuint vertex_attr_count; - - /** - * Cached pointer to the buffer where Mesa will store vertex data. - */ - GLubyte *verts; - - /* Fallback rasterization functions - */ - r200_point_func draw_point; - r200_line_func draw_line; - r200_tri_func draw_tri; - - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - - /** - * Offset of the 4UB color data within a hardware (swtcl) vertex. - */ - GLuint coloroffset; - - /** - * Offset of the 3UB specular color data within a hardware (swtcl) vertex. - */ - GLuint specoffset; - - /** - * Should Mesa project vertex data or will the hardware do it? - */ - GLboolean needproj; - - struct r200_dma_region indexed_verts; -}; - -struct r200_ioctl { - GLuint vertex_offset; - GLuint vertex_size; -}; - -#define R200_MAX_PRIMS 64 - -/* Want to keep a cache of these around. Each is parameterized by - * only a single value which has only a small range. Only expect a - * few, so just rescan the list each time? - */ -struct dynfn { - struct dynfn *next, *prev; - int key[2]; - char *code; -}; - -struct dfn_lists { - struct dynfn Vertex2f; - struct dynfn Vertex2fv; - struct dynfn Vertex3f; - struct dynfn Vertex3fv; - struct dynfn Color4ub; - struct dynfn Color4ubv; - struct dynfn Color3ub; - struct dynfn Color3ubv; - struct dynfn Color4f; - struct dynfn Color4fv; - struct dynfn Color3f; - struct dynfn Color3fv; - struct dynfn SecondaryColor3ubEXT; - struct dynfn SecondaryColor3ubvEXT; - struct dynfn SecondaryColor3fEXT; - struct dynfn SecondaryColor3fvEXT; - struct dynfn Normal3f; - struct dynfn Normal3fv; - struct dynfn TexCoord3f; - struct dynfn TexCoord3fv; - struct dynfn TexCoord2f; - struct dynfn TexCoord2fv; - struct dynfn TexCoord1f; - struct dynfn TexCoord1fv; - struct dynfn MultiTexCoord3fARB; - struct dynfn MultiTexCoord3fvARB; - struct dynfn MultiTexCoord2fARB; - struct dynfn MultiTexCoord2fvARB; - struct dynfn MultiTexCoord1fARB; - struct dynfn MultiTexCoord1fvARB; -}; - -struct dfn_generators { - struct dynfn *(*Vertex2f) (GLcontext *, const int *); - struct dynfn *(*Vertex2fv) (GLcontext *, const int *); - struct dynfn *(*Vertex3f) (GLcontext *, const int *); - struct dynfn *(*Vertex3fv) (GLcontext *, const int *); - struct dynfn *(*Color4ub) (GLcontext *, const int *); - struct dynfn *(*Color4ubv) (GLcontext *, const int *); - struct dynfn *(*Color3ub) (GLcontext *, const int *); - struct dynfn *(*Color3ubv) (GLcontext *, const int *); - struct dynfn *(*Color4f) (GLcontext *, const int *); - struct dynfn *(*Color4fv) (GLcontext *, const int *); - struct dynfn *(*Color3f) (GLcontext *, const int *); - struct dynfn *(*Color3fv) (GLcontext *, const int *); - struct dynfn *(*SecondaryColor3ubEXT) (GLcontext *, const int *); - struct dynfn *(*SecondaryColor3ubvEXT) (GLcontext *, const int *); - struct dynfn *(*SecondaryColor3fEXT) (GLcontext *, const int *); - struct dynfn *(*SecondaryColor3fvEXT) (GLcontext *, const int *); - struct dynfn *(*Normal3f) (GLcontext *, const int *); - struct dynfn *(*Normal3fv) (GLcontext *, const int *); - struct dynfn *(*TexCoord3f) (GLcontext *, const int *); - struct dynfn *(*TexCoord3fv) (GLcontext *, const int *); - struct dynfn *(*TexCoord2f) (GLcontext *, const int *); - struct dynfn *(*TexCoord2fv) (GLcontext *, const int *); - struct dynfn *(*TexCoord1f) (GLcontext *, const int *); - struct dynfn *(*TexCoord1fv) (GLcontext *, const int *); - struct dynfn *(*MultiTexCoord3fARB) (GLcontext *, const int *); - struct dynfn *(*MultiTexCoord3fvARB) (GLcontext *, const int *); - struct dynfn *(*MultiTexCoord2fARB) (GLcontext *, const int *); - struct dynfn *(*MultiTexCoord2fvARB) (GLcontext *, const int *); - struct dynfn *(*MultiTexCoord1fARB) (GLcontext *, const int *); - struct dynfn *(*MultiTexCoord1fvARB) (GLcontext *, const int *); -}; - -struct r200_prim { - GLuint start; - GLuint end; - GLuint prim; -}; - - /* A maximum total of 29 elements per vertex: 3 floats for position, 3 - * floats for normal, 4 floats for color, 4 bytes for secondary color, - * 3 floats for each texture unit (18 floats total). - * - * we maybe need add. 4 to prevent segfault if someone specifies - * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) - * - * The position data is never actually stored here, so 3 elements could be - * trimmed out of the buffer. - */ - -#define R200_MAX_VERTEX_SIZE ((3*6)+11) - -struct r200_vbinfo { - GLint counter, initial_counter; - GLint *dmaptr; - void (*notify) (void); - GLint vertex_size; - - union { - float f; - int i; - r200_color_t color; - } vertex[R200_MAX_VERTEX_SIZE]; - - GLfloat *normalptr; - GLfloat *floatcolorptr; - r200_color_t *colorptr; - GLfloat *floatspecptr; - r200_color_t *specptr; - GLfloat *texcoordptr[8]; /* 6 (TMU) + 2 for r200_vtxfmt_c.c when GL_TEXTURE6/7 */ - - GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ - GLuint primflags; - GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */ - GLboolean installed; - GLboolean fell_back; - GLboolean recheck; - GLint nrverts; - GLuint vtxfmt_0, vtxfmt_1; - - GLuint installed_vertex_format; - GLuint installed_color_3f_sz; - - struct r200_prim primlist[R200_MAX_PRIMS]; - int nrprims; - - struct dfn_lists dfn_cache; - struct dfn_generators codegen; - GLvertexformat vtxfmt; -}; - -/** - * R200 context structure. - */ -struct r200_context { - struct radeon_context radeon; /* parent class, must be first */ - - /* Driver and hardware state management - */ - struct r200_hw_state hw; - struct r200_state state; - - /* Texture object bookkeeping - */ - unsigned nr_heaps; - driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS]; - driTextureObject swapped; - int texture_depth; - float initialMaxAnisotropy; - - /* Rasterization and vertex state: - */ - GLuint NewGLState; - - /* Vertex buffers - */ - struct r200_ioctl ioctl; - struct r200_dma dma; - struct r200_store store; - GLboolean save_on_next_unlock; - - /* Clientdata textures; - */ - GLuint prefer_gart_client_texturing; - - /* TCL stuff - */ - GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; - GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; - GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; - GLuint TexMatEnabled; - GLuint TexMatCompSel; - GLuint TexGenEnabled; - GLuint TexGenInputs; - GLuint TexGenCompSel; - GLmatrix tmpmat; - - /* r200_tcl.c - */ - struct r200_tcl_info tcl; - - /* r200_swtcl.c - */ - struct r200_swtcl_info swtcl; - - /* r200_vtxfmt.c - */ - struct r200_vbinfo vb; -}; - -#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) - -extern void r200DestroyContext(__DRIcontextPrivate * driContextPriv); -extern GLboolean r200CreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate); - -#endif -#endif /* __R200_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/r200_ioctl.h b/src/mesa/drivers/dri/r300/r200_ioctl.h deleted file mode 100644 index db7bd7697f..0000000000 --- a/src/mesa/drivers/dri/r300/r200_ioctl.h +++ /dev/null @@ -1,204 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keith@tungstengraphics.com> - */ - -#ifndef __R200_IOCTL_H__ -#define __R200_IOCTL_H__ - -#include "simple_list.h" -#include "radeon_dri.h" -#include "radeon_lock.h" - -#include "xf86drm.h" -#include "drm.h" -#include "r200_context.h" -#include "radeon_drm.h" - -extern void r200EmitState(r200ContextPtr rmesa); -extern void r200EmitVertexAOS(r200ContextPtr rmesa, - GLuint vertex_size, GLuint offset); - -extern void r200EmitVbufPrim(r200ContextPtr rmesa, - GLuint primitive, GLuint vertex_nr); - -extern void r200FlushElts(r200ContextPtr rmesa); - -extern GLushort *r200AllocEltsOpenEnded(r200ContextPtr rmesa, - GLuint primitive, GLuint min_nr); - -extern void r200EmitAOS(r200ContextPtr rmesa, - struct r200_dma_region **regions, - GLuint n, GLuint offset); - -extern void r200EmitBlit(r200ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, GLuint w, GLuint h); - -extern void r200EmitWait(r200ContextPtr rmesa, GLuint flags); - -extern void r200FlushCmdBuf(r200ContextPtr rmesa, const char *); -extern int r200FlushCmdBufLocked(r200ContextPtr rmesa, const char *caller); -extern void r200Flush(GLcontext * ctx); - -extern void r200RefillCurrentDmaRegion(r200ContextPtr rmesa); - -extern void r200AllocDmaRegion(r200ContextPtr rmesa, - struct r200_dma_region *region, - int bytes, int alignment); - -extern void r200AllocDmaRegionVerts(r200ContextPtr rmesa, - struct r200_dma_region *region, - int numverts, int vertsize, int alignment); - -extern void r200ReleaseDmaRegion(r200ContextPtr rmesa, - struct r200_dma_region *region, - const char *caller); - -extern void r200WaitForVBlank(r200ContextPtr rmesa); -extern void r200InitIoctlFuncs(struct dd_function_table *functions); - -extern void *r200AllocateMemoryMESA(__DRInativeDisplay * dpy, int scrn, - GLsizei size, GLfloat readfreq, - GLfloat writefreq, GLfloat priority); -extern void r200FreeMemoryMESA(__DRInativeDisplay * dpy, int scrn, - GLvoid * pointer); -extern GLuint r200GetMemoryOffsetMESA(__DRInativeDisplay * dpy, int scrn, - const GLvoid * pointer); - -extern GLboolean r200IsGartMemory(r200ContextPtr rmesa, const GLvoid * pointer, - GLint size); - -extern GLuint r200GartOffsetFromVirtual(r200ContextPtr rmesa, - const GLvoid * pointer); - -void r200SaveHwState(r200ContextPtr radeon); -void r200SetUpAtomList(r200ContextPtr rmesa); - -/* ================================================================ - * Helper macros: - */ - -/* Close off the last primitive, if it exists. - */ -#define R200_NEWPRIM( rmesa ) \ -do { \ - if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa ); \ -} while (0) - -/* Can accomodate several state changes and primitive changes without - * actually firing the buffer. - */ -#define R200_STATECHANGE( rmesa, ATOM ) \ -do { \ - R200_NEWPRIM( rmesa ); \ - rmesa->hw.ATOM.dirty = GL_TRUE; \ - rmesa->hw.is_dirty = GL_TRUE; \ -} while (0) - -#define R200_DB_STATE( ATOM ) \ - memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \ - rmesa->hw.ATOM.cmd_size * 4) - -static __inline int R200_DB_STATECHANGE(r200ContextPtr rmesa, - struct r200_state_atom *atom) -{ - if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size * 4)) { - int *tmp; - R200_NEWPRIM(rmesa); - atom->dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; - tmp = atom->cmd; - atom->cmd = atom->lastcmd; - atom->lastcmd = tmp; - return 1; - } else - return 0; -} - -/* Fire the buffered vertices no matter what. - */ -#define R200_FIREVERTICES( r200 ) \ -do { \ - if ( (r200)->store.cmd_used || (r200)->dma.flush ) { \ - radeonFlush( (r200)->radeon.glCtx ); \ - } \ -} while (0) - -/* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ - * are available, you will also be adding an rmesa->state.max_state_size because - * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. - */ -#define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int)) -#define VERT_AOS_BUFSZ (5 * sizeof(int)) -#define ELTS_BUFSZ(nr) (12 + nr * 2) -#define VBUF_BUFSZ (3 * sizeof(int)) - -/* Ensure that a minimum amount of space is available in the command buffer. - * This is used to ensure atomicity of state updates with the rendering requests - * that rely on them. - * - * An alternative would be to implement a "soft lock" such that when the buffer - * wraps at an inopportune time, we grab the lock, flush the current buffer, - * and hang on to the lock until the critical section is finished and we flush - * the buffer again and unlock. - */ -static __inline void r200EnsureCmdBufSpace(r200ContextPtr rmesa, int bytes) -{ - if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - r200FlushCmdBuf(rmesa, __FUNCTION__); - assert(bytes <= R200_CMD_BUF_SZ); -} - -/* Alloc space in the command buffer - */ -static __inline char *r200AllocCmdBuf(r200ContextPtr rmesa, - int bytes, const char *where) -{ - char *head; - - if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - r200FlushCmdBuf(rmesa, where); - - head = rmesa->store.cmd_buf + rmesa->store.cmd_used; - rmesa->store.cmd_used += bytes; - assert(rmesa->store.cmd_used <= R200_CMD_BUF_SZ); - return head; -} - -#endif /* __R200_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r300/r200_reg.h b/src/mesa/drivers/dri/r300/r200_reg.h deleted file mode 100644 index 1336e961ac..0000000000 --- a/src/mesa/drivers/dri/r300/r200_reg.h +++ /dev/null @@ -1,1423 +0,0 @@ -/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_reg.h,v 1.2 2002/12/16 16:18:54 dawes Exp $ */ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -#ifndef _R200_REG_H_ -#define _R200_REG_H_ - -#define R200_PP_MISC 0x1c14 -#define R200_REF_ALPHA_MASK 0x000000ff -#define R200_ALPHA_TEST_FAIL (0 << 8) -#define R200_ALPHA_TEST_LESS (1 << 8) -#define R200_ALPHA_TEST_LEQUAL (2 << 8) -#define R200_ALPHA_TEST_EQUAL (3 << 8) -#define R200_ALPHA_TEST_GEQUAL (4 << 8) -#define R200_ALPHA_TEST_GREATER (5 << 8) -#define R200_ALPHA_TEST_NEQUAL (6 << 8) -#define R200_ALPHA_TEST_PASS (7 << 8) -#define R200_ALPHA_TEST_OP_MASK (7 << 8) -#define R200_CHROMA_FUNC_FAIL (0 << 16) -#define R200_CHROMA_FUNC_PASS (1 << 16) -#define R200_CHROMA_FUNC_NEQUAL (2 << 16) -#define R200_CHROMA_FUNC_EQUAL (3 << 16) -#define R200_CHROMA_KEY_NEAREST (0 << 18) -#define R200_CHROMA_KEY_ZERO (1 << 18) -#define R200_RIGHT_HAND_CUBE_D3D (0 << 24) -#define R200_RIGHT_HAND_CUBE_OGL (1 << 24) -#define R200_PP_FOG_COLOR 0x1c18 -#define R200_FOG_COLOR_MASK 0x00ffffff -#define R200_FOG_VERTEX (0 << 24) -#define R200_FOG_TABLE (1 << 24) -#define R200_FOG_USE_DEPTH (0 << 25) -#define R200_FOG_USE_W (1 << 25) -#define R200_FOG_USE_DIFFUSE_ALPHA (2 << 25) -#define R200_FOG_USE_SPEC_ALPHA (3 << 25) -#define R200_FOG_USE_VTX_FOG (4 << 25) -#define R200_FOG_USE_MASK (7 << 25) -#define R200_RE_SOLID_COLOR 0x1c1c -#define R200_RB3D_BLENDCNTL 0x1c20 -#define R200_COMB_FCN_MASK (7 << 12) -#define R200_COMB_FCN_ADD_CLAMP (0 << 12) -#define R200_COMB_FCN_ADD_NOCLAMP (1 << 12) -#define R200_COMB_FCN_SUB_CLAMP (2 << 12) -#define R200_COMB_FCN_SUB_NOCLAMP (3 << 12) -#define R200_COMB_FCN_MIN (4 << 12) -#define R200_COMB_FCN_MAX (5 << 12) -#define R200_COMB_FCN_RSUB_CLAMP (6 << 12) -#define R200_COMB_FCN_RSUB_NOCLAMP (7 << 12) -#define R200_BLEND_GL_ZERO (32) -#define R200_BLEND_GL_ONE (33) -#define R200_BLEND_GL_SRC_COLOR (34) -#define R200_BLEND_GL_ONE_MINUS_SRC_COLOR (35) -#define R200_BLEND_GL_DST_COLOR (36) -#define R200_BLEND_GL_ONE_MINUS_DST_COLOR (37) -#define R200_BLEND_GL_SRC_ALPHA (38) -#define R200_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) -#define R200_BLEND_GL_DST_ALPHA (40) -#define R200_BLEND_GL_ONE_MINUS_DST_ALPHA (41) -#define R200_BLEND_GL_SRC_ALPHA_SATURATE (42) /* src factor only */ -#define R200_BLEND_GL_CONST_COLOR (43) -#define R200_BLEND_GL_ONE_MINUS_CONST_COLOR (44) -#define R200_BLEND_GL_CONST_ALPHA (45) -#define R200_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) -#define R200_BLEND_MASK (63) -#define R200_SRC_BLEND_SHIFT (16) -#define R200_DST_BLEND_SHIFT (24) -#define R200_RB3D_DEPTHOFFSET 0x1c24 -#define R200_RB3D_DEPTHPITCH 0x1c28 -#define R200_DEPTHPITCH_MASK 0x00001ff8 -#define R200_DEPTH_ENDIAN_NO_SWAP (0 << 18) -#define R200_DEPTH_ENDIAN_WORD_SWAP (1 << 18) -#define R200_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) -#define R200_RB3D_ZSTENCILCNTL 0x1c2c -#define R200_DEPTH_FORMAT_MASK (0xf << 0) -#define R200_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -#define R200_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) -#define R200_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) -#define R200_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) -#define R200_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) -#define R200_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) -#define R200_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) -#define R200_Z_TEST_NEVER (0 << 4) -#define R200_Z_TEST_LESS (1 << 4) -#define R200_Z_TEST_LEQUAL (2 << 4) -#define R200_Z_TEST_EQUAL (3 << 4) -#define R200_Z_TEST_GEQUAL (4 << 4) -#define R200_Z_TEST_GREATER (5 << 4) -#define R200_Z_TEST_NEQUAL (6 << 4) -#define R200_Z_TEST_ALWAYS (7 << 4) -#define R200_Z_TEST_MASK (7 << 4) -#define R200_STENCIL_TEST_NEVER (0 << 12) -#define R200_STENCIL_TEST_LESS (1 << 12) -#define R200_STENCIL_TEST_LEQUAL (2 << 12) -#define R200_STENCIL_TEST_EQUAL (3 << 12) -#define R200_STENCIL_TEST_GEQUAL (4 << 12) -#define R200_STENCIL_TEST_GREATER (5 << 12) -#define R200_STENCIL_TEST_NEQUAL (6 << 12) -#define R200_STENCIL_TEST_ALWAYS (7 << 12) -#define R200_STENCIL_TEST_MASK (0x7 << 12) -#define R200_STENCIL_FAIL_KEEP (0 << 16) -#define R200_STENCIL_FAIL_ZERO (1 << 16) -#define R200_STENCIL_FAIL_REPLACE (2 << 16) -#define R200_STENCIL_FAIL_INC (3 << 16) -#define R200_STENCIL_FAIL_DEC (4 << 16) -#define R200_STENCIL_FAIL_INVERT (5 << 16) -#define R200_STENCIL_FAIL_INC_WRAP (6 << 16) -#define R200_STENCIL_FAIL_DEC_WRAP (7 << 16) -#define R200_STENCIL_FAIL_MASK (0x7 << 16) -#define R200_STENCIL_ZPASS_KEEP (0 << 20) -#define R200_STENCIL_ZPASS_ZERO (1 << 20) -#define R200_STENCIL_ZPASS_REPLACE (2 << 20) -#define R200_STENCIL_ZPASS_INC (3 << 20) -#define R200_STENCIL_ZPASS_DEC (4 << 20) -#define R200_STENCIL_ZPASS_INVERT (5 << 20) -#define R200_STENCIL_ZPASS_INC_WRAP (6 << 20) -#define R200_STENCIL_ZPASS_DEC_WRAP (7 << 20) -#define R200_STENCIL_ZPASS_MASK (0x7 << 20) -#define R200_STENCIL_ZFAIL_KEEP (0 << 24) -#define R200_STENCIL_ZFAIL_ZERO (1 << 24) -#define R200_STENCIL_ZFAIL_REPLACE (2 << 24) -#define R200_STENCIL_ZFAIL_INC (3 << 24) -#define R200_STENCIL_ZFAIL_DEC (4 << 24) -#define R200_STENCIL_ZFAIL_INVERT (5 << 24) -#define R200_STENCIL_ZFAIL_INC_WRAP (6 << 24) -#define R200_STENCIL_ZFAIL_DEC_WRAP (7 << 24) -#define R200_STENCIL_ZFAIL_MASK (0x7 << 24) -#define R200_Z_WRITE_ENABLE (1 << 30) -/*gap*/ -#define R200_PP_CNTL 0x1c38 -#define R200_TEX_0_ENABLE 0x00000010 -#define R200_TEX_1_ENABLE 0x00000020 -#define R200_TEX_2_ENABLE 0x00000040 -#define R200_TEX_3_ENABLE 0x00000080 -#define R200_TEX_4_ENABLE 0x00000100 -#define R200_TEX_5_ENABLE 0x00000200 -#define R200_TEX_ENABLE_MASK 0x000003f0 -#define R200_FILTER_ROUND_MODE_MASK 0x00000400 -#define R200_TEX_BLEND_7_ENABLE 0x00000800 -#define R200_TEX_BLEND_0_ENABLE 0x00001000 -#define R200_TEX_BLEND_1_ENABLE 0x00002000 -#define R200_TEX_BLEND_2_ENABLE 0x00004000 -#define R200_TEX_BLEND_3_ENABLE 0x00008000 -#define R200_TEX_BLEND_4_ENABLE 0x00010000 -#define R200_TEX_BLEND_5_ENABLE 0x00020000 -#define R200_TEX_BLEND_6_ENABLE 0x00040000 -#define R200_MULTI_PASS_ENABLE 0x00080000 -#define R200_SPECULAR_ENABLE 0x00200000 -#define R200_FOG_ENABLE 0x00400000 -#define R200_ALPHA_TEST_ENABLE 0x00800000 -#define R200_ANTI_ALIAS_NONE 0x00000000 -#define R200_ANTI_ALIAS_LINE 0x01000000 -#define R200_ANTI_ALIAS_POLY 0x02000000 -#define R200_ANTI_ALIAS_MASK 0x03000000 -#define R200_RB3D_CNTL 0x1c3c -#define R200_ALPHA_BLEND_ENABLE (1 << 0) -#define R200_PLANE_MASK_ENABLE (1 << 1) -#define R200_DITHER_ENABLE (1 << 2) -#define R200_ROUND_ENABLE (1 << 3) -#define R200_SCALE_DITHER_ENABLE (1 << 4) -#define R200_DITHER_INIT (1 << 5) -#define R200_ROP_ENABLE (1 << 6) -#define R200_STENCIL_ENABLE (1 << 7) -#define R200_Z_ENABLE (1 << 8) -#define R200_DEPTH_XZ_OFFEST_ENABLE (1 << 9) -#define R200_COLOR_FORMAT_ARGB1555 (3 << 10) -#define R200_COLOR_FORMAT_RGB565 (4 << 10) -#define R200_COLOR_FORMAT_ARGB8888 (6 << 10) -#define R200_COLOR_FORMAT_RGB332 (7 << 10) -#define R200_COLOR_FORMAT_Y8 (8 << 10) -#define R200_COLOR_FORMAT_RGB8 (9 << 10) -#define R200_COLOR_FORMAT_YUV422_VYUY (11 << 10) -#define R200_COLOR_FORMAT_YUV422_YVYU (12 << 10) -#define R200_COLOR_FORMAT_aYUV444 (14 << 10) -#define R200_COLOR_FORMAT_ARGB4444 (15 << 10) -#define R200_CLRCMP_FLIP_ENABLE (1 << 14) -#define R200_SEPARATE_ALPHA_ENABLE (1 << 16) -#define R200_RB3D_COLOROFFSET 0x1c40 -#define R200_COLOROFFSET_MASK 0xfffffff0 -#define R200_RE_WIDTH_HEIGHT 0x1c44 -#define R200_RE_WIDTH_SHIFT 0 -#define R200_RE_HEIGHT_SHIFT 16 -#define R200_RB3D_COLORPITCH 0x1c48 -#define R200_COLORPITCH_MASK 0x000001ff8 -#define R200_COLOR_ENDIAN_NO_SWAP (0 << 18) -#define R200_COLOR_ENDIAN_WORD_SWAP (1 << 18) -#define R200_COLOR_ENDIAN_DWORD_SWAP (2 << 18) -#define R200_SE_CNTL 0x1c4c -#define R200_FFACE_CULL_CW (0 << 0) -#define R200_FFACE_CULL_CCW (1 << 0) -#define R200_FFACE_CULL_DIR_MASK (1 << 0) -#define R200_BFACE_CULL (0 << 1) -#define R200_BFACE_SOLID (3 << 1) -#define R200_FFACE_CULL (0 << 3) -#define R200_FFACE_SOLID (3 << 3) -#define R200_FFACE_CULL_MASK (3 << 3) -#define R200_FLAT_SHADE_VTX_0 (0 << 6) -#define R200_FLAT_SHADE_VTX_1 (1 << 6) -#define R200_FLAT_SHADE_VTX_2 (2 << 6) -#define R200_FLAT_SHADE_VTX_LAST (3 << 6) -#define R200_DIFFUSE_SHADE_SOLID (0 << 8) -#define R200_DIFFUSE_SHADE_FLAT (1 << 8) -#define R200_DIFFUSE_SHADE_GOURAUD (2 << 8) -#define R200_DIFFUSE_SHADE_MASK (3 << 8) -#define R200_ALPHA_SHADE_SOLID (0 << 10) -#define R200_ALPHA_SHADE_FLAT (1 << 10) -#define R200_ALPHA_SHADE_GOURAUD (2 << 10) -#define R200_ALPHA_SHADE_MASK (3 << 10) -#define R200_SPECULAR_SHADE_SOLID (0 << 12) -#define R200_SPECULAR_SHADE_FLAT (1 << 12) -#define R200_SPECULAR_SHADE_GOURAUD (2 << 12) -#define R200_SPECULAR_SHADE_MASK (3 << 12) -#define R200_FOG_SHADE_SOLID (0 << 14) -#define R200_FOG_SHADE_FLAT (1 << 14) -#define R200_FOG_SHADE_GOURAUD (2 << 14) -#define R200_FOG_SHADE_MASK (3 << 14) -#define R200_ZBIAS_ENABLE_POINT (1 << 16) -#define R200_ZBIAS_ENABLE_LINE (1 << 17) -#define R200_ZBIAS_ENABLE_TRI (1 << 18) -#define R200_WIDELINE_ENABLE (1 << 20) -#define R200_VTX_PIX_CENTER_D3D (0 << 27) -#define R200_VTX_PIX_CENTER_OGL (1 << 27) -#define R200_ROUND_MODE_TRUNC (0 << 28) -#define R200_ROUND_MODE_ROUND (1 << 28) -#define R200_ROUND_MODE_ROUND_EVEN (2 << 28) -#define R200_ROUND_MODE_ROUND_ODD (3 << 28) -#define R200_ROUND_PREC_16TH_PIX (0 << 30) -#define R200_ROUND_PREC_8TH_PIX (1 << 30) -#define R200_ROUND_PREC_4TH_PIX (2 << 30) -#define R200_ROUND_PREC_HALF_PIX (3 << 30) -#define R200_RE_CNTL 0x1c50 -#define R200_STIPPLE_ENABLE 0x1 -#define R200_SCISSOR_ENABLE 0x2 -#define R200_PATTERN_ENABLE 0x4 -#define R200_PERSPECTIVE_ENABLE 0x8 -#define R200_POINT_SMOOTH 0x20 -#define R200_VTX_STQ0_D3D 0x00010000 -#define R200_VTX_STQ1_D3D 0x00040000 -#define R200_VTX_STQ2_D3D 0x00100000 -#define R200_VTX_STQ3_D3D 0x00400000 -#define R200_VTX_STQ4_D3D 0x01000000 -#define R200_VTX_STQ5_D3D 0x04000000 -/* gap */ -#define R200_RE_STIPPLE_ADDR 0x1cc8 -#define R200_RE_STIPPLE_DATA 0x1ccc -#define R200_RE_LINE_PATTERN 0x1cd0 -#define R200_LINE_PATTERN_MASK 0x0000ffff -#define R200_LINE_REPEAT_COUNT_SHIFT 16 -#define R200_LINE_PATTERN_START_SHIFT 24 -#define R200_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) -#define R200_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) -#define R200_LINE_PATTERN_AUTO_RESET (1 << 29) -#define R200_RE_LINE_STATE 0x1cd4 -#define R200_LINE_CURRENT_PTR_SHIFT 0 -#define R200_LINE_CURRENT_COUNT_SHIFT 8 -#define R200_RE_SCISSOR_TL_0 0x1cd8 -#define R200_RE_SCISSOR_BR_0 0x1cdc -#define R200_RE_SCISSOR_TL_1 0x1ce0 -#define R200_RE_SCISSOR_BR_1 0x1ce4 -#define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RE_SCISSOR_BR_2 0x1cec -/* gap */ -#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 -#define R200_DEPTHX_SHIFT 0 -#define R200_DEPTHY_SHIFT 16 -/* gap */ -#define R200_RB3D_STENCILREFMASK 0x1d7c -#define R200_STENCIL_REF_SHIFT 0 -#define R200_STENCIL_REF_MASK (0xff << 0) -#define R200_STENCIL_MASK_SHIFT 16 -#define R200_STENCIL_VALUE_MASK (0xff << 16) -#define R200_STENCIL_WRITEMASK_SHIFT 24 -#define R200_STENCIL_WRITE_MASK (0xff << 24) -#define R200_RB3D_ROPCNTL 0x1d80 -#define R200_ROP_MASK (15 << 8) -#define R200_ROP_CLEAR (0 << 8) -#define R200_ROP_NOR (1 << 8) -#define R200_ROP_AND_INVERTED (2 << 8) -#define R200_ROP_COPY_INVERTED (3 << 8) -#define R200_ROP_AND_REVERSE (4 << 8) -#define R200_ROP_INVERT (5 << 8) -#define R200_ROP_XOR (6 << 8) -#define R200_ROP_NAND (7 << 8) -#define R200_ROP_AND (8 << 8) -#define R200_ROP_EQUIV (9 << 8) -#define R200_ROP_NOOP (10 << 8) -#define R200_ROP_OR_INVERTED (11 << 8) -#define R200_ROP_COPY (12 << 8) -#define R200_ROP_OR_REVERSE (13 << 8) -#define R200_ROP_OR (14 << 8) -#define R200_ROP_SET (15 << 8) -#define R200_RB3D_PLANEMASK 0x1d84 -/* gap */ -#define R200_SE_VPORT_XSCALE 0x1d98 -#define R200_SE_VPORT_XOFFSET 0x1d9c -#define R200_SE_VPORT_YSCALE 0x1da0 -#define R200_SE_VPORT_YOFFSET 0x1da4 -#define R200_SE_VPORT_ZSCALE 0x1da8 -#define R200_SE_VPORT_ZOFFSET 0x1dac -#define R200_SE_ZBIAS_FACTOR 0x1db0 -#define R200_SE_ZBIAS_CONSTANT 0x1db4 -#define R200_SE_LINE_WIDTH 0x1db8 -#define R200_LINE_WIDTH_SHIFT 0x00000000 -#define R200_MINPOINTSIZE_SHIFT 0x00000010 -/* gap */ -#define R200_SE_VAP_CNTL 0x2080 -#define R200_VAP_TCL_ENABLE 0x00000001 -#define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 -#define R200_VAP_FORCE_W_TO_ONE 0x00010000 -#define R200_VAP_D3D_TEX_DEFAULT 0x00020000 -#define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 -#define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 -#define R200_SE_VF_CNTL 0x2084 -#define R200_VF_PRIM_NONE 0x00000000 -#define R200_VF_PRIM_POINTS 0x00000001 -#define R200_VF_PRIM_LINES 0x00000002 -#define R200_VF_PRIM_LINE_STRIP 0x00000003 -#define R200_VF_PRIM_TRIANGLES 0x00000004 -#define R200_VF_PRIM_TRIANGLE_FAN 0x00000005 -#define R200_VF_PRIM_TRIANGLE_STRIP 0x00000006 -#define R200_VF_PRIM_RECT_LIST 0x00000008 -#define R200_VF_PRIM_3VRT_POINTS 0x00000009 -#define R200_VF_PRIM_3VRT_LINES 0x0000000a -#define R200_VF_PRIM_POINT_SPRITES 0x0000000b -#define R200_VF_PRIM_LINE_LOOP 0x0000000c -#define R200_VF_PRIM_QUADS 0x0000000d -#define R200_VF_PRIM_QUAD_STRIP 0x0000000e -#define R200_VF_PRIM_POLYGON 0x0000000f -#define R200_VF_PRIM_MASK 0x0000000f -#define R200_VF_PRIM_WALK_IND 0x00000010 -#define R200_VF_PRIM_WALK_LIST 0x00000020 -#define R200_VF_PRIM_WALK_RING 0x00000030 -#define R200_VF_PRIM_WALK_MASK 0x00000030 -#define R200_VF_COLOR_ORDER_RGBA 0x00000040 -#define R200_VF_TCL_OUTPUT_VTX_ENABLE 0x00000200 -#define R200_VF_INDEX_SZ_4 0x00000800 -#define R200_VF_VERTEX_NUMBER_MASK 0xffff0000 -#define R200_VF_VERTEX_NUMBER_SHIFT 16 -#define R200_SE_VTX_FMT_0 0x2088 -#define R200_VTX_XY 0 /* always have xy */ -#define R200_VTX_Z0 (1<<0) -#define R200_VTX_W0 (1<<1) -#define R200_VTX_WEIGHT_COUNT_SHIFT (2) -#define R200_VTX_PV_MATRIX_SEL (1<<5) -#define R200_VTX_N0 (1<<6) -#define R200_VTX_POINT_SIZE (1<<7) -#define R200_VTX_DISCRETE_FOG (1<<8) -#define R200_VTX_SHININESS_0 (1<<9) -#define R200_VTX_SHININESS_1 (1<<10) -#define R200_VTX_COLOR_NOT_PRESENT 0 -#define R200_VTX_PK_RGBA 1 -#define R200_VTX_FP_RGB 2 -#define R200_VTX_FP_RGBA 3 -#define R200_VTX_COLOR_MASK 3 -#define R200_VTX_COLOR_0_SHIFT 11 -#define R200_VTX_COLOR_1_SHIFT 13 -#define R200_VTX_COLOR_2_SHIFT 15 -#define R200_VTX_COLOR_3_SHIFT 17 -#define R200_VTX_COLOR_4_SHIFT 19 -#define R200_VTX_COLOR_5_SHIFT 21 -#define R200_VTX_COLOR_6_SHIFT 23 -#define R200_VTX_COLOR_7_SHIFT 25 -#define R200_VTX_XY1 (1<<28) -#define R200_VTX_Z1 (1<<29) -#define R200_VTX_W1 (1<<30) -#define R200_VTX_N1 (1<<31) -#define R200_SE_VTX_FMT_1 0x208c -#define R200_VTX_TEX0_COMP_CNT_SHIFT 0 -#define R200_VTX_TEX1_COMP_CNT_SHIFT 3 -#define R200_VTX_TEX2_COMP_CNT_SHIFT 6 -#define R200_VTX_TEX3_COMP_CNT_SHIFT 9 -#define R200_VTX_TEX4_COMP_CNT_SHIFT 12 -#define R200_VTX_TEX5_COMP_CNT_SHIFT 15 -#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 -#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 -/* gap */ -#define R200_SE_VTE_CNTL 0x20b0 -#define R200_VPORT_X_SCALE_ENA 0x00000001 -#define R200_VPORT_X_OFFSET_ENA 0x00000002 -#define R200_VPORT_Y_SCALE_ENA 0x00000004 -#define R200_VPORT_Y_OFFSET_ENA 0x00000008 -#define R200_VPORT_Z_SCALE_ENA 0x00000010 -#define R200_VPORT_Z_OFFSET_ENA 0x00000020 -#define R200_VTX_XY_FMT 0x00000100 -#define R200_VTX_Z_FMT 0x00000200 -#define R200_VTX_W0_FMT 0x00000400 -#define R200_VTX_W0_NORMALIZE 0x00000800 -#define R200_VTX_ST_DENORMALIZED 0x00001000 -/* gap */ -#define R200_SE_VTX_NUM_ARRAYS 0x20c0 -#define R200_SE_VTX_AOS_ATTR01 0x20c4 -#define R200_SE_VTX_AOS_ADDR0 0x20c8 -#define R200_SE_VTX_AOS_ADDR1 0x20cc -#define R200_SE_VTX_AOS_ATTR23 0x20d0 -#define R200_SE_VTX_AOS_ADDR2 0x20d4 -#define R200_SE_VTX_AOS_ADDR3 0x20d8 -#define R200_SE_VTX_AOS_ATTR45 0x20dc -#define R200_SE_VTX_AOS_ADDR4 0x20e0 -#define R200_SE_VTX_AOS_ADDR5 0x20e4 -#define R200_SE_VTX_AOS_ATTR67 0x20e8 -#define R200_SE_VTX_AOS_ADDR6 0x20ec -#define R200_SE_VTX_AOS_ADDR7 0x20f0 -#define R200_SE_VTX_AOS_ATTR89 0x20f4 -#define R200_SE_VTX_AOS_ADDR8 0x20f8 -#define R200_SE_VTX_AOS_ADDR9 0x20fc -#define R200_SE_VTX_AOS_ATTR1011 0x2100 -#define R200_SE_VTX_AOS_ADDR10 0x2104 -#define R200_SE_VTX_AOS_ADDR11 0x2108 -#define R200_SE_VF_MAX_VTX_INDX 0x210c -#define R200_SE_VF_MIN_VTX_INDX 0x2110 -/* gap */ -#define R200_SE_VAP_CNTL_STATUS 0x2140 -#define R200_VC_NO_SWAP (0 << 0) -#define R200_VC_16BIT_SWAP (1 << 0) -#define R200_VC_32BIT_SWAP (2 << 0) -/* gap */ -#define R200_SE_VTX_STATE_CNTL 0x2180 -#define R200_VSC_COLOR_0_ASSEMBLY_CNTL_SHIFT 0x00000000 -#define R200_VSC_COLOR_1_ASSEMBLY_CNTL_SHIFT 0x00000002 -#define R200_VSC_COLOR_2_ASSEMBLY_CNTL_SHIFT 0x00000004 -#define R200_VSC_COLOR_3_ASSEMBLY_CNTL_SHIFT 0x00000006 -#define R200_VSC_COLOR_4_ASSEMBLY_CNTL_SHIFT 0x00000008 -#define R200_VSC_COLOR_5_ASSEMBLY_CNTL_SHIFT 0x0000000a -#define R200_VSC_COLOR_6_ASSEMBLY_CNTL_SHIFT 0x0000000c -#define R200_VSC_COLOR_7_ASSEMBLY_CNTL_SHIFT 0x0000000e -#define R200_VSC_UPDATE_USER_COLOR_0_ENABLE 0x00010000 -#define R200_VSC_UPDATE_USER_COLOR_1_ENABLE 0x00020000 -/* gap */ -#define R200_SE_TCL_VECTOR_INDX_REG 0x2200 -#define R200_SE_TCL_VECTOR_DATA_REG 0x2204 -#define R200_SE_TCL_SCALAR_INDX_REG 0x2208 -#define R200_SE_TCL_SCALAR_DATA_REG 0x220c -/* gap */ -#define R200_SE_TCL_MATRIX_SEL_0 0x2230 -#define R200_MODELVIEW_0_SHIFT (0) -#define R200_MODELVIEW_1_SHIFT (8) -#define R200_MODELVIEW_2_SHIFT (16) -#define R200_MODELVIEW_3_SHIFT (24) -#define R200_SE_TCL_MATRIX_SEL_1 0x2234 -#define R200_IT_MODELVIEW_0_SHIFT (0) -#define R200_IT_MODELVIEW_1_SHIFT (8) -#define R200_IT_MODELVIEW_2_SHIFT (16) -#define R200_IT_MODELVIEW_3_SHIFT (24) -#define R200_SE_TCL_MATRIX_SEL_2 0x2238 -#define R200_MODELPROJECT_0_SHIFT (0) -#define R200_MODELPROJECT_1_SHIFT (8) -#define R200_MODELPROJECT_2_SHIFT (16) -#define R200_MODELPROJECT_3_SHIFT (24) -#define R200_SE_TCL_MATRIX_SEL_3 0x223c -#define R200_TEXMAT_0_SHIFT 0 -#define R200_TEXMAT_1_SHIFT 8 -#define R200_TEXMAT_2_SHIFT 16 -#define R200_TEXMAT_3_SHIFT 24 -#define R200_SE_TCL_MATRIX_SEL_4 0x2240 -#define R200_TEXMAT_4_SHIFT 0 -#define R200_TEXMAT_5_SHIFT 8 -/* gap */ -#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 -#define R200_OUTPUT_XYZW (1<<0) -#define R200_OUTPUT_COLOR_0 (1<<8) -#define R200_OUTPUT_COLOR_1 (1<<9) -#define R200_OUTPUT_TEX_0 (1<<16) -#define R200_OUTPUT_TEX_1 (1<<17) -#define R200_OUTPUT_TEX_2 (1<<18) -#define R200_OUTPUT_TEX_3 (1<<19) -#define R200_OUTPUT_TEX_4 (1<<20) -#define R200_OUTPUT_TEX_5 (1<<21) -#define R200_OUTPUT_TEX_MASK (0x3f<<16) -#define R200_OUTPUT_DISCRETE_FOG (1<<24) -#define R200_OUTPUT_PT_SIZE (1<<25) -#define R200_FORCE_INORDER_PROC (1<<31) -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 -#define R200_VERTEX_POSITION_ADDR__SHIFT 0x00000000 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1 0x2258 -#define R200_VTX_COLOR_0_ADDR__SHIFT 0x00000000 -#define R200_VTX_COLOR_1_ADDR__SHIFT 0x00000008 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2 0x225c -#define R200_VTX_TEX_0_ADDR__SHIFT 0x00000000 -#define R200_VTX_TEX_1_ADDR__SHIFT 0x00000008 -#define R200_VTX_TEX_2_ADDR__SHIFT 0x00000010 -#define R200_VTX_TEX_3_ADDR__SHIFT 0x00000018 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3 0x2260 -#define R200_VTX_TEX_4_ADDR__SHIFT 0x00000000 -#define R200_VTX_TEX_5_ADDR__SHIFT 0x00000008 - -/* gap */ -#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 -#define R200_LIGHTING_ENABLE (1<<0) -#define R200_LIGHT_IN_MODELSPACE (1<<1) -#define R200_LOCAL_VIEWER (1<<2) -#define R200_NORMALIZE_NORMALS (1<<3) -#define R200_RESCALE_NORMALS (1<<4) -#define R200_SPECULAR_LIGHTS (1<<5) -#define R200_DIFFUSE_SPECULAR_COMBINE (1<<6) -#define R200_LIGHT_ALPHA (1<<7) -#define R200_LOCAL_LIGHT_VEC_GL (1<<8) -#define R200_LIGHT_NO_NORMAL_AMBIENT_ONLY (1<<9) -#define R200_LIGHT_TWOSIDE (1<<10) -#define R200_FRONT_SHININESS_SOURCE_SHIFT (0xb) -#define R200_BACK_SHININESS_SOURCE_SHIFT (0xd) -#define R200_LM0_SOURCE_MATERIAL_0 (0) -#define R200_LM0_SOURCE_MATERIAL_1 (1) -#define R200_LM0_SOURCE_VERTEX_SHININESS_0 (2) -#define R200_LM0_SOURCE_VERTEX_SHININESS_1 (3) -#define R200_SE_TCL_LIGHT_MODEL_CTL_1 0x226c -#define R200_LM1_SOURCE_LIGHT_PREMULT (0) -#define R200_LM1_SOURCE_MATERIAL_0 (1) -#define R200_LM1_SOURCE_VERTEX_COLOR_0 (2) -#define R200_LM1_SOURCE_VERTEX_COLOR_1 (3) -#define R200_LM1_SOURCE_VERTEX_COLOR_2 (4) -#define R200_LM1_SOURCE_VERTEX_COLOR_3 (5) -#define R200_LM1_SOURCE_VERTEX_COLOR_4 (6) -#define R200_LM1_SOURCE_VERTEX_COLOR_5 (7) -#define R200_LM1_SOURCE_VERTEX_COLOR_6 (8) -#define R200_LM1_SOURCE_VERTEX_COLOR_7 (9) -#define R200_LM1_SOURCE_MATERIAL_1 (0xf) -#define R200_FRONT_EMISSIVE_SOURCE_SHIFT (0) -#define R200_FRONT_AMBIENT_SOURCE_SHIFT (4) -#define R200_FRONT_DIFFUSE_SOURCE_SHIFT (8) -#define R200_FRONT_SPECULAR_SOURCE_SHIFT (12) -#define R200_BACK_EMISSIVE_SOURCE_SHIFT (16) -#define R200_BACK_AMBIENT_SOURCE_SHIFT (20) -#define R200_BACK_DIFFUSE_SOURCE_SHIFT (24) -#define R200_BACK_SPECULAR_SOURCE_SHIFT (28) -#define R200_SE_TCL_PER_LIGHT_CTL_0 0x2270 -#define R200_LIGHT_0_ENABLE (1<<0) -#define R200_LIGHT_0_ENABLE_AMBIENT (1<<1) -#define R200_LIGHT_0_ENABLE_SPECULAR (1<<2) -#define R200_LIGHT_0_IS_LOCAL (1<<3) -#define R200_LIGHT_0_IS_SPOT (1<<4) -#define R200_LIGHT_0_DUAL_CONE (1<<5) -#define R200_LIGHT_0_ENABLE_RANGE_ATTEN (1<<6) -#define R200_LIGHT_0_CONSTANT_RANGE_ATTEN (1<<7) -#define R200_LIGHT_1_ENABLE (1<<16) -#define R200_LIGHT_1_ENABLE_AMBIENT (1<<17) -#define R200_LIGHT_1_ENABLE_SPECULAR (1<<18) -#define R200_LIGHT_1_IS_LOCAL (1<<19) -#define R200_LIGHT_1_IS_SPOT (1<<20) -#define R200_LIGHT_1_DUAL_CONE (1<<21) -#define R200_LIGHT_1_ENABLE_RANGE_ATTEN (1<<22) -#define R200_LIGHT_1_CONSTANT_RANGE_ATTEN (1<<23) -#define R200_LIGHT_0_SHIFT (0) -#define R200_LIGHT_1_SHIFT (16) -#define R200_SE_TCL_PER_LIGHT_CTL_1 0x2274 -#define R200_LIGHT_2_SHIFT (0) -#define R200_LIGHT_3_SHIFT (16) -#define R200_SE_TCL_PER_LIGHT_CTL_2 0x2278 -#define R200_LIGHT_4_SHIFT (0) -#define R200_LIGHT_5_SHIFT (16) -#define R200_SE_TCL_PER_LIGHT_CTL_3 0x227c -#define R200_LIGHT_6_SHIFT (0) -#define R200_LIGHT_7_SHIFT (16) -/* gap */ -#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 -#define R200_TEXGEN_0_COMP_MASK_SHIFT (0) -#define R200_TEXGEN_1_COMP_MASK_SHIFT (4) -#define R200_TEXGEN_2_COMP_MASK_SHIFT (8) -#define R200_TEXGEN_3_COMP_MASK_SHIFT (12) -#define R200_TEXGEN_4_COMP_MASK_SHIFT (16) -#define R200_TEXGEN_5_COMP_MASK_SHIFT (20) -#define R200_SE_TCL_TEX_PROC_CTL_3 0x22ac -#define R200_TEXGEN_0_INPUT_TEX_SHIFT (0) -#define R200_TEXGEN_1_INPUT_TEX_SHIFT (4) -#define R200_TEXGEN_2_INPUT_TEX_SHIFT (8) -#define R200_TEXGEN_3_INPUT_TEX_SHIFT (12) -#define R200_TEXGEN_4_INPUT_TEX_SHIFT (16) -#define R200_TEXGEN_5_INPUT_TEX_SHIFT (20) -#define R200_SE_TCL_TEX_PROC_CTL_0 0x22b0 -#define R200_TEXGEN_TEXMAT_0_ENABLE (1<<0) -#define R200_TEXGEN_TEXMAT_1_ENABLE (1<<1) -#define R200_TEXGEN_TEXMAT_2_ENABLE (1<<2) -#define R200_TEXGEN_TEXMAT_3_ENABLE (1<<3) -#define R200_TEXGEN_TEXMAT_4_ENABLE (1<<4) -#define R200_TEXGEN_TEXMAT_5_ENABLE (1<<5) -#define R200_TEXMAT_0_ENABLE (1<<8) -#define R200_TEXMAT_1_ENABLE (1<<9) -#define R200_TEXMAT_2_ENABLE (1<<10) -#define R200_TEXMAT_3_ENABLE (1<<11) -#define R200_TEXMAT_4_ENABLE (1<<12) -#define R200_TEXMAT_5_ENABLE (1<<13) -#define R200_TEXGEN_FORCE_W_TO_ONE (1<<16) -#define R200_SE_TCL_TEX_PROC_CTL_1 0x22b4 -#define R200_TEXGEN_INPUT_MASK (0xf) -#define R200_TEXGEN_INPUT_TEXCOORD_0 (0) -#define R200_TEXGEN_INPUT_TEXCOORD_1 (1) -#define R200_TEXGEN_INPUT_TEXCOORD_2 (2) -#define R200_TEXGEN_INPUT_TEXCOORD_3 (3) -#define R200_TEXGEN_INPUT_TEXCOORD_4 (4) -#define R200_TEXGEN_INPUT_TEXCOORD_5 (5) -#define R200_TEXGEN_INPUT_OBJ (8) -#define R200_TEXGEN_INPUT_EYE (9) -#define R200_TEXGEN_INPUT_EYE_NORMAL (0xa) -#define R200_TEXGEN_INPUT_EYE_REFLECT (0xb) -#define R200_TEXGEN_INPUT_SPHERE (0xd) -#define R200_TEXGEN_0_INPUT_SHIFT (0) -#define R200_TEXGEN_1_INPUT_SHIFT (4) -#define R200_TEXGEN_2_INPUT_SHIFT (8) -#define R200_TEXGEN_3_INPUT_SHIFT (12) -#define R200_TEXGEN_4_INPUT_SHIFT (16) -#define R200_TEXGEN_5_INPUT_SHIFT (20) -#define R200_SE_TC_TEX_CYL_WRAP_CTL 0x22b8 -/* gap */ -#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 -#define R200_UCP_IN_CLIP_SPACE (1<<0) -#define R200_UCP_IN_MODEL_SPACE (1<<1) -#define R200_UCP_ENABLE_0 (1<<2) -#define R200_UCP_ENABLE_1 (1<<3) -#define R200_UCP_ENABLE_2 (1<<4) -#define R200_UCP_ENABLE_3 (1<<5) -#define R200_UCP_ENABLE_4 (1<<6) -#define R200_UCP_ENABLE_5 (1<<7) -#define R200_TCL_FOG_MASK (3<<8) -#define R200_TCL_FOG_DISABLE (0<<8) -#define R200_TCL_FOG_EXP (1<<8) -#define R200_TCL_FOG_EXP2 (2<<8) -#define R200_TCL_FOG_LINEAR (3<<8) -#define R200_RNG_BASED_FOG (1<<10) -#define R200_CLIP_DISABLE (1<<11) -#define R200_CULL_FRONT_IS_CW (0<<28) -#define R200_CULL_FRONT_IS_CCW (1<<28) -#define R200_CULL_FRONT (1<<29) -#define R200_CULL_BACK (1<<30) -#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 -/* gap */ -#define R200_SE_VTX_ST_POS_0_X_4 0x2300 -#define R200_SE_VTX_ST_POS_0_Y_4 0x2304 -#define R200_SE_VTX_ST_POS_0_Z_4 0x2308 -#define R200_SE_VTX_ST_POS_0_W_4 0x230c -#define R200_SE_VTX_ST_NORM_0_X 0x2310 -#define R200_SE_VTX_ST_NORM_0_Y 0x2314 -#define R200_SE_VTX_ST_NORM_0_Z 0x2318 -#define R200_SE_VTX_ST_PVMS 0x231c -#define R200_SE_VTX_ST_CLR_0_R 0x2320 -#define R200_SE_VTX_ST_CLR_0_G 0x2324 -#define R200_SE_VTX_ST_CLR_0_B 0x2328 -#define R200_SE_VTX_ST_CLR_0_A 0x232c -#define R200_SE_VTX_ST_CLR_1_R 0x2330 -#define R200_SE_VTX_ST_CLR_1_G 0x2334 -#define R200_SE_VTX_ST_CLR_1_B 0x2338 -#define R200_SE_VTX_ST_CLR_1_A 0x233c -#define R200_SE_VTX_ST_CLR_2_R 0x2340 -#define R200_SE_VTX_ST_CLR_2_G 0x2344 -#define R200_SE_VTX_ST_CLR_2_B 0x2348 -#define R200_SE_VTX_ST_CLR_2_A 0x234c -#define R200_SE_VTX_ST_CLR_3_R 0x2350 -#define R200_SE_VTX_ST_CLR_3_G 0x2354 -#define R200_SE_VTX_ST_CLR_3_B 0x2358 -#define R200_SE_VTX_ST_CLR_3_A 0x235c -#define R200_SE_VTX_ST_CLR_4_R 0x2360 -#define R200_SE_VTX_ST_CLR_4_G 0x2364 -#define R200_SE_VTX_ST_CLR_4_B 0x2368 -#define R200_SE_VTX_ST_CLR_4_A 0x236c -#define R200_SE_VTX_ST_CLR_5_R 0x2370 -#define R200_SE_VTX_ST_CLR_5_G 0x2374 -#define R200_SE_VTX_ST_CLR_5_B 0x2378 -#define R200_SE_VTX_ST_CLR_5_A 0x237c -#define R200_SE_VTX_ST_CLR_6_R 0x2380 -#define R200_SE_VTX_ST_CLR_6_G 0x2384 -#define R200_SE_VTX_ST_CLR_6_B 0x2388 -#define R200_SE_VTX_ST_CLR_6_A 0x238c -#define R200_SE_VTX_ST_CLR_7_R 0x2390 -#define R200_SE_VTX_ST_CLR_7_G 0x2394 -#define R200_SE_VTX_ST_CLR_7_B 0x2398 -#define R200_SE_VTX_ST_CLR_7_A 0x239c -#define R200_SE_VTX_ST_TEX_0_S 0x23a0 -#define R200_SE_VTX_ST_TEX_0_T 0x23a4 -#define R200_SE_VTX_ST_TEX_0_R 0x23a8 -#define R200_SE_VTX_ST_TEX_0_Q 0x23ac -#define R200_SE_VTX_ST_TEX_1_S 0x23b0 -#define R200_SE_VTX_ST_TEX_1_T 0x23b4 -#define R200_SE_VTX_ST_TEX_1_R 0x23b8 -#define R200_SE_VTX_ST_TEX_1_Q 0x23bc -#define R200_SE_VTX_ST_TEX_2_S 0x23c0 -#define R200_SE_VTX_ST_TEX_2_T 0x23c4 -#define R200_SE_VTX_ST_TEX_2_R 0x23c8 -#define R200_SE_VTX_ST_TEX_2_Q 0x23cc -#define R200_SE_VTX_ST_TEX_3_S 0x23d0 -#define R200_SE_VTX_ST_TEX_3_T 0x23d4 -#define R200_SE_VTX_ST_TEX_3_R 0x23d8 -#define R200_SE_VTX_ST_TEX_3_Q 0x23dc -#define R200_SE_VTX_ST_TEX_4_S 0x23e0 -#define R200_SE_VTX_ST_TEX_4_T 0x23e4 -#define R200_SE_VTX_ST_TEX_4_R 0x23e8 -#define R200_SE_VTX_ST_TEX_4_Q 0x23ec -#define R200_SE_VTX_ST_TEX_5_S 0x23f0 -#define R200_SE_VTX_ST_TEX_5_T 0x23f4 -#define R200_SE_VTX_ST_TEX_5_R 0x23f8 -#define R200_SE_VTX_ST_TEX_5_Q 0x23fc -#define R200_SE_VTX_ST_PNT_SPRT_SZ 0x2400 -#define R200_SE_VTX_ST_DISC_FOG 0x2404 -#define R200_SE_VTX_ST_SHININESS_0 0x2408 -#define R200_SE_VTX_ST_SHININESS_1 0x240c -#define R200_SE_VTX_ST_BLND_WT_0 0x2410 -#define R200_SE_VTX_ST_BLND_WT_1 0x2414 -#define R200_SE_VTX_ST_BLND_WT_2 0x2418 -#define R200_SE_VTX_ST_BLND_WT_3 0x241c -#define R200_SE_VTX_ST_POS_1_X 0x2420 -#define R200_SE_VTX_ST_POS_1_Y 0x2424 -#define R200_SE_VTX_ST_POS_1_Z 0x2428 -#define R200_SE_VTX_ST_POS_1_W 0x242c -#define R200_SE_VTX_ST_NORM_1_X 0x2430 -#define R200_SE_VTX_ST_NORM_1_Y 0x2434 -#define R200_SE_VTX_ST_NORM_1_Z 0x2438 -#define R200_SE_VTX_ST_USR_CLR_0_R 0x2440 -#define R200_SE_VTX_ST_USR_CLR_0_G 0x2444 -#define R200_SE_VTX_ST_USR_CLR_0_B 0x2448 -#define R200_SE_VTX_ST_USR_CLR_0_A 0x244c -#define R200_SE_VTX_ST_USR_CLR_1_R 0x2450 -#define R200_SE_VTX_ST_USR_CLR_1_G 0x2454 -#define R200_SE_VTX_ST_USR_CLR_1_B 0x2458 -#define R200_SE_VTX_ST_USR_CLR_1_A 0x245c -#define R200_SE_VTX_ST_CLR_0_PKD 0x2460 -#define R200_SE_VTX_ST_CLR_1_PKD 0x2464 -#define R200_SE_VTX_ST_CLR_2_PKD 0x2468 -#define R200_SE_VTX_ST_CLR_3_PKD 0x246c -#define R200_SE_VTX_ST_CLR_4_PKD 0x2470 -#define R200_SE_VTX_ST_CLR_5_PKD 0x2474 -#define R200_SE_VTX_ST_CLR_6_PKD 0x2478 -#define R200_SE_VTX_ST_CLR_7_PKD 0x247c -#define R200_SE_VTX_ST_POS_0_X_2 0x2480 -#define R200_SE_VTX_ST_POS_0_Y_2 0x2484 -#define R200_SE_VTX_ST_PAR_CLR_LD 0x2488 -#define R200_SE_VTX_ST_USR_CLR_PKD 0x248c -#define R200_SE_VTX_ST_POS_0_X_3 0x2490 -#define R200_SE_VTX_ST_POS_0_Y_3 0x2494 -#define R200_SE_VTX_ST_POS_0_Z_3 0x2498 -#define R200_SE_VTX_ST_END_OF_PKT 0x249c -/* gap */ -#define R200_RE_POINTSIZE 0x2648 -#define R200_POINTSIZE_SHIFT 0 -#define R200_MAXPOINTSIZE_SHIFT 16 -/* gap */ -#define R200_RE_TOP_LEFT 0x26c0 -#define R200_RE_LEFT_SHIFT 0 -#define R200_RE_TOP_SHIFT 16 -#define R200_RE_MISC 0x26c4 -#define R200_STIPPLE_COORD_MASK 0x1f -#define R200_STIPPLE_X_OFFSET_SHIFT 0 -#define R200_STIPPLE_X_OFFSET_MASK (0x1f << 0) -#define R200_STIPPLE_Y_OFFSET_SHIFT 8 -#define R200_STIPPLE_Y_OFFSET_MASK (0x1f << 8) -#define R200_STIPPLE_LITTLE_BIT_ORDER (0 << 16) -#define R200_STIPPLE_BIG_BIT_ORDER (1 << 16) -/* gap */ -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -#define R200_EXCLUSIVE_SCISSOR_0 0x01000000 -#define R200_EXCLUSIVE_SCISSOR_1 0x02000000 -#define R200_EXCLUSIVE_SCISSOR_2 0x04000000 -#define R200_SCISSOR_ENABLE_0 0x10000000 -#define R200_SCISSOR_ENABLE_1 0x20000000 -#define R200_SCISSOR_ENABLE_2 0x40000000 -/* gap */ -#define R200_PP_TXFILTER_0 0x2c00 -#define R200_MAG_FILTER_NEAREST (0 << 0) -#define R200_MAG_FILTER_LINEAR (1 << 0) -#define R200_MAG_FILTER_MASK (1 << 0) -#define R200_MIN_FILTER_NEAREST (0 << 1) -#define R200_MIN_FILTER_LINEAR (1 << 1) -#define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) -#define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) -#define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) -#define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) -#define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) -#define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) -#define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) -#define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) -#define R200_MIN_FILTER_MASK (15 << 1) -#define R200_MAX_ANISO_1_TO_1 (0 << 5) -#define R200_MAX_ANISO_2_TO_1 (1 << 5) -#define R200_MAX_ANISO_4_TO_1 (2 << 5) -#define R200_MAX_ANISO_8_TO_1 (3 << 5) -#define R200_MAX_ANISO_16_TO_1 (4 << 5) -#define R200_MAX_ANISO_MASK (7 << 5) -#define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) -#define R200_MAX_MIP_LEVEL_SHIFT 16 -#define R200_YUV_TO_RGB (1 << 20) -#define R200_YUV_TEMPERATURE_COOL (0 << 21) -#define R200_YUV_TEMPERATURE_HOT (1 << 21) -#define R200_YUV_TEMPERATURE_MASK (1 << 21) -#define R200_WRAPEN_S (1 << 22) -#define R200_CLAMP_S_WRAP (0 << 23) -#define R200_CLAMP_S_MIRROR (1 << 23) -#define R200_CLAMP_S_CLAMP_LAST (2 << 23) -#define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) -#define R200_CLAMP_S_CLAMP_BORDER (4 << 23) -#define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) -#define R200_CLAMP_S_CLAMP_GL (6 << 23) -#define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) -#define R200_CLAMP_S_MASK (7 << 23) -#define R200_WRAPEN_T (1 << 26) -#define R200_CLAMP_T_WRAP (0 << 27) -#define R200_CLAMP_T_MIRROR (1 << 27) -#define R200_CLAMP_T_CLAMP_LAST (2 << 27) -#define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) -#define R200_CLAMP_T_CLAMP_BORDER (4 << 27) -#define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) -#define R200_CLAMP_T_CLAMP_GL (6 << 27) -#define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) -#define R200_CLAMP_T_MASK (7 << 27) -#define R200_KILL_LT_ZERO (1 << 30) -#define R200_BORDER_MODE_OGL (0 << 31) -#define R200_BORDER_MODE_D3D (1 << 31) -#define R200_PP_TXFORMAT_0 0x2c04 -#define R200_TXFORMAT_I8 (0 << 0) -#define R200_TXFORMAT_AI88 (1 << 0) -#define R200_TXFORMAT_RGB332 (2 << 0) -#define R200_TXFORMAT_ARGB1555 (3 << 0) -#define R200_TXFORMAT_RGB565 (4 << 0) -#define R200_TXFORMAT_ARGB4444 (5 << 0) -#define R200_TXFORMAT_ARGB8888 (6 << 0) -#define R200_TXFORMAT_RGBA8888 (7 << 0) -#define R200_TXFORMAT_Y8 (8 << 0) -#define R200_TXFORMAT_AVYU4444 (9 << 0) -#define R200_TXFORMAT_VYUY422 (10 << 0) -#define R200_TXFORMAT_YVYU422 (11 << 0) -#define R200_TXFORMAT_DXT1 (12 << 0) -#define R200_TXFORMAT_DXT23 (14 << 0) -#define R200_TXFORMAT_DXT45 (15 << 0) -#define R200_TXFORMAT_FORMAT_MASK (31 << 0) -#define R200_TXFORMAT_FORMAT_SHIFT 0 -#define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) -#define R200_TXFORMAT_NON_POWER2 (1 << 7) -#define R200_TXFORMAT_WIDTH_MASK (15 << 8) -#define R200_TXFORMAT_WIDTH_SHIFT 8 -#define R200_TXFORMAT_HEIGHT_MASK (15 << 12) -#define R200_TXFORMAT_HEIGHT_SHIFT 12 -#define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ -#define R200_TXFORMAT_F5_WIDTH_SHIFT 16 -#define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) -#define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 -#define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) -#define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) -#define R200_TXFORMAT_ST_ROUTE_SHIFT 24 -#define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) -#define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) -#define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) -#define R200_PP_TXFORMAT_X_0 0x2c08 -#define R200_DEPTH_LOG2_MASK (0xf << 0) -#define R200_DEPTH_LOG2_SHIFT 0 -#define R200_VOLUME_FILTER_SHIFT 4 -#define R200_VOLUME_FILTER_MASK (1 << 4) -#define R200_VOLUME_FILTER_NEAREST (0 << 4) -#define R200_VOLUME_FILTER_LINEAR (1 << 4) -#define R200_WRAPEN_Q (1 << 8) -#define R200_CLAMP_Q_WRAP (0 << 9) -#define R200_CLAMP_Q_MIRROR (1 << 9) -#define R200_CLAMP_Q_CLAMP_LAST (2 << 9) -#define R200_CLAMP_Q_MIRROR_CLAMP_LAST (3 << 9) -#define R200_CLAMP_Q_CLAMP_BORDER (4 << 9) -#define R200_CLAMP_Q_MIRROR_CLAMP_BORDER (5 << 9) -#define R200_CLAMP_Q_CLAMP_GL (6 << 9) -#define R200_CLAMP_Q_MIRROR_CLAMP_GL (7 << 9) -#define R200_CLAMP_Q_MASK (7 << 9) -#define R200_MIN_MIP_LEVEL_MASK (0xff << 12) -#define R200_MIN_MIP_LEVEL_SHIFT 12 -#define R200_TEXCOORD_NONPROJ (0 << 16) -#define R200_TEXCOORD_CUBIC_ENV (1 << 16) -#define R200_TEXCOORD_VOLUME (2 << 16) -#define R200_TEXCOORD_PROJ (3 << 16) -#define R200_TEXCOORD_DEPTH (4 << 16) -#define R200_TEXCOORD_1D_PROJ (5 << 16) -#define R200_TEXCOORD_1D (6 << 16) -#define R200_TEXCOORD_ZERO (7 << 16) -#define R200_TEXCOORD_MASK (7 << 16) -#define R200_LOD_BIAS_MASK (0xfff80000) -#define R200_LOD_BIAS_SHIFT 19 -#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ -#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ -#define R200_PP_BORDER_COLOR_0 0x2c14 -#define R200_PP_CUBIC_FACES_0 0x2c18 -#define R200_FACE_WIDTH_1_SHIFT 0 -#define R200_FACE_HEIGHT_1_SHIFT 4 -#define R200_FACE_WIDTH_1_MASK (0xf << 0) -#define R200_FACE_HEIGHT_1_MASK (0xf << 4) -#define R200_FACE_WIDTH_2_SHIFT 8 -#define R200_FACE_HEIGHT_2_SHIFT 12 -#define R200_FACE_WIDTH_2_MASK (0xf << 8) -#define R200_FACE_HEIGHT_2_MASK (0xf << 12) -#define R200_FACE_WIDTH_3_SHIFT 16 -#define R200_FACE_HEIGHT_3_SHIFT 20 -#define R200_FACE_WIDTH_3_MASK (0xf << 16) -#define R200_FACE_HEIGHT_3_MASK (0xf << 20) -#define R200_FACE_WIDTH_4_SHIFT 24 -#define R200_FACE_HEIGHT_4_SHIFT 28 -#define R200_FACE_WIDTH_4_MASK (0xf << 24) -#define R200_FACE_HEIGHT_4_MASK (0xf << 28) -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFORMAT_1 0x2c24 -#define R200_PP_TXFORMAT_X_1 0x2c28 -#define R200_PP_TXSIZE_1 0x2c2c -#define R200_PP_TXPITCH_1 0x2c30 -#define R200_PP_BORDER_COLOR_1 0x2c34 -#define R200_PP_CUBIC_FACES_1 0x2c38 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFORMAT_2 0x2c44 -#define R200_PP_TXSIZE_2 0x2c4c -#define R200_PP_TXFORMAT_X_2 0x2c48 -#define R200_PP_TXPITCH_2 0x2c50 -#define R200_PP_BORDER_COLOR_2 0x2c54 -#define R200_PP_CUBIC_FACES_2 0x2c58 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFORMAT_3 0x2c64 -#define R200_PP_TXSIZE_3 0x2c6c -#define R200_PP_TXFORMAT_X_3 0x2c68 -#define R200_PP_TXPITCH_3 0x2c70 -#define R200_PP_BORDER_COLOR_3 0x2c74 -#define R200_PP_CUBIC_FACES_3 0x2c78 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFORMAT_4 0x2c84 -#define R200_PP_TXSIZE_4 0x2c8c -#define R200_PP_TXFORMAT_X_4 0x2c88 -#define R200_PP_TXPITCH_4 0x2c90 -#define R200_PP_BORDER_COLOR_4 0x2c94 -#define R200_PP_CUBIC_FACES_4 0x2c98 -#define R200_PP_TXFILTER_5 0x2ca0 -#define R200_PP_TXFORMAT_5 0x2ca4 -#define R200_PP_TXSIZE_5 0x2cac -#define R200_PP_TXFORMAT_X_5 0x2ca8 -#define R200_PP_TXPITCH_5 0x2cb0 -#define R200_PP_BORDER_COLOR_5 0x2cb4 -#define R200_PP_CUBIC_FACES_5 0x2cb8 -/* gap */ -#define R200_PP_CNTL_X 0x2cc4 -/* gap */ -#define R200_PP_TXOFFSET_0 0x2d00 -#define R200_TXO_ENDIAN_NO_SWAP (0 << 0) -#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) -#define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) -#define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -#define R200_TXO_OFFSET_MASK 0xffffffe0 -#define R200_TXO_OFFSET_SHIFT 5 -#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 -#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 -#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c -#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 -#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 -#define R200_PP_TXOFFSET_1 0x2d18 -#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c -#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 -#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 -#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 -#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c -#define R200_PP_TXOFFSET_2 0x2d30 -#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 -#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 -#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c -#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 -#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 -#define R200_PP_TXOFFSET_3 0x2d48 -#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c -#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 -#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 -#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 -#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c -#define R200_PP_TXOFFSET_4 0x2d60 -#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 -#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 -#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c -#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 -#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 -#define R200_PP_TXOFFSET_5 0x2d78 -#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c -#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 -#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 -#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 -#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c -/* gap */ -#define R200_PP_TAM_DEBUG3 0x2d9c -/* gap */ -#define R200_PP_TFACTOR_0 0x2ee0 -#define R200_PP_TFACTOR_1 0x2ee4 -#define R200_PP_TFACTOR_2 0x2ee8 -#define R200_PP_TFACTOR_3 0x2eec -#define R200_PP_TFACTOR_4 0x2ef0 -#define R200_PP_TFACTOR_5 0x2ef4 -/* gap */ -#define R200_PP_TXCBLEND_0 0x2f00 -#define R200_TXC_ARG_A_ZERO (0) -#define R200_TXC_ARG_A_CURRENT_COLOR (2) -#define R200_TXC_ARG_A_CURRENT_ALPHA (3) -#define R200_TXC_ARG_A_DIFFUSE_COLOR (4) -#define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) -#define R200_TXC_ARG_A_SPECULAR_COLOR (6) -#define R200_TXC_ARG_A_SPECULAR_ALPHA (7) -#define R200_TXC_ARG_A_TFACTOR_COLOR (8) -#define R200_TXC_ARG_A_TFACTOR_ALPHA (9) -#define R200_TXC_ARG_A_R0_COLOR (10) -#define R200_TXC_ARG_A_R0_ALPHA (11) -#define R200_TXC_ARG_A_R1_COLOR (12) -#define R200_TXC_ARG_A_R1_ALPHA (13) -#define R200_TXC_ARG_A_R2_COLOR (14) -#define R200_TXC_ARG_A_R2_ALPHA (15) -#define R200_TXC_ARG_A_R3_COLOR (16) -#define R200_TXC_ARG_A_R3_ALPHA (17) -#define R200_TXC_ARG_A_R4_COLOR (18) -#define R200_TXC_ARG_A_R4_ALPHA (19) -#define R200_TXC_ARG_A_R5_COLOR (20) -#define R200_TXC_ARG_A_R5_ALPHA (21) -#define R200_TXC_ARG_A_TFACTOR1_COLOR (26) -#define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) -#define R200_TXC_ARG_A_MASK (31 << 0) -#define R200_TXC_ARG_A_SHIFT 0 -#define R200_TXC_ARG_B_ZERO (0<<5) -#define R200_TXC_ARG_B_CURRENT_COLOR (2<<5) -#define R200_TXC_ARG_B_CURRENT_ALPHA (3<<5) -#define R200_TXC_ARG_B_DIFFUSE_COLOR (4<<5) -#define R200_TXC_ARG_B_DIFFUSE_ALPHA (5<<5) -#define R200_TXC_ARG_B_SPECULAR_COLOR (6<<5) -#define R200_TXC_ARG_B_SPECULAR_ALPHA (7<<5) -#define R200_TXC_ARG_B_TFACTOR_COLOR (8<<5) -#define R200_TXC_ARG_B_TFACTOR_ALPHA (9<<5) -#define R200_TXC_ARG_B_R0_COLOR (10<<5) -#define R200_TXC_ARG_B_R0_ALPHA (11<<5) -#define R200_TXC_ARG_B_R1_COLOR (12<<5) -#define R200_TXC_ARG_B_R1_ALPHA (13<<5) -#define R200_TXC_ARG_B_R2_COLOR (14<<5) -#define R200_TXC_ARG_B_R2_ALPHA (15<<5) -#define R200_TXC_ARG_B_R3_COLOR (16<<5) -#define R200_TXC_ARG_B_R3_ALPHA (17<<5) -#define R200_TXC_ARG_B_R4_COLOR (18<<5) -#define R200_TXC_ARG_B_R4_ALPHA (19<<5) -#define R200_TXC_ARG_B_R5_COLOR (20<<5) -#define R200_TXC_ARG_B_R5_ALPHA (21<<5) -#define R200_TXC_ARG_B_TFACTOR1_COLOR (26<<5) -#define R200_TXC_ARG_B_TFACTOR1_ALPHA (27<<5) -#define R200_TXC_ARG_B_MASK (31 << 5) -#define R200_TXC_ARG_B_SHIFT 5 -#define R200_TXC_ARG_C_ZERO (0<<10) -#define R200_TXC_ARG_C_CURRENT_COLOR (2<<10) -#define R200_TXC_ARG_C_CURRENT_ALPHA (3<<10) -#define R200_TXC_ARG_C_DIFFUSE_COLOR (4<<10) -#define R200_TXC_ARG_C_DIFFUSE_ALPHA (5<<10) -#define R200_TXC_ARG_C_SPECULAR_COLOR (6<<10) -#define R200_TXC_ARG_C_SPECULAR_ALPHA (7<<10) -#define R200_TXC_ARG_C_TFACTOR_COLOR (8<<10) -#define R200_TXC_ARG_C_TFACTOR_ALPHA (9<<10) -#define R200_TXC_ARG_C_R0_COLOR (10<<10) -#define R200_TXC_ARG_C_R0_ALPHA (11<<10) -#define R200_TXC_ARG_C_R1_COLOR (12<<10) -#define R200_TXC_ARG_C_R1_ALPHA (13<<10) -#define R200_TXC_ARG_C_R2_COLOR (14<<10) -#define R200_TXC_ARG_C_R2_ALPHA (15<<10) -#define R200_TXC_ARG_C_R3_COLOR (16<<10) -#define R200_TXC_ARG_C_R3_ALPHA (17<<10) -#define R200_TXC_ARG_C_R4_COLOR (18<<10) -#define R200_TXC_ARG_C_R4_ALPHA (19<<10) -#define R200_TXC_ARG_C_R5_COLOR (20<<10) -#define R200_TXC_ARG_C_R5_ALPHA (21<<10) -#define R200_TXC_ARG_C_TFACTOR1_COLOR (26<<10) -#define R200_TXC_ARG_C_TFACTOR1_ALPHA (27<<10) -#define R200_TXC_ARG_C_MASK (31 << 10) -#define R200_TXC_ARG_C_SHIFT 10 -#define R200_TXC_COMP_ARG_A (1 << 16) -#define R200_TXC_COMP_ARG_A_SHIFT (16) -#define R200_TXC_BIAS_ARG_A (1 << 17) -#define R200_TXC_SCALE_ARG_A (1 << 18) -#define R200_TXC_NEG_ARG_A (1 << 19) -#define R200_TXC_COMP_ARG_B (1 << 20) -#define R200_TXC_COMP_ARG_B_SHIFT (20) -#define R200_TXC_BIAS_ARG_B (1 << 21) -#define R200_TXC_SCALE_ARG_B (1 << 22) -#define R200_TXC_NEG_ARG_B (1 << 23) -#define R200_TXC_COMP_ARG_C (1 << 24) -#define R200_TXC_COMP_ARG_C_SHIFT (24) -#define R200_TXC_BIAS_ARG_C (1 << 25) -#define R200_TXC_SCALE_ARG_C (1 << 26) -#define R200_TXC_NEG_ARG_C (1 << 27) -#define R200_TXC_OP_MADD (0 << 28) -#define R200_TXC_OP_CND0 (2 << 28) -#define R200_TXC_OP_LERP (3 << 28) -#define R200_TXC_OP_DOT3 (4 << 28) -#define R200_TXC_OP_DOT4 (5 << 28) -#define R200_TXC_OP_CONDITIONAL (6 << 28) -#define R200_TXC_OP_DOT2_ADD (7 << 28) -#define R200_TXC_OP_MASK (7 << 28) -#define R200_PP_TXCBLEND2_0 0x2f04 -#define R200_TXC_TFACTOR_SEL_SHIFT 0 -#define R200_TXC_TFACTOR_SEL_MASK 0x7 -#define R200_TXC_TFACTOR1_SEL_SHIFT 4 -#define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) -#define R200_TXC_SCALE_SHIFT 8 -#define R200_TXC_SCALE_MASK (7 << 8) -#define R200_TXC_SCALE_1X (0 << 8) -#define R200_TXC_SCALE_2X (1 << 8) -#define R200_TXC_SCALE_4X (2 << 8) -#define R200_TXC_SCALE_8X (3 << 8) -#define R200_TXC_SCALE_INV2 (5 << 8) -#define R200_TXC_SCALE_INV4 (6 << 8) -#define R200_TXC_SCALE_INV8 (7 << 8) -#define R200_TXC_CLAMP_SHIFT 12 -#define R200_TXC_CLAMP_MASK (3 << 12) -#define R200_TXC_CLAMP_WRAP (0 << 12) -#define R200_TXC_CLAMP_0_1 (1 << 12) -#define R200_TXC_CLAMP_8_8 (2 << 12) -#define R200_TXC_OUTPUT_REG_MASK (7 << 16) -#define R200_TXC_OUTPUT_REG_NONE (0 << 16) -#define R200_TXC_OUTPUT_REG_R0 (1 << 16) -#define R200_TXC_OUTPUT_REG_R1 (2 << 16) -#define R200_TXC_OUTPUT_REG_R2 (3 << 16) -#define R200_TXC_OUTPUT_REG_R3 (4 << 16) -#define R200_TXC_OUTPUT_REG_R4 (5 << 16) -#define R200_TXC_OUTPUT_REG_R5 (6 << 16) -#define R200_TXC_OUTPUT_MASK_MASK (7 << 20) -#define R200_TXC_OUTPUT_MASK_RGB (0 << 20) -#define R200_TXC_OUTPUT_MASK_RG (1 << 20) -#define R200_TXC_OUTPUT_MASK_RB (2 << 20) -#define R200_TXC_OUTPUT_MASK_R (3 << 20) -#define R200_TXC_OUTPUT_MASK_GB (4 << 20) -#define R200_TXC_OUTPUT_MASK_G (5 << 20) -#define R200_TXC_OUTPUT_MASK_B (6 << 20) -#define R200_TXC_OUTPUT_MASK_NONE (7 << 20) -#define R200_TXC_REPL_NORMAL 0 -#define R200_TXC_REPL_RED 1 -#define R200_TXC_REPL_GREEN 2 -#define R200_TXC_REPL_BLUE 3 -#define R200_TXC_REPL_ARG_A_SHIFT 26 -#define R200_TXC_REPL_ARG_A_MASK (3 << 26) -#define R200_TXC_REPL_ARG_B_SHIFT 28 -#define R200_TXC_REPL_ARG_B_MASK (3 << 28) -#define R200_TXC_REPL_ARG_C_SHIFT 30 -#define R200_TXC_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXABLEND_0 0x2f08 -#define R200_TXA_ARG_A_ZERO (0) -#define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ -#define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ -#define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) -#define R200_TXA_ARG_A_DIFFUSE_BLUE (5) -#define R200_TXA_ARG_A_SPECULAR_ALPHA (6) -#define R200_TXA_ARG_A_SPECULAR_BLUE (7) -#define R200_TXA_ARG_A_TFACTOR_ALPHA (8) -#define R200_TXA_ARG_A_TFACTOR_BLUE (9) -#define R200_TXA_ARG_A_R0_ALPHA (10) -#define R200_TXA_ARG_A_R0_BLUE (11) -#define R200_TXA_ARG_A_R1_ALPHA (12) -#define R200_TXA_ARG_A_R1_BLUE (13) -#define R200_TXA_ARG_A_R2_ALPHA (14) -#define R200_TXA_ARG_A_R2_BLUE (15) -#define R200_TXA_ARG_A_R3_ALPHA (16) -#define R200_TXA_ARG_A_R3_BLUE (17) -#define R200_TXA_ARG_A_R4_ALPHA (18) -#define R200_TXA_ARG_A_R4_BLUE (19) -#define R200_TXA_ARG_A_R5_ALPHA (20) -#define R200_TXA_ARG_A_R5_BLUE (21) -#define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) -#define R200_TXA_ARG_A_TFACTOR1_BLUE (27) -#define R200_TXA_ARG_A_MASK (31 << 0) -#define R200_TXA_ARG_A_SHIFT 0 -#define R200_TXA_ARG_B_ZERO (0<<5) -#define R200_TXA_ARG_B_CURRENT_ALPHA (2<<5) /* guess */ -#define R200_TXA_ARG_B_CURRENT_BLUE (3<<5) /* guess */ -#define R200_TXA_ARG_B_DIFFUSE_ALPHA (4<<5) -#define R200_TXA_ARG_B_DIFFUSE_BLUE (5<<5) -#define R200_TXA_ARG_B_SPECULAR_ALPHA (6<<5) -#define R200_TXA_ARG_B_SPECULAR_BLUE (7<<5) -#define R200_TXA_ARG_B_TFACTOR_ALPHA (8<<5) -#define R200_TXA_ARG_B_TFACTOR_BLUE (9<<5) -#define R200_TXA_ARG_B_R0_ALPHA (10<<5) -#define R200_TXA_ARG_B_R0_BLUE (11<<5) -#define R200_TXA_ARG_B_R1_ALPHA (12<<5) -#define R200_TXA_ARG_B_R1_BLUE (13<<5) -#define R200_TXA_ARG_B_R2_ALPHA (14<<5) -#define R200_TXA_ARG_B_R2_BLUE (15<<5) -#define R200_TXA_ARG_B_R3_ALPHA (16<<5) -#define R200_TXA_ARG_B_R3_BLUE (17<<5) -#define R200_TXA_ARG_B_R4_ALPHA (18<<5) -#define R200_TXA_ARG_B_R4_BLUE (19<<5) -#define R200_TXA_ARG_B_R5_ALPHA (20<<5) -#define R200_TXA_ARG_B_R5_BLUE (21<<5) -#define R200_TXA_ARG_B_TFACTOR1_ALPHA (26<<5) -#define R200_TXA_ARG_B_TFACTOR1_BLUE (27<<5) -#define R200_TXA_ARG_B_MASK (31 << 5) -#define R200_TXA_ARG_B_SHIFT 5 -#define R200_TXA_ARG_C_ZERO (0<<10) -#define R200_TXA_ARG_C_CURRENT_ALPHA (2<<10) /* guess */ -#define R200_TXA_ARG_C_CURRENT_BLUE (3<<10) /* guess */ -#define R200_TXA_ARG_C_DIFFUSE_ALPHA (4<<10) -#define R200_TXA_ARG_C_DIFFUSE_BLUE (5<<10) -#define R200_TXA_ARG_C_SPECULAR_ALPHA (6<<10) -#define R200_TXA_ARG_C_SPECULAR_BLUE (7<<10) -#define R200_TXA_ARG_C_TFACTOR_ALPHA (8<<10) -#define R200_TXA_ARG_C_TFACTOR_BLUE (9<<10) -#define R200_TXA_ARG_C_R0_ALPHA (10<<10) -#define R200_TXA_ARG_C_R0_BLUE (11<<10) -#define R200_TXA_ARG_C_R1_ALPHA (12<<10) -#define R200_TXA_ARG_C_R1_BLUE (13<<10) -#define R200_TXA_ARG_C_R2_ALPHA (14<<10) -#define R200_TXA_ARG_C_R2_BLUE (15<<10) -#define R200_TXA_ARG_C_R3_ALPHA (16<<10) -#define R200_TXA_ARG_C_R3_BLUE (17<<10) -#define R200_TXA_ARG_C_R4_ALPHA (18<<10) -#define R200_TXA_ARG_C_R4_BLUE (19<<10) -#define R200_TXA_ARG_C_R5_ALPHA (20<<10) -#define R200_TXA_ARG_C_R5_BLUE (21<<10) -#define R200_TXA_ARG_C_TFACTOR1_ALPHA (26<<10) -#define R200_TXA_ARG_C_TFACTOR1_BLUE (27<<10) -#define R200_TXA_ARG_C_MASK (31 << 10) -#define R200_TXA_ARG_C_SHIFT 10 -#define R200_TXA_COMP_ARG_A (1 << 16) -#define R200_TXA_COMP_ARG_A_SHIFT (16) -#define R200_TXA_BIAS_ARG_A (1 << 17) -#define R200_TXA_SCALE_ARG_A (1 << 18) -#define R200_TXA_NEG_ARG_A (1 << 19) -#define R200_TXA_COMP_ARG_B (1 << 20) -#define R200_TXA_COMP_ARG_B_SHIFT (20) -#define R200_TXA_BIAS_ARG_B (1 << 21) -#define R200_TXA_SCALE_ARG_B (1 << 22) -#define R200_TXA_NEG_ARG_B (1 << 23) -#define R200_TXA_COMP_ARG_C (1 << 24) -#define R200_TXA_COMP_ARG_C_SHIFT (24) -#define R200_TXA_BIAS_ARG_C (1 << 25) -#define R200_TXA_SCALE_ARG_C (1 << 26) -#define R200_TXA_NEG_ARG_C (1 << 27) -#define R200_TXA_OP_MADD (0 << 28) -#define R200_TXA_OP_CND0 (2 << 28) -#define R200_TXA_OP_LERP (3 << 28) -#define R200_TXA_OP_CONDITIONAL (6 << 28) -#define R200_TXA_OP_MASK (7 << 28) -#define R200_PP_TXABLEND2_0 0x2f0c -#define R200_TXA_TFACTOR_SEL_SHIFT 0 -#define R200_TXA_TFACTOR_SEL_MASK 0x7 -#define R200_TXA_TFACTOR1_SEL_SHIFT 4 -#define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) -#define R200_TXA_SCALE_SHIFT 8 -#define R200_TXA_SCALE_MASK (7 << 8) -#define R200_TXA_SCALE_1X (0 << 8) -#define R200_TXA_SCALE_2X (1 << 8) -#define R200_TXA_SCALE_4X (2 << 8) -#define R200_TXA_SCALE_8X (3 << 8) -#define R200_TXA_SCALE_INV2 (5 << 8) -#define R200_TXA_SCALE_INV4 (6 << 8) -#define R200_TXA_SCALE_INV8 (7 << 8) -#define R200_TXA_CLAMP_SHIFT 12 -#define R200_TXA_CLAMP_MASK (3 << 12) -#define R200_TXA_CLAMP_WRAP (0 << 12) -#define R200_TXA_CLAMP_0_1 (1 << 12) -#define R200_TXA_CLAMP_8_8 (2 << 12) -#define R200_TXA_OUTPUT_REG_MASK (7 << 16) -#define R200_TXA_OUTPUT_REG_NONE (0 << 16) -#define R200_TXA_OUTPUT_REG_R0 (1 << 16) -#define R200_TXA_OUTPUT_REG_R1 (2 << 16) -#define R200_TXA_OUTPUT_REG_R2 (3 << 16) -#define R200_TXA_OUTPUT_REG_R3 (4 << 16) -#define R200_TXA_OUTPUT_REG_R4 (5 << 16) -#define R200_TXA_OUTPUT_REG_R5 (6 << 16) -#define R200_TXA_DOT_ALPHA (1 << 20) -#define R200_TXA_REPL_NORMAL 0 -#define R200_TXA_REPL_RED 1 -#define R200_TXA_REPL_GREEN 2 -#define R200_TXA_REPL_ARG_A_SHIFT 26 -#define R200_TXA_REPL_ARG_A_MASK (3 << 26) -#define R200_TXA_REPL_ARG_B_SHIFT 28 -#define R200_TXA_REPL_ARG_B_MASK (3 << 28) -#define R200_TXA_REPL_ARG_C_SHIFT 30 -#define R200_TXA_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXCBLEND_1 0x2f10 -#define R200_PP_TXCBLEND2_1 0x2f14 -#define R200_PP_TXABLEND_1 0x2f18 -#define R200_PP_TXABLEND2_1 0x2f1c -#define R200_PP_TXCBLEND_2 0x2f20 -#define R200_PP_TXCBLEND2_2 0x2f24 -#define R200_PP_TXABLEND_2 0x2f28 -#define R200_PP_TXABLEND2_2 0x2f2c -#define R200_PP_TXCBLEND_3 0x2f30 -#define R200_PP_TXCBLEND2_3 0x2f34 -#define R200_PP_TXABLEND_3 0x2f38 -#define R200_PP_TXABLEND2_3 0x2f3c -#define R200_PP_TXCBLEND_4 0x2f40 -#define R200_PP_TXCBLEND2_4 0x2f44 -#define R200_PP_TXABLEND_4 0x2f48 -#define R200_PP_TXABLEND2_4 0x2f4c -#define R200_PP_TXCBLEND_5 0x2f50 -#define R200_PP_TXCBLEND2_5 0x2f54 -#define R200_PP_TXABLEND_5 0x2f58 -#define R200_PP_TXABLEND2_5 0x2f5c -#define R200_PP_TXCBLEND_6 0x2f60 -#define R200_PP_TXCBLEND2_6 0x2f64 -#define R200_PP_TXABLEND_6 0x2f68 -#define R200_PP_TXABLEND2_6 0x2f6c -#define R200_PP_TXCBLEND_7 0x2f70 -#define R200_PP_TXCBLEND2_7 0x2f74 -#define R200_PP_TXABLEND_7 0x2f78 -#define R200_PP_TXABLEND2_7 0x2f7c -/* gap */ -#define R200_RB3D_BLENDCOLOR 0x3218 /* ARGB 8888 */ -#define R200_RB3D_ABLENDCNTL 0x321C /* see BLENDCTL */ -#define R200_RB3D_CBLENDCNTL 0x3220 /* see BLENDCTL */ - -/* - * Offsets in TCL vector state. NOTE: Hardwiring matrix positions. - * Multiple contexts could collaberate to eliminate state bouncing. - */ -#define R200_VS_LIGHT_AMBIENT_ADDR 0x00000028 -#define R200_VS_LIGHT_DIFFUSE_ADDR 0x00000030 -#define R200_VS_LIGHT_SPECULAR_ADDR 0x00000038 -#define R200_VS_LIGHT_DIRPOS_ADDR 0x00000040 -#define R200_VS_LIGHT_HWVSPOT_ADDR 0x00000048 -#define R200_VS_LIGHT_ATTENUATION_ADDR 0x00000050 -#define R200_VS_SPOT_DUAL_CONE 0x00000058 -#define R200_VS_GLOBAL_AMBIENT_ADDR 0x0000005C -#define R200_VS_FOG_PARAM_ADDR 0x0000005D -#define R200_VS_EYE_VECTOR_ADDR 0x0000005E -#define R200_VS_UCP_ADDR 0x00000060 -#define R200_VS_PNT_SPRITE_VPORT_SCALE 0x00000068 -#define R200_VS_MATRIX_0_MV 0x00000080 -#define R200_VS_MATRIX_1_INV_MV 0x00000084 -#define R200_VS_MATRIX_2_MVP 0x00000088 -#define R200_VS_MATRIX_3_TEX0 0x0000008C -#define R200_VS_MATRIX_4_TEX1 0x00000090 -#define R200_VS_MATRIX_5_TEX2 0x00000094 -#define R200_VS_MATRIX_6_TEX3 0x00000098 -#define R200_VS_MATRIX_7_TEX4 0x0000009C -#define R200_VS_MATRIX_8_TEX5 0x000000A0 -#define R200_VS_MAT_0_EMISS 0x000000B0 -#define R200_VS_MAT_0_AMB 0x000000B1 -#define R200_VS_MAT_0_DIF 0x000000B2 -#define R200_VS_MAT_0_SPEC 0x000000B3 -#define R200_VS_MAT_1_EMISS 0x000000B4 -#define R200_VS_MAT_1_AMB 0x000000B5 -#define R200_VS_MAT_1_DIF 0x000000B6 -#define R200_VS_MAT_1_SPEC 0x000000B7 -#define R200_VS_EYE2CLIP_MTX 0x000000B8 -#define R200_VS_PNT_SPRITE_ATT_CONST 0x000000BC -#define R200_VS_PNT_SPRITE_EYE_IN_MODEL 0x000000BD -#define R200_VS_PNT_SPRITE_CLAMP 0x000000BE -#define R200_VS_MAX 0x000001C0 - -/* - * Offsets in TCL scalar state - */ -#define R200_SS_LIGHT_DCD_ADDR 0x00000000 -#define R200_SS_LIGHT_DCM_ADDR 0x00000008 -#define R200_SS_LIGHT_SPOT_EXPONENT_ADDR 0x00000010 -#define R200_SS_LIGHT_SPOT_CUTOFF_ADDR 0x00000018 -#define R200_SS_LIGHT_SPECULAR_THRESH_ADDR 0x00000020 -#define R200_SS_LIGHT_RANGE_CUTOFF_SQRD 0x00000028 -#define R200_SS_LIGHT_RANGE_ATT_CONST 0x00000030 -#define R200_SS_VERT_GUARD_CLIP_ADJ_ADDR 0x00000080 -#define R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR 0x00000081 -#define R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR 0x00000082 -#define R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 0x00000083 -#define R200_SS_MAT_0_SHININESS 0x00000100 -#define R200_SS_MAT_1_SHININESS 0x00000101 - -/* - * Matrix indices - */ -#define R200_MTX_MV 0 -#define R200_MTX_IMV 1 -#define R200_MTX_MVP 2 -#define R200_MTX_TEX0 3 -#define R200_MTX_TEX1 4 -#define R200_MTX_TEX2 5 -#define R200_MTX_TEX3 6 -#define R200_MTX_TEX4 7 -#define R200_MTX_TEX5 8 - -/* Color formats for 2d packets - */ -#define R200_CP_COLOR_FORMAT_CI8 2 -#define R200_CP_COLOR_FORMAT_ARGB1555 3 -#define R200_CP_COLOR_FORMAT_RGB565 4 -#define R200_CP_COLOR_FORMAT_ARGB8888 6 -#define R200_CP_COLOR_FORMAT_RGB332 7 -#define R200_CP_COLOR_FORMAT_RGB8 9 -#define R200_CP_COLOR_FORMAT_ARGB4444 15 - -/* - * CP type-3 packets - */ -#define R200_CP_CMD_NOP 0xC0001000 -#define R200_CP_CMD_NEXT_CHAR 0xC0001900 -#define R200_CP_CMD_PLY_NEXTSCAN 0xC0001D00 -#define R200_CP_CMD_SET_SCISSORS 0xC0001E00 -#define R200_CP_CMD_LOAD_MICROCODE 0xC0002400 -#define R200_CP_CMD_WAIT_FOR_IDLE 0xC0002600 -#define R200_CP_CMD_3D_DRAW_VBUF 0xC0002800 -#define R200_CP_CMD_3D_DRAW_IMMD 0xC0002900 -#define R200_CP_CMD_3D_DRAW_INDX 0xC0002A00 -#define R200_CP_CMD_LOAD_PALETTE 0xC0002C00 -#define R200_CP_CMD_3D_LOAD_VBPNTR 0xC0002F00 -#define R200_CP_CMD_INDX_BUFFER 0xC0003300 -#define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400 -#define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500 -#define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600 -#define R200_CP_CMD_PAINT 0xC0009100 -#define R200_CP_CMD_BITBLT 0xC0009200 -#define R200_CP_CMD_SMALLTEXT 0xC0009300 -#define R200_CP_CMD_HOSTDATA_BLT 0xC0009400 -#define R200_CP_CMD_POLYLINE 0xC0009500 -#define R200_CP_CMD_POLYSCANLINES 0xC0009800 -#define R200_CP_CMD_PAINT_MULTI 0xC0009A00 -#define R200_CP_CMD_BITBLT_MULTI 0xC0009B00 -#define R200_CP_CMD_TRANS_BITBLT 0xC0009C00 - -#endif diff --git a/src/mesa/drivers/dri/r300/r200_state.h b/src/mesa/drivers/dri/r300/r200_state.h deleted file mode 100644 index 3e1a9c8ba1..0000000000 --- a/src/mesa/drivers/dri/r300/r200_state.h +++ /dev/null @@ -1,58 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keith@tungstengraphics.com> - */ - -#ifndef __R200_STATE_H__ -#define __R200_STATE_H__ - -#ifdef GLX_DIRECT_RENDERING - -#include "r200_context.h" - -extern void r200InitState(r200ContextPtr rmesa); -extern void r200InitStateFuncs(struct dd_function_table *functions); -extern void r200InitTnlFuncs(GLcontext * ctx); - -extern void r200UpdateMaterial(GLcontext * ctx); - -extern void r200UpdateViewportOffset(GLcontext * ctx); -extern void r200UpdateWindow(GLcontext * ctx); - -extern void r200ValidateState(GLcontext * ctx); - -extern void r200PrintDirty(r200ContextPtr rmesa, const char *msg); - -extern void r200LightingSpaceChange(GLcontext * ctx); - -#endif -#endif diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 54eb081d05..d10a9d87d3 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -44,7 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" -#include "array_cache/acache.h" +#include "vbo/vbo.h" #include "tnl/tnl.h" #include "tnl/t_pipeline.h" @@ -73,6 +73,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. int future_hw_tcl_on=1; int hw_tcl_on=1; +#define need_GL_EXT_stencil_two_side #define need_GL_ARB_multisample #define need_GL_ARB_texture_compression #define need_GL_ARB_vertex_buffer_object @@ -126,6 +127,10 @@ const struct dri_extension card_extensions[] = { {NULL, NULL} }; +const struct dri_extension stencil_two_side[] = { + {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions}, +}; + extern struct tnl_pipeline_stage _r300_render_stage; extern const struct tnl_pipeline_stage _r300_tcl_stage; extern const struct tnl_pipeline_stage _r300_texrect_stage; @@ -195,6 +200,8 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, */ driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r300"); + r300->initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, + "def_max_anisotropy"); //r300->texmicrotile = GL_TRUE; @@ -287,7 +294,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, /* Initialize the software rasterizer and helper modules. */ _swrast_CreateContext(ctx); - _ac_CreateContext(ctx); + _vbo_CreateContext(ctx); _tnl_CreateContext(ctx); _swsetup_CreateContext(ctx); _swsetup_Wakeup(ctx); @@ -300,7 +307,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, /* Try and keep materials and vertices separate: */ - _tnl_isolate_materials(ctx, GL_TRUE); +/* _tnl_isolate_materials(ctx, GL_TRUE); */ /* Configure swrast and TNL to match hardware characteristics: */ @@ -331,6 +338,9 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, driInitExtensions(ctx, card_extensions, GL_TRUE); + if (driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side") == 0) + driInitSingleExtension(ctx, stencil_two_side); + if (r300->radeon.glCtx->Mesa_DXTn && !driQueryOptionb (&r300->radeon.optionCache, "disable_s3tc")) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); _mesa_enable_extension( ctx, "GL_S3_s3tc" ); @@ -478,7 +488,7 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) _swsetup_DestroyContext(r300->radeon.glCtx); _tnl_ProgramCacheDestroy(r300->radeon.glCtx); _tnl_DestroyContext(r300->radeon.glCtx); - _ac_DestroyContext(r300->radeon.glCtx); + _vbo_DestroyContext(r300->radeon.glCtx); _swrast_DestroyContext(r300->radeon.glCtx); if (r300->dma.current.buf) { diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index dd3ecbb235..48b50bca65 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -48,7 +48,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" #define USER_BUFFERS -#define RADEON_VTXFMT_A +/* KW: Disable this code. Driver should hook into vbo module + * directly, see i965 driver for example. + */ +/* #define RADEON_VTXFMT_A */ #define HW_VBOS /* We don't handle 16 bits elts swapping yet */ @@ -726,6 +729,11 @@ struct r300_fragment_program { GLboolean params_uptodate; int max_temp_idx; + + /* the index of the sin constant is stored here */ + GLint const_sin[2]; + + GLuint optimization; }; #define R300_MAX_AOS_ARRAYS 16 @@ -754,7 +762,7 @@ struct radeon_vertex_buffer { struct dt AttribPtr[VERT_ATTRIB_MAX]; - struct tnl_prim *Primitive; + const struct _mesa_prim *Primitive; GLuint PrimitiveCount; GLint LockFirst; GLsizei LockCount; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 32c0128eaa..8e45bd5403 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -33,7 +33,6 @@ /*TODO'S * - * - COS/SIN/SCS instructions * - Depth write, WPOS/FOGC inputs * - FogOption * - Verify results of opcodes for accuracy, I've only checked them @@ -51,18 +50,110 @@ #include "r300_fragprog.h" #include "r300_reg.h" +/* + * Usefull macros and values + */ +#define ERROR(fmt, args...) do { \ + fprintf(stderr, "%s::%s(): " fmt "\n", \ + __FILE__, __func__, ##args); \ + rp->error = GL_TRUE; \ + } while(0) + #define PFS_INVAL 0xFFFFFFFF #define COMPILE_STATE struct r300_pfs_compile_state *cs = rp->cs -static void dump_program(struct r300_fragment_program *rp); -static void emit_arith(struct r300_fragment_program *rp, int op, - pfs_reg_t dest, int mask, - pfs_reg_t src0, pfs_reg_t src1, pfs_reg_t src2, - int flags); +#define SWIZZLE_XYZ 0 +#define SWIZZLE_XXX 1 +#define SWIZZLE_YYY 2 +#define SWIZZLE_ZZZ 3 +#define SWIZZLE_WWW 4 +#define SWIZZLE_YZX 5 +#define SWIZZLE_ZXY 6 +#define SWIZZLE_WZY 7 +#define SWIZZLE_111 8 +#define SWIZZLE_000 9 +#define SWIZZLE_HHH 10 + +#define swizzle(r, x, y, z, w) do_swizzle(rp, r, \ + ((SWIZZLE_##x<<0)| \ + (SWIZZLE_##y<<3)| \ + (SWIZZLE_##z<<6)| \ + (SWIZZLE_##w<<9)), \ + 0) + +#define REG_TYPE_INPUT 0 +#define REG_TYPE_OUTPUT 1 +#define REG_TYPE_TEMP 2 +#define REG_TYPE_CONST 3 + +#define REG_TYPE_SHIFT 0 +#define REG_INDEX_SHIFT 2 +#define REG_VSWZ_SHIFT 8 +#define REG_SSWZ_SHIFT 13 +#define REG_NEGV_SHIFT 18 +#define REG_NEGS_SHIFT 19 +#define REG_ABS_SHIFT 20 +#define REG_NO_USE_SHIFT 21 +#define REG_VALID_SHIFT 22 + +#define REG_TYPE_MASK (0x03 << REG_TYPE_SHIFT) +#define REG_INDEX_MASK (0x3F << REG_INDEX_SHIFT) +#define REG_VSWZ_MASK (0x1F << REG_VSWZ_SHIFT) +#define REG_SSWZ_MASK (0x1F << REG_SSWZ_SHIFT) +#define REG_NEGV_MASK (0x01 << REG_NEGV_SHIFT) +#define REG_NEGS_MASK (0x01 << REG_NEGS_SHIFT) +#define REG_ABS_MASK (0x01 << REG_ABS_SHIFT) +#define REG_NO_USE_MASK (0x01 << REG_NO_USE_SHIFT) +#define REG_VALID_MASK (0x01 << REG_VALID_SHIFT) + +#define REG(type, index, vswz, sswz, nouse, valid) \ + (((type << REG_TYPE_SHIFT) & REG_TYPE_MASK) | \ + ((index << REG_INDEX_SHIFT) & REG_INDEX_MASK) | \ + ((nouse << REG_NO_USE_SHIFT) & REG_NO_USE_MASK) | \ + ((valid << REG_VALID_SHIFT) & REG_VALID_MASK) | \ + ((vswz << REG_VSWZ_SHIFT) & REG_VSWZ_MASK) | \ + ((sswz << REG_SSWZ_SHIFT) & REG_SSWZ_MASK)) +#define REG_GET_TYPE(reg) \ + ((reg & REG_TYPE_MASK) >> REG_TYPE_SHIFT) +#define REG_GET_INDEX(reg) \ + ((reg & REG_INDEX_MASK) >> REG_INDEX_SHIFT) +#define REG_GET_VSWZ(reg) \ + ((reg & REG_VSWZ_MASK) >> REG_VSWZ_SHIFT) +#define REG_GET_SSWZ(reg) \ + ((reg & REG_SSWZ_MASK) >> REG_SSWZ_SHIFT) +#define REG_GET_NO_USE(reg) \ + ((reg & REG_NO_USE_MASK) >> REG_NO_USE_SHIFT) +#define REG_GET_VALID(reg) \ + ((reg & REG_VALID_MASK) >> REG_VALID_SHIFT) +#define REG_SET_TYPE(reg, type) \ + reg = ((reg & ~REG_TYPE_MASK) | \ + ((type << REG_TYPE_SHIFT) & REG_TYPE_MASK)) +#define REG_SET_INDEX(reg, index) \ + reg = ((reg & ~REG_INDEX_MASK) | \ + ((index << REG_INDEX_SHIFT) & REG_INDEX_MASK)) +#define REG_SET_VSWZ(reg, vswz) \ + reg = ((reg & ~REG_VSWZ_MASK) | \ + ((vswz << REG_VSWZ_SHIFT) & REG_VSWZ_MASK)) +#define REG_SET_SSWZ(reg, sswz) \ + reg = ((reg & ~REG_SSWZ_MASK) | \ + ((sswz << REG_SSWZ_SHIFT) & REG_SSWZ_MASK)) +#define REG_SET_NO_USE(reg, nouse) \ + reg = ((reg & ~REG_NO_USE_MASK) | \ + ((nouse << REG_NO_USE_SHIFT) & REG_NO_USE_MASK)) +#define REG_SET_VALID(reg, valid) \ + reg = ((reg & ~REG_VALID_MASK) | \ + ((valid << REG_VALID_SHIFT) & REG_VALID_MASK)) +#define REG_ABS(reg) \ + reg = (reg | REG_ABS_MASK) +#define REG_NEGV(reg) \ + reg = (reg | REG_NEGV_MASK) +#define REG_NEGS(reg) \ + reg = (reg | REG_NEGS_MASK) -/*************************************** - * begin: useful data structions for fragment program generation - ***************************************/ + +/* + * Datas structures for fragment program generation + */ /* description of r300 native hw instructions */ static const struct { @@ -86,20 +177,23 @@ static const struct { { "CMPH", 3, R300_FPI0_OUTC_CMPH, PFS_INVAL }, }; -#define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, \ - SWIZZLE_##y, \ - SWIZZLE_##z, \ - SWIZZLE_ZERO)) - -#define SLOT_VECTOR (1<<0) -#define SLOT_SCALAR (1<<3) -#define SLOT_BOTH (SLOT_VECTOR|SLOT_SCALAR) /* vector swizzles r300 can support natively, with a couple of * cases we handle specially * - * pfs_reg_t.v_swz/pfs_reg_t.s_swz is an index into this table - **/ + * REG_VSWZ/REG_SSWZ is an index into this table + */ +#define SLOT_VECTOR (1<<0) +#define SLOT_SCALAR (1<<3) +#define SLOT_BOTH (SLOT_VECTOR | SLOT_SCALAR) + +/* mapping from SWIZZLE_* to r300 native values for scalar insns */ +#define SWIZZLE_HALF 6 + +#define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, \ + SWIZZLE_##y, \ + SWIZZLE_##z, \ + SWIZZLE_ZERO)) static const struct r300_pfs_swizzle { GLuint hash; /* swizzle value this matches */ GLuint base; /* base value for hw swizzle */ @@ -117,42 +211,30 @@ static const struct r300_pfs_swizzle { { MAKE_SWZ3(W, Z, Y), R300_FPI0_ARGC_SRC0CA_WZY, 1, SLOT_BOTH }, { MAKE_SWZ3(ONE, ONE, ONE), R300_FPI0_ARGC_ONE, 0, 0}, { MAKE_SWZ3(ZERO, ZERO, ZERO), R300_FPI0_ARGC_ZERO, 0, 0}, - { PFS_INVAL, R300_FPI0_ARGC_HALF, 0, 0}, + { MAKE_SWZ3(HALF, HALF, HALF), R300_FPI0_ARGC_HALF, 0, 0}, { PFS_INVAL, 0, 0, 0}, }; -#define SWIZZLE_XYZ 0 -#define SWIZZLE_XXX 1 -#define SWIZZLE_YYY 2 -#define SWIZZLE_ZZZ 3 -#define SWIZZLE_WWW 4 -#define SWIZZLE_YZX 5 -#define SWIZZLE_ZXY 6 -#define SWIZZLE_WZY 7 -#define SWIZZLE_111 8 -#define SWIZZLE_000 9 -#define SWIZZLE_HHH 10 +/* used during matching of non-native swizzles */ #define SWZ_X_MASK (7 << 0) #define SWZ_Y_MASK (7 << 3) #define SWZ_Z_MASK (7 << 6) #define SWZ_W_MASK (7 << 9) -/* used during matching of non-native swizzles */ static const struct { - GLuint hash; /* used to mask matching swizzle components */ + GLuint hash; /* used to mask matching swizzle components */ int mask; /* actual outmask */ int count; /* count of components matched */ } s_mask[] = { - { SWZ_X_MASK|SWZ_Y_MASK|SWZ_Z_MASK, 1|2|4, 3}, - { SWZ_X_MASK|SWZ_Y_MASK, 1|2, 2}, - { SWZ_X_MASK|SWZ_Z_MASK, 1|4, 2}, - { SWZ_Y_MASK|SWZ_Z_MASK, 2|4, 2}, - { SWZ_X_MASK, 1, 1}, - { SWZ_Y_MASK, 2, 1}, - { SWZ_Z_MASK, 4, 1}, - { PFS_INVAL, PFS_INVAL, PFS_INVAL} + { SWZ_X_MASK|SWZ_Y_MASK|SWZ_Z_MASK, 1|2|4, 3}, + { SWZ_X_MASK|SWZ_Y_MASK, 1|2, 2}, + { SWZ_X_MASK|SWZ_Z_MASK, 1|4, 2}, + { SWZ_Y_MASK|SWZ_Z_MASK, 2|4, 2}, + { SWZ_X_MASK, 1, 1}, + { SWZ_Y_MASK, 2, 1}, + { SWZ_Z_MASK, 4, 1}, + { PFS_INVAL, PFS_INVAL, PFS_INVAL} }; -/* mapping from SWIZZLE_* to r300 native values for scalar insns */ static const struct { int base; /* hw value of swizzle */ int stride; /* difference between SRC0/1/2 */ @@ -166,58 +248,51 @@ static const struct { { R300_FPI2_ARGA_ONE , 0, 0 }, { R300_FPI2_ARGA_HALF , 0, 0 } }; -#define SWIZZLE_HALF 6 /* boiler-plate reg, for convenience */ -static const pfs_reg_t undef = { - type: REG_TYPE_TEMP, - index: 0, - v_swz: SWIZZLE_XYZ, - s_swz: SWIZZLE_W, - negate_v: 0, - negate_s: 0, - absolute: 0, - no_use: GL_FALSE, - valid: GL_FALSE -}; +static const GLuint undef = REG(REG_TYPE_TEMP, + 0, + SWIZZLE_XYZ, + SWIZZLE_W, + GL_FALSE, + GL_FALSE); /* constant one source */ -static const pfs_reg_t pfs_one = { - type: REG_TYPE_CONST, - index: 0, - v_swz: SWIZZLE_111, - s_swz: SWIZZLE_ONE, - valid: GL_TRUE -}; +static const GLuint pfs_one = REG(REG_TYPE_CONST, + 0, + SWIZZLE_111, + SWIZZLE_ONE, + GL_FALSE, + GL_TRUE); /* constant half source */ -static const pfs_reg_t pfs_half = { - type: REG_TYPE_CONST, - index: 0, - v_swz: SWIZZLE_HHH, - s_swz: SWIZZLE_HALF, - valid: GL_TRUE -}; +static const GLuint pfs_half = REG(REG_TYPE_CONST, + 0, + SWIZZLE_HHH, + SWIZZLE_HALF, + GL_FALSE, + GL_TRUE); /* constant zero source */ -static const pfs_reg_t pfs_zero = { - type: REG_TYPE_CONST, - index: 0, - v_swz: SWIZZLE_000, - s_swz: SWIZZLE_ZERO, - valid: GL_TRUE -}; - -/*************************************** - * end: data structures - ***************************************/ +static const GLuint pfs_zero = REG(REG_TYPE_CONST, + 0, + SWIZZLE_000, + SWIZZLE_ZERO, + GL_FALSE, + GL_TRUE); -#define ERROR(fmt, args...) do { \ - fprintf(stderr, "%s::%s(): " fmt "\n",\ - __FILE__, __func__, ##args); \ - rp->error = GL_TRUE; \ -} while(0) +/* + * Common functions prototypes + */ +static void dump_program(struct r300_fragment_program *rp); +static void emit_arith(struct r300_fragment_program *rp, int op, + GLuint dest, int mask, + GLuint src0, GLuint src1, GLuint src2, + int flags); +/* + * Helper functions prototypes + */ static int get_hw_temp(struct r300_fragment_program *rp) { COMPILE_STATE; @@ -256,263 +331,360 @@ static void free_hw_temp(struct r300_fragment_program *rp, int idx) cs->hwreg_in_use &= ~(1<<idx); } -static pfs_reg_t get_temp_reg(struct r300_fragment_program *rp) +static GLuint get_temp_reg(struct r300_fragment_program *rp) { COMPILE_STATE; - pfs_reg_t r = undef; + GLuint r = undef; + GLuint index; - r.index = ffs(~cs->temp_in_use); - if (!r.index) { + index = ffs(~cs->temp_in_use); + if (!index) { ERROR("Out of program temps\n"); return r; } - cs->temp_in_use |= (1 << --r.index); - - cs->temps[r.index].refcount = 0xFFFFFFFF; - cs->temps[r.index].reg = -1; - r.valid = GL_TRUE; + + cs->temp_in_use |= (1 << --index); + cs->temps[index].refcount = 0xFFFFFFFF; + cs->temps[index].reg = -1; + + REG_SET_TYPE(r, REG_TYPE_TEMP); + REG_SET_INDEX(r, index); + REG_SET_VALID(r, GL_TRUE); return r; } -static pfs_reg_t get_temp_reg_tex(struct r300_fragment_program *rp) +static GLuint get_temp_reg_tex(struct r300_fragment_program *rp) { COMPILE_STATE; - pfs_reg_t r = undef; + GLuint r = undef; + GLuint index; - r.index = ffs(~cs->temp_in_use); - if (!r.index) { + index = ffs(~cs->temp_in_use); + if (!index) { ERROR("Out of program temps\n"); return r; } - cs->temp_in_use |= (1 << --r.index); - - cs->temps[r.index].refcount = 0xFFFFFFFF; - cs->temps[r.index].reg = get_hw_temp_tex(rp); - r.valid = GL_TRUE; + + cs->temp_in_use |= (1 << --index); + cs->temps[index].refcount = 0xFFFFFFFF; + cs->temps[index].reg = get_hw_temp_tex(rp); + + REG_SET_TYPE(r, REG_TYPE_TEMP); + REG_SET_INDEX(r, index); + REG_SET_VALID(r, GL_TRUE); return r; } -static void free_temp(struct r300_fragment_program *rp, pfs_reg_t r) +static void free_temp(struct r300_fragment_program *rp, GLuint r) { COMPILE_STATE; - if (!(cs->temp_in_use & (1<<r.index))) return; + GLuint index = REG_GET_INDEX(r); + + if (!(cs->temp_in_use & (1 << index))) + return; - if (r.type == REG_TYPE_TEMP) { - free_hw_temp(rp, cs->temps[r.index].reg); - cs->temps[r.index].reg = -1; - cs->temp_in_use &= ~(1<<r.index); - } else if (r.type == REG_TYPE_INPUT) { - free_hw_temp(rp, cs->inputs[r.index].reg); - cs->inputs[r.index].reg = -1; + if (REG_GET_TYPE(r) == REG_TYPE_TEMP) { + free_hw_temp(rp, cs->temps[index].reg); + cs->temps[index].reg = -1; + cs->temp_in_use &= ~(1 << index); + } else if (REG_GET_TYPE(r) == REG_TYPE_INPUT) { + free_hw_temp(rp, cs->inputs[index].reg); + cs->inputs[index].reg = -1; } } -static pfs_reg_t emit_param4fv(struct r300_fragment_program *rp, - GLfloat *values) +static GLuint emit_param4fv(struct r300_fragment_program *rp, + GLfloat *values) { - pfs_reg_t r = undef; - r.type = REG_TYPE_CONST; + GLuint r = undef; + GLuint index; int pidx; pidx = rp->param_nr++; - r.index = rp->const_nr++; - if (pidx >= PFS_NUM_CONST_REGS || r.index >= PFS_NUM_CONST_REGS) { + index = rp->const_nr++; + if (pidx >= PFS_NUM_CONST_REGS || index >= PFS_NUM_CONST_REGS) { ERROR("Out of const/param slots!\n"); return r; } - - rp->param[pidx].idx = r.index; + + rp->param[pidx].idx = index; rp->param[pidx].values = values; rp->params_uptodate = GL_FALSE; - r.valid = GL_TRUE; + REG_SET_TYPE(r, REG_TYPE_CONST); + REG_SET_INDEX(r, index); + REG_SET_VALID(r, GL_TRUE); return r; } -static pfs_reg_t emit_const4fv(struct r300_fragment_program *rp, GLfloat *cp) +static GLuint emit_const4fv(struct r300_fragment_program *rp, GLfloat *cp) { - pfs_reg_t r = undef; - r.type = REG_TYPE_CONST; + GLuint r = undef; + GLuint index; - r.index = rp->const_nr++; - if (r.index >= PFS_NUM_CONST_REGS) { + index = rp->const_nr++; + if (index >= PFS_NUM_CONST_REGS) { ERROR("Out of hw constants!\n"); return r; } - COPY_4V(rp->constant[r.index], cp); - r.valid = GL_TRUE; + COPY_4V(rp->constant[index], cp); + + REG_SET_TYPE(r, REG_TYPE_CONST); + REG_SET_INDEX(r, index); + REG_SET_VALID(r, GL_TRUE); return r; } -static __inline pfs_reg_t negate(pfs_reg_t r) +static inline GLuint negate(GLuint r) { - r.negate_v = 1; - r.negate_s = 1; + REG_NEGS(r); + REG_NEGV(r); return r; } /* Hack, to prevent clobbering sources used multiple times when * emulating non-native instructions */ -static __inline pfs_reg_t keep(pfs_reg_t r) +static inline GLuint keep(GLuint r) { - r.no_use = GL_TRUE; + REG_SET_NO_USE(r, GL_TRUE); return r; } -static __inline pfs_reg_t absolute(pfs_reg_t r) +static inline GLuint absolute(GLuint r) { - r.absolute = 1; + REG_ABS(r); return r; } static int swz_native(struct r300_fragment_program *rp, - pfs_reg_t src, pfs_reg_t *r, GLuint arbneg) + GLuint src, + GLuint *r, + GLuint arbneg) { - /* Native swizzle, nothing to see here */ - src.negate_s = (arbneg >> 3) & 1; + /* Native swizzle, handle negation */ + src = (src & ~REG_NEGS_MASK) | + (((arbneg >> 3) & 1) << REG_NEGS_SHIFT); if ((arbneg & 0x7) == 0x0) { - src.negate_v = 0; + src = src & ~REG_NEGV_MASK; *r = src; } else if ((arbneg & 0x7) == 0x7) { - src.negate_v = 1; + src |= REG_NEGV_MASK; *r = src; } else { - if (!r->valid) + if (!REG_GET_VALID(*r)) *r = get_temp_reg(rp); - src.negate_v = 1; - emit_arith(rp, PFS_OP_MAD, *r, arbneg & 0x7, - keep(src), pfs_one, pfs_zero, 0); - src.negate_v = 0; - emit_arith(rp, PFS_OP_MAD, *r, + src |= REG_NEGV_MASK; + emit_arith(rp, + PFS_OP_MAD, + *r, + arbneg & 0x7, + keep(src), + pfs_one, + pfs_zero, + 0); + src = src & ~REG_NEGV_MASK; + emit_arith(rp, + PFS_OP_MAD, + *r, (arbneg ^ 0x7) | WRITEMASK_W, - src, pfs_one, pfs_zero, 0); + src, + pfs_one, + pfs_zero, + 0); } return 3; } -static int swz_emit_partial(struct r300_fragment_program *rp, pfs_reg_t src, - pfs_reg_t *r, int mask, int mc, GLuint arbneg) +static int swz_emit_partial(struct r300_fragment_program *rp, + GLuint src, + GLuint *r, + int mask, + int mc, + GLuint arbneg) { GLuint tmp; GLuint wmask = 0; - if (!r->valid) + if (!REG_GET_VALID(*r)) *r = get_temp_reg(rp); - /* A partial match, src.v_swz/mask define what parts of the - * desired swizzle we match */ + /* A partial match, VSWZ/mask define what parts of the + * desired swizzle we match + */ if (mc + s_mask[mask].count == 3) { wmask = WRITEMASK_W; - src.negate_s = (arbneg >> 3) & 1; + src |= ((arbneg >> 3) & 1) << REG_NEGS_SHIFT; } tmp = arbneg & s_mask[mask].mask; if (tmp) { tmp = tmp ^ s_mask[mask].mask; if (tmp) { - src.negate_v = 1; - emit_arith(rp, PFS_OP_MAD, *r, + emit_arith(rp, + PFS_OP_MAD, + *r, arbneg & s_mask[mask].mask, - keep(src), pfs_one, pfs_zero, 0); - src.negate_v = 0; - if (!wmask) src.no_use = GL_TRUE; - else src.no_use = GL_FALSE; - emit_arith(rp, PFS_OP_MAD, *r, tmp | wmask, - src, pfs_one, pfs_zero, 0); + keep(src) | REG_NEGV_MASK, + pfs_one, + pfs_zero, + 0); + if (!wmask) { + REG_SET_NO_USE(src, GL_TRUE); + } else { + REG_SET_NO_USE(src, GL_FALSE); + } + emit_arith(rp, + PFS_OP_MAD, + *r, + tmp | wmask, + src, + pfs_one, + pfs_zero, + 0); } else { - src.negate_v = 1; - if (!wmask) src.no_use = GL_TRUE; - else src.no_use = GL_FALSE; - emit_arith(rp, PFS_OP_MAD, *r, + if (!wmask) { + REG_SET_NO_USE(src, GL_TRUE); + } else { + REG_SET_NO_USE(src, GL_FALSE); + } + emit_arith(rp, + PFS_OP_MAD, + *r, (arbneg & s_mask[mask].mask) | wmask, - src, pfs_one, pfs_zero, 0); - src.negate_v = 0; + src | REG_NEGV_MASK, + pfs_one, + pfs_zero, + 0); } } else { - if (!wmask) src.no_use = GL_TRUE; - else src.no_use = GL_FALSE; - emit_arith(rp, PFS_OP_MAD, *r, + if (!wmask) { + REG_SET_NO_USE(src, GL_TRUE); + } else { + REG_SET_NO_USE(src, GL_FALSE); + } + emit_arith(rp, PFS_OP_MAD, + *r, s_mask[mask].mask | wmask, - src, pfs_one, pfs_zero, 0); + src, + pfs_one, + pfs_zero, + 0); } return s_mask[mask].count; } -#define swizzle(r, x, y, z, w) do_swizzle(rp, r, \ - ((SWIZZLE_##x<<0)| \ - (SWIZZLE_##y<<3)| \ - (SWIZZLE_##z<<6)| \ - (SWIZZLE_##w<<9)), \ - 0) - -static pfs_reg_t do_swizzle(struct r300_fragment_program *rp, - pfs_reg_t src, GLuint arbswz, GLuint arbneg) +static GLuint do_swizzle(struct r300_fragment_program *rp, + GLuint src, + GLuint arbswz, + GLuint arbneg) { - pfs_reg_t r = undef; - + GLuint r = undef; + GLuint vswz; int c_mask = 0; - int v_matched = 0; + int v_match = 0; /* If swizzling from something without an XYZW native swizzle, * emit result to a temp, and do new swizzle from the temp. */ - if (src.v_swz != SWIZZLE_XYZ || src.s_swz != SWIZZLE_W) { - pfs_reg_t temp = get_temp_reg(rp); - emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_XYZW, src, pfs_one, - pfs_zero, 0); +#if 0 + if (REG_GET_VSWZ(src) != SWIZZLE_XYZ || + REG_GET_SSWZ(src) != SWIZZLE_W) { + GLuint temp = get_temp_reg(rp); + emit_arith(rp, + PFS_OP_MAD, + temp, + WRITEMASK_XYZW, + src, + pfs_one, + pfs_zero, + 0); src = temp; } - src.s_swz = GET_SWZ(arbswz, 3); +#endif + + if (REG_GET_VSWZ(src) != SWIZZLE_XYZ || + REG_GET_SSWZ(src) != SWIZZLE_W) { + GLuint vsrcswz = (v_swiz[REG_GET_VSWZ(src)].hash & (SWZ_X_MASK|SWZ_Y_MASK|SWZ_Z_MASK)) | REG_GET_SSWZ(src) << 9; + GLint i; + + GLuint newswz = 0; + GLuint offset; + for(i=0; i < 4; ++i){ + offset = GET_SWZ(arbswz, i); + + newswz |= (offset <= 3)?GET_SWZ(vsrcswz, offset) << i*3:offset << i*3; + } + + arbswz = newswz & (SWZ_X_MASK|SWZ_Y_MASK|SWZ_Z_MASK); + REG_SET_SSWZ(src, GET_SWZ(newswz, 3)); + } + else + { + /* set scalar swizzling */ + REG_SET_SSWZ(src, GET_SWZ(arbswz, 3)); + } do { + vswz = REG_GET_VSWZ(src); do { -#define CUR_HASH (v_swiz[src.v_swz].hash & s_mask[c_mask].hash) - if (CUR_HASH == (arbswz & s_mask[c_mask].hash)) { - if (s_mask[c_mask].count == 3) - v_matched += swz_native(rp, src, &r, + int chash; + + REG_SET_VSWZ(src, vswz); + chash = v_swiz[REG_GET_VSWZ(src)].hash & + s_mask[c_mask].hash; + + if (chash == (arbswz & s_mask[c_mask].hash)) { + if (s_mask[c_mask].count == 3) { + v_match += swz_native(rp, + src, + &r, arbneg); - else - v_matched += swz_emit_partial(rp, src, - &r, - c_mask, - v_matched, - arbneg); - - if (v_matched == 3) + } else { + v_match += swz_emit_partial(rp, + src, + &r, + c_mask, + v_match, + arbneg); + } + + if (v_match == 3) return r; /* Fill with something invalid.. all 0's was * wrong before, matched SWIZZLE_X. So all - * 1's will be okay for now */ + * 1's will be okay for now + */ arbswz |= (PFS_INVAL & s_mask[c_mask].hash); } - } while(v_swiz[++src.v_swz].hash != PFS_INVAL); - src.v_swz = SWIZZLE_XYZ; + } while(v_swiz[++vswz].hash != PFS_INVAL); + REG_SET_VSWZ(src, SWIZZLE_XYZ); } while (s_mask[++c_mask].hash != PFS_INVAL); ERROR("should NEVER get here\n"); return r; } - -static pfs_reg_t t_src(struct r300_fragment_program *rp, - struct prog_src_register fpsrc) + +static GLuint t_src(struct r300_fragment_program *rp, + struct prog_src_register fpsrc) { - pfs_reg_t r = undef; + GLuint r = undef; switch (fpsrc.File) { case PROGRAM_TEMPORARY: - r.index = fpsrc.Index; - r.valid = GL_TRUE; + REG_SET_INDEX(r, fpsrc.Index); + REG_SET_VALID(r, GL_TRUE); + REG_SET_TYPE(r, REG_TYPE_TEMP); break; case PROGRAM_INPUT: - r.index = fpsrc.Index; - r.type = REG_TYPE_INPUT; - r.valid = GL_TRUE; + REG_SET_INDEX(r, fpsrc.Index); + REG_SET_VALID(r, GL_TRUE); + REG_SET_TYPE(r, REG_TYPE_INPUT); break; case PROGRAM_LOCAL_PARAM: r = emit_param4fv(rp, @@ -533,13 +705,13 @@ static pfs_reg_t t_src(struct r300_fragment_program *rp, } /* no point swizzling ONE/ZERO/HALF constants... */ - if (r.v_swz < SWIZZLE_111 || r.s_swz < SWIZZLE_ZERO) + if (REG_GET_VSWZ(r) < SWIZZLE_111 || REG_GET_SSWZ(r) < SWIZZLE_ZERO) r = do_swizzle(rp, r, fpsrc.Swizzle, fpsrc.NegateBase); return r; } -static pfs_reg_t t_scalar_src(struct r300_fragment_program *rp, - struct prog_src_register fpsrc) +static GLuint t_scalar_src(struct r300_fragment_program *rp, + struct prog_src_register fpsrc) { struct prog_src_register src = fpsrc; int sc = GET_SWZ(fpsrc.Swizzle, 0); /* X */ @@ -549,22 +721,24 @@ static pfs_reg_t t_scalar_src(struct r300_fragment_program *rp, return t_src(rp, src); } -static pfs_reg_t t_dst(struct r300_fragment_program *rp, - struct prog_dst_register dest) { - pfs_reg_t r = undef; +static GLuint t_dst(struct r300_fragment_program *rp, + struct prog_dst_register dest) +{ + GLuint r = undef; switch (dest.File) { case PROGRAM_TEMPORARY: - r.index = dest.Index; - r.valid = GL_TRUE; + REG_SET_INDEX(r, dest.Index); + REG_SET_VALID(r, GL_TRUE); + REG_SET_TYPE(r, REG_TYPE_TEMP); return r; case PROGRAM_OUTPUT: - r.type = REG_TYPE_OUTPUT; + REG_SET_TYPE(r, REG_TYPE_OUTPUT); switch (dest.Index) { case FRAG_RESULT_COLR: case FRAG_RESULT_DEPR: - r.index = dest.Index; - r.valid = GL_TRUE; + REG_SET_INDEX(r, dest.Index); + REG_SET_VALID(r, GL_TRUE); return r; default: ERROR("Bad DstReg->Index 0x%x\n", dest.Index); @@ -576,66 +750,77 @@ static pfs_reg_t t_dst(struct r300_fragment_program *rp, } } -static int t_hw_src(struct r300_fragment_program *rp, pfs_reg_t src, +static int t_hw_src(struct r300_fragment_program *rp, + GLuint src, GLboolean tex) { COMPILE_STATE; int idx; + int index = REG_GET_INDEX(src); - switch (src.type) { + switch(REG_GET_TYPE(src)) { case REG_TYPE_TEMP: /* NOTE: if reg==-1 here, a source is being read that - * hasn't been written to. Undefined results */ - if (cs->temps[src.index].reg == -1) - cs->temps[src.index].reg = get_hw_temp(rp); - idx = cs->temps[src.index].reg; + * hasn't been written to. Undefined results + */ + if (cs->temps[index].reg == -1) + cs->temps[index].reg = get_hw_temp(rp); + + idx = cs->temps[index].reg; - if (!src.no_use && (--cs->temps[src.index].refcount == 0)) + if (!REG_GET_NO_USE(src) && + (--cs->temps[index].refcount == 0)) free_temp(rp, src); break; case REG_TYPE_INPUT: - idx = cs->inputs[src.index].reg; + idx = cs->inputs[index].reg; - if (!src.no_use && (--cs->inputs[src.index].refcount == 0)) - free_hw_temp(rp, cs->inputs[src.index].reg); + if (!REG_GET_NO_USE(src) && + (--cs->inputs[index].refcount == 0)) + free_hw_temp(rp, cs->inputs[index].reg); break; case REG_TYPE_CONST: - return (src.index | SRC_CONST); + return (index | SRC_CONST); default: ERROR("Invalid type for source reg\n"); return (0 | SRC_CONST); } - if (!tex) cs->used_in_node |= (1 << idx); + if (!tex) + cs->used_in_node |= (1 << idx); return idx; } -static int t_hw_dst(struct r300_fragment_program *rp, pfs_reg_t dest, +static int t_hw_dst(struct r300_fragment_program *rp, + GLuint dest, GLboolean tex) { COMPILE_STATE; int idx; - assert(dest.valid); + GLuint index = REG_GET_INDEX(dest); + assert(REG_GET_VALID(dest)); - switch (dest.type) { + switch(REG_GET_TYPE(dest)) { case REG_TYPE_TEMP: - if (cs->temps[dest.index].reg == -1) { - if (!tex) - cs->temps[dest.index].reg = get_hw_temp(rp); - else - cs->temps[dest.index].reg = get_hw_temp_tex(rp); + if (cs->temps[REG_GET_INDEX(dest)].reg == -1) { + if (!tex) { + cs->temps[index].reg = get_hw_temp(rp); + } else { + cs->temps[index].reg = get_hw_temp_tex(rp); + } } - idx = cs->temps[dest.index].reg; + idx = cs->temps[index].reg; - if (!dest.no_use && (--cs->temps[dest.index].refcount == 0)) + if (!REG_GET_NO_USE(dest) && + (--cs->temps[index].refcount == 0)) free_temp(rp, dest); cs->dest_in_node |= (1 << idx); cs->used_in_node |= (1 << idx); break; case REG_TYPE_OUTPUT: - switch (dest.index) { + switch(index) { case FRAG_RESULT_COLR: rp->node[rp->cur_node].flags |= R300_PFS_NODE_OUTPUT_COLOR; break; @@ -643,17 +828,18 @@ static int t_hw_dst(struct r300_fragment_program *rp, pfs_reg_t dest, rp->node[rp->cur_node].flags |= R300_PFS_NODE_OUTPUT_DEPTH; break; } - return dest.index; + return index; break; default: - ERROR("invalid dest reg type %d\n", dest.type); + ERROR("invalid dest reg type %d\n", REG_GET_TYPE(dest)); return 0; } return idx; } -static void emit_nop(struct r300_fragment_program *rp, GLuint mask, +static void emit_nop(struct r300_fragment_program *rp, + GLuint mask, GLboolean sync) { COMPILE_STATE; @@ -679,8 +865,8 @@ static void emit_tex(struct r300_fragment_program *rp, int opcode) { COMPILE_STATE; - pfs_reg_t coord = t_src(rp, fpi->SrcReg[0]); - pfs_reg_t dest = undef, rdest = undef; + GLuint coord = t_src(rp, fpi->SrcReg[0]); + GLuint dest = undef, rdest = undef; GLuint din = cs->dest_in_node, uin = cs->used_in_node; int unit = fpi->TexSrcUnit; int hwsrc, hwdest; @@ -691,7 +877,7 @@ static void emit_tex(struct r300_fragment_program *rp, dest = t_dst(rp, fpi->DstReg); /* r300 doesn't seem to be able to do TEX->output reg */ - if (dest.type == REG_TYPE_OUTPUT) { + if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { rdest = dest; dest = get_temp_reg_tex(rp); } @@ -703,7 +889,7 @@ static void emit_tex(struct r300_fragment_program *rp, if (uin & (1 << hwdest)) { free_hw_temp(rp, hwdest); hwdest = get_hw_temp_tex(rp); - cs->temps[dest.index].reg = hwdest; + cs->temps[REG_GET_INDEX(dest)].reg = hwdest; } } else { hwdest = 0; @@ -713,8 +899,8 @@ static void emit_tex(struct r300_fragment_program *rp, /* Indirection if source has been written in this node, or if the * dest has been read/written in this node */ - if ((coord.type != REG_TYPE_CONST && (din & (1<<hwsrc))) || - (uin & (1<<hwdest))) { + if ((REG_GET_TYPE(coord) != REG_TYPE_CONST && + (din & (1<<hwsrc))) || (uin & (1<<hwdest))) { /* Finish off current node */ cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos); @@ -754,13 +940,13 @@ static void emit_tex(struct r300_fragment_program *rp, | (opcode << R300_FPITX_OPCODE_SHIFT); cs->dest_in_node |= (1 << hwdest); - if (coord.type != REG_TYPE_CONST) + if (REG_GET_TYPE(coord) != REG_TYPE_CONST) cs->used_in_node |= (1 << hwsrc); rp->node[rp->cur_node].tex_end++; /* Copy from temp to output if needed */ - if (rdest.valid) { + if (REG_GET_VALID(rdest)) { emit_arith(rp, PFS_OP_MAD, rdest, WRITEMASK_XYZW, dest, pfs_one, pfs_zero, 0); free_temp(rp, dest); @@ -770,7 +956,9 @@ static void emit_tex(struct r300_fragment_program *rp, /* Add sources to FPI1/FPI3 lists. If source is already on list, * reuse the index instead of wasting a source. */ -static int add_src(struct r300_fragment_program *rp, int reg, int pos, +static int add_src(struct r300_fragment_program *rp, + int reg, + int pos, int srcmask) { COMPILE_STATE; @@ -819,9 +1007,12 @@ static int add_src(struct r300_fragment_program *rp, int reg, int pos, * It's not necessary to force the first case, but it makes disassembled * shaders easier to read. */ -static GLboolean force_same_slot(int vop, int sop, - GLboolean emit_vop, GLboolean emit_sop, - int argc, pfs_reg_t *src) +static GLboolean force_same_slot(int vop, + int sop, + GLboolean emit_vop, + GLboolean emit_sop, + int argc, + GLuint *src) { int i; @@ -833,20 +1024,24 @@ static GLboolean force_same_slot(int vop, int sop, if (emit_vop) { for (i=0;i<argc;i++) - if (src[i].v_swz == SWIZZLE_WZY) + if (REG_GET_VSWZ(src[i]) == SWIZZLE_WZY) return GL_TRUE; } return GL_FALSE; } -static void emit_arith(struct r300_fragment_program *rp, int op, - pfs_reg_t dest, int mask, - pfs_reg_t src0, pfs_reg_t src1, pfs_reg_t src2, +static void emit_arith(struct r300_fragment_program *rp, + int op, + GLuint dest, + int mask, + GLuint src0, + GLuint src1, + GLuint src2, int flags) { COMPILE_STATE; - pfs_reg_t src[3] = { src0, src1, src2 }; + GLuint src[3] = { src0, src1, src2 }; int hwsrc[3], sswz[3], vswz[3]; int hwdest; GLboolean emit_vop = GL_FALSE, emit_sop = GL_FALSE; @@ -863,7 +1058,8 @@ static void emit_arith(struct r300_fragment_program *rp, int op, if ((mask & WRITEMASK_W) || vop == R300_FPI0_OUTC_REPL_ALPHA) emit_sop = GL_TRUE; - if (dest.type == REG_TYPE_OUTPUT && dest.index == FRAG_RESULT_DEPR) + if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT && + REG_GET_INDEX(dest) == FRAG_RESULT_DEPR) emit_vop = GL_FALSE; if (force_same_slot(vop, sop, emit_vop, emit_sop, argc, src)) { @@ -879,12 +1075,12 @@ static void emit_arith(struct r300_fragment_program *rp, int op, */ for (i=0;i<3;i++) { if (emit_vop && - (v_swiz[src[i].v_swz].flags & SLOT_SCALAR)) { + (v_swiz[REG_GET_VSWZ(src[i])].flags & SLOT_SCALAR)) { vpos = spos = MAX2(vpos, spos); break; } if (emit_sop && - (s_swiz[src[i].s_swz].flags & SLOT_VECTOR)) { + (s_swiz[REG_GET_SSWZ(src[i])].flags & SLOT_VECTOR)) { vpos = spos = MAX2(vpos, spos); break; } @@ -908,20 +1104,22 @@ static void emit_arith(struct r300_fragment_program *rp, int op, if (emit_vop && vop != R300_FPI0_OUTC_REPL_ALPHA) { srcpos = add_src(rp, hwsrc[i], vpos, - v_swiz[src[i].v_swz].flags); - vswz[i] = (v_swiz[src[i].v_swz].base + - (srcpos * v_swiz[src[i].v_swz].stride)) | - (src[i].negate_v ? ARG_NEG : 0) | - (src[i].absolute ? ARG_ABS : 0); + v_swiz[REG_GET_VSWZ(src[i])].flags); + vswz[i] = (v_swiz[REG_GET_VSWZ(src[i])].base + + (srcpos * + v_swiz[REG_GET_VSWZ(src[i])].stride)) | + ((src[i] & REG_NEGV_MASK) ? ARG_NEG : 0) | + ((src[i] & REG_ABS_MASK) ? ARG_ABS : 0); } else vswz[i] = R300_FPI0_ARGC_ZERO; if (emit_sop) { srcpos = add_src(rp, hwsrc[i], spos, - s_swiz[src[i].s_swz].flags); - sswz[i] = (s_swiz[src[i].s_swz].base + - (srcpos * s_swiz[src[i].s_swz].stride)) | - (src[i].negate_s ? ARG_NEG : 0) | - (src[i].absolute ? ARG_ABS : 0); + s_swiz[REG_GET_SSWZ(src[i])].flags); + sswz[i] = (s_swiz[REG_GET_SSWZ(src[i])].base + + (srcpos * + s_swiz[REG_GET_SSWZ(src[i])].stride)) | + ((src[i] & REG_NEGS_MASK) ? ARG_NEG : 0) | + ((src[i] & REG_ABS_MASK) ? ARG_ABS : 0); } else sswz[i] = R300_FPI2_ARGA_ZERO; } hwdest = t_hw_dst(rp, dest, GL_FALSE); @@ -943,8 +1141,8 @@ static void emit_arith(struct r300_fragment_program *rp, int op, (vswz[2] << R300_FPI0_ARG2C_SHIFT); rp->alu.inst[vpos].inst1 |= hwdest << R300_FPI1_DSTC_SHIFT; - if (dest.type == REG_TYPE_OUTPUT) { - if (dest.index == FRAG_RESULT_COLR) { + if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { + if (REG_GET_INDEX(dest) == FRAG_RESULT_COLR) { rp->alu.inst[vpos].inst1 |= (mask & WRITEMASK_XYZ) << R300_FPI1_DSTC_OUTPUT_MASK_SHIFT; } else assert(0); @@ -968,11 +1166,11 @@ static void emit_arith(struct r300_fragment_program *rp, int op, sswz[2] << R300_FPI2_ARG2A_SHIFT; if (mask & WRITEMASK_W) { - if (dest.type == REG_TYPE_OUTPUT) { - if (dest.index == FRAG_RESULT_COLR) { + if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { + if (REG_GET_INDEX(dest) == FRAG_RESULT_COLR) { rp->alu.inst[spos].inst3 |= (hwdest << R300_FPI3_DSTA_SHIFT) | R300_FPI3_DSTA_OUTPUT; - } else if (dest.index == FRAG_RESULT_DEPR) { + } else if (REG_GET_INDEX(dest) == FRAG_RESULT_DEPR) { rp->alu.inst[spos].inst3 |= R300_FPI3_DSTA_DEPTH; } else assert(0); } else { @@ -985,33 +1183,52 @@ static void emit_arith(struct r300_fragment_program *rp, int op, rp->alu.inst[vpos].inst2 = NOP_INST2; return; -}; +} #if 0 -static pfs_reg_t get_attrib(struct r300_fragment_program *rp, GLuint attr) +static GLuint get_attrib(struct r300_fragment_program *rp, GLuint attr) { struct gl_fragment_program *mp = &rp->mesa_program; - pfs_reg_t r = undef; + GLuint r = undef; if (!(mp->Base.InputsRead & (1<<attr))) { ERROR("Attribute %d was not provided!\n", attr); return undef; } - r.type = REG_TYPE_INPUT; - r.index = attr; - r.valid = GL_TRUE; + REG_SET_TYPE(r, REG_TYPE_INPUT); + REG_SET_INDEX(r, attr); + REG_SET_VALID(r, GL_TRUE); return r; } #endif +static void make_sin_const(struct r300_fragment_program *rp) +{ + if(rp->const_sin[0] == -1){ + GLfloat cnstv[4]; + + cnstv[0] = 1.273239545; // 4/PI + cnstv[1] =-0.405284735; // -4/(PI*PI) + cnstv[2] = 3.141592654; // PI + cnstv[3] = 0.2225; // weight + rp->const_sin[0] = emit_const4fv(rp, cnstv); + + cnstv[0] = 0.5; + cnstv[1] = -1.5; + cnstv[2] = 0.159154943; // 1/(2*PI) + cnstv[3] = 6.283185307; // 2*PI + rp->const_sin[1] = emit_const4fv(rp, cnstv); + } +} + static GLboolean parse_program(struct r300_fragment_program *rp) { struct gl_fragment_program *mp = &rp->mesa_program; const struct prog_instruction *inst = mp->Base.Instructions; struct prog_instruction *fpi; - pfs_reg_t src[3], dest, temp; - pfs_reg_t cnst; + GLuint src[3], dest, temp; + GLuint cnst; int flags, mask = 0; GLfloat cnstv[4] = {0.0, 0.0, 0.0, 0.0}; @@ -1058,62 +1275,71 @@ static GLboolean parse_program(struct r300_fragment_program *rp) break; case OPCODE_COS: /* - * cos using taylor serie: - * cos(x) = 1 - x^2/2! + x^4/4! - x^6/6! + * cos using a parabola (see SIN): + * cos(x): + * x += PI/2 + * x = (x/(2*PI))+0.5 + * x = frac(x) + * x = (x*2*PI)-PI + * result = sin(x) */ temp = get_temp_reg(rp); - cnstv[0] = 0.5; - cnstv[1] = 0.041666667; - cnstv[2] = 0.001388889; - cnstv[4] = 0.0; - cnst = emit_const4fv(rp, cnstv); + make_sin_const(rp); src[0] = t_scalar_src(rp, fpi->SrcReg[0]); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_XYZ, - src[0], - src[0], - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_Y | WRITEMASK_Z, - temp, temp, - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_Z, - temp, - swizzle(temp, X, X, X, W), - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_XYZ, - temp, cnst, - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_X, - pfs_one, - pfs_one, - negate(temp), - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_X, - temp, - pfs_one, - swizzle(temp, Y, Y, Y, W), - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_X, - temp, - pfs_one, - negate(swizzle(temp, Z, Z, Z, W)), - flags); - emit_arith(rp, PFS_OP_MAD, dest, mask, + /* add 0.5*PI and do range reduction */ + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X, + swizzle(rp->const_sin[0], Z, Z, Z, Z), //PI + pfs_half, + swizzle(keep(src[0]), X, X, X, X), + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X, swizzle(temp, X, X, X, X), - pfs_one, + swizzle(rp->const_sin[1], Z, Z, Z, Z), + pfs_half, + 0); + + emit_arith(rp, PFS_OP_FRC, temp, WRITEMASK_X, + swizzle(temp, X, X, X, X), + undef, + undef, + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_Z, + swizzle(temp, X, X, X, X), + swizzle(rp->const_sin[1], W, W, W, W), //2*PI + negate(swizzle(rp->const_sin[0], Z, Z, Z, Z)), //-PI + 0); + + /* SIN */ + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X | WRITEMASK_Y, + swizzle(temp, Z, Z, Z, Z), + rp->const_sin[0], pfs_zero, + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X, + swizzle(temp, Y, Y, Y, Y), + absolute(swizzle(temp, Z, Z, Z, Z)), + swizzle(temp, X, X, X, X), + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_Y, + swizzle(temp, X, X, X, X), + absolute(swizzle(temp, X, X, X, X)), + negate(swizzle(temp, X, X, X, X)), + 0); + + + emit_arith(rp, PFS_OP_MAD, dest, mask, + swizzle(temp, Y, Y, Y, Y), + swizzle(rp->const_sin[0], W, W, W, W), + swizzle(temp, X, X, X, X), flags); + free_temp(rp, temp); break; case OPCODE_DP3: @@ -1167,7 +1393,7 @@ static GLboolean parse_program(struct r300_fragment_program *rp) /* result.x = 1.0 * result.w = src1.w */ if (mask & WRITEMASK_XW) { - src[1].v_swz = SWIZZLE_111; /* Cheat.. */ + REG_SET_VSWZ(src[1], SWIZZLE_111); /*Cheat*/ emit_arith(rp, PFS_OP_MAD, dest, mask & WRITEMASK_XW, src[1], pfs_one, pfs_zero, @@ -1222,7 +1448,7 @@ static GLboolean parse_program(struct r300_fragment_program *rp) * change the compare to (t.x + 0.5) > 0.5 we may * save one instruction by doing CMP -t.x */ - cnstv[0] = cnstv[1] = cnstv[2] = cnstv[4] = 0.50001; + cnstv[0] = cnstv[1] = cnstv[2] = cnstv[3] = 0.50001; src[0] = t_src(rp, fpi->SrcReg[0]); temp = get_temp_reg(rp); cnst = emit_const4fv(rp, cnstv); @@ -1353,7 +1579,93 @@ static GLboolean parse_program(struct r300_fragment_program *rp) flags); break; case OPCODE_SCS: - ERROR("SCS not implemented\n"); + /* + * cos using a parabola (see SIN): + * cos(x): + * x += PI/2 + * x = (x/(2*PI))+0.5 + * x = frac(x) + * x = (x*2*PI)-PI + * result = sin(x) + */ + temp = get_temp_reg(rp); + make_sin_const(rp); + src[0] = t_scalar_src(rp, fpi->SrcReg[0]); + + /* add 0.5*PI and do range reduction */ + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X|WRITEMASK_Y, + swizzle(rp->const_sin[0], Z, Z, Z, Z), + rp->const_sin[1], + swizzle(keep(src[0]), X, X, X, X), + 0); + + emit_arith(rp, PFS_OP_CMP, temp, WRITEMASK_W, + swizzle(rp->const_sin[0], Z, Z, Z, Z), + negate(pfs_half), + swizzle(keep(src[0]), X, X, X, X), + 0); + + emit_arith(rp, PFS_OP_CMP, temp, WRITEMASK_Z, + swizzle(temp, X, X, X, X), + swizzle(temp, Y, Y, Y, Y), + swizzle(temp, W, W, W, W), + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X | WRITEMASK_Y, + swizzle(temp, Z, Z, Z, Z), + rp->const_sin[0], + pfs_zero, + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_W, + swizzle(temp, Y, Y, Y, Y), + absolute(swizzle(temp, Z, Z, Z, Z)), + swizzle(temp, X, X, X, X), + 0); + + if(mask & WRITEMASK_Y) + { + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X | WRITEMASK_Y, + swizzle(keep(src[0]), X, X, X, X), + rp->const_sin[0], + pfs_zero, + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X, + swizzle(temp, Y, Y, Y, Y), + absolute(swizzle(keep(src[0]), X, X, X, X)), + swizzle(temp, X, X, X, X), + 0); + } + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_Z, + swizzle(temp, W, W, W, W), + absolute(swizzle(temp, W, W, W, W)), + negate(swizzle(temp, W, W, W, W)), + 0); + + emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_X, + swizzle(temp, Z, Z, Z, Z), + swizzle(rp->const_sin[0], W, W, W, W), + swizzle(temp, W, W, W, W), + flags); + + if(mask & WRITEMASK_Y) + { + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_W, + swizzle(temp, X, X, X, X), + absolute(swizzle(temp, X, X, X, X)), + negate(swizzle(temp, X, X, X, X)), + 0); + + emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_Y, + swizzle(temp, W, W, W, W), + swizzle(rp->const_sin[0], W, W, W, W), + swizzle(temp, X, X, X, X), + flags); + } + free_temp(rp, temp); break; case OPCODE_SGE: src[0] = t_src(rp, fpi->SrcReg[0]); @@ -1372,68 +1684,63 @@ static GLboolean parse_program(struct r300_fragment_program *rp) break; case OPCODE_SIN: /* - * sin using taylor serie: - * sin(x) = x - x^3/3! + x^5/5! - x^7/7! + * using a parabola: + * sin(x) = 4/pi * x + -4/(pi*pi) * x * abs(x) + * extra precision is obtained by weighting against + * itself squared. */ + temp = get_temp_reg(rp); - cnstv[0] = 0.333333333; - cnstv[1] = 0.008333333; - cnstv[2] = 0.000198413; - cnstv[4] = 0.0; - cnst = emit_const4fv(rp, cnstv); + make_sin_const(rp); src[0] = t_scalar_src(rp, fpi->SrcReg[0]); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_XYZ, - src[0], - src[0], - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_Y | WRITEMASK_Z, - temp, temp, - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_Z, - temp, - swizzle(temp, X, X, X, W), - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_XYZ, - src[0], - temp, - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_XYZ, - temp, cnst, - pfs_zero, - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_X, - src[0], - pfs_one, - negate(temp), - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_X, - temp, - pfs_one, - swizzle(temp, Y, Y, Y, W), - flags); - emit_arith(rp, PFS_OP_MAD, temp, - WRITEMASK_X, - temp, - pfs_one, - negate(swizzle(temp, Z, Z, Z, W)), - flags); - emit_arith(rp, PFS_OP_MAD, dest, mask, + /* do range reduction */ + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X, + swizzle(keep(src[0]), X, X, X, X), + swizzle(rp->const_sin[1], Z, Z, Z, Z), + pfs_half, + 0); + + emit_arith(rp, PFS_OP_FRC, temp, WRITEMASK_X, swizzle(temp, X, X, X, X), - pfs_one, + undef, + undef, + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_Z, + swizzle(temp, X, X, X, X), + swizzle(rp->const_sin[1], W, W, W, W), //2*PI + negate(swizzle(rp->const_sin[0], Z, Z, Z, Z)), //PI + 0); + + /* SIN */ + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X | WRITEMASK_Y, + swizzle(temp, Z, Z, Z, Z), + rp->const_sin[0], pfs_zero, + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X, + swizzle(temp, Y, Y, Y, Y), + absolute(swizzle(temp, Z, Z, Z, Z)), + swizzle(temp, X, X, X, X), + 0); + + emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_Y, + swizzle(temp, X, X, X, X), + absolute(swizzle(temp, X, X, X, X)), + negate(swizzle(temp, X, X, X, X)), + 0); + + + emit_arith(rp, PFS_OP_MAD, dest, mask, + swizzle(temp, Y, Y, Y, Y), + swizzle(rp->const_sin[0], W, W, W, W), + swizzle(temp, X, X, X, X), flags); + free_temp(rp, temp); break; case OPCODE_SLT: @@ -1505,7 +1812,7 @@ static GLboolean parse_program(struct r300_fragment_program *rp) /* - Init structures * - Determine what hwregs each input corresponds to */ -static void init_program(struct r300_fragment_program *rp) +static void init_program(r300ContextPtr r300, struct r300_fragment_program *rp) { struct r300_pfs_compile_state *cs = NULL; struct gl_fragment_program *mp = &rp->mesa_program; @@ -1515,6 +1822,7 @@ static void init_program(struct r300_fragment_program *rp) int i,j; /* New compile, reset tracking data */ + rp->optimization = driQueryOptioni(&r300->radeon.optionCache, "fp_optimization"); rp->translated = GL_FALSE; rp->error = GL_FALSE; rp->cs = cs = &(R300_CONTEXT(rp->ctx)->state.pfs_compile); @@ -1527,6 +1835,7 @@ static void init_program(struct r300_fragment_program *rp) rp->max_temp_idx = 0; rp->node[0].alu_end = -1; rp->node[0].tex_end = -1; + rp->const_sin[0] = -1; _mesa_memset(cs, 0, sizeof(*rp->cs)); for (i=0;i<PFS_MAX_ALU_INST;i++) { @@ -1640,13 +1949,13 @@ static void update_params(struct r300_fragment_program *rp) rp->params_uptodate = GL_TRUE; } -void r300_translate_fragment_shader(struct r300_fragment_program *rp) +void r300_translate_fragment_shader(r300ContextPtr r300, struct r300_fragment_program *rp) { struct r300_pfs_compile_state *cs = NULL; if (!rp->translated) { - init_program(rp); + init_program(r300, rp); cs = rp->cs; if (parse_program(rp) == GL_FALSE) { diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 4bbaa07e01..73986abc3c 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -41,6 +41,7 @@ #include "r300_context.h" #include "program_instruction.h" +#if 0 /* representation of a register for emit_arith/swizzle */ typedef struct _pfs_reg_t { enum { @@ -58,7 +59,7 @@ typedef struct _pfs_reg_t { GLboolean no_use:1; GLboolean valid:1; } pfs_reg_t; - +#endif typedef struct r300_fragment_program_swizzle { GLuint length; GLuint src[4]; @@ -111,8 +112,11 @@ typedef struct r300_fragment_program_swizzle { ((0 | SRC_CONST) << R300_FPI3_SRC1A_SHIFT) | \ ((0 | SRC_CONST) << R300_FPI3_SRC2A_SHIFT)) +#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 +#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 + struct r300_fragment_program; -extern void r300_translate_fragment_shader(struct r300_fragment_program *rp); +extern void r300_translate_fragment_shader(r300ContextPtr r300, struct r300_fragment_program *rp); #endif diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_swz.c b/src/mesa/drivers/dri/r300/r300_fragprog_swz.c deleted file mode 100644 index b29331d7bd..0000000000 --- a/src/mesa/drivers/dri/r300/r300_fragprog_swz.c +++ /dev/null @@ -1,1328 +0,0 @@ -/* - * Copyright (C) 2005 Jerome Glisse. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "r300_fragprog.h" -#include "r300_reg.h" - - -#define I0_000 ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_ZERO) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_111 ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_ZERO) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG2C_SHIFT) ) -#define I0_XXX ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0C_XXX) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_YYY ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0C_YYY) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_ZZZ ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0C_ZZZ) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_XYZ ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0C_XYZ) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_YZX ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0C_YZX) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_ZXY ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0C_ZXY) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_WZY ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0CA_WZY) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) -#define I0_WWW ( (R300_FPI0_OUTC_MAD) | \ - (R300_FPI0_ARGC_SRC0A) | \ - (R300_FPI0_ARGC_ONE << R300_FPI0_ARG1C_SHIFT) | \ - (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT) ) - -#define IEMPTY 0 - -#define I1_XYZ ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_X | \ - R300_FPI1_DSTC_REG_Y | \ - R300_FPI1_DSTC_REG_Z ) -#define I1_XY_ ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_X | \ - R300_FPI1_DSTC_REG_Y ) -#define I1_X_Z ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_X | \ - R300_FPI1_DSTC_REG_Z ) -#define I1__YZ ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_Y | \ - R300_FPI1_DSTC_REG_Z ) -#define I1_X__ ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_X ) -#define I1__Y_ ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_Y ) -#define I1___Z ( R300_FPI1_SRC1C_CONST | \ - R300_FPI1_SRC2C_CONST | \ - R300_FPI1_DSTC_REG_Z ) - -#define SEMPTY {0,{0,0,0,0},{0,0,0,0,0,0,0,0}} - -struct r300_fragment_program_swizzle r300_swizzle [512] = { - /* XXX */ - {1,{0,0,0,0},{ I0_XXX, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* YXX */ - {2,{0,0,0,0},{ I0_YZX, I1_X_Z, - I0_XXX, I1__Y_, - 0,0, - 0,0 } }, - /* ZXX */ - {2,{0,0,0,0},{ I0_ZZZ, I1_X__, - I0_XXX, I1__YZ, - 0,0, - 0,0 } }, - /* WXX */ - {2,{0,0,0,0},{ I0_WZY, I1_X__, - I0_XXX, I1__YZ, - 0,0, - 0,0} }, - /* 0XX */ - {2,{0,2,0,0},{ I0_XXX, I1__YZ, - I0_000, I1_X__, - 0,0, - 0,0 } }, - /* 1XX */ - {2,{0,2,0,0},{ I0_XXX, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XYX */ - {2,{0,0,0,0},{ I0_YYY, I1__Y_, - I0_XXX, I1_X_Z, - 0,0,0,0}}, - /* YYX */ - {2,{0,0,0,0},{ I0_YYY, I1_XY_, - I0_XXX, I1___Z, - 0,0,0,0}}, - /* ZYX */ - {3,{0,0,0,0},{ I0_ZZZ, I1_X__, - I0_YYY, I1__Y_, - I0_XXX, I1___Z, - 0,0}}, - /* WYX */ - {3,{0,0,0,0},{ I0_WZY, I1_X__, - I0_YYY, I1__Y_, - I0_XXX, I1___Z, - 0,0}}, - /* 0YX */ - {3,{0,0,2,0},{ I0_YYY, I1__Y_, - I0_XXX, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1YX */ - {3,{0,0,2,0},{ I0_YYY, I1__Y_, - I0_XXX, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* XZX */ - {2,{0,0,0,0},{ I0_YZX, I1__YZ, - I0_XXX, I1_X__, - 0,0,0,0}}, - /* YZX */ - {1,{0,0,0,0},{ I0_YZX, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* ZZX */ - {2,{0,0,0,0},{ I0_YZX, I1__YZ, - I0_ZZZ, I1_X__,0,0,0,0}}, - /* WZX */ - {2,{0,0,0,0},{ I0_WZY, I1_XY_, - I0_XXX, I1___Z,0,0,0,0}}, - /* 0ZX */ - {2,{0,2,0,0},{ I0_YZX, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1ZX */ - {2,{0,2,0,0},{ I0_YZX, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XWX */ - {2,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_XXX, I1_X_Z, - 0,0,0,0}}, - /* YWX */ - {2,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_YZX, I1_X_Z, - 0,0,0,0}}, - /* ZWX */ - {3,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_ZZZ, I1_X__, - I0_XXX, I1___Z, - 0,0}}, - /* WWX */ - {2,{0,0,0,0},{ I0_WWW, I1_XY_, - I0_YZX, I1___Z, - 0,0,0,0}}, - /* 0WX */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_XXX, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1WX */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_XXX, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X0X */ - {2,{0,2,0,0},{ I0_XXX, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* Y0X */ - {2,{0,2,0,0},{ I0_YZX, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* Z0X */ - {3,{0,2,0,0},{ I0_XXX, I1___Z, - I0_000, I1__Y_, - I0_ZZZ, I1_X__, - 0,0}}, - /* W0X */ - {3,{0,0,2,0},{ I0_WZY, I1_XYZ, - I0_XXX, I1___Z, - I0_000, I1__Y_, - 0,0}}, - /* 00X */ - {2,{0,2,0,0},{ I0_XXX, I1___Z, - I0_000, I1_XY_, - 0,0,0,0}}, - /* 10X */ - {3,{0,2,0,0},{ I0_XXX, I1___Z, - I0_000, I1__Y_, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X1X */ - {2,{0,2,0,0},{ I0_XXX, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* Y1X */ - {2,{0,2,0,0},{ I0_YZX, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* Z1X */ - {3,{0,2,0,0},{ I0_XXX, I1___Z, - I0_111, I1__Y_, - I0_ZZZ, I1_X__, - 0,0}}, - /* W1X */ - {3,{0,0,2,0},{ I0_WZY, I1_XYZ, - I0_XXX, I1___Z, - I0_111, I1__Y_, - 0,0}}, - /* 01X */ - {3,{0,2,0,0},{ I0_XXX, I1___Z, - I0_111, I1__Y_, - I0_000, I1_X__, - 0,0}}, - /* 11X */ - {2,{0,2,0,0},{ I0_XXX, I1___Z, - I0_111, I1_XY_, - 0,0,0,0}}, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - /* XXY */ - {2,{0,0,0,0},{ I0_YYY, I1___Z, - I0_XXX, I1_XY_, - 0,0,0,0}}, - /* YXY */ - {2,{0,0,0,0},{ I0_YYY, I1_X_Z, - I0_XXX, I1__Y_, - 0,0,0,0}}, - /* ZXY */ - {1,{0,0,0,0},{ I0_ZXY, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* WXY */ - {2,{0,0,0,0},{ I0_WZY, I1_X__, - I0_ZXY, I1__YZ, - 0,0,0,0}}, - /* 0XY */ - {2,{0,0,0,0},{ I0_ZXY, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1XY */ - {2,{0,0,0,0},{ I0_ZXY, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XYY */ - {2,{0,0,0,0},{ I0_YYY, I1__YZ, - I0_XXX, I1_X__, - 0,0,0,0}}, - /* YYY */ - {1,{0,0,0,0},{ I0_YYY, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* ZYY */ - {2,{0,0,0,0},{ I0_YYY, I1__YZ, - I0_ZZZ, I1_X__, - 0,0,0,0}}, - /* WYY */ - {2,{0,0,0,0},{ I0_WZY, I1_XYZ, - I0_YYY, I1__YZ, - 0,0,0,0}}, - /* 0YY */ - {2,{0,0,0,0},{ I0_YYY, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1YY */ - {2,{0,0,0,0},{ I0_YYY, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XZY */ - {2,{0,0,0,0},{ I0_WZY, I1__YZ, - I0_XXX, I1_X__, - 0,0,0,0}}, - /* YZY */ - {2,{0,0,0,0},{ I0_WZY, I1__YZ, - I0_YYY, I1_X__, - 0,0,0,0}}, - /* ZZY */ - {2,{0,0,0,0},{ I0_WZY, I1__YZ, - I0_ZZZ, I1_X__, - 0,0,0,0}}, - /* WZY */ - {1,{0,0,0,0},{ I0_WZY, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* 0ZY */ - {2,{0,0,0,0},{ I0_WZY, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1ZY */ - {2,{0,0,0,0},{ I0_WZY, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XWY */ - {3,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_XXX, I1_X__, - I0_YYY, I1___Z, - 0,0}}, - /* YWY */ - {2,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_YYY, I1_X_Z, - 0,0,0,0}}, - /* ZWY */ - {2,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_ZXY, I1_X_Z, - 0,0,0,0}}, - /* WWY */ - {2,{0,0,0,0},{ I0_WWW, I1_XY_, - I0_ZXY, I1___Z, - 0,0,0,0}}, - /* 0WY */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_ZXY, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1WY */ - {3,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_ZXY, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X0Y */ - {3,{0,2,0,0},{ I0_XXX, I1_X__, - I0_000, I1__Y_, - I0_YYY, I1___Z, - 0,0}}, - /* Y0Y */ - {2,{0,2,0,0},{ I0_YYY, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* Z0Y */ - {2,{0,2,0,0},{ I0_ZXY, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* W0Y */ - {2,{0,2,0,0},{ I0_WZY, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* 00Y */ - {2,{0,2,0,0},{ I0_YYY, I1___Z, - I0_000, I1_XY_, - 0,0,0,0}}, - /* 10Y */ - {3,{0,2,0,0},{ I0_YYY, I1___Z, - I0_000, I1__Y_, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X1Y */ - {3,{0,2,0,0},{ I0_XXX, I1_X__, - I0_111, I1__Y_, - I0_YYY, I1___Z, - 0,0}}, - /* Y1Y */ - {2,{0,2,0,0},{ I0_YYY, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* Z1Y */ - {2,{0,2,0,0},{ I0_ZXY, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* W1Y */ - {3,{0,2,0,0},{ I0_WZY, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* 01Y */ - {3,{0,2,0,0},{ I0_YYY, I1___Z, - I0_111, I1__Y_, - I0_000, I1_X__, - 0,0}}, - /* 11Y */ - {2,{0,2,0,0},{ I0_YYY, I1___Z, - I0_111, I1_XY_, - 0,0,0,0}}, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - /* XXZ */ - {2,{0,0,0,0},{ I0_XXX, I1_XY_, - I0_ZZZ, I1___Z, - 0,0,0,0}}, - /* YXZ */ - {3,{0,0,0,0},{ I0_XXX, I1__Y_, - I0_YYY, I1_X__, - I0_ZZZ, I1___Z, - 0,0}}, - /* ZXZ */ - {2,{0,0,0,0},{ I0_XXX, I1__Y_, - I0_ZZZ, I1_X_Z, - 0,0,0,0}}, - /* WXZ */ - {3,{0,0,0,0},{ I0_WZY, I1_XYZ, - I0_XXX, I1__Y_, - I0_ZZZ, I1___Z, - 0,0}}, - /* 0XZ */ - {3,{0,0,2,0},{ I0_XXX, I1__Y_, - I0_ZZZ, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1XZ */ - {3,{0,0,2,0},{ I0_XXX, I1__Y_, - I0_ZZZ, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* XYZ */ - {1,{0,0,0,0},{ I0_XYZ, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* YYZ */ - {2,{0,0,0,0},{ I0_ZZZ, I1___Z, - I0_YYY, I1_XY_, - 0,0,0,0}}, - /* ZYZ */ - {2,{0,0,0,0},{ I0_ZZZ, I1_X_Z, - I0_YYY, I1__Y_, - 0,0,0,0}}, - /* WYZ */ - {2,{0,0,0,0},{ I0_WZY, I1_XYZ, - I0_XYZ, I1__YZ, - 0,0,0,0}}, - /* 0YZ */ - {2,{0,2,0,0},{ I0_XYZ, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1YZ */ - {2,{0,2,0,0},{ I0_XYZ, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XZZ */ - {2,{0,0,0,0},{ I0_ZZZ, I1__YZ, - I0_XXX, I1_X__, - 0,0,0,0}}, - /* YZZ */ - {2,{0,0,0,0},{ I0_ZZZ, I1__YZ, - I0_YYY, I1_X__, - 0,0,0,0}}, - /* ZZZ */ - {1,{0,0,0,0},{ I0_ZZZ, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* WZZ */ - {2,{0,0,0,0},{ I0_WZY, I1_XYZ, - I0_ZZZ, I1__YZ, - 0,0,0,0}}, - /* 0ZZ */ - {2,{0,2,0,0},{ I0_ZZZ, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1ZZ */ - {2,{0,2,0,0},{ I0_ZZZ, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XWZ */ - {2,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_XYZ, I1_X_Z, - 0,0,0,0}}, - /* YWZ */ - {3,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_YYY, I1_X__, - I0_XYZ, I1___Z, - 0,0}}, - /* ZWZ */ - {2,{0,0,0,0},{ I0_WWW, I1__Y_, - I0_ZZZ, I1_X_Z, - 0,0,0,0}}, - /* WWZ */ - {2,{0,0,0,0},{ I0_WWW, I1_XY_, - I0_XYZ, I1___Z, - 0,0,0,0}}, - /* 0WZ */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_XYZ, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1WZ */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_XYZ, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X0Z */ - {2,{0,2,0,0},{ I0_XYZ, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* Y0Z */ - {3,{0,2,0,0},{ I0_ZZZ, I1___Z, - I0_000, I1__Y_, - I0_YYY, I1_X__, - 0,0}}, - /* Z0Z */ - {2,{0,2,0,0},{ I0_ZZZ, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* W0Z */ - {3,{0,0,2,0},{ I0_WZY, I1_X_Z, - I0_ZZZ, I1___Z, - I0_000, I1__Y_, - 0,0}}, - /* 00Z */ - {2,{0,2,0,0},{ I0_ZZZ, I1___Z, - I0_000, I1_XY_, - 0,0,0,0}}, - /* 10Z */ - {3,{0,2,2,0},{ I0_ZZZ, I1___Z, - I0_000, I1__Y_, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X1Z */ - {2,{0,2,0,0},{ I0_XYZ, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* Y1Z */ - {3,{0,2,0,0},{ I0_ZZZ, I1___Z, - I0_111, I1__Y_, - I0_YYY, I1_X__, - 0,0}}, - /* Z1Z */ - {2,{0,2,0,0},{ I0_ZZZ, I1_X_Z, - I0_111, I1__Y_, - 0,0,0,0}}, - /* W1Z */ - {3,{0,0,2,0},{ I0_WZY, I1_XYZ, - I0_ZZZ, I1___Z, - I0_111, I1__Y_, - 0,0}}, - /* 01Z */ - {3,{0,2,2,0},{ I0_ZZZ, I1___Z, - I0_111, I1__Y_, - I0_000, I1_X__, - 0,0}}, - /* 11Z */ - {2,{0,2,0,0},{ I0_ZZZ, I1___Z, - I0_111, I1_XY_, - 0,0,0,0}}, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - /* XXW */ - {2,{0,0,0,0},{ I0_WWW, I1___Z, - I0_XXX, I1_XY_, - 0,0,0,0}}, - /* YXW */ - {3,{0,0,0,0},{ I0_WWW, I1___Z, - I0_XXX, I1__Y_, - I0_YYY, I1_X__, - 0,0}}, - /* ZXW */ - {2,{0,0,0,0},{ I0_WWW, I1___Z, - I0_ZXY, I1_XY_, - 0,0,0,0}}, - /* WXW */ - {2,{0,0,0,0},{ I0_WWW, I1_X_Z, - I0_XXX, I1__Y_, - 0,0,0,0}}, - /* 0XW */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_XXX, I1__Y_, - I0_000, I1_X__, - 0,0}}, - /* 1XW */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_XXX, I1__Y_, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* XYW */ - {2,{0,0,0,0},{ I0_WWW, I1___Z, - I0_XYZ, I1_XY_, - 0,0,0,0}}, - /* YYW */ - {2,{0,0,0,0},{ I0_WWW, I1___Z, - I0_YYY, I1_XY_, - 0,0}}, - /* ZYW */ - {3,{0,0,0,0},{ I0_WWW, I1___Z, - I0_XYZ, I1__Y_, - I0_ZZZ, I1_X__, - 0,0}}, - /* WYW */ - {2,{0,0,0,0},{ I0_WWW, I1_X_Z, - I0_YYY, I1__Y_, - 0,0,0,0}}, - /* 0YW */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_YYY, I1__Y_, - I0_000, I1_X__, - 0,0}}, - /* 1YW */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_YYY, I1__Y_, - I0_111, I1_X__, - 0,0}}, - - SEMPTY,SEMPTY, - /* XZW */ - {3,{0,0,0,0},{ I0_WWW, I1___Z, - I0_XYZ, I1_X__, - I0_ZZZ, I1__Y_, - 0,0}}, - /* YZW */ - {2,{0,0,0,0},{ I0_WWW, I1___Z, - I0_YZX, I1_XY_, - 0,0,0,0}}, - /* ZZW */ - {2,{0,0,0,0},{ I0_WWW, I1___Z, - I0_ZZZ, I1_XY_, - 0,0,0,0}}, - /* WZW */ - {2,{0,0,0,0},{ I0_WWW, I1_X_Z, - I0_ZZZ, I1__Y_, - 0,0,0,0}}, - /* 0ZW */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_ZZZ, I1__Y_, - I0_000, I1_X__, - 0,0}}, - /* 1ZW */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_ZZZ, I1__Y_, - I0_111, I1_X__, - 0,0}}, - - SEMPTY,SEMPTY, - /* XWW */ - {2,{0,0,0,0},{ I0_WWW, I1__YZ, - I0_XYZ, I1_X__, - 0,0,0,0}}, - /* YWW */ - {2,{0,0,0,0},{ I0_WWW, I1__YZ, - I0_YYY, I1_X__, - 0,0,0,0}}, - /* ZWW */ - {2,{0,0,0,0},{ I0_WWW, I1__YZ, - I0_ZZZ, I1_X__, - 0,0,0,0}}, - /* WWW */ - {1,{0,0,0,0},{ I0_WWW, I1_XYZ, - 0,0,0,0,0,0}}, - /* 0WW */ - {2,{0,2,0,0},{ I0_WWW, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 1WW */ - {2,{0,2,0,0},{ I0_WWW, I1__YZ, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X0W */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_XYZ, I1_X__, - I0_000, I1__Y_, - 0,0}}, - /* Y0W */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_YYY, I1_X__, - I0_000, I1__Y_, - 0,0}}, - /* Z0W */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_ZZZ, I1_X__, - I0_000, I1__Y_, - 0,0}}, - /* W0W */ - {2,{0,2,0,0},{ I0_WWW, I1_X_Z, - I0_000, I1__Y_, - 0,0,0,0}}, - /* 00W */ - {2,{0,2,0,0},{ I0_WWW, I1___Z, - I0_000, I1_XY_, - 0,0,0,0}}, - /* 10W */ - {3,{0,2,2,0},{ I0_WWW, I1___Z, - I0_111, I1_X__, - I0_000, I1__Y_, - 0,0}}, - SEMPTY,SEMPTY, - /* X1W */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_XYZ, I1_X__, - I0_111, I1__Y_, - 0,0}}, - /* Y1W */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_YYY, I1_X__, - I0_111, I1__Y_, - 0,0}}, - /* Z1W */ - {3,{0,0,2,0},{ I0_WWW, I1___Z, - I0_ZZZ, I1_X__, - I0_111, I1__Y_, - 0,0}}, - /* W1W */ - {2,{0,2,0,0},{ I0_WWW, I1_XYZ, - I0_111, I1__Y_, - 0,0,0,0}}, - /* 01W */ - {3,{0,2,2,0},{ I0_WWW, I1___Z, - I0_000, I1_X__, - I0_111, I1__Y_, - 0,0}}, - /* 11W */ - {2,{0,2,0,0},{ I0_WWW, I1___Z, - I0_111, I1_XY_, - 0,0,0,0}}, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - /* XX0 */ - {2,{0,2,0,0},{ I0_XXX, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* YX0 */ - {3,{0,0,2,0},{ I0_YYY, I1_X__, - I0_XXX, I1__Y_, - I0_000, I1___Z, - 0,0}}, - /* ZX0 */ - {2,{0,2,0,0},{ I0_ZXY, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* WX0 */ - {3,{0,0,2,0},{ I0_WZY, I1_X__, - I0_XXX, I1__Y_, - I0_000, I1___Z, - 0,0}}, - /* 0X0 */ - {2,{0,2,0,0},{ I0_XXX, I1__Y_, - I0_000, I1_X_Z, - 0,0,0,0}}, - /* 1X0 */ - {3,{0,2,2,0},{ I0_XXX, I1__Y_, - I0_000, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* XY0 */ - {2,{0,2,0,0},{ I0_XYZ, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* YY0 */ - {2,{0,2,0,0},{ I0_YYY, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* ZY0 */ - {3,{0,0,2,0},{ I0_YYY, I1__Y_, - I0_ZZZ, I1_X__, - I0_000, I1___Z, - 0,0}}, - /* WY0 */ - {3,{0,0,2,0},{ I0_WZY, I1_X__, - I0_XYZ, I1__Y_, - I0_000, I1___Z, - 0,0}}, - /* 0Y0 */ - {2,{0,2,0,0},{ I0_XYZ, I1__Y_, - I0_000, I1_X_Z, - 0,0,0,0}}, - /* 1Y0 */ - {3,{0,2,2,0},{ I0_XYZ, I1__Y_, - I0_000, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* XZ0 */ - {3,{0,0,2,0},{ I0_ZZZ, I1__Y_, - I0_XYZ, I1_X__, - I0_000, I1___Z, - 0,0}}, - /* YZ0 */ - {2,{0,2,0,0},{ I0_YZX, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* ZZ0 */ - {2,{0,2,0,0},{ I0_ZZZ, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* WZ0 */ - {3,{0,0,2,0},{ I0_XYZ, I1_XYZ, - I0_WZY, I1_XY_, - I0_000, I1___Z, - 0,0}}, - /* 0Z0 */ - {2,{0,2,0,0},{ I0_ZZZ, I1__Y_, - I0_000, I1_X_Z, - 0,0,0,0}}, - /* 1Z0 */ - {3,{0,2,2,0},{ I0_ZZZ, I1__Y_, - I0_000, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* XW0 */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_XYZ, I1_X__, - I0_000, I1___Z, - 0,0}}, - /* YW0 */ - {3,{0,2,0,0},{ I0_WWW, I1__Y_, - I0_000, I1___Z, - I0_YYY, I1_X__, - 0,0}}, - /* ZW0 */ - {3,{0,2,0,0},{ I0_WWW, I1__Y_, - I0_000, I1___Z, - I0_ZZZ, I1_X__, - 0,0}}, - /* WW0 */ - {2,{0,2,0,0},{ I0_WWW, I1_XY_, - I0_000, I1___Z, - 0,0,0,0}}, - /* 0W0 */ - {2,{0,2,0,0},{ I0_WWW, I1__Y_, - I0_000, I1_X_Z, - 0,0,0,0}}, - /* 1W0 */ - {3,{0,2,2,0},{ I0_WWW, I1__Y_, - I0_000, I1___Z, - I0_111, I1_X__, - 0,0}}, - SEMPTY,SEMPTY, - /* X00 */ - {2,{0,2,0,0},{ I0_XYZ, I1_X__, - I0_000, I1__YZ, - 0,0,0,0}}, - /* Y00 */ - {2,{0,2,0,0},{ I0_YYY, I1_X__, - I0_000, I1__YZ, - 0,0,0,0}}, - /* Z00 */ - {2,{0,2,0,0},{ I0_ZZZ, I1_X__, - I0_000, I1__YZ, - 0,0,0,0}}, - /* W00 */ - {2,{2,0,0,0},{ I0_WZY, I1_X__, - I0_000, I1__YZ, - 0,0,0,0}}, - /* 000 */ - {1,{2,0,0,0},{ I0_000, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - /* 100 */ - {2,{2,2,0,0},{ I0_000, I1__YZ, - I0_111, I1_X__, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* X10 */ - {3,{0,2,2,0},{ I0_XYZ, I1_XYZ, - I0_000, I1___Z, - I0_111, I1__Y_, - 0,0}}, - /* Y10 */ - {3,{0,2,2,0},{ I0_YYY, I1_XYZ, - I0_000, I1___Z, - I0_111, I1__Y_, - 0,0}}, - /* Z10 */ - {3,{0,2,2,0},{ I0_ZZZ, I1_XYZ, - I0_000, I1___Z, - I0_111, I1__Y_, - 0,0}}, - /* W10 */ - {3,{0,2,2,0},{ I0_WZY, I1_XYZ, - I0_000, I1___Z, - I0_111, I1__Y_, - 0,0}}, - /* 010 */ - {2,{2,2,0,0},{ I0_000, I1_X_Z, - I0_111, I1__Y_, - 0, 0, 0, 0 } }, - /* 110 */ - {2,{2,2,0,0},{ I0_000, I1___Z, - I0_111, I1_XY_, - 0,0,0,0}}, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - - - - /* XX1 */ - {2,{0,2,0,0},{ I0_XXX, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* YX1 */ - {3,{0,0,2,0},{ I0_YYY, I1_X__, - I0_XXX, I1__Y_, - I0_111, I1___Z, - 0,0}}, - /* ZX1 */ - {2,{0,2,0,0},{ I0_ZXY, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* WX1 */ - {3,{0,0,2,0},{ I0_WZY, I1_XYZ, - I0_XXX, I1__Y_, - I0_111, I1___Z, - 0,0}}, - /* 0X1 */ - {3,{0,2,2,0},{ I0_XXX, I1__Y_, - I0_111, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1X1 */ - {2,{0,2,0,0},{ I0_XXX, I1__Y_, - I0_111, I1_X_Z, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XY1 */ - {2,{0,2,0,0},{ I0_XYZ, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* YY1 */ - {2,{0,2,0,0},{ I0_YYY, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* ZY1 */ - {3,{0,0,2,0},{ I0_YYY, I1__Y_, - I0_ZZZ, I1_X__, - I0_111, I1___Z, - 0,0}}, - /* WY1 */ - {3,{0,0,2,0},{ I0_WZY, I1_XYZ, - I0_XYZ, I1__Y_, - I0_111, I1___Z, - 0,0}}, - /* 0Y1 */ - {3,{0,2,2,0},{ I0_XYZ, I1__Y_, - I0_111, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1Y1 */ - {2,{0,2,0,0},{ I0_XYZ, I1__Y_, - I0_111, I1_X_Z, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XZ1 */ - {3,{0,0,2,0},{ I0_ZZZ, I1__Y_, - I0_XYZ, I1_X__, - I0_111, I1___Z, - 0,0}}, - /* YZ1 */ - {2,{0,2,0,0},{ I0_YZX, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* ZZ1 */ - {2,{0,2,0,0},{ I0_ZZZ, I1_XYZ, - I0_111, I1___Z, - 0,0,0,0}}, - /* WZ1 */ - {2,{0,2,0,0},{ I0_WZY, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* 0Z1 */ - {3,{0,2,2,0},{ I0_ZZZ, I1_XYZ, - I0_111, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1Z1 */ - {2,{0,2,0,0},{ I0_ZZZ, I1__Y_, - I0_111, I1_X_Z, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* XW1 */ - {3,{0,0,2,0},{ I0_WWW, I1__Y_, - I0_XYZ, I1_X__, - I0_111, I1___Z, - 0,0}}, - /* YW1 */ - {3,{0,2,0,0},{ I0_WWW, I1__Y_, - I0_111, I1___Z, - I0_YYY, I1_X__, - 0,0}}, - /* ZW1 */ - {3,{0,2,0,0},{ I0_WWW, I1__Y_, - I0_111, I1___Z, - I0_ZZZ, I1_X__, - 0,0}}, - /* WW1 */ - {2,{0,2,0,0},{ I0_WWW, I1_XY_, - I0_111, I1___Z, - 0,0,0,0}}, - /* 0W1 */ - {3,{0,2,2,0},{ I0_WWW, I1__Y_, - I0_111, I1___Z, - I0_000, I1_X__, - 0,0}}, - /* 1W1 */ - {2,{0,2,0,0},{ I0_WWW, I1__Y_, - I0_111, I1_X_Z, - 0,0,0,0}}, - SEMPTY,SEMPTY, - /* X01 */ - {3,{0,2,2,0},{ I0_XYZ, I1_X__, - I0_111, I1___Z, - I0_000, I1__Y_, - 0,0}}, - /* Y01 */ - {3,{0,2,2,0},{ I0_YYY, I1_X__, - I0_111, I1___Z, - I0_000, I1__Y_, - 0,0}}, - /* Z01 */ - {3,{0,2,2,0},{ I0_ZZZ, I1_X__, - I0_111, I1___Z, - I0_000, I1__Y_, - 0,0}}, - /* W01 */ - {3,{0,2,2,0},{ I0_WZY, I1_XYZ, - I0_111, I1___Z, - I0_000, I1__Y_, - 0,0}}, - /* 001 */ - {2,{2,2,0,0},{ I0_111, I1___Z, - I0_000, I1_XY_, - 0,0,0,0}}, - /* 101 */ - {2,{2,2,0,0},{ I0_111, I1_X_Z, - I0_000, I1__Y_, - 0, 0, 0, 0 } }, - SEMPTY,SEMPTY, - /* X11 */ - {2,{0,2,0,0},{ I0_XYZ, I1_X__, - I0_111, I1__YZ, - 0,0,0,0}}, - /* Y11 */ - {2,{0,2,0,0},{ I0_YYY, I1_X__, - I0_111, I1__YZ, - 0,0,0,0}}, - /* Z11 */ - {2,{0,2,0,0},{ I0_ZZZ, I1_X__, - I0_111, I1__YZ, - 0,0,0,0}}, - /* W11 */ - {2,{0,2,0,0},{ I0_WZY, I1_XYZ, - I0_111, I1__YZ, - 0,0,0,0}}, - /* 011 */ - {2,{2,2,0,0},{ I0_111, I1__YZ, - I0_000, I1_X__, - 0,0,0,0}}, - /* 111 */ - {1,{2,0,0,0},{ I0_111, I1_XYZ, - 0, 0, 0, 0, 0, 0 } }, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY, - SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY,SEMPTY -}; - -/****************************************************************************** -* Color source mask table -******************************************************************************/ - -#define S_111 R300_FPI0_ARGC_ONE -#define S_000 R300_FPI0_ARGC_ZERO - -#define S0XXX R300_FPI0_ARGC_SRC0C_XXX -#define S0YYY R300_FPI0_ARGC_SRC0C_YYY -#define S0ZZZ R300_FPI0_ARGC_SRC0C_ZZZ -#define S0WWW R300_FPI0_ARGC_SRC0A -#define S0XYZ R300_FPI0_ARGC_SRC0C_XYZ -#define S0ZXY R300_FPI0_ARGC_SRC0C_ZXY -#define S0YZX R300_FPI0_ARGC_SRC0C_YZX -#define S0WZY R300_FPI0_ARGC_SRC0CA_WZY -#define S0WZY R300_FPI0_ARGC_SRC0CA_WZY - -#define S1XXX R300_FPI0_ARGC_SRC1C_XXX -#define S1YYY R300_FPI0_ARGC_SRC1C_YYY -#define S1ZZZ R300_FPI0_ARGC_SRC1C_ZZZ -#define S1WWW R300_FPI0_ARGC_SRC1A -#define S1XYZ R300_FPI0_ARGC_SRC1C_XYZ -#define S1ZXY R300_FPI0_ARGC_SRC1C_ZXY -#define S1YZX R300_FPI0_ARGC_SRC1C_YZX -#define S1WZY R300_FPI0_ARGC_SRC1CA_WZY - -#define S2XXX R300_FPI0_ARGC_SRC2C_XXX -#define S2YYY R300_FPI0_ARGC_SRC2C_YYY -#define S2ZZZ R300_FPI0_ARGC_SRC2C_ZZZ -#define S2WWW R300_FPI0_ARGC_SRC2A -#define S2XYZ R300_FPI0_ARGC_SRC2C_XYZ -#define S2ZXY R300_FPI0_ARGC_SRC2C_ZXY -#define S2YZX R300_FPI0_ARGC_SRC2C_YZX -#define S2WZY R300_FPI0_ARGC_SRC2CA_WZY - -#define ntnat 32 - -const GLuint r300_swz_srcc_mask[3][512] = { - { - S0XXX,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S0YZX,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S0ZXY,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,S0YYY,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,S0WZY,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S0XYZ,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S0ZZZ,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S0WWW, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,S_000,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,S_111,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat - }, - { - S1XXX,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S1YZX,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S1ZXY,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,S1YYY,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,S1WZY,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S1XYZ,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S1ZZZ,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S1WWW, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,S_000,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,S_111,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat - }, - { - S2XXX,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S2YZX,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S2ZXY,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,S2YYY,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,S2WZY,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S2XYZ,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S2ZZZ,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,S2WWW, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,S_000,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,S_111,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat,ntnat, - ntnat,ntnat - } -}; - -/****************************************************************************** -* Alpha source mask table -******************************************************************************/ - -GLuint r300_swz_srca_mask[3][6] = { - { R300_FPI2_ARGA_SRC0C_X, - R300_FPI2_ARGA_SRC0C_Y, - R300_FPI2_ARGA_SRC0C_Z, - R300_FPI2_ARGA_SRC0A, - R300_FPI2_ARGA_ZERO, - R300_FPI2_ARGA_ONE }, - { R300_FPI2_ARGA_SRC1C_X, - R300_FPI2_ARGA_SRC1C_Y, - R300_FPI2_ARGA_SRC1C_Z, - R300_FPI2_ARGA_SRC1A, - R300_FPI2_ARGA_ZERO, - R300_FPI2_ARGA_ONE }, - { R300_FPI2_ARGA_SRC2C_X, - R300_FPI2_ARGA_SRC2C_Y, - R300_FPI2_ARGA_SRC2C_Z, - R300_FPI2_ARGA_SRC2A, - R300_FPI2_ARGA_ZERO, - R300_FPI2_ARGA_ONE }, -}; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 03f168365d..211c451f66 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -42,7 +42,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "api_arrayelt.h" #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" -#include "array_cache/acache.h" +#include "vbo/vbo.h" #include "tnl/tnl.h" #include "tnl/t_vp_build.h" @@ -352,7 +352,7 @@ GLboolean r300_run_vb_render(GLcontext *ctx, r300EmitState(rmesa); for(i=0; i < VB->PrimitiveCount; i++){ - GLuint prim = VB->Primitive[i].mode; + GLuint prim = _tnl_translate_prim(&VB->Primitive[i]); GLuint start = VB->Primitive[i].start; GLuint length = VB->Primitive[i].count; @@ -385,8 +385,18 @@ GLboolean r300_run_vb_render(GLcontext *ctx, int r300Fallback(GLcontext *ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_fragment_program *rp = + (struct r300_fragment_program *) + (char *)ctx->FragmentProgram._Current; int i; + if (rp) { + if (!rp->translated) + r300_translate_fragment_shader(r300, rp); + + FALLBACK_IF(!rp->translated); + } + /* We do not do SELECT or FEEDBACK (yet ?) * Is it worth doing them ? */ @@ -406,6 +416,10 @@ int r300Fallback(GLcontext *ctx) */ FALLBACK_IF(ctx->Fog.Enabled); #endif + FALLBACK_IF(ctx->Stencil._TestTwoSide && + (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[1] || + ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[1] || + ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[1])); if(!r300->disable_lowimpact_fallback){ /* GL_POLYGON_OFFSET_POINT */ diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 72255066d5..906dfceb48 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -46,7 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "api_arrayelt.h" #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" -#include "array_cache/acache.h" +#include "vbo/vbo.h" #include "tnl/tnl.h" #include "texformat.h" @@ -509,7 +509,6 @@ static void r300Enable(GLcontext* ctx, GLenum cap, GLboolean state) if (r300->state.stencil.hw_stencil) { R300_STATECHANGE(r300, zs); if (state) { - WARN_ONCE("TODO - double side stencil !\n"); r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_RB3D_STENCIL_ENABLE; } else { @@ -863,9 +862,12 @@ static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face, (R300_RB3D_ZS2_STENCIL_MASK << R300_RB3D_ZS2_STENCIL_MASK_SHIFT)); flag = translate_func(ctx->Stencil.Function[0]); - - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= (flag << R300_RB3D_ZS1_FRONT_FUNC_SHIFT) - | (flag << R300_RB3D_ZS1_BACK_FUNC_SHIFT); + rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= (flag << R300_RB3D_ZS1_FRONT_FUNC_SHIFT); + + if (ctx->Stencil._TestTwoSide) + flag = translate_func(ctx->Stencil.Function[1]); + + rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= (flag << R300_RB3D_ZS1_BACK_FUNC_SHIFT); rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask; } @@ -894,10 +896,19 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, GLenum fail, rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= (translate_stencil_op(ctx->Stencil.FailFunc[0]) << R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT) |(translate_stencil_op(ctx->Stencil.ZFailFunc[0]) << R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT) - |(translate_stencil_op(ctx->Stencil.ZPassFunc[0]) << R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT) - |(translate_stencil_op(ctx->Stencil.FailFunc[0]) << R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT) - |(translate_stencil_op(ctx->Stencil.ZFailFunc[0]) << R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT) - |(translate_stencil_op(ctx->Stencil.ZPassFunc[0]) << R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT); + |(translate_stencil_op(ctx->Stencil.ZPassFunc[0]) << R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT); + + if (ctx->Stencil._TestTwoSide) { + rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= + (translate_stencil_op(ctx->Stencil.FailFunc[1]) << R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT) + |(translate_stencil_op(ctx->Stencil.ZFailFunc[1]) << R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT) + |(translate_stencil_op(ctx->Stencil.ZPassFunc[1]) << R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT); + } else { + rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= + (translate_stencil_op(ctx->Stencil.FailFunc[0]) << R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT) + |(translate_stencil_op(ctx->Stencil.ZFailFunc[0]) << R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT) + |(translate_stencil_op(ctx->Stencil.ZPassFunc[0]) << R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT); + } } static void r300ClearStencil(GLcontext * ctx, GLint s) @@ -1809,10 +1820,10 @@ void r300SetupPixelShader(r300ContextPtr rmesa) if (!rp) /* should only happenen once, just after context is created */ return; - r300_translate_fragment_shader(rp); + r300_translate_fragment_shader(rmesa, rp); if (!rp->translated) { fprintf(stderr, "%s: No valid fragment shader, exiting\n", __func__); - exit(-1); + return; } #define OUTPUT_FIELD(st, reg, field) \ @@ -1874,7 +1885,7 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) _swrast_InvalidateState(ctx, new_state); _swsetup_InvalidateState(ctx, new_state); - _ac_InvalidateState(ctx, new_state); + _vbo_InvalidateState(ctx, new_state); _tnl_InvalidateState(ctx, new_state); _ae_invalidate_state(ctx, new_state); diff --git a/src/mesa/drivers/dri/r300/r300_vertexprog.c b/src/mesa/drivers/dri/r300/r300_vertexprog.c index 2492a4a3a0..2ff92e1328 100644 --- a/src/mesa/drivers/dri/r300/r300_vertexprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertexprog.c @@ -960,26 +960,23 @@ static void position_invariant(struct gl_program *prog) static void insert_wpos(struct r300_vertex_program *vp, struct gl_program *prog, - GLint pos) + GLuint temp_index) { GLint tokens[6] = { STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0, 0 }; struct prog_instruction *vpi; struct prog_instruction *vpi_insert; - GLuint temp_index; GLuint window_index; int i = 0; vpi = malloc((prog->NumInstructions + 5) * sizeof(struct prog_instruction)); - memcpy(vpi, prog->Instructions, (pos+1) * sizeof(struct prog_instruction)); + /* all but END */ + memcpy(vpi, prog->Instructions, (prog->NumInstructions - 1) * sizeof(struct prog_instruction)); + /* END */ + memcpy(&vpi[prog->NumInstructions + 4], &prog->Instructions[prog->NumInstructions - 1], + sizeof(struct prog_instruction)); - vpi_insert = &vpi[pos]; - - /* make a copy before outputting VERT_RESULT_HPOS */ - vpi_insert->DstReg.File = vpi_insert->SrcReg[2].File; - vpi_insert->DstReg.Index = temp_index = vpi_insert->SrcReg[2].Index; - - vpi_insert++; + vpi_insert = &vpi[prog->NumInstructions - 1]; memset(vpi_insert, 0, 5 * sizeof(struct prog_instruction)); vpi_insert[i].Opcode = OPCODE_MOV; @@ -1062,8 +1059,6 @@ static void insert_wpos(struct r300_vertex_program *vp, vpi_insert[i].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ONE, SWIZZLE_ONE); i++; - memcpy(&vpi_insert[i], &prog->Instructions[pos+1], (prog->NumInstructions-(pos+1)) * sizeof(struct prog_instruction)); - free(prog->Instructions); prog->Instructions = vpi; @@ -1078,16 +1073,18 @@ static void pos_as_texcoord(struct r300_vertex_program *vp, struct gl_program *prog) { struct prog_instruction *vpi; - int pos = 0; - - for(vpi = prog->Instructions; vpi->Opcode != OPCODE_END; vpi++, pos++){ + GLuint tempregi = prog->NumTemporaries; + /* should do something else if no temps left... */ + prog->NumTemporaries++; + + for(vpi = prog->Instructions; vpi->Opcode != OPCODE_END; vpi++){ if( vpi->DstReg.File == PROGRAM_OUTPUT && vpi->DstReg.Index == VERT_RESULT_HPOS ){ - insert_wpos(vp, prog, pos); - break; + vpi->DstReg.File = PROGRAM_TEMPORARY; + vpi->DstReg.Index = tempregi; } } - + insert_wpos(vp, prog, tempregi); } static struct r300_vertex_program *build_program(struct r300_vertex_program_key *wanted_key, @@ -1101,8 +1098,9 @@ static struct r300_vertex_program *build_program(struct r300_vertex_program_key vp->wpos_idx = wpos_idx; - if(mesa_vp->IsPositionInvariant) + if(mesa_vp->IsPositionInvariant) { position_invariant(&mesa_vp->Base); + } if(wpos_idx > -1) pos_as_texcoord(vp, &mesa_vp->Base); @@ -1158,6 +1156,10 @@ void r300_select_vertex_shader(r300ContextPtr r300) wanted_key.OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); wanted_key.InputsRead = vpc->mesa_program.Base.InputsRead; + if(vpc->mesa_program.IsPositionInvariant) { + /* we wan't position don't we ? */ + wanted_key.InputsRead |= (1 << VERT_ATTRIB_POS); + } for (vp = vpc->progs; vp; vp = vp->next) if (_mesa_memcmp(&vp->key, &wanted_key, sizeof(wanted_key)) == 0) { @@ -1170,6 +1172,5 @@ void r300_select_vertex_shader(r300ContextPtr r300) vp = build_program(&wanted_key, &vpc->mesa_program, wpos_idx); vp->next = vpc->progs; vpc->progs = vp; - r300->selected_vp = vp; } diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c index 0ceaf7ebb7..ddadf83a00 100644 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ b/src/mesa/drivers/dri/r300/radeon_state.c @@ -41,7 +41,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "light.h" #include "swrast/swrast.h" -#include "array_cache/acache.h" +#include "vbo/vbo.h" #include "tnl/tnl.h" #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" diff --git a/src/mesa/drivers/dri/r300/radeon_vtxfmt_a.c b/src/mesa/drivers/dri/r300/radeon_vtxfmt_a.c index 72c03c53ad..0625e5bc57 100644 --- a/src/mesa/drivers/dri/r300/radeon_vtxfmt_a.c +++ b/src/mesa/drivers/dri/r300/radeon_vtxfmt_a.c @@ -46,6 +46,8 @@ #include "state.h" #include "image.h" +#include "vbo/vbo_context.h" + #define CONV_VB(a, b) rvb->AttribPtr[(a)].size = vb->b->size, \ rvb->AttribPtr[(a)].type = GL_FLOAT, \ rvb->AttribPtr[(a)].stride = vb->b->stride, \ @@ -129,15 +131,7 @@ static int setup_arrays(r300ContextPtr rmesa, GLint start) CONV(i, VertexAttrib[i]); for (i=0; i < VERT_ATTRIB_MAX; i++) { - if (enabled & (1 << i)) { - rmesa->state.VB.AttribPtr[i].data += rmesa->state.VB.AttribPtr[i].stride * start; - } else { - def.data = ctx->Current.Attrib[i]; - memcpy(&rmesa->state.VB.AttribPtr[i], &def, sizeof(struct dt)); - } - - /*if(rmesa->state.VB.AttribPtr[i].data == ctx->Current.Attrib[i]) - fprintf(stderr, "%d is default coord\n", i);*/ + rmesa->state.VB.AttribPtr[i].data += rmesa->state.VB.AttribPtr[i].stride * start; } for(i=0; i < VERT_ATTRIB_MAX; i++){ @@ -177,177 +171,18 @@ static int setup_arrays(r300ContextPtr rmesa, GLint start) void radeon_init_vtxfmt_a(r300ContextPtr rmesa); -static void radeonDrawElements( GLenum mode, GLsizei count, GLenum type, const GLvoid *c_indices ) -{ - GET_CURRENT_CONTEXT(ctx); - r300ContextPtr rmesa = R300_CONTEXT(ctx); - int elt_size; - int i; - unsigned int min = ~0, max = 0; - struct tnl_prim prim; - static void *ptr = NULL; - struct r300_dma_region rvb; - const GLvoid *indices = c_indices; - - if (count > 65535) { - WARN_ONCE("Too many verts!\n"); - goto fallback; - } - - if (ctx->Array.ElementArrayBufferObj->Name) { - /* use indices in the buffer object */ - if (!ctx->Array.ElementArrayBufferObj->Data) { - _mesa_warning(ctx, "DrawRangeElements with empty vertex elements buffer!"); - return; - } - /* actual address is the sum of pointers */ - indices = (GLvoid *) - ADD_POINTERS(ctx->Array.ElementArrayBufferObj->Data, (const GLubyte *) c_indices); - } - - if (!_mesa_validate_DrawElements( ctx, mode, count, type, indices )) - return; - - FLUSH_CURRENT( ctx, 0 ); - - memset(&rvb, 0, sizeof(rvb)); - switch (type) { - case GL_UNSIGNED_BYTE: - for (i=0; i < count; i++) { - if(((unsigned char *)indices)[i] < min) - min = ((unsigned char *)indices)[i]; - if(((unsigned char *)indices)[i] > max) - max = ((unsigned char *)indices)[i]; - } - -#ifdef FORCE_32BITS_ELTS - elt_size = 4; -#else - elt_size = 2; -#endif - r300AllocDmaRegion(rmesa, &rvb, count * elt_size, elt_size); - rvb.aos_offset = GET_START(&rvb); - ptr = rvb.address + rvb.start; - -#ifdef FORCE_32BITS_ELTS - for (i=0; i < count; i++) - ((unsigned int *)ptr)[i] = ((unsigned char *)indices)[i] - min; -#else - for (i=0; i < count; i++) - ((unsigned short int *)ptr)[i] = ((unsigned char *)indices)[i] - min; -#endif - break; - - case GL_UNSIGNED_SHORT: - for (i=0; i < count; i++) { - if(((unsigned short int *)indices)[i] < min) - min = ((unsigned short int *)indices)[i]; - if(((unsigned short int *)indices)[i] > max) - max = ((unsigned short int *)indices)[i]; - } - -#ifdef FORCE_32BITS_ELTS - elt_size = 4; -#else - elt_size = 2; -#endif - - r300AllocDmaRegion(rmesa, &rvb, count * elt_size, elt_size); - rvb.aos_offset = GET_START(&rvb); - ptr = rvb.address + rvb.start; - -#ifdef FORCE_32BITS_ELTS - for (i=0; i < count; i++) - ((unsigned int *)ptr)[i] = ((unsigned short int *)indices)[i] - min; -#else - for (i=0; i < count; i++) - ((unsigned short int *)ptr)[i] = ((unsigned short int *)indices)[i] - min; -#endif - break; - - case GL_UNSIGNED_INT: - for (i=0; i < count; i++) { - if(((unsigned int *)indices)[i] < min) - min = ((unsigned int *)indices)[i]; - if(((unsigned int *)indices)[i] > max) - max = ((unsigned int *)indices)[i]; - } - -#ifdef FORCE_32BITS_ELTS - elt_size = 4; -#else - if (max - min <= 65535) - elt_size = 2; - else - elt_size = 4; -#endif - r300AllocDmaRegion(rmesa, &rvb, count * elt_size, elt_size); - rvb.aos_offset = GET_START(&rvb); - ptr = rvb.address + rvb.start; - - - if (elt_size == 2) - for (i=0; i < count; i++) - ((unsigned short int *)ptr)[i] = ((unsigned int *)indices)[i] - min; - else - for (i=0; i < count; i++) - ((unsigned int *)ptr)[i] = ((unsigned int *)indices)[i] - min; - break; - - default: - WARN_ONCE("Unknown elt type!\n"); - goto fallback; - } - - if (ctx->NewState) - _mesa_update_state( ctx ); - - r300UpdateShaders(rmesa); - - if (setup_arrays(rmesa, min) >= R300_FALLBACK_TCL) { - r300ReleaseDmaRegion(rmesa, &rvb, __FUNCTION__); - goto fallback; - } - - rmesa->state.VB.Count = max - min + 1; - - r300UpdateShaderStates(rmesa); - - rmesa->state.VB.Primitive = &prim; - rmesa->state.VB.PrimitiveCount = 1; - - prim.mode = mode | PRIM_BEGIN | PRIM_END; - if (rmesa->state.VB.LockCount) - prim.start = min - rmesa->state.VB.LockFirst; - else - prim.start = 0; - prim.count = count; - - rmesa->state.VB.Elts = ptr; - rmesa->state.VB.elt_size = elt_size; - - if (r300_run_vb_render(ctx, NULL)) { - r300ReleaseDmaRegion(rmesa, &rvb, __FUNCTION__); - goto fallback; - } - - if(rvb.buf) - radeon_mm_use(rmesa, rvb.buf->id); - - r300ReleaseDmaRegion(rmesa, &rvb, __FUNCTION__); - return; - - fallback: - _tnl_array_init(ctx); - _mesa_install_exec_vtxfmt( ctx, &TNL_CONTEXT(ctx)->exec_vtxfmt ); - CALL_DrawElements(GET_DISPATCH(), (mode, count, type, c_indices)); - radeon_init_vtxfmt_a(rmesa); - _mesa_install_exec_vtxfmt( ctx, &TNL_CONTEXT(ctx)->exec_vtxfmt ); -} -static void radeonDrawRangeElements(GLenum mode, GLuint min, GLuint max, GLsizei count, GLenum type, const GLvoid *c_indices) +static void radeonDrawRangeElements(GLcontext *ctx, + GLenum mode, + GLuint min, + GLuint max, + GLsizei count, + GLenum type, + const GLvoid *c_indices) { - GET_CURRENT_CONTEXT(ctx); +#if 1 + return GL_FALSE; +#else r300ContextPtr rmesa = R300_CONTEXT(ctx); struct tnl_prim prim; int elt_size; @@ -371,26 +206,23 @@ static void radeonDrawRangeElements(GLenum mode, GLuint min, GLuint max, GLsizei indices += i * _mesa_sizeof_type(type); count -= i; } - return ; + return GL_TRUE; } WARN_ONCE("Too many verts!\n"); - goto fallback; + return GL_FALSE; } if (ctx->Array.ElementArrayBufferObj->Name) { /* use indices in the buffer object */ if (!ctx->Array.ElementArrayBufferObj->Data) { _mesa_warning(ctx, "DrawRangeElements with empty vertex elements buffer!"); - return; + return GL_TRUE; } /* actual address is the sum of pointers */ indices = (GLvoid *) ADD_POINTERS(ctx->Array.ElementArrayBufferObj->Data, (const GLubyte *) c_indices); } - if (!_mesa_validate_DrawRangeElements( ctx, mode, min, max, count, type, indices )) - return; - FLUSH_CURRENT( ctx, 0 ); #ifdef OPTIMIZE_ELTS min = 0; @@ -465,7 +297,7 @@ static void radeonDrawRangeElements(GLenum mode, GLuint min, GLuint max, GLsizei default: WARN_ONCE("Unknown elt type!\n"); - goto fallback; + return GL_FALSE; } /* XXX: setup_arrays before state update? */ @@ -477,7 +309,7 @@ static void radeonDrawRangeElements(GLenum mode, GLuint min, GLuint max, GLsizei if (setup_arrays(rmesa, min) >= R300_FALLBACK_TCL) { r300ReleaseDmaRegion(rmesa, &rvb, __FUNCTION__); - goto fallback; + return GL_FALSE; } rmesa->state.VB.Count = max - min + 1; @@ -501,37 +333,34 @@ static void radeonDrawRangeElements(GLenum mode, GLuint min, GLuint max, GLsizei if (r300_run_vb_render(ctx, NULL)) { r300ReleaseDmaRegion(rmesa, &rvb, __FUNCTION__); - goto fallback; + return GL_FALSE; } if(rvb.buf) radeon_mm_use(rmesa, rvb.buf->id); r300ReleaseDmaRegion(rmesa, &rvb, __FUNCTION__); - return ; - - fallback: - _tnl_array_init(ctx); - _mesa_install_exec_vtxfmt( ctx, &TNL_CONTEXT(ctx)->exec_vtxfmt ); - CALL_DrawRangeElements(GET_DISPATCH(), (mode, min, max, count, type, c_indices)); - radeon_init_vtxfmt_a(rmesa); - _mesa_install_exec_vtxfmt( ctx, &TNL_CONTEXT(ctx)->exec_vtxfmt ); + return GL_TRUE; +#endif } -static void radeonDrawArrays( GLenum mode, GLint start, GLsizei count ) +static GLboolean radeonDrawArrays( GLcontext *ctx, + GLenum mode, GLint start, GLsizei count ) { +#if 1 + return GL_FALSE; +#else GET_CURRENT_CONTEXT(ctx); r300ContextPtr rmesa = R300_CONTEXT(ctx); struct tnl_prim prim; if (count > 65535) { + /* TODO: split into multiple draws. + */ WARN_ONCE("Too many verts!\n"); - goto fallback; + return GL_FALSE; } - if (!_mesa_validate_DrawArrays( ctx, mode, start, count )) - return; - FLUSH_CURRENT( ctx, 0 ); if (ctx->NewState) @@ -542,7 +371,7 @@ static void radeonDrawArrays( GLenum mode, GLint start, GLsizei count ) r300UpdateShaders(rmesa); if (setup_arrays(rmesa, start) >= R300_FALLBACK_TCL) - goto fallback; + return GL_FALSE; rmesa->state.VB.Count = count; @@ -564,31 +393,70 @@ static void radeonDrawArrays( GLenum mode, GLint start, GLsizei count ) rmesa->state.VB.elt_max = 0; if (r300_run_vb_render(ctx, NULL)) - goto fallback; + return GL_FALSE; - return ; - - fallback: - _tnl_array_init(ctx); - _mesa_install_exec_vtxfmt( ctx, &TNL_CONTEXT(ctx)->exec_vtxfmt ); - CALL_DrawArrays(GET_DISPATCH(), (mode, start, count)); - radeon_init_vtxfmt_a(rmesa); - _mesa_install_exec_vtxfmt( ctx, &TNL_CONTEXT(ctx)->exec_vtxfmt ); + return GL_TRUE; +#endif } +static void radeon_draw_prims( GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLuint min_index, + GLuint max_index) +{ + if (ib == NULL) { + for (i = 0; i < nr_prims; i++) { + if (!radeonDrawArrays(ctx, + prim->mode, + prim->start, + prim->count)) { + /* Fallback + */ + _tnl_draw_prims(ctx, + arrays, + prim + i, + nr_prims - i, + ib, + min_index, + max_index); + return; + } + } + } else { + for (i = 0; i < nr_prims; i++) { + if (!radeonDrawRangeElements(ctx, + prim->mode, + min_index, + max_index, + prim->count, + ib->types, + ib->ptr)) { + /* Fallback + */ + _tnl_draw_prims(ctx, + arrays, + prim + i, + nr_prims - i, + ib, + min_index, + max_index); + return; + } + } + } +} + void radeon_init_vtxfmt_a(r300ContextPtr rmesa) { GLcontext *ctx; - GLvertexformat *vfmt; - - ctx = rmesa->radeon.glCtx; - vfmt = (GLvertexformat *)ctx->TnlModule.Current; - - vfmt->DrawElements = radeonDrawElements; - vfmt->DrawArrays = radeonDrawArrays; - vfmt->DrawRangeElements = radeonDrawRangeElements; + struct vbo_context *vbo = vbo_context(ctx); + vbo->draw_prims = radeon_draw_prims; } + #endif #ifdef HW_VBOS |