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-rw-r--r--src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c1
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_code.h3
-rw-r--r--src/mesa/drivers/dri/r300/r300_cmdbuf.c81
-rw-r--r--src/mesa/drivers/dri/r300/r300_context.c5
-rw-r--r--src/mesa/drivers/dri/r300/r300_draw.c7
-rw-r--r--src/mesa/drivers/dri/r300/r300_ioctl.c13
-rw-r--r--src/mesa/drivers/dri/r300/r300_state.c40
7 files changed, 83 insertions, 67 deletions
diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
index 3a527210c1..d694725c9b 100644
--- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
@@ -279,7 +279,6 @@ void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compi
_mesa_bzero(code, sizeof(*code));
code->max_temp_idx = 1;
- code->inst_offset = 0;
code->inst_end = -1;
radeonPairProgram(compiler, &pair_handler, compiler);
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_code.h b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
index 6f5bc28831..0806fb1b5c 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_code.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
@@ -160,8 +160,7 @@ struct r500_fragment_program_code {
uint32_t inst5;
} inst[R500_PFS_MAX_INST];
- int inst_offset;
- int inst_end;
+ int inst_end; /* Number of instructions - 1; also, last instruction to be executed */
int max_temp_idx;
};
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index af535037d0..bd46f9acf2 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -164,47 +164,46 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
- int notexture = 0;
-
- if (numtmus) {
- int i;
-
- for(i = 0; i < numtmus; ++i) {
- radeonTexObj *t = r300->hw.textures[i];
-
- if (!t)
- notexture = 1;
- }
-
- if (r300->radeon.radeonScreen->kernel_mm && notexture) {
- return;
- }
- for(i = 0; i < numtmus; ++i) {
- radeonTexObj *t = r300->hw.textures[i];
- if (t && !t->image_override) {
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- } else if (!t) {
- /* Texture unit hasn't a texture bound nothings to do */
- } else { /* override cases */
- if (t->bo) {
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- } else if (!r300->radeon.radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH(t->override_offset);
- END_BATCH();
- } else {
- /* Texture unit hasn't a texture bound nothings to do */
- }
- }
+ int i;
+
+ for(i = 0; i < numtmus; ++i) {
+ radeonTexObj *t = r300->hw.textures[i];
+ if (t && !t->image_override) {
+ BEGIN_BATCH_NO_AUTOSTATE(4);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ END_BATCH();
+ } else if (!t) {
+ /* Texture unit hasn't a texture bound.
+ * We assign the current color buffer as a fakery to make
+ * KIL work on KMS (without it, the CS checker will complain).
+ */
+ if (r300->radeon.radeonScreen->kernel_mm) {
+ struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
+ if (rrb && rrb->bo) {
+ BEGIN_BATCH_NO_AUTOSTATE(4);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+ OUT_BATCH_RELOC(0, rrb->bo, 0,
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ END_BATCH();
+ }
+ }
+ } else { /* override cases */
+ if (t->bo) {
+ BEGIN_BATCH_NO_AUTOSTATE(4);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+ OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ END_BATCH();
+ } else if (!r300->radeon.radeonScreen->kernel_mm) {
+ BEGIN_BATCH_NO_AUTOSTATE(2);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+ OUT_BATCH(t->override_offset);
+ END_BATCH();
+ } else {
+ /* Texture unit hasn't a texture bound nothings to do */
+ }
}
}
}
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 6f3aab986d..db404b3847 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -451,11 +451,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
r300InitState(r300);
r300InitShaderFunctions(r300);
- if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 ||
- screen->chip_family == CHIP_FAMILY_RS740) {
- r300->radeon.texture_row_align = 64;
- }
-
r300InitGLExtensions(ctx);
return GL_TRUE;
diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c
index fcfd309933..aedc6cfb2a 100644
--- a/src/mesa/drivers/dri/r300/r300_draw.c
+++ b/src/mesa/drivers/dri/r300/r300_draw.c
@@ -462,6 +462,7 @@ static void r300DrawPrims(GLcontext *ctx,
const struct _mesa_prim *prim,
GLuint nr_prims,
const struct _mesa_index_buffer *ib,
+ GLboolean index_bounds_valid,
GLuint min_index,
GLuint max_index)
{
@@ -476,6 +477,12 @@ static void r300DrawPrims(GLcontext *ctx,
limits.max_indices = 65535;
limits.max_vb_size = 1024*1024;
+ /* This check should get folded into just the places that
+ * min/max index are really needed.
+ */
+ if (!index_bounds_valid)
+ vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
+
if (min_index) {
vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r300DrawPrims );
return;
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 5bded642ef..7558f9e225 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -168,18 +168,21 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
}
#if 1
if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
- assert(rrbd != 0);
- cbpitch = (rrbd->pitch / rrbd->cpp);
+ uint32_t zbpitch = (rrbd->pitch / rrbd->cpp);
if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
- cbpitch |= R300_DEPTHMACROTILE_ENABLE;
+ zbpitch |= R300_DEPTHMACROTILE_ENABLE;
}
if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
- cbpitch |= R300_DEPTHMICROTILE_TILED;
+ zbpitch |= R300_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(6);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch);
+ OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
+ if (!r300->radeon.radeonScreen->kernel_mm)
+ OUT_BATCH(zbpitch);
+ else
+ OUT_BATCH_RELOC(zbpitch, rrbd->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
}
#endif
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 1ac14267d5..050e8cd2a7 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1253,6 +1253,7 @@ static GLuint translate_lod_bias(GLfloat bias)
return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
}
+
static void r300SetupTextures(GLcontext * ctx)
{
int i, mtu;
@@ -1345,6 +1346,28 @@ static void r300SetupTextures(GLcontext * ctx)
}
}
+ /* R3xx and R4xx chips require that the texture unit corresponding to
+ * KIL instructions is really enabled.
+ *
+ * We do some fakery here and in the state atom emit logic to enable
+ * the texture without tripping up the CS checker in the kernel.
+ */
+ if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
+ if (ctx->FragmentProgram._Current->UsesKill && last_hw_tmu < 0) {
+ last_hw_tmu++;
+
+ r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
+
+ r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0] = 0;
+ r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0] = 0;
+ r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
+ r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0] = 0;
+ r300->hw.tex.size.cmd[R300_TEX_VALUE_0] = 0; /* 1x1 texture */
+ r300->hw.tex.format.cmd[R300_TEX_VALUE_0] = 0; /* A8 format */
+ r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0] = 0;
+ }
+ }
+
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
@@ -1362,16 +1385,6 @@ static void r300SetupTextures(GLcontext * ctx)
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
- if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
- if (ctx->FragmentProgram._Current->UsesKill && last_hw_tmu < 0) {
- // The KILL operation requires the first texture unit
- // to be enabled.
- r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
- r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
- r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1);
- }
- }
r300->vtbl.SetupFragmentShaderTextures(ctx, tmu_mappings);
if (RADEON_DEBUG & DEBUG_STATE)
@@ -2103,13 +2116,13 @@ static void r500SetupPixelShader(GLcontext *ctx)
rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx;
rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] =
- R500_US_CODE_START_ADDR(code->inst_offset) |
+ R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(code->inst_end);
rmesa->hw.fp.cmd[R500_FP_CODE_RANGE] =
- R500_US_CODE_RANGE_ADDR(code->inst_offset) |
+ R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(code->inst_end);
rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] =
- R500_US_CODE_OFFSET_ADDR(0); /* FIXME when we add flow control */
+ R500_US_CODE_OFFSET_ADDR(0);
R300_STATECHANGE(rmesa, r500fp);
/* Emit our shader... */
@@ -2234,6 +2247,7 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
_mesa_update_draw_buffer_bounds(ctx);
R300_STATECHANGE(r300, cb);
+ R300_STATECHANGE(r300, zb);
}
r300->radeon.NewGLState |= new_state;
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-13 08:28:38 +0000