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path: root/src/mesa/drivers/dri/r600/r700_chip.c
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Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_chip.c')
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c119
1 files changed, 80 insertions, 39 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index c083862f36..e5e0f556cb 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -38,6 +38,8 @@
#include "r700_vertprog.h"
#include "r700_ioctl.h"
+#include "radeon_mipmap_tree.h"
+
#define LINK_STATES(reg) \
do \
{ \
@@ -241,6 +243,67 @@ GLboolean r700InitChipObject(context_t *context)
return GL_TRUE;
}
+GLboolean r700SendTextureState(context_t *context)
+{
+ unsigned int i;
+ R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+ struct radeon_bo *bo = NULL;
+ BATCH_LOCALS(&context->radeon);
+
+ for (i=0; i<R700_TEXTURE_NUMBERUNITS; i++) {
+ radeonTexObj *t = r700->textures[i];
+ if (t) {
+ if (!t->image_override)
+ bo = t->mt->bo;
+ else
+ bo = t->bo;
+ if (bo) {
+
+ r700SyncSurf(context, bo,
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
+ 0, TC_ACTION_ENA_bit);
+
+ BEGIN_BATCH_NO_AUTOSTATE(9);
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+ R600_OUT_BATCH(i * 7);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
+ R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
+ bo,
+ 0,
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
+ bo,
+ r700->textures[i]->SQ_TEX_RESOURCE3,
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
+ END_BATCH();
+
+ BEGIN_BATCH_NO_AUTOSTATE(5);
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
+ R600_OUT_BATCH(i * 3);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
+ R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
+ END_BATCH();
+
+ BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
+ R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
+ R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
+ R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
+ R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
+ R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
+ END_BATCH();
+
+ COMMIT_BATCH();
+ }
+ }
+ }
+ return GL_TRUE;
+}
+
void r700SetupVTXConstants(GLcontext * ctx,
unsigned int nStreamID,
void * pAos,
@@ -249,10 +312,7 @@ void r700SetupVTXConstants(GLcontext * ctx,
unsigned int count) /* number of vectors in stream */
{
context_t *context = R700_CONTEXT(ctx);
- uint32_t *dest;
struct radeon_aos * paos = (struct radeon_aos *)pAos;
- offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
-
BATCH_LOCALS(&context->radeon);
unsigned int uSQ_VTX_CONSTANT_WORD0_0;
@@ -261,6 +321,9 @@ void r700SetupVTXConstants(GLcontext * ctx,
unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
+ if (!paos->bo)
+ return;
+
if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
@@ -294,7 +357,7 @@ void r700SetupVTXConstants(GLcontext * ctx,
R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
paos->bo,
uSQ_VTX_CONSTANT_WORD0_0,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
@@ -310,7 +373,6 @@ void r700SetupVTXConstants(GLcontext * ctx,
int r700SetupStreams(GLcontext * ctx)
{
context_t *context = R700_CONTEXT(ctx);
-
BATCH_LOCALS(&context->radeon);
struct r700_vertex_program *vpc
@@ -324,7 +386,7 @@ int r700SetupStreams(GLcontext * ctx)
BEGIN_BATCH_NO_AUTOSTATE(6);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
+ R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
R600_OUT_BATCH(0);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
@@ -417,11 +479,10 @@ GLboolean r700SendContextStates(context_t *context)
return GL_TRUE;
}
-GLboolean r700SendDepthTargetState(context_t *context, int id)
+GLboolean r700SendDepthTargetState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_renderbuffer *rrb;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
rrb = radeon_get_depthbuffer(&context->radeon);
@@ -430,10 +491,6 @@ GLboolean r700SendDepthTargetState(context_t *context, int id)
return GL_FALSE;
}
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
BEGIN_BATCH_NO_AUTOSTATE(9);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
@@ -442,7 +499,7 @@ GLboolean r700SendDepthTargetState(context_t *context, int id)
R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
rrb->bo,
r700->DB_DEPTH_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
+ 0, RADEON_GEM_DOMAIN_VRAM, 0);
R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All);
END_BATCH();
@@ -479,7 +536,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_renderbuffer *rrb;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
rrb = radeon_get_colorbuffer(&context->radeon);
@@ -494,16 +550,12 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
if (!r700->render_target[id].enabled)
return GL_FALSE;
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
BEGIN_BATCH_NO_AUTOSTATE(3);
R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
rrb->bo,
r700->render_target[id].CB_COLOR0_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
+ 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
@@ -540,16 +592,13 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
GLboolean r700SendPSState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_renderbuffer *rrb;
struct radeon_bo * pbo;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
+ if (!pbo)
+ return GL_FALSE;
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
@@ -558,7 +607,7 @@ GLboolean r700SendPSState(context_t *context)
R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
pbo,
r700->ps.SQ_PGM_START_PS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(9);
@@ -575,16 +624,13 @@ GLboolean r700SendPSState(context_t *context)
GLboolean r700SendVSState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_renderbuffer *rrb;
struct radeon_bo * pbo;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
+ if (!pbo)
+ return GL_FALSE;
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
@@ -593,7 +639,7 @@ GLboolean r700SendVSState(context_t *context)
R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
pbo,
r700->vs.SQ_PGM_START_VS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -609,9 +655,7 @@ GLboolean r700SendVSState(context_t *context)
GLboolean r700SendFSState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_renderbuffer *rrb;
struct radeon_bo * pbo;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
/* XXX fixme
@@ -625,9 +669,8 @@ GLboolean r700SendFSState(context_t *context)
r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
/* XXX */
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
+ if (!pbo)
+ return GL_FALSE;
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
@@ -636,7 +679,7 @@ GLboolean r700SendFSState(context_t *context)
R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
pbo,
r700->fs.SQ_PGM_START_FS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -652,8 +695,6 @@ GLboolean r700SendFSState(context_t *context)
GLboolean r700SendViewportState(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_renderbuffer *rrb;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
if (id > R700_MAX_VIEWPORTS)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-06 23:36:36 +0000