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-rw-r--r--src/mesa/drivers/dri/r600/Makefile9
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.c22
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.h33
-rw-r--r--src/mesa/drivers/dri/r600/r600_context.c12
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c28
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c4
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c2
-rw-r--r--src/mesa/drivers/dri/r600/r700_oglprog.c2
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c24
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c6
-rw-r--r--src/mesa/drivers/dri/r600/r700_vertprog.c2
l---------src/mesa/drivers/dri/r600/radeon_pixel_read.c1
l---------src/mesa/drivers/dri/r600/radeon_tex_getimage.c1
l---------src/mesa/drivers/dri/r600/radeon_tile.c1
l---------src/mesa/drivers/dri/r600/radeon_tile.h1
l---------src/mesa/drivers/dri/r600/server/radeon_dri.c1
16 files changed, 101 insertions, 48 deletions
diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile
index 5d50941539..17915621ee 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
LIBNAME = r600_dri.so
-MINIGLX_SOURCES = server/radeon_dri.c
-
ifeq ($(RADEON_LDFLAGS),)
CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
endif
@@ -33,10 +31,13 @@ RADEON_COMMON_SOURCES = \
radeon_fbo.c \
radeon_lock.c \
radeon_mipmap_tree.c \
+ radeon_pixel_read.c \
+ radeon_queryobj.c \
radeon_span.c \
radeon_texture.c \
- radeon_queryobj.c \
- radeon_tex_copy.c
+ radeon_tex_copy.c \
+ radeon_tex_getimage.c \
+ radeon_tile.c
DRIVER_SOURCES = \
radeon_screen.c \
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 4bb77a398f..244fdc4ffb 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -33,7 +33,7 @@
#include "r600_cmdbuf.h"
/* common formats supported as both textures and render targets */
-static unsigned is_blit_supported(gl_format mesa_format)
+unsigned r600_check_blit(gl_format mesa_format)
{
switch (mesa_format) {
case MESA_FORMAT_RGBA8888:
@@ -1532,24 +1532,22 @@ static GLboolean validate_buffers(context_t *rmesa,
struct radeon_bo *dst_bo)
{
int ret;
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rmesa->blit_bo, RADEON_GEM_DOMAIN_GTT, 0);
+ ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
+ src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+ if (ret)
+ return GL_FALSE;
ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- rmesa->blit_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
+ dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
if (ret)
return GL_FALSE;
ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- first_elem(&rmesa->radeon.dma.reserved)->bo,
- RADEON_GEM_DOMAIN_GTT, 0);
+ rmesa->blit_bo,
+ RADEON_GEM_DOMAIN_GTT, 0);
if (ret)
return GL_FALSE;
@@ -1580,7 +1578,7 @@ unsigned r600_blit(GLcontext *ctx,
context_t *context = R700_CONTEXT(ctx);
int id = 0;
- if (!is_blit_supported(dst_mesaformat))
+ if (!r600_check_blit(dst_mesaformat))
return GL_FALSE;
if (src_bo == dst_bo) {
diff --git a/src/mesa/drivers/dri/r600/r600_blit.h b/src/mesa/drivers/dri/r600/r600_blit.h
index f280e23489..d56b21ba9b 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.h
+++ b/src/mesa/drivers/dri/r600/r600_blit.h
@@ -1,3 +1,35 @@
+/*
+ * Copyright (C) 2009 Advanced Micro Devices, Inc.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef R600_BLIT_H
+#define R600_BLIT_H
+
+unsigned r600_check_blit(gl_format mesa_format);
+
unsigned r600_blit(GLcontext *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
@@ -19,3 +51,4 @@ unsigned r600_blit(GLcontext *ctx,
unsigned h,
unsigned flip_y);
+#endif // R600_BLIT_H
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index f575e74c3e..76d5027649 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -140,6 +140,7 @@ static const struct dri_extension card_extensions[] = {
{"GL_NV_blend_square", NULL},
{"GL_NV_vertex_program", GL_NV_vertex_program_functions},
{"GL_SGIS_generate_mipmap", NULL},
+ {"GL_ARB_pixel_buffer_object", NULL},
{NULL, NULL}
/* *INDENT-ON* */
};
@@ -236,7 +237,9 @@ static void r600_init_vtbl(radeonContextPtr radeon)
radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms;
radeon->vtbl.fallback = r600_fallback;
radeon->vtbl.emit_query_finish = r600_emit_query_finish;
+ radeon->vtbl.check_blit = r600_check_blit;
radeon->vtbl.blit = r600_blit;
+ radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
}
static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
@@ -340,9 +343,12 @@ static void r600InitGLExtensions(GLcontext *ctx)
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
}
- /* XXX: RV740 only seems to report results from half of its DBs */
- if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740)
- _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
+ /* RV740 had a broken pipe config prior to drm 1.32 */
+ if (!r600->radeon.radeonScreen->kernel_mm) {
+ if ((r600->radeon.dri.drmMinor < 32) &&
+ (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740))
+ _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
+ }
}
/* Create the device specific rendering context.
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index dd33ef3c6a..1600033b9b 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -373,17 +373,11 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
break;
*/
case MESA_FORMAT_RGB_DXT1: /* not supported yet */
-
- break;
case MESA_FORMAT_RGBA_DXT1: /* not supported yet */
-
- break;
case MESA_FORMAT_RGBA_DXT3: /* not supported yet */
-
- break;
case MESA_FORMAT_RGBA_DXT5: /* not supported yet */
+ return GL_FALSE;
- break;
case MESA_FORMAT_RGBA_FLOAT32:
SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
@@ -701,8 +695,8 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj)
t = radeon_tex_obj(tObj);
- r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat);
-
+ if(!r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat))
+ t->validated = GL_FALSE;
}
/**
@@ -711,7 +705,7 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj)
* \param rmesa Context pointer
* \param t the r300 texture object
*/
-static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texObj, int unit)
+static GLboolean setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texObj, int unit)
{
context_t *rmesa = R700_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
@@ -721,15 +715,15 @@ static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texO
if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
t->image_override &&
t->bo)
- return;
+ return GL_TRUE;
firstImage = t->base.Image[0][t->minLod];
if (!t->image_override) {
if (!r600GetTexFormat(texObj, firstImage->TexFormat)) {
- radeon_error("unexpected texture format in %s\n",
- __FUNCTION__);
- return;
+ radeon_warning("unsupported texture format in %s\n",
+ __FUNCTION__);
+ return GL_FALSE;
}
}
@@ -754,7 +748,7 @@ static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texO
break;
default:
radeon_error("unexpected texture target type in %s\n", __FUNCTION__);
- return;
+ return GL_FALSE;
}
row_align = rmesa->radeon.texture_row_align - 1;
@@ -799,6 +793,7 @@ static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texO
CLEARfield(t->SQ_TEX_SAMPLER0, DEPTH_COMPARE_FUNCTION_mask);
}
+ return GL_TRUE;
}
/**
@@ -815,7 +810,8 @@ static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object
/* Configure the hardware registers (more precisely, the cached version
* of the hardware registers). */
- setup_hardware_state(ctx, texObj, unit);
+ if (!setup_hardware_state(ctx, texObj, unit))
+ return GL_FALSE;
t->validated = GL_TRUE;
return GL_TRUE;
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index d0059fad2e..834bcc63e3 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1250,6 +1250,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm,
if(pAsm->aArgSubst[1+src] >= 0)
{
+ assert(fld >= 0);
setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE);
pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY;
pAsm->S[fld].src.reg = pAsm->aArgSubst[1+src];
@@ -1745,18 +1746,21 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr,
switch (source_index)
{
case 0:
+ assert(alu_instruction_ptr);
alu_instruction_ptr->m_Word0.f.src0_sel = src_sel;
alu_instruction_ptr->m_Word0.f.src0_rel = src_rel;
alu_instruction_ptr->m_Word0.f.src0_chan = src_chan;
alu_instruction_ptr->m_Word0.f.src0_neg = src_neg;
break;
case 1:
+ assert(alu_instruction_ptr);
alu_instruction_ptr->m_Word0.f.src1_sel = src_sel;
alu_instruction_ptr->m_Word0.f.src1_rel = src_rel;
alu_instruction_ptr->m_Word0.f.src1_chan = src_chan;
alu_instruction_ptr->m_Word0.f.src1_neg = src_neg;
break;
case 2:
+ assert(alu_instruction_ptr);
alu_instruction_ptr->m_Word1_OP3.f.src2_sel = src_sel;
alu_instruction_ptr->m_Word1_OP3.f.src2_rel = src_rel;
alu_instruction_ptr->m_Word1_OP3.f.src2_chan = src_chan;
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index a742dbcf12..63614b160c 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -1349,7 +1349,7 @@ void r600InitAtoms(context_t *context)
ALLOC_STATE(poly, always, 10, r700SendPolyState);
ALLOC_STATE(cb, cb, 18, r700SendCBState);
ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
- ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState);
+ ALLOC_STATE(cb_target, always, 29, r700SendRenderTargetState);
ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
ALLOC_STATE(sx, always, 9, r700SendSXState);
diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c
index 2a50361199..b7124e644a 100644
--- a/src/mesa/drivers/dri/r600/r700_oglprog.c
+++ b/src/mesa/drivers/dri/r600/r700_oglprog.c
@@ -53,7 +53,7 @@ static void freeVertProgCache(GLcontext *ctx, struct r700_vertex_program_cont *c
Clean_Up_Shader(&(vp->r700Shader));
_mesa_reference_vertprog(ctx, &vp->mesa_program, NULL);
- _mesa_free(vp);
+ free(vp);
vp = tmp;
}
}
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 8f14af7472..1929b7cc12 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -419,7 +419,7 @@ static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end,
}
/* start 3d, idle, cb/db flush */
-#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 18
+#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
static GLuint r700PredictRenderSize(GLcontext* ctx,
const struct _mesa_prim *prim,
@@ -594,7 +594,7 @@ static void r700AlignDataToDword(GLcontext *ctx,
for (i = 0; i < count; ++i)
{
- _mesa_memcpy(dst_ptr, src_ptr, input->StrideB);
+ memcpy(dst_ptr, src_ptr, input->StrideB);
src_ptr += input->StrideB;
dst_ptr += dst_stride;
}
@@ -829,11 +829,10 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer
#if MESA_BIG_ENDIAN
if (mesa_ind_buf->type == GL_UNSIGNED_INT)
- {
#else
if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
- {
#endif
+ {
const GLvoid *src_ptr;
GLvoid *dst_ptr;
GLboolean mapped_named_bo = GL_FALSE;
@@ -855,7 +854,7 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer
assert(context->ind_buf.bo->ptr != NULL);
dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- _mesa_memcpy(dst_ptr, src_ptr, size);
+ memcpy(dst_ptr, src_ptr, size);
radeon_bo_unmap(context->ind_buf.bo);
context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
@@ -872,6 +871,14 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer
}
}
+static GLboolean check_fallbacks(GLcontext *ctx)
+{
+ if (ctx->RenderMode != GL_RENDER)
+ return GL_TRUE;
+
+ return GL_FALSE;
+}
+
static GLboolean r700TryDrawPrims(GLcontext *ctx,
const struct gl_client_array *arrays[],
const struct _mesa_prim *prim,
@@ -888,6 +895,9 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx,
if (ctx->NewState)
_mesa_update_state( ctx );
+ if (check_fallbacks(ctx))
+ return GL_FALSE;
+
_tnl_UpdateFixedFunctionProgram(ctx);
r700SetVertexFormat(ctx, arrays, max_index + 1);
/* shaders need to be updated before buffers are validated */
@@ -983,8 +993,10 @@ static void r700DrawPrims(GLcontext *ctx,
retval = r700TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
/* If failed run tnl pipeline - it should take care of fallbacks */
- if (!retval)
+ if (!retval) {
+ _swsetup_Wakeup(ctx);
_tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
+ }
}
void r700InitDraw(GLcontext *ctx)
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 0240eefd5c..6f156b5409 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -65,7 +65,7 @@ void r700UpdateShaders(GLcontext * ctx)
/* should only happenen once, just after context is created */
/* TODO: shouldn't we fallback to sw here? */
if (!ctx->FragmentProgram._Current) {
- _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
+ fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
return;
}
@@ -911,10 +911,12 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
case GL_POINT_SIZE_MIN:
SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
MIN_SIZE_shift, MIN_SIZE_mask);
+ r700PointSize(ctx, ctx->Point.Size);
break;
case GL_POINT_SIZE_MAX:
SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
MAX_SIZE_shift, MAX_SIZE_mask);
+ r700PointSize(ctx, ctx->Point.Size);
break;
case GL_POINT_DISTANCE_ATTENUATION:
break;
@@ -1626,8 +1628,6 @@ void r700InitState(GLcontext * ctx) //-------------------
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
int id = 0;
- radeon_firevertices(&context->radeon);
-
r700->TA_CNTL_AUX.u32All = 0;
SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
r700->VC_ENHANCE.u32All = 0;
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index 46481cdff4..07e0adc890 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -307,7 +307,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
struct r700_vertex_program *vp;
unsigned int i;
- vp = _mesa_calloc(sizeof(*vp));
+ vp = calloc(1, sizeof(*vp));
vp->mesa_program = _mesa_clone_vertex_program(ctx, mesa_vp);
if (mesa_vp->IsPositionInvariant)
diff --git a/src/mesa/drivers/dri/r600/radeon_pixel_read.c b/src/mesa/drivers/dri/r600/radeon_pixel_read.c
new file mode 120000
index 0000000000..3b03803126
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_pixel_read.c
@@ -0,0 +1 @@
+../radeon/radeon_pixel_read.c \ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_tex_getimage.c b/src/mesa/drivers/dri/r600/radeon_tex_getimage.c
new file mode 120000
index 0000000000..d9836d7326
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_tex_getimage.c
@@ -0,0 +1 @@
+../radeon/radeon_tex_getimage.c \ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_tile.c b/src/mesa/drivers/dri/r600/radeon_tile.c
new file mode 120000
index 0000000000..d4bfe27da6
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_tile.c
@@ -0,0 +1 @@
+../radeon/radeon_tile.c \ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_tile.h b/src/mesa/drivers/dri/r600/radeon_tile.h
new file mode 120000
index 0000000000..31074c581e
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_tile.h
@@ -0,0 +1 @@
+../radeon/radeon_tile.h \ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_dri.c b/src/mesa/drivers/dri/r600/server/radeon_dri.c
deleted file mode 120000
index d05847d650..0000000000
--- a/src/mesa/drivers/dri/r600/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c \ No newline at end of file
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-08 17:55:25 +0000