diff options
Diffstat (limited to 'src/mesa/drivers/dri/r600')
-rw-r--r-- | src/mesa/drivers/dri/r600/evergreen_chip.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r600/evergreen_state.c | 8 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r600/evergreen_tex.c | 22 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r600/r600_context.c | 11 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r600/r600_texstate.c | 14 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r600/r700_assembler.c | 66 |
6 files changed, 101 insertions, 26 deletions
diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c index 2c9e4e2b84..53dacbfdf3 100644 --- a/src/mesa/drivers/dri/r600/evergreen_chip.c +++ b/src/mesa/drivers/dri/r600/evergreen_chip.c @@ -286,7 +286,11 @@ static void evergreenSetupVTXConstants(struct gl_context * ctx, if (!paos->bo) return; - r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); + if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM)) + r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit); + else + r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); //uSQ_VTX_CONSTANT_WORD0_0 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; diff --git a/src/mesa/drivers/dri/r600/evergreen_state.c b/src/mesa/drivers/dri/r600/evergreen_state.c index a77be183a1..076a608573 100644 --- a/src/mesa/drivers/dri/r600/evergreen_state.c +++ b/src/mesa/drivers/dri/r600/evergreen_state.c @@ -1461,6 +1461,14 @@ static void evergreenInitSQConfig(struct gl_context * ctx) uMaxThreads = 248; uMaxStackEntries = 512; break; + case CHIP_FAMILY_PALM: + uSqNumCfInsts = 1; + bVC_ENABLE = GL_FALSE; + uMaxGPRs = 256; + uPSThreadCount = 96; + uMaxThreads = 192; + uMaxStackEntries = 256; + break; default: uSqNumCfInsts = 2; bVC_ENABLE = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/evergreen_tex.c b/src/mesa/drivers/dri/r600/evergreen_tex.c index 58420ed123..3b5448a0e4 100644 --- a/src/mesa/drivers/dri/r600/evergreen_tex.c +++ b/src/mesa/drivers/dri/r600/evergreen_tex.c @@ -31,9 +31,7 @@ #include "main/enums.h" #include "main/image.h" #include "main/teximage.h" -#include "main/mipmap.h" #include "main/simple_list.h" -#include "main/texstore.h" #include "main/texobj.h" #include "texmem.h" @@ -1024,15 +1022,15 @@ static GLboolean evergreen_setup_hardware_state(struct gl_context * ctx, struct SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask); SETfield(t->SQ_TEX_SAMPLER1, - EG_S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 6), + EG_S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 8), EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift, EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask); SETfield(t->SQ_TEX_SAMPLER1, - EG_S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 6), + EG_S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 8), EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift, EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask); SETfield(t->SQ_TEX_SAMPLER2, - EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 6), + EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 8), EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift, EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask); @@ -1152,6 +1150,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur radeonTexObjPtr t; uint32_t pitch_val; uint32_t internalFormat, type, format; + gl_format texFormat; type = GL_BGRA; format = GL_UNSIGNED_BYTE; @@ -1191,10 +1190,6 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur radeon_miptree_unreference(&t->mt); radeon_miptree_unreference(&rImage->mt); - _mesa_init_teximage_fields(radeon->glCtx, target, texImage, - rb->base.Width, rb->base.Height, 1, 0, rb->cpp); - texImage->RowStride = rb->pitch / rb->cpp; - rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; @@ -1205,6 +1200,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur switch (rb->cpp) { case 4: if (glx_texture_format == __DRI_TEXTURE_FORMAT_RGB) { + texFormat = MESA_FORMAT_RGB888; SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); @@ -1218,6 +1214,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); } else { + texFormat = MESA_FORMAT_ARGB8888; SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); @@ -1236,6 +1233,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur case 3: default: // FMT_8_8_8 ??? + texFormat = MESA_FORMAT_RGB888; SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); @@ -1251,6 +1249,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur pitch_val /= 4; break; case 2: + texFormat = MESA_FORMAT_RGB565; SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); @@ -1267,6 +1266,11 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur break; } + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->base.Width, rb->base.Height, 1, 0, + rb->cpp, texFormat); + texImage->RowStride = rb->pitch / rb->cpp; + pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index b6443bf0c5..aa1891eac3 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -259,7 +259,7 @@ static void r600InitConstValues(struct gl_context *ctx, radeonScreenPtr screen) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); if( (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR) - &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_HEMLOCK) ) + &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_PALM) ) { r700->bShaderUseMemConstant = GL_TRUE; } @@ -285,8 +285,13 @@ static void r600InitConstValues(struct gl_context *ctx, radeonScreenPtr screen) ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; - ctx->Const.MaxTextureLevels = 13; /* hw support 14 */ - ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */ + if (screen->chip_family >= CHIP_FAMILY_CEDAR) { + ctx->Const.MaxTextureLevels = 15; + ctx->Const.MaxTextureRectSize = 16384; + } else { + ctx->Const.MaxTextureLevels = 14; + ctx->Const.MaxTextureRectSize = 8192; + } ctx->Const.MinPointSize = 0x0001 / 8.0; ctx->Const.MinPointSizeAA = 0x0001 / 8.0; diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 3869768bf0..aafa687577 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -1001,6 +1001,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo radeonTexObjPtr t; uint32_t pitch_val; uint32_t internalFormat, type, format; + gl_format texFormat; type = GL_BGRA; format = GL_UNSIGNED_BYTE; @@ -1046,10 +1047,6 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo radeon_miptree_unreference(&t->mt); radeon_miptree_unreference(&rImage->mt); - _mesa_init_teximage_fields(radeon->glCtx, target, texImage, - rb->base.Width, rb->base.Height, 1, 0, rb->cpp); - texImage->RowStride = rb->pitch / rb->cpp; - rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; @@ -1060,6 +1057,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo switch (rb->cpp) { case 4: if (glx_texture_format == __DRI_TEXTURE_FORMAT_RGB) { + texFormat = MESA_FORMAT_RGB888; SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); @@ -1072,6 +1070,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); } else { + texFormat = MESA_FORMAT_ARGB8888; SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); @@ -1089,6 +1088,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo case 3: default: // FMT_8_8_8 ??? + texFormat = MESA_FORMAT_RGB888; SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); @@ -1103,6 +1103,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo pitch_val /= 4; break; case 2: + texFormat = MESA_FORMAT_RGB565; SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); @@ -1118,6 +1119,11 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo break; } + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->base.Width, rb->base.Height, 1, 0, + rb->cpp, texFormat); + texImage->RowStride = rb->pitch / rb->cpp; + pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 2bf24096a0..bee9c3bc6d 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1134,7 +1134,7 @@ GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm, EG_VTX_WORD1__DST_SEL_W_shift, EG_VTX_WORD1__DST_SEL_W_mask); - SETfield(vfetch_instruction_ptr->m_Word1.val, 0, /* use format here, in r6/r7, format used set in const, need to use same */ + SETfield(vfetch_instruction_ptr->m_Word1.val, 1, EG_VTX_WORD1__UCF_shift, EG_VTX_WORD1__UCF_bit); SETfield(vfetch_instruction_ptr->m_Word1.val, data_format, @@ -3334,7 +3334,14 @@ GLboolean assemble_CMP(r700_AssemblerBase *pAsm) return GL_FALSE; } - pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_CNDGE; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE; + } pAsm->D.dst.op3 = 1; tmp = (-1); @@ -3416,8 +3423,14 @@ GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode) checkop1(pAsm); tmp = gethelpr(pAsm); - - pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_MULADD; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + } pAsm->D.dst.op3 = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); @@ -3457,7 +3470,14 @@ GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode) { return GL_FALSE; } - pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_MULADD; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + } pAsm->D.dst.op3 = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); @@ -4742,7 +4762,14 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm) tmp = gethelpr(pAsm); - pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_MULADD; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + } pAsm->D.dst.op3 = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); @@ -4782,7 +4809,14 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm) { return GL_FALSE; } - pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_MULADD; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + } pAsm->D.dst.op3 = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); @@ -5010,7 +5044,14 @@ GLboolean assemble_SSG(r700_AssemblerBase *pAsm) GLuint tmp = gethelpr(pAsm); /* tmp = (src > 0 ? 1 : src) */ - pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_CNDGT; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT; + } pAsm->D.dst.op3 = 1; pAsm->D.dst.rtype = DST_REG_TEMPORARY; pAsm->D.dst.reg = tmp; @@ -5033,7 +5074,14 @@ GLboolean assemble_SSG(r700_AssemblerBase *pAsm) } /* dst = (-tmp > 0 ? -1 : tmp) */ - pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT; + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_CNDGT; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT; + } pAsm->D.dst.op3 = 1; if( GL_FALSE == assemble_dst(pAsm) ) |