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-rw-r--r--src/mesa/drivers/dri/r600/r600_context.c9
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c28
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c4
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c2
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c20
5 files changed, 39 insertions, 24 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index f575e74c3e..1a4b014d9f 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -340,9 +340,12 @@ static void r600InitGLExtensions(GLcontext *ctx)
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
}
- /* XXX: RV740 only seems to report results from half of its DBs */
- if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740)
- _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
+ /* RV740 had a broken pipe config prior to drm 1.32 */
+ if (!r600->radeon.radeonScreen->kernel_mm) {
+ if ((r600->radeon.dri.drmMinor < 32) &&
+ (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740))
+ _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
+ }
}
/* Create the device specific rendering context.
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index dd33ef3c6a..1600033b9b 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -373,17 +373,11 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
break;
*/
case MESA_FORMAT_RGB_DXT1: /* not supported yet */
-
- break;
case MESA_FORMAT_RGBA_DXT1: /* not supported yet */
-
- break;
case MESA_FORMAT_RGBA_DXT3: /* not supported yet */
-
- break;
case MESA_FORMAT_RGBA_DXT5: /* not supported yet */
+ return GL_FALSE;
- break;
case MESA_FORMAT_RGBA_FLOAT32:
SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
@@ -701,8 +695,8 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj)
t = radeon_tex_obj(tObj);
- r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat);
-
+ if(!r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat))
+ t->validated = GL_FALSE;
}
/**
@@ -711,7 +705,7 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj)
* \param rmesa Context pointer
* \param t the r300 texture object
*/
-static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texObj, int unit)
+static GLboolean setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texObj, int unit)
{
context_t *rmesa = R700_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
@@ -721,15 +715,15 @@ static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texO
if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
t->image_override &&
t->bo)
- return;
+ return GL_TRUE;
firstImage = t->base.Image[0][t->minLod];
if (!t->image_override) {
if (!r600GetTexFormat(texObj, firstImage->TexFormat)) {
- radeon_error("unexpected texture format in %s\n",
- __FUNCTION__);
- return;
+ radeon_warning("unsupported texture format in %s\n",
+ __FUNCTION__);
+ return GL_FALSE;
}
}
@@ -754,7 +748,7 @@ static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texO
break;
default:
radeon_error("unexpected texture target type in %s\n", __FUNCTION__);
- return;
+ return GL_FALSE;
}
row_align = rmesa->radeon.texture_row_align - 1;
@@ -799,6 +793,7 @@ static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texO
CLEARfield(t->SQ_TEX_SAMPLER0, DEPTH_COMPARE_FUNCTION_mask);
}
+ return GL_TRUE;
}
/**
@@ -815,7 +810,8 @@ static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object
/* Configure the hardware registers (more precisely, the cached version
* of the hardware registers). */
- setup_hardware_state(ctx, texObj, unit);
+ if (!setup_hardware_state(ctx, texObj, unit))
+ return GL_FALSE;
t->validated = GL_TRUE;
return GL_TRUE;
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index d0059fad2e..834bcc63e3 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1250,6 +1250,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm,
if(pAsm->aArgSubst[1+src] >= 0)
{
+ assert(fld >= 0);
setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE);
pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY;
pAsm->S[fld].src.reg = pAsm->aArgSubst[1+src];
@@ -1745,18 +1746,21 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr,
switch (source_index)
{
case 0:
+ assert(alu_instruction_ptr);
alu_instruction_ptr->m_Word0.f.src0_sel = src_sel;
alu_instruction_ptr->m_Word0.f.src0_rel = src_rel;
alu_instruction_ptr->m_Word0.f.src0_chan = src_chan;
alu_instruction_ptr->m_Word0.f.src0_neg = src_neg;
break;
case 1:
+ assert(alu_instruction_ptr);
alu_instruction_ptr->m_Word0.f.src1_sel = src_sel;
alu_instruction_ptr->m_Word0.f.src1_rel = src_rel;
alu_instruction_ptr->m_Word0.f.src1_chan = src_chan;
alu_instruction_ptr->m_Word0.f.src1_neg = src_neg;
break;
case 2:
+ assert(alu_instruction_ptr);
alu_instruction_ptr->m_Word1_OP3.f.src2_sel = src_sel;
alu_instruction_ptr->m_Word1_OP3.f.src2_rel = src_rel;
alu_instruction_ptr->m_Word1_OP3.f.src2_chan = src_chan;
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index a742dbcf12..63614b160c 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -1349,7 +1349,7 @@ void r600InitAtoms(context_t *context)
ALLOC_STATE(poly, always, 10, r700SendPolyState);
ALLOC_STATE(cb, cb, 18, r700SendCBState);
ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
- ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState);
+ ALLOC_STATE(cb_target, always, 29, r700SendRenderTargetState);
ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
ALLOC_STATE(sx, always, 9, r700SendSXState);
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index fdd02fac23..1929b7cc12 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -419,7 +419,7 @@ static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end,
}
/* start 3d, idle, cb/db flush */
-#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 18
+#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
static GLuint r700PredictRenderSize(GLcontext* ctx,
const struct _mesa_prim *prim,
@@ -829,11 +829,10 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer
#if MESA_BIG_ENDIAN
if (mesa_ind_buf->type == GL_UNSIGNED_INT)
- {
#else
if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
- {
#endif
+ {
const GLvoid *src_ptr;
GLvoid *dst_ptr;
GLboolean mapped_named_bo = GL_FALSE;
@@ -872,6 +871,14 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer
}
}
+static GLboolean check_fallbacks(GLcontext *ctx)
+{
+ if (ctx->RenderMode != GL_RENDER)
+ return GL_TRUE;
+
+ return GL_FALSE;
+}
+
static GLboolean r700TryDrawPrims(GLcontext *ctx,
const struct gl_client_array *arrays[],
const struct _mesa_prim *prim,
@@ -888,6 +895,9 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx,
if (ctx->NewState)
_mesa_update_state( ctx );
+ if (check_fallbacks(ctx))
+ return GL_FALSE;
+
_tnl_UpdateFixedFunctionProgram(ctx);
r700SetVertexFormat(ctx, arrays, max_index + 1);
/* shaders need to be updated before buffers are validated */
@@ -983,8 +993,10 @@ static void r700DrawPrims(GLcontext *ctx,
retval = r700TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
/* If failed run tnl pipeline - it should take care of fallbacks */
- if (!retval)
+ if (!retval) {
+ _swsetup_Wakeup(ctx);
_tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
+ }
}
void r700InitDraw(GLcontext *ctx)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-28 15:58:56 +0000