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-rw-r--r--src/mesa/drivers/dri/r600/Makefile4
-rw-r--r--src/mesa/drivers/dri/r600/r600_context.c16
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.h2
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c72
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c15
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c3
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c10
l---------src/mesa/drivers/dri/r600/server/radeon_egl.c1
8 files changed, 86 insertions, 37 deletions
diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile
index 8a45fc51b3..5d50941539 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -9,10 +9,6 @@ LIBNAME = r600_dri.so
MINIGLX_SOURCES = server/radeon_dri.c
-ifeq ($(USING_EGL), 1)
-EGL_SOURCES = server/radeon_egl.c
-endif
-
ifeq ($(RADEON_LDFLAGS),)
CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
endif
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 68112c49dc..ab3c7723c9 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -246,12 +246,11 @@ static void r600_init_vtbl(radeonContextPtr radeon)
static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
{
- context_t *r600 = R700_CONTEXT(ctx);
-
- ctx->Const.MaxTextureImageUnits =
- driQueryOptioni(&r600->radeon.optionCache, "texture_image_units");
- ctx->Const.MaxTextureCoordUnits =
- driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units");
+ ctx->Const.MaxTextureImageUnits = 16;
+ /* 8 per clause on r6xx, 16 on r7xx
+ * but I think mesa only supports 8 at the moment
+ */
+ ctx->Const.MaxTextureCoordUnits = 8;
ctx->Const.MaxTextureUnits =
MIN2(ctx->Const.MaxTextureImageUnits,
ctx->Const.MaxTextureCoordUnits);
@@ -286,9 +285,8 @@ static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
ctx->Const.FragmentProgram.MaxNativeAttribs = 32;
ctx->Const.FragmentProgram.MaxNativeParameters = 256;
ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192;
- /* 8 per clause on r6xx, 16 on rv670/r7xx */
- if ((screen->chip_family == CHIP_FAMILY_RV670) ||
- (screen->chip_family >= CHIP_FAMILY_RV770))
+ /* 8 per clause on r6xx, 16 on r7xx */
+ if (screen->chip_family >= CHIP_FAMILY_RV770)
ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16;
else
ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8;
diff --git a/src/mesa/drivers/dri/r600/r600_tex.h b/src/mesa/drivers/dri/r600/r600_tex.h
index c2141ef5e5..1d75a2ecd6 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.h
+++ b/src/mesa/drivers/dri/r600/r600_tex.h
@@ -42,7 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Texel pitch is 8 alignment. */
#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7
-#define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */
+#define R700_MAX_TEXTURE_UNITS 16
extern void r600SetDepthTexMode(struct gl_texture_object *tObj);
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index b8466bdd75..3289d89c92 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -85,6 +85,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+ CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -95,6 +96,11 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
+ CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
+ SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL,
+ SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
+ SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
+
switch (mesa_format) /* This is mesa format. */
{
case MESA_FORMAT_RGBA8888:
@@ -158,6 +164,32 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
break;
+ case MESA_FORMAT_XRGB8888:
+ SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
+ SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+ break;
+ case MESA_FORMAT_XRGB8888_REV:
+ SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
+ SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+ break;
case MESA_FORMAT_ARGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
@@ -515,6 +547,10 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
case MESA_FORMAT_Z24_S8:
case MESA_FORMAT_Z32:
case MESA_FORMAT_S8:
+ SETbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
+ SETfield(t->SQ_TEX_RESOURCE0, ARRAY_1D_TILED_THIN1,
+ SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
+ SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
switch (mesa_format) {
case MESA_FORMAT_Z16:
SETfield(t->SQ_TEX_RESOURCE1, FMT_16,
@@ -651,6 +687,12 @@ static GLuint r600_translate_shadow_func(GLenum func)
}
}
+static INLINE uint32_t
+S_FIXED(float value, uint32_t frac_bits)
+{
+ return value * (1 << frac_bits);
+}
+
void r600SetDepthTexMode(struct gl_texture_object *tObj)
{
radeonTexObjPtr t;
@@ -670,8 +712,9 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj)
* \param rmesa Context pointer
* \param t the r300 texture object
*/
-static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *texObj)
+static void setup_hardware_state(GLcontext * ctx, struct gl_texture_object *texObj, int unit)
{
+ context_t *rmesa = R700_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
const struct gl_texture_image *firstImage;
GLuint uTexelPitch, row_align;
@@ -733,11 +776,21 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
t->SQ_TEX_RESOURCE2 = get_base_teximage_offset(t) / 256;
- if ((t->maxLod - t->minLod) > 0) {
- t->SQ_TEX_RESOURCE3 = radeon_miptree_image_offset(t->mt, 0, t->minLod + 1) / 256;
- SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
- SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
- }
+ t->SQ_TEX_RESOURCE3 = radeon_miptree_image_offset(t->mt, 0, t->minLod + 1) / 256;
+
+ SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
+ SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
+
+ SETfield(t->SQ_TEX_SAMPLER1,
+ S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 6),
+ MIN_LOD_shift, MIN_LOD_mask);
+ SETfield(t->SQ_TEX_SAMPLER1,
+ S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 6),
+ MAX_LOD_shift, MAX_LOD_mask);
+ SETfield(t->SQ_TEX_SAMPLER1,
+ S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 6),
+ SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift, SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask);
+
if(texObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
{
SETfield(t->SQ_TEX_SAMPLER0, r600_translate_shadow_func(texObj->CompareFunc), DEPTH_COMPARE_FUNCTION_shift, DEPTH_COMPARE_FUNCTION_mask);
@@ -754,9 +807,8 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
*
* Mostly this means populating the texture object's mipmap tree.
*/
-static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj)
+static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj, int unit)
{
- context_t *rmesa = R700_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
if (!radeon_validate_texture_miptree(ctx, texObj))
@@ -764,7 +816,7 @@ static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object
/* Configure the hardware registers (more precisely, the cached version
* of the hardware registers). */
- setup_hardware_state(rmesa, texObj);
+ setup_hardware_state(ctx, texObj, unit);
t->validated = GL_TRUE;
return GL_TRUE;
@@ -805,7 +857,7 @@ GLboolean r600ValidateBuffers(GLcontext * ctx)
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
- if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
+ if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current, i)) {
radeon_warning("failed to validate texture for unit %d.\n", i);
}
t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index c01b2fbb14..89adb77bf5 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -4491,20 +4491,21 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
GLboolean assemble_XPD(r700_AssemblerBase *pAsm)
{
- BITS tmp;
+ BITS tmp1;
+ BITS tmp2 = 0;
if( GL_FALSE == checkop2(pAsm) )
{
return GL_FALSE;
}
- tmp = gethelpr(pAsm);
+ tmp1 = gethelpr(pAsm);
pAsm->D.dst.opcode = SQ_OP2_INST_MUL;
setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
+ pAsm->D.dst.reg = tmp1;
nomask_PVSDST(&(pAsm->D.dst));
if( GL_FALSE == assemble_src(pAsm, 0, -1) )
@@ -4530,11 +4531,11 @@ GLboolean assemble_XPD(r700_AssemblerBase *pAsm)
if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask)
{
- tmp = gethelpr(pAsm);
+ tmp2 = gethelpr(pAsm);
setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
+ pAsm->D.dst.reg = tmp2;
nomask_PVSDST(&(pAsm->D.dst));
}
@@ -4562,7 +4563,7 @@ GLboolean assemble_XPD(r700_AssemblerBase *pAsm)
// result1 + (neg) result0
setaddrmode_PVSSRC(&(pAsm->S[2].src),ADDR_ABSOLUTE);
pAsm->S[2].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[2].src.reg = tmp;
+ pAsm->S[2].src.reg = tmp1;
neg_PVSSRC(&(pAsm->S[2].src));
noswizzle_PVSSRC(&(pAsm->S[2].src));
@@ -4585,7 +4586,7 @@ GLboolean assemble_XPD(r700_AssemblerBase *pAsm)
// Use tmp as source
setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
+ pAsm->S[0].src.reg = tmp2;
noneg_PVSSRC(&(pAsm->S[0].src));
noswizzle_PVSSRC(&(pAsm->S[0].src));
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 1a1a87c3cf..ef25cd93fe 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -303,14 +303,13 @@ static void r700SetRenderTarget(context_t *context, int id)
R600_STATECHANGE(context, cb_target);
/* color buffer */
- r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
+ r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
nPitchInPixel = rrb->pitch/rrb->cpp;
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
- r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 3c8cb579f9..20e8afefba 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -59,6 +59,7 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
static void r700UpdatePolygonMode(GLcontext * ctx);
static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
static void r700SetStencilState(GLcontext * ctx, GLboolean state);
+static void r700UpdateWindow(GLcontext * ctx, int id);
void r700UpdateShaders(GLcontext * ctx)
{
@@ -780,6 +781,9 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
case GL_LINE_STIPPLE:
r700UpdateLineStipple(ctx);
break;
+ case GL_DEPTH_CLAMP:
+ r700UpdateWindow(ctx, 0);
+ break;
default:
break;
}
@@ -1576,9 +1580,9 @@ static void r700InitSQConfig(GLcontext * ctx)
SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
+ SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
+ SETfield(r700->sq_config.SQ_CONFIG.u32All, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
+ SETfield(r700->sq_config.SQ_CONFIG.u32All, es_prio, ES_PRIO_shift, ES_PRIO_mask);
r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
diff --git a/src/mesa/drivers/dri/r600/server/radeon_egl.c b/src/mesa/drivers/dri/r600/server/radeon_egl.c
deleted file mode 120000
index d7735a7643..0000000000
--- a/src/mesa/drivers/dri/r600/server/radeon_egl.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_egl.c \ No newline at end of file
generated by cgit v1.2.3 (git 2.51.0) at 2025-10-26 13:31:01 +0000