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-rw-r--r--src/mesa/drivers/dri/r600/r600_cmdbuf.c3
-rw-r--r--src/mesa/drivers/dri/r600/r600_context.c2
-rw-r--r--src/mesa/drivers/dri/r600/r600_context.h11
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c12
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c3
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c64
-rw-r--r--src/mesa/drivers/dri/r600/r700_clear.c1
-rw-r--r--src/mesa/drivers/dri/r600/r700_fragprog.c105
-rw-r--r--src/mesa/drivers/dri/r600/r700_oglprog.c2
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c27
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c126
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.h4
-rw-r--r--src/mesa/drivers/dri/r600/r700_vertprog.c20
13 files changed, 219 insertions, 161 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 8debecbab9..dc2fb0144a 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -457,6 +457,9 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */
GLuint size;
rmesa->hw.max_state_size = 4000; /* rough estimate */
+ rmesa->hw.all_dirty = GL_TRUE;
+ rmesa->hw.is_dirty = GL_TRUE;
+
/* Initialize command buffer */
size = 256 * driQueryOptioni(&rmesa->optionCache,
"command_buffer_size");
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index eacf811282..7009374b0c 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -395,6 +395,8 @@ r600DestroyContext (__DRIcontextPrivate * driContextPriv)
if (context)
FREE(context->hw.pStateList);
+
+ radeonDestroyContext(driContextPriv);
}
diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index fbb8164af5..30ddce682c 100644
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -158,6 +158,17 @@ extern GLboolean r700InitChipObject(context_t *context);
extern GLboolean r700SendContextStates(context_t *context);
extern GLboolean r700SendViewportState(context_t *context, int id);
extern GLboolean r700SendRenderTargetState(context_t *context, int id);
+extern GLboolean r700SendTextureState(context_t *context);
+extern GLboolean r700SendDepthTargetState(context_t *context);
+extern GLboolean r700SendUCPState(context_t *context);
+extern GLboolean r700SendFSState(context_t *context);
+extern void r700EmitState(GLcontext * ctx);
+
+extern GLboolean r700SyncSurf(context_t *context,
+ struct radeon_bo *pbo,
+ uint32_t read_domain,
+ uint32_t write_domain,
+ uint32_t sync_type);
extern int r700SetupStreams(GLcontext * ctx);
extern void r700SetupVTXConstants(GLcontext * ctx,
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 4840586858..ee9b64ee43 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -568,9 +568,6 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
}
}
- if (t->image_override && t->bo)
- return;
-
switch (texObj->Target) {
case GL_TEXTURE_1D:
SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D, DIM_shift, DIM_mask);
@@ -701,7 +698,7 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
struct gl_texture_object *tObj =
_mesa_lookup_texture(rmesa->radeon.glCtx, texname);
radeonTexObjPtr t = radeon_tex_obj(tObj);
- uint32_t pitch_val;
+ uint32_t pitch_val, size;
if (!tObj)
return;
@@ -711,7 +708,12 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
if (!offset)
return;
- t->bo = NULL;
+ size = pitch;//h * w * (depth / 8);
+ if (t->bo) {
+ radeon_bo_unref(t->bo);
+ t->bo = NULL;
+ }
+ t->bo = radeon_legacy_bo_alloc_fake(rmesa->radeon.radeonScreen->bom, size, offset);
t->override_offset = offset;
pitch_val = pitch;
switch (depth) {
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 0abf112b55..eaacd06113 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -3839,6 +3839,9 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm,
if (export_count == 1)
{
ucWriteMask = pAsm->pucOutMask[starting_register_number - pAsm->starting_export_register_number];
+ /* exports Z as a float into Red channel */
+ if (GL_TRUE == is_depth_export)
+ ucWriteMask = 0x1;
if( (ucWriteMask & 0x1) != 0)
{
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 78779e841d..0fb355a0b6 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -138,6 +138,19 @@ GLboolean r700InitChipObject(context_t *context)
LINK_STATES(CB_CLRCMP_MSK);
LINK_STATES(CB_BLEND_CONTROL);
+ //DB
+ LINK_STATES(DB_HTILE_DATA_BASE);
+ LINK_STATES(DB_STENCIL_CLEAR);
+ LINK_STATES(DB_DEPTH_CLEAR);
+ LINK_STATES(DB_STENCILREFMASK);
+ LINK_STATES(DB_STENCILREFMASK_BF);
+ LINK_STATES(DB_DEPTH_CONTROL);
+ LINK_STATES(DB_SHADER_CONTROL);
+ LINK_STATES(DB_RENDER_CONTROL);
+ LINK_STATES(DB_RENDER_OVERRIDE);
+ LINK_STATES(DB_HTILE_SURFACE);
+ LINK_STATES(DB_ALPHA_TO_MASK);
+
// SX
LINK_STATES(SX_MISC);
LINK_STATES(SX_ALPHA_TEST_CONTROL);
@@ -322,7 +335,7 @@ void r700SetupVTXConstants(GLcontext * ctx,
unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
if (!paos->bo)
- return GL_FALSE;
+ return;
if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
@@ -474,6 +487,18 @@ GLboolean r700SendContextStates(context_t *context)
for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
END_BATCH();
+
+ if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
+ for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
+ if (r700->render_target[ui].enabled) {
+ BEGIN_BATCH_NO_AUTOSTATE(3);
+ R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
+ r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
+ END_BATCH();
+ }
+ }
+ }
+
COMMIT_BATCH();
return GL_TRUE;
@@ -491,38 +516,25 @@ GLboolean r700SendDepthTargetState(context_t *context)
return GL_FALSE;
}
- BEGIN_BATCH_NO_AUTOSTATE(9);
+ BEGIN_BATCH_NO_AUTOSTATE(8);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
- R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 3);
+ R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
rrb->bo,
r700->DB_DEPTH_BASE.u32All,
0, RADEON_GEM_DOMAIN_VRAM, 0);
R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
- R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All);
END_BATCH();
- BEGIN_BATCH_NO_AUTOSTATE(24);
- R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
- R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
- R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
-
- R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
- R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
- R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
-
- R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
- R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
-
- R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
- R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
- R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
-
- R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
- R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
- END_BATCH();
+ if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
+ (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
+ BEGIN_BATCH_NO_AUTOSTATE(2);
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
+ R600_OUT_BATCH(1 << 0);
+ END_BATCH();
+ }
COMMIT_BATCH();
@@ -575,12 +587,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
END_BATCH();
- if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All);
- END_BATCH();
- }
-
COMMIT_BATCH();
r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c
index e84be38622..05d4af331e 100644
--- a/src/mesa/drivers/dri/r600/r700_clear.c
+++ b/src/mesa/drivers/dri/r600/r700_clear.c
@@ -31,6 +31,7 @@
#include "main/imports.h"
#include "main/mtypes.h"
#include "main/enums.h"
+#include "swrast/swrast.h"
#include "radeon_lock.h"
#include "r600_context.h"
diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c
index 4ac37f1dfe..6249bde6f1 100644
--- a/src/mesa/drivers/dri/r600/r700_fragprog.c
+++ b/src/mesa/drivers/dri/r600/r700_fragprog.c
@@ -55,6 +55,12 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm,
//Input mapping : mesa_fp->Base.InputsRead set the flag, set in
//The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
//MUST match order in Map_Vertex_Output
+ unBit = 1 << FRAG_ATTRIB_WPOS;
+ if(mesa_fp->Base.InputsRead & unBit)
+ {
+ pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
+ }
+
unBit = 1 << FRAG_ATTRIB_COL0;
if(mesa_fp->Base.InputsRead & unBit)
{
@@ -112,6 +118,7 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm,
pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++;
pAsm->number_of_exports++;
pAsm->number_of_colorandz_exports++;
+ pAsm->pR700Shader->depthIsExported = 1;
}
pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
@@ -263,11 +270,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
+ BATCH_LOCALS(&context->radeon);
struct r700_fragment_program *fp = (struct r700_fragment_program *)
(ctx->FragmentProgram._Current);
r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
+ struct gl_program_parameter_list *paramList;
+ unsigned int unNumParamData;
unsigned int ui, i;
unsigned int unNumOfReg;
unsigned int unBit;
@@ -302,6 +311,16 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
+ /* PS uses fragment.position */
+ if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+ {
+ ui += 1;
+ SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
+ SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
+ SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
+ SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
+ }
+
ui = (unNumOfReg < ui) ? ui : unNumOfReg;
SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
@@ -335,7 +354,49 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
}
+ /* sent out shader constants. */
+ paramList = fp->mesa_program.Base.Parameters;
+
+ if(NULL != paramList)
+ {
+ _mesa_load_state_parameters(ctx, paramList);
+
+ unNumParamData = paramList->NumParameters * 4;
+
+ BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData);
+
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
+
+ /* assembler map const from very beginning. */
+ R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
+
+ unNumParamData = paramList->NumParameters;
+
+ for(ui=0; ui<unNumParamData; ui++)
+ {
+ R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
+ R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
+ R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
+ R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
+ }
+ END_BATCH();
+ COMMIT_BATCH();
+ }
+
// emit ps input map
+ unBit = 1 << FRAG_ATTRIB_WPOS;
+ if(mesa_fp->Base.InputsRead & unBit)
+ {
+ ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
+ SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+ SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+ SEMANTIC_shift, SEMANTIC_mask);
+ if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+ SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+ else
+ CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+ }
+
unBit = 1 << FRAG_ATTRIB_COL0;
if(mesa_fp->Base.InputsRead & unBit)
{
@@ -391,45 +452,3 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
return GL_TRUE;
}
-GLboolean r700SendPSConstants(GLcontext * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- struct r700_fragment_program *fp = (struct r700_fragment_program *)
- (ctx->FragmentProgram._Current);
- struct gl_program_parameter_list *paramList;
- unsigned int unNumParamData;
- unsigned int ui;
-
- /* sent out shader constants. */
- paramList = fp->mesa_program.Base.Parameters;
-
- if(NULL != paramList)
- {
- _mesa_load_state_parameters(ctx, paramList);
-
- unNumParamData = paramList->NumParameters * 4;
-
- BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
-
- /* assembler map const from very beginning. */
- R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
-
- unNumParamData = paramList->NumParameters;
-
- for(ui=0; ui<unNumParamData; ui++)
- {
- R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
- R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
- R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
- R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
- }
- END_BATCH();
- COMMIT_BATCH();
- }
-
- return GL_TRUE;
-}
-
diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c
index 36de143b1a..c49b90c1cc 100644
--- a/src/mesa/drivers/dri/r600/r700_oglprog.c
+++ b/src/mesa/drivers/dri/r600/r700_oglprog.c
@@ -33,6 +33,7 @@
#include "tnl/tnl.h"
#include "r600_context.h"
+#include "r600_emit.h"
#include "r700_oglprog.h"
#include "r700_fragprog.h"
@@ -87,7 +88,6 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog)
{
struct r700_vertex_program * vp;
struct r700_fragment_program * fp;
- context_t *context = R700_CONTEXT(ctx);
switch (prog->Target)
{
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 2592d7df14..6705dbcf4b 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -139,6 +139,13 @@ static GLboolean r700SetupShaders(GLcontext * ctx)
r600UpdateTextureState(ctx);
+ r700SendFSState(context); // FIXME just a place holder for now
+ r700SendPSState(context);
+ r700SendVSState(context);
+
+ r700SendTextureState(context);
+ r700SetupStreams(ctx);
+
return GL_TRUE;
}
@@ -274,20 +281,15 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
void r700EmitState(GLcontext * ctx)
{
context_t *context = R700_CONTEXT(ctx);
+ radeonContextPtr radeon = &context->radeon;
+
+ if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
+ return;
rcommonEnsureCmdBufSpace(&context->radeon,
context->radeon.hw.max_state_size, __FUNCTION__);
- r700Start3D(context);
r700SendSQConfig(context);
- r700SendFSState(context); // FIXME just a place holder for now
- r700SendPSState(context);
- r700SendVSState(context);
- r700SendVSConstants(ctx);
- r700SendPSConstants(ctx);
-
- r700SendTextureState(context);
- r700SetupStreams(ctx);
r700SendUCPState(context);
r700SendContextStates(context);
@@ -305,13 +307,12 @@ static GLboolean r700RunRender(GLcontext * ctx,
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
+ r700Start3D(context);
+
r700UpdateShaders(ctx);
r700SetScissor(context);
r700SetupShaders(ctx);
- r700SetRenderTarget(context, 0);
- r700SetDepthTarget(context);
-
r700EmitState(ctx);
/* richard test code */
@@ -327,8 +328,6 @@ static GLboolean r700RunRender(GLcontext * ctx,
radeonReleaseArrays(ctx, ~0);
- rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ );
-
return GL_FALSE;
}
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index e0a5742591..835b5e18c2 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -60,6 +60,8 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
static void r700UpdatePolygonMode(GLcontext * ctx);
static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
static void r700SetStencilState(GLcontext * ctx, GLboolean state);
+static void r700SetRenderTarget(context_t *context, int id);
+static void r700SetDepthTarget(context_t *context);
void r700SetDefaultStates(context_t *context) //--------------------
{
@@ -158,29 +160,16 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
*/
void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
{
-#if 0 /* to be enabled */
- context_t *context = R700_CONTEXT(ctx);
+ context_t *context = R700_CONTEXT(ctx);
- switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
- {
- case BUFFER_FRONT_LEFT:
- context->target.rt = context->screen->frontBuffer;
- break;
- case BUFFER_BACK_LEFT:
- context->target.rt = context->screen->backBuffer;
- break;
- default:
- memset (&context->target.rt, sizeof(context->target.rt), 0);
- }
-#endif /* to be enabled */
+ r700SetRenderTarget(context, 0);
+ r700SetDepthTarget(context);
}
static void r700FetchStateParameter(GLcontext * ctx,
const gl_state_index state[STATE_LENGTH],
GLfloat * value)
{
- context_t *context = R700_CONTEXT(ctx);
-
/* TODO */
}
@@ -600,14 +589,46 @@ static void r700BlendFuncSeparate(GLcontext * ctx,
/**
* Translate LogicOp enums into hardware representation.
- * Both use a very logical bit-wise layout, but unfortunately the order
- * of bits is reversed.
*/
static GLuint translate_logicop(GLenum logicop)
{
- GLuint bits = logicop - GL_CLEAR;
- bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
- return bits;
+ switch (logicop) {
+ case GL_CLEAR:
+ return 0x00;
+ case GL_SET:
+ return 0xff;
+ case GL_COPY:
+ return 0xcc;
+ case GL_COPY_INVERTED:
+ return 0x33;
+ case GL_NOOP:
+ return 0xaa;
+ case GL_INVERT:
+ return 0x55;
+ case GL_AND:
+ return 0x88;
+ case GL_NAND:
+ return 0x77;
+ case GL_OR:
+ return 0xee;
+ case GL_NOR:
+ return 0x11;
+ case GL_XOR:
+ return 0x66;
+ case GL_EQUIV:
+ return 0xaa;
+ case GL_AND_REVERSE:
+ return 0x44;
+ case GL_AND_INVERTED:
+ return 0x22;
+ case GL_OR_REVERSE:
+ return 0xdd;
+ case GL_OR_INVERTED:
+ return 0xbb;
+ default:
+ fprintf(stderr, "unknown blend logic operation %x\n", logicop);
+ return 0xcc;
+ }
}
/**
@@ -1327,22 +1348,22 @@ void r700SetScissor(context_t *context) //---------------
r700->viewport[id].enabled = GL_TRUE;
}
-void r700SetRenderTarget(context_t *context, int id)
+static void r700SetRenderTarget(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
+ rrb = radeon_get_colorbuffer(&context->radeon);
+ if (!rrb || !rrb->bo) {
+ fprintf(stderr, "no rrb\n");
+ return;
+ }
+
/* screen/window/view */
SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
- }
-
/* color buffer */
r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
@@ -1375,39 +1396,22 @@ void r700SetRenderTarget(context_t *context, int id)
r700->render_target[id].enabled = GL_TRUE;
}
-void r700SetDepthTarget(context_t *context)
+static void r700SetDepthTarget(context_t *context)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
+ rrb = radeon_get_depthbuffer(&context->radeon);
+ if (!rrb)
+ return;
+
/* depth buf */
r700->DB_DEPTH_SIZE.u32All = 0;
r700->DB_DEPTH_BASE.u32All = 0;
r700->DB_DEPTH_INFO.u32All = 0;
-
- r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
- r700->DB_DEPTH_VIEW.u32All = 0;
- r700->DB_RENDER_CONTROL.u32All = 0;
- SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
- SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
- r700->DB_RENDER_OVERRIDE.u32All = 0;
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
-
- r700->DB_ALPHA_TO_MASK.u32All = 0;
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (!rrb)
- return;
+ r700->DB_DEPTH_VIEW.u32All = 0;
nPitchInPixel = rrb->pitch/rrb->cpp;
@@ -1757,6 +1761,24 @@ void r700InitState(GLcontext * ctx) //-------------------
r700DepthFunc(ctx, ctx->Depth.Func);
SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
+ r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
+
+ r700->DB_RENDER_CONTROL.u32All = 0;
+ SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
+ SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
+ r700->DB_RENDER_OVERRIDE.u32All = 0;
+ if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+ SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
+
+ r700->DB_ALPHA_TO_MASK.u32All = 0;
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
+
/* stencil */
r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
@@ -1822,6 +1844,8 @@ void r700InitState(GLcontext * ctx) //-------------------
/* Set up color compare mask */
r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
+ context->radeon.hw.all_dirty = GL_TRUE;
+
}
void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h
index 23246367db..30eb54e8b0 100644
--- a/src/mesa/drivers/dri/r600/r700_state.h
+++ b/src/mesa/drivers/dri/r600/r700_state.h
@@ -42,10 +42,8 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx);
extern void r700InitState (GLcontext * ctx);
extern void r700InitStateFuncs (struct dd_function_table *functions);
-extern void r700SetRenderTarget(context_t *context, int id);
extern void r700SetDefaultStates(context_t * context);
-void r700SetScissor(context_t *context);
-void r700SetDepthTarget(context_t *context);
+extern void r700SetScissor(context_t *context);
#endif /* _R600_SCREEN_H */
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index 1c5c20f66e..31e71cdfa3 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -336,10 +336,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
+ BATCH_LOCALS(&context->radeon);
struct r700_vertex_program *vp
= (struct r700_vertex_program *)ctx->VertexProgram._Current;
+ struct gl_program_parameter_list *paramList;
+ unsigned int unNumParamData;
+ unsigned int ui;
+
if(GL_FALSE == vp->loaded)
{
if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
@@ -385,21 +389,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
*/
- return GL_TRUE;
-}
-
-GLboolean r700SendVSConstants(GLcontext * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- struct r700_vertex_program *vp
- = (struct r700_vertex_program *)ctx->VertexProgram._Current;
- struct gl_program_parameter_list *paramList;
- unsigned int unNumParamData;
- unsigned int ui;
-
/* sent out shader constants. */
-
paramList = vp->mesa_program.Base.Parameters;
if(NULL != paramList)
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-12 11:08:11 +0000