diff options
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_bo_legacy.c')
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 181 |
1 files changed, 127 insertions, 54 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 1fec7444cd..992eb4611b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -69,6 +69,9 @@ struct bo_legacy { void *ptr; struct bo_legacy *next, *prev; struct bo_legacy *pnext, *pprev; +#ifdef RADEON_DEBUG_BO + char szBufUsage[16]; +#endif /* RADEON_DEBUG_BO */ }; struct bo_manager_legacy { @@ -168,7 +171,9 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml) unsigned char *RADEONMMIO = NULL; int r; - if (IS_R300_CLASS(boml->screen)) { + if ( IS_R300_CLASS(boml->screen) + || IS_R600_CLASS(boml->screen) ) + { gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&boml->current_age; r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM, @@ -177,7 +182,8 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml) fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); exit(1); } - } else { + } + else { RADEONMMIO = boml->screen->mmio.map; boml->current_age = boml->screen->scratch[3]; boml->current_age = INREG(RADEON_GUI_SCRATCH_REG3); @@ -283,7 +289,12 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, uint32_t size, uint32_t alignment, uint32_t domains, +#ifdef RADEON_DEBUG_BO + uint32_t flags, + char * szBufUsage) +#else uint32_t flags) +#endif /* RADEON_DEBUG_BO */ { struct bo_legacy *bo_legacy; static int pgsize; @@ -315,6 +326,11 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, if (bo_legacy->next) { bo_legacy->next->prev = bo_legacy; } + +#ifdef RADEON_DEBUG_BO + sprintf(bo_legacy->szBufUsage, "%s", szBufUsage); +#endif /* RADEON_DEBUG_BO */ + return bo_legacy; } @@ -413,7 +429,12 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, uint32_t size, uint32_t alignment, uint32_t domains, +#ifdef RADEON_DEBUG_BO + uint32_t flags, + char * szBufUsage) +#else uint32_t flags) +#endif /* RADEON_DEBUG_BO */ { struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom; struct bo_legacy *bo_legacy; @@ -430,29 +451,37 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, } return NULL; } - +#ifdef RADEON_DEBUG_BO + bo_legacy = bo_allocate(boml, size, alignment, domains, flags, szBufUsage); +#else bo_legacy = bo_allocate(boml, size, alignment, domains, flags); +#endif /* RADEON_DEBUG_BO */ bo_legacy->static_bo = 0; r = legacy_new_handle(boml, &bo_legacy->base.handle); if (r) { bo_free(bo_legacy); return NULL; } - if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) { - retry: + if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) + { +retry: legacy_track_pending(boml, 0); /* dma buffers */ r = bo_dma_alloc(&(bo_legacy->base)); - if (r) { - if (legacy_wait_any_pending(boml) == -1) { - bo_free(bo_legacy); - return NULL; - } - goto retry; - return NULL; + if (r) + { + if (legacy_wait_any_pending(boml) == -1) + { + bo_free(bo_legacy); + return NULL; + } + goto retry; + return NULL; } - } else { + } + else + { bo_legacy->ptr = malloc(bo_legacy->base.size); if (bo_legacy->ptr == NULL) { bo_free(bo_legacy); @@ -460,6 +489,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, } } radeon_bo_ref(&(bo_legacy->base)); + return (struct radeon_bo*)bo_legacy; } @@ -488,7 +518,7 @@ static int bo_map(struct radeon_bo *bo, int write) { struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; - + legacy_wait_pending(bo); bo_legacy->validated = 0; bo_legacy->dirty = 1; @@ -514,6 +544,7 @@ static int bo_map(struct radeon_bo *bo, int write) volatile int *buf = (int*)boml->screen->driScreen->pFB; p = *buf; } + return 0; } @@ -521,10 +552,13 @@ static int bo_unmap(struct radeon_bo *bo) { struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; - if (--bo_legacy->map_count > 0) { + if (--bo_legacy->map_count > 0) + { return 0; } + bo->ptr = NULL; + return 0; } @@ -587,44 +621,53 @@ static int bo_vram_validate(struct radeon_bo *bo, driUpdateTextureLRU(&bo_legacy->tobj->base); if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) { - /* Copy to VRAM using a blit. - * All memory is 4K aligned. We're using 1024 pixels wide blits. - */ - drm_radeon_texture_t tex; - drm_radeon_tex_image_t tmp; - int ret; - - tex.offset = bo_legacy->offset; - tex.image = &tmp; - assert(!(tex.offset & 1023)); - - tmp.x = 0; - tmp.y = 0; - if (bo->size < 4096) { - tmp.width = (bo->size + 3) / 4; - tmp.height = 1; - } else { - tmp.width = 1024; - tmp.height = (bo->size + 4095) / 4096; - } - tmp.data = bo_legacy->ptr; - tex.format = RADEON_TXFORMAT_ARGB8888; - tex.width = tmp.width; - tex.height = tmp.height; - tex.pitch = MAX2(tmp.width / 16, 1); - do { - ret = drmCommandWriteRead(bo->bom->fd, - DRM_RADEON_TEXTURE, - &tex, - sizeof(drm_radeon_texture_t)); - if (ret) { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n"); - usleep(1); - } - } while (ret == -EAGAIN); - bo_legacy->dirty = 0; - bo_legacy->tobj->base.dirty_images[0] = 0; + if (IS_R600_CLASS(boml->screen)) { + char *src = bo_legacy->ptr; + char *dst = (char *) boml->screen->driScreen->pFB + + (bo_legacy->offset - boml->fb_location); + + /* FIXME: alignment, pitch, etc. */ + memcpy(dst, src, bo->size); + } else { + /* Copy to VRAM using a blit. + * All memory is 4K aligned. We're using 1024 pixels wide blits. + */ + drm_radeon_texture_t tex; + drm_radeon_tex_image_t tmp; + int ret; + + tex.offset = bo_legacy->offset; + tex.image = &tmp; + assert(!(tex.offset & 1023)); + + tmp.x = 0; + tmp.y = 0; + if (bo->size < 4096) { + tmp.width = (bo->size + 3) / 4; + tmp.height = 1; + } else { + tmp.width = 1024; + tmp.height = (bo->size + 4095) / 4096; + } + tmp.data = bo_legacy->ptr; + tex.format = RADEON_TXFORMAT_ARGB8888; + tex.width = tmp.width; + tex.height = tmp.height; + tex.pitch = MAX2(tmp.width / 16, 1); + do { + ret = drmCommandWriteRead(bo->bom->fd, + DRM_RADEON_TEXTURE, + &tex, + sizeof(drm_radeon_texture_t)); + if (ret) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n"); + usleep(1); + } + } while (ret == -EAGAIN); + } + bo_legacy->dirty = 0; + bo_legacy->tobj->base.dirty_images[0] = 0; } return 0; } @@ -646,13 +689,20 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo, int retries = 0; if (bo_legacy->map_count) { +#ifdef RADEON_DEBUG_BO + fprintf(stderr, "bo(%p, %d, %s) is mapped (%d) can't valide it.\n", + bo, bo->size, bo_legacy->szBufUsage, bo_legacy->map_count); +#else fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n", bo, bo->size, bo_legacy->map_count); +#endif /* RADEON_DEBUG_BO */ + return -EINVAL; } if (bo_legacy->static_bo || bo_legacy->validated) { *soffset = bo_legacy->offset; *eoffset = bo_legacy->offset + bo->size; + return 0; } if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) { @@ -673,6 +723,7 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo, *soffset = bo_legacy->offset; *eoffset = bo_legacy->offset + bo->size; bo_legacy->validated = 1; + return 0; } @@ -717,11 +768,21 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom) } static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy *bom, - int size, uint32_t offset) + int size, +#ifdef RADEON_DEBUG_BO + uint32_t offset, + char * szBufUsage) +#else + uint32_t offset) +#endif /* RADEON_DEBUG_BO */ { struct bo_legacy *bo; +#ifdef RADEON_DEBUG_BO + bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0, szBufUsage); +#else bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); +#endif /* RADEON_DEBUG_BO */ if (bo == NULL) return NULL; bo->static_bo = 1; @@ -782,7 +843,11 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc size = 4096*4096*4; /* allocate front */ +#ifdef RADEON_DEBUG_BO + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset, "FRONT BUF"); +#else bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset); +#endif /* RADEON_DEBUG_BO */ if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; @@ -792,7 +857,11 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc } /* allocate back */ +#ifdef RADEON_DEBUG_BO + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset, "BACK BUF"); +#else bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset); +#endif /* RADEON_DEBUG_BO */ if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; @@ -802,7 +871,11 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc } /* allocate depth */ +#ifdef RADEON_DEBUG_BO + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset, "Z BUF"); +#else bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset); +#endif /* RADEON_DEBUG_BO */ if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; |