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path: root/src/mesa/drivers/dri/radeon/radeon_tcl.c
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Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_tcl.c')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_tcl.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c
index 779e9ae5df..b59685790c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c
@@ -104,7 +104,7 @@ static GLboolean discrete_prim[0x10] = {
};
-#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
+#define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
#define ELT_TYPE GLushort
#define ELT_INIT(prim, hw_prim) \
@@ -143,10 +143,10 @@ static GLboolean discrete_prim[0x10] = {
#define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
-static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr )
+static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
{
if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa );
+ rmesa->dma.flush( rmesa->radeon.glCtx );
radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + ELTS_BUFSZ(nr));
@@ -174,7 +174,7 @@ static void radeonEmitPrim( GLcontext *ctx,
GLuint start,
GLuint count)
{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+ r100ContextPtr rmesa = R100_CONTEXT( ctx );
radeonTclPrimitive( ctx, prim, hwprim );
radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
@@ -254,7 +254,7 @@ void radeonTclPrimitive( GLcontext *ctx,
GLenum prim,
int hw_prim )
{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
GLuint se_cntl;
GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
@@ -371,7 +371,7 @@ radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord )
static GLboolean radeon_run_tcl_render( GLcontext *ctx,
struct tnl_pipeline_stage *stage )
{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
@@ -379,7 +379,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx,
/* TODO: separate this from the swtnl pipeline
*/
- if (rmesa->TclFallback)
+ if (rmesa->radeon.TclFallback)
return GL_TRUE; /* fallback to software t&l */
if (VB->Count == 0)
@@ -461,7 +461,7 @@ const struct tnl_pipeline_stage _radeon_tcl_stage =
static void transition_to_swtnl( GLcontext *ctx )
{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
GLuint se_cntl;
@@ -490,7 +490,7 @@ static void transition_to_swtnl( GLcontext *ctx )
static void transition_to_hwtnl( GLcontext *ctx )
{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
@@ -510,7 +510,7 @@ static void transition_to_hwtnl( GLcontext *ctx )
tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
if ( rmesa->dma.flush )
- rmesa->dma.flush( rmesa );
+ rmesa->dma.flush( rmesa->radeon.glCtx );
rmesa->dma.flush = NULL;
rmesa->swtcl.vertex_format = 0;
@@ -550,11 +550,11 @@ static char *getFallbackString(GLuint bit)
void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint oldfallback = rmesa->TclFallback;
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ GLuint oldfallback = rmesa->radeon.TclFallback;
if (mode) {
- rmesa->TclFallback |= bit;
+ rmesa->radeon.TclFallback |= bit;
if (oldfallback == 0) {
if (RADEON_DEBUG & DEBUG_FALLBACKS)
fprintf(stderr, "Radeon begin tcl fallback %s\n",
@@ -563,7 +563,7 @@ void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
}
}
else {
- rmesa->TclFallback &= ~bit;
+ rmesa->radeon.TclFallback &= ~bit;
if (oldfallback == bit) {
if (RADEON_DEBUG & DEBUG_FALLBACKS)
fprintf(stderr, "Radeon end tcl fallback %s\n",