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-rw-r--r--src/mesa/drivers/dri/radeon/radeon_chipset.h113
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.c44
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.h11
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_ioctl.c28
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_ioctl.h10
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c526
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.h4
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_span.c4
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state.c24
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_tcl.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_tex.h4
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_texmem.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_texstate.c83
13 files changed, 601 insertions, 254 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index 7318099093..55a73eab20 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -106,6 +106,7 @@
#define PCI_CHIP_RV410_564F 0x564F
#define PCI_CHIP_RV410_5652 0x5652
#define PCI_CHIP_RV410_5653 0x5653
+#define PCI_CHIP_RV410_5657 0x5657
#define PCI_CHIP_RS300_5834 0x5834
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS480_5954 0x5954
@@ -145,8 +146,112 @@
#define PCI_CHIP_RV410_5E4C 0x5E4C
#define PCI_CHIP_RV410_5E4D 0x5E4D
#define PCI_CHIP_RV410_5E4F 0x5E4F
+
+#define PCI_CHIP_R520_7100 0x7100
+#define PCI_CHIP_R520_7101 0x7101
+#define PCI_CHIP_R520_7102 0x7102
+#define PCI_CHIP_R520_7103 0x7103
+#define PCI_CHIP_R520_7104 0x7104
+#define PCI_CHIP_R520_7105 0x7105
+#define PCI_CHIP_R520_7106 0x7106
+#define PCI_CHIP_R520_7108 0x7108
+#define PCI_CHIP_R520_7109 0x7109
+#define PCI_CHIP_R520_710A 0x710A
+#define PCI_CHIP_R520_710B 0x710B
+#define PCI_CHIP_R520_710C 0x710C
+#define PCI_CHIP_R520_710E 0x710E
+#define PCI_CHIP_R520_710F 0x710F
+#define PCI_CHIP_RV515_7140 0x7140
+#define PCI_CHIP_RV515_7141 0x7141
+#define PCI_CHIP_RV515_7142 0x7142
+#define PCI_CHIP_RV515_7143 0x7143
+#define PCI_CHIP_RV515_7144 0x7144
+#define PCI_CHIP_RV515_7145 0x7145
+#define PCI_CHIP_RV515_7146 0x7146
+#define PCI_CHIP_RV515_7147 0x7147
+#define PCI_CHIP_RV515_7149 0x7149
+#define PCI_CHIP_RV515_714A 0x714A
+#define PCI_CHIP_RV515_714B 0x714B
+#define PCI_CHIP_RV515_714C 0x714C
+#define PCI_CHIP_RV515_714D 0x714D
+#define PCI_CHIP_RV515_714E 0x714E
+#define PCI_CHIP_RV515_714F 0x714F
+#define PCI_CHIP_RV515_7151 0x7151
+#define PCI_CHIP_RV515_7152 0x7152
+#define PCI_CHIP_RV515_7153 0x7153
+#define PCI_CHIP_RV515_715E 0x715E
+#define PCI_CHIP_RV515_715F 0x715F
+#define PCI_CHIP_RV515_7180 0x7180
+#define PCI_CHIP_RV515_7181 0x7181
+#define PCI_CHIP_RV515_7183 0x7183
+#define PCI_CHIP_RV515_7186 0x7186
+#define PCI_CHIP_RV515_7187 0x7187
+#define PCI_CHIP_RV515_7188 0x7188
+#define PCI_CHIP_RV515_718A 0x718A
+#define PCI_CHIP_RV515_718B 0x718B
+#define PCI_CHIP_RV515_718C 0x718C
+#define PCI_CHIP_RV515_718D 0x718D
+#define PCI_CHIP_RV515_718F 0x718F
+#define PCI_CHIP_RV515_7193 0x7193
+#define PCI_CHIP_RV515_7196 0x7196
+#define PCI_CHIP_RV515_719B 0x719B
+#define PCI_CHIP_RV515_719F 0x719F
+#define PCI_CHIP_RV530_71C0 0x71C0
+#define PCI_CHIP_RV530_71C1 0x71C1
+#define PCI_CHIP_RV530_71C2 0x71C2
+#define PCI_CHIP_RV530_71C3 0x71C3
+#define PCI_CHIP_RV530_71C4 0x71C4
+#define PCI_CHIP_RV530_71C5 0x71C5
+#define PCI_CHIP_RV530_71C6 0x71C6
+#define PCI_CHIP_RV530_71C7 0x71C7
+#define PCI_CHIP_RV530_71CD 0x71CD
+#define PCI_CHIP_RV530_71CE 0x71CE
+#define PCI_CHIP_RV530_71D2 0x71D2
+#define PCI_CHIP_RV530_71D4 0x71D4
+#define PCI_CHIP_RV530_71D5 0x71D5
+#define PCI_CHIP_RV530_71D6 0x71D6
+#define PCI_CHIP_RV530_71DA 0x71DA
+#define PCI_CHIP_RV530_71DE 0x71DE
+#define PCI_CHIP_RV515_7200 0x7200
+#define PCI_CHIP_RV515_7210 0x7210
+#define PCI_CHIP_RV515_7211 0x7211
+#define PCI_CHIP_R580_7240 0x7240
+#define PCI_CHIP_R580_7243 0x7243
+#define PCI_CHIP_R580_7244 0x7244
+#define PCI_CHIP_R580_7245 0x7245
+#define PCI_CHIP_R580_7246 0x7246
+#define PCI_CHIP_R580_7247 0x7247
+#define PCI_CHIP_R580_7248 0x7248
+#define PCI_CHIP_R580_7249 0x7249
+#define PCI_CHIP_R580_724A 0x724A
+#define PCI_CHIP_R580_724B 0x724B
+#define PCI_CHIP_R580_724C 0x724C
+#define PCI_CHIP_R580_724D 0x724D
+#define PCI_CHIP_R580_724E 0x724E
+#define PCI_CHIP_R580_724F 0x724F
+#define PCI_CHIP_RV570_7280 0x7280
+#define PCI_CHIP_RV560_7281 0x7281
+#define PCI_CHIP_RV560_7283 0x7283
+#define PCI_CHIP_R580_7284 0x7284
+#define PCI_CHIP_RV560_7287 0x7287
+#define PCI_CHIP_RV570_7288 0x7288
+#define PCI_CHIP_RV570_7289 0x7289
+#define PCI_CHIP_RV570_728B 0x728B
+#define PCI_CHIP_RV570_728C 0x728C
+#define PCI_CHIP_RV560_7290 0x7290
+#define PCI_CHIP_RV560_7291 0x7291
+#define PCI_CHIP_RV560_7293 0x7293
+#define PCI_CHIP_RV560_7297 0x7297
+
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
+#define PCI_CHIP_RS690_791E 0x791E
+#define PCI_CHIP_RS690_791F 0x791F
+#define PCI_CHIP_RS740_796C 0x796C
+#define PCI_CHIP_RS740_796D 0x796D
+#define PCI_CHIP_RS740_796E 0x796E
+#define PCI_CHIP_RS740_796F 0x796F
+
enum {
CHIP_FAMILY_R100,
@@ -165,6 +270,14 @@ enum {
CHIP_FAMILY_R420,
CHIP_FAMILY_RV410,
CHIP_FAMILY_RS400,
+ CHIP_FAMILY_RS690,
+ CHIP_FAMILY_RS740,
+ CHIP_FAMILY_RV515,
+ CHIP_FAMILY_R520,
+ CHIP_FAMILY_RV530,
+ CHIP_FAMILY_R580,
+ CHIP_FAMILY_RV560,
+ CHIP_FAMILY_RV570,
CHIP_FAMILY_LAST
};
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index ba93a054ae..1e992c0b3d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -34,14 +34,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* Keith Whitwell <keith@tungstengraphics.com>
*/
-#include "glheader.h"
-#include "api_arrayelt.h"
-#include "context.h"
-#include "simple_list.h"
-#include "imports.h"
-#include "matrix.h"
-#include "extensions.h"
-#include "framebuffer.h"
+#include "main/glheader.h"
+#include "main/api_arrayelt.h"
+#include "main/context.h"
+#include "main/simple_list.h"
+#include "main/imports.h"
+#include "main/matrix.h"
+#include "main/extensions.h"
+#include "main/framebuffer.h"
+#include "main/state.h"
#include "swrast/swrast.h"
#include "swrast_setup/swrast_setup.h"
@@ -231,14 +232,14 @@ radeonCreateContext( const __GLcontextModes *glVisual,
"def_max_anisotropy");
if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
- if ( sPriv->drmMinor < 13 )
+ if ( sPriv->drm_version.minor < 13 )
fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
- "disabling.\n",sPriv->drmMinor );
+ "disabling.\n", sPriv->drm_version.minor );
else
rmesa->using_hyperz = GL_TRUE;
}
- if ( sPriv->drmMinor >= 15 )
+ if ( sPriv->drm_version.minor >= 15 )
rmesa->texmicrotile = GL_TRUE;
/* Init default driver functions then plug in our Radeon-specific functions
@@ -269,7 +270,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
rmesa->dri.hwContext = driContextPriv->hHWContext;
rmesa->dri.hwLock = &sPriv->pSAREA->lock;
rmesa->dri.fd = sPriv->fd;
- rmesa->dri.drmMinor = sPriv->drmMinor;
+ rmesa->dri.drmMinor = sPriv->drm_version.minor;
rmesa->radeonScreen = screen;
rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
@@ -422,10 +423,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
- rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
- ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
-
- (*dri_interface->getUST)( & rmesa->swap_ust );
+ (*sPriv->systemTime->getUST)( & rmesa->swap_ust );
#if DO_DEBUG
@@ -590,16 +588,18 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
- if ( newCtx->dri.drawable != driDrawPriv ) {
- /* XXX we may need to validate the drawable here!!! */
- driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags,
- &newCtx->vbl_seq );
- }
-
newCtx->dri.readable = driReadPriv;
if ( (newCtx->dri.drawable != driDrawPriv) ||
newCtx->lastStamp != driDrawPriv->lastStamp ) {
+ if (driDrawPriv->swap_interval == (unsigned)-1) {
+ driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0)
+ ? driGetDefaultVBlankFlags(&newCtx->optionCache)
+ : VBLANK_FLAG_NO_IRQ;
+
+ driDrawableInitVBlank( driDrawPriv );
+ }
+
newCtx->dri.drawable = driDrawPriv;
radeonSetCliprects(newCtx);
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 8dedd66f56..bc43fc5960 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -161,6 +161,8 @@ struct radeon_tex_obj {
drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
/* Six, for the cube faces */
+ GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
+
GLuint pp_txfilter; /* hardware register values */
GLuint pp_txformat;
GLuint pp_txoffset; /* Image location in texmem.
@@ -667,9 +669,6 @@ struct radeon_context {
/* VBI
*/
- GLuint vbl_seq;
- GLuint vblank_flags;
-
int64_t swap_ust;
int64_t swap_missed_ust;
@@ -708,9 +707,9 @@ struct radeon_context {
#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
-static __inline GLuint radeonPackColor(GLuint cpp,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a)
+static INLINE GLuint radeonPackColor(GLuint cpp,
+ GLubyte r, GLubyte g,
+ GLubyte b, GLubyte a)
{
switch (cpp) {
case 2:
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index a0c563c7cb..e681ca0889 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -862,13 +862,14 @@ static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
/* Copy the back color buffer to the front color buffer.
*/
-void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv,
+void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
const drm_clip_rect_t *rect)
{
radeonContextPtr rmesa;
GLint nbox, i, ret;
GLboolean missed_target;
int64_t ust;
+ __DRIscreenPrivate *psp;
assert(dPriv);
assert(dPriv->driContextPriv);
@@ -890,7 +891,7 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv,
if (!rect)
{
UNLOCK_HARDWARE( rmesa );
- driWaitForVBlank( dPriv, & rmesa->vbl_seq, rmesa->vblank_flags, & missed_target );
+ driWaitForVBlank( dPriv, & missed_target );
LOCK_HARDWARE( rmesa );
}
@@ -917,16 +918,18 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv,
if (rect->y2 < b->y2)
b->y2 = rect->y2;
- if (b->x1 < b->x2 && b->y1 < b->y2)
- b++;
+ if (b->x1 >= b->x2 || b->y1 >= b->y2)
+ continue;
}
- else
- b++;
+ b++;
n++;
}
rmesa->sarea->nbox = n;
+ if (!n)
+ continue;
+
ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
if ( ret ) {
@@ -939,8 +942,9 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv,
UNLOCK_HARDWARE( rmesa );
if (!rect)
{
+ psp = dPriv->driScreenPriv;
rmesa->swap_count++;
- (*dri_interface->getUST)( & ust );
+ (*psp->systemTime->getUST)( & ust );
if ( missed_target ) {
rmesa->swap_missed_count++;
rmesa->swap_missed_ust = ust - rmesa->swap_ust;
@@ -951,17 +955,19 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv,
}
}
-void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
+void radeonPageFlip( __DRIdrawablePrivate *dPriv )
{
radeonContextPtr rmesa;
GLint ret;
GLboolean missed_target;
+ __DRIscreenPrivate *psp;
assert(dPriv);
assert(dPriv->driContextPriv);
assert(dPriv->driContextPriv->driverPrivate);
rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
+ psp = dPriv->driScreenPriv;
if ( RADEON_DEBUG & DEBUG_IOCTL ) {
fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
@@ -986,10 +992,10 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
*/
radeonWaitForFrameCompletion( rmesa );
UNLOCK_HARDWARE( rmesa );
- driWaitForVBlank( dPriv, & rmesa->vbl_seq, rmesa->vblank_flags, & missed_target );
+ driWaitForVBlank( dPriv, & missed_target );
if ( missed_target ) {
rmesa->swap_missed_count++;
- (void) (*dri_interface->getUST)( & rmesa->swap_missed_ust );
+ (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust );
}
LOCK_HARDWARE( rmesa );
@@ -1003,7 +1009,7 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
}
rmesa->swap_count++;
- (void) (*dri_interface->getUST)( & rmesa->swap_ust );
+ (void) (*psp->systemTime->getUST)( & rmesa->swap_ust );
/* Get ready for drawing next frame. Update the renderbuffers'
* flippedOffset/Pitch fields so we draw into the right place.
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
index 020a5c21e2..f8c96af3f7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
@@ -86,9 +86,9 @@ extern void radeonReleaseDmaRegion( radeonContextPtr rmesa,
struct radeon_dma_region *region,
const char *caller );
-extern void radeonCopyBuffer( const __DRIdrawablePrivate *drawable,
+extern void radeonCopyBuffer( __DRIdrawablePrivate *drawable,
const drm_clip_rect_t *rect);
-extern void radeonPageFlip( const __DRIdrawablePrivate *drawable );
+extern void radeonPageFlip( __DRIdrawablePrivate *drawable );
extern void radeonFlush( GLcontext *ctx );
extern void radeonFinish( GLcontext *ctx );
extern void radeonWaitForIdleLocked( radeonContextPtr rmesa );
@@ -123,7 +123,7 @@ do { \
memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \
rmesa->hw.ATOM.cmd_size * 4)
-static __inline int RADEON_DB_STATECHANGE(
+static INLINE int RADEON_DB_STATECHANGE(
radeonContextPtr rmesa,
struct radeon_state_atom *atom )
{
@@ -176,7 +176,7 @@ do { \
* and hang on to the lock until the critical section is finished and we flush
* the buffer again and unlock.
*/
-static __inline void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
+static INLINE void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
int bytes )
{
if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
@@ -186,7 +186,7 @@ static __inline void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
/* Alloc space in the command buffer
*/
-static __inline char *radeonAllocCmdBuf( radeonContextPtr rmesa,
+static INLINE char *radeonAllocCmdBuf( radeonContextPtr rmesa,
int bytes, const char *where )
{
if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 762848fc26..edf804c60a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -48,10 +48,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#if !RADEON_COMMON
#include "radeon_context.h"
#include "radeon_span.h"
+#include "radeon_tex.h"
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_span.h"
+#include "r200_tex.h"
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
#include "r300_context.h"
#include "r300_fragprog.h"
@@ -88,7 +90,7 @@ DRI_CONF_BEGIN
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
- DRI_CONF_ALLOW_LARGE_TEXTURES(1)
+ DRI_CONF_ALLOW_LARGE_TEXTURES(2)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
@@ -115,7 +117,7 @@ DRI_CONF_BEGIN
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
- DRI_CONF_ALLOW_LARGE_TEXTURES(1)
+ DRI_CONF_ALLOW_LARGE_TEXTURES(2)
DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
@@ -177,7 +179,7 @@ DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
-const char __driConfigOptions[] =
+PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
@@ -186,14 +188,13 @@ DRI_CONF_BEGIN
DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
- DRI_CONF_DISABLE_FALLBACK(false)
+ DRI_CONF_DISABLE_FALLBACK(true)
DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
- DRI_CONF_NO_NEG_LOD_BIAS(false)
- DRI_CONF_FORCE_S3TC_ENABLE(false)
+ DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_DISABLE_S3TC(false)
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
@@ -204,7 +205,7 @@ DRI_CONF_BEGIN
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 18;
+static const GLuint __driNConfigOptions = 17;
#ifndef RADEON_DEBUG
int RADEON_DEBUG = 0;
@@ -242,25 +243,26 @@ radeonGetParam(int fd, int param, void *value)
{
int ret;
drm_radeon_getparam_t gp;
-
+
gp.param = param;
gp.value = value;
-
+
ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
return ret;
}
-static __GLcontextModes *
-radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
- unsigned stencil_bits, GLboolean have_back_buffer )
+static const __DRIconfig **
+radeonFillInModes( __DRIscreenPrivate *psp,
+ unsigned pixel_bits, unsigned depth_bits,
+ unsigned stencil_bits, GLboolean have_back_buffer )
{
- __GLcontextModes * modes;
- __GLcontextModes * m;
- unsigned num_modes;
+ __DRIconfig **configs;
+ __GLcontextModes *m;
unsigned depth_buffer_factor;
unsigned back_buffer_factor;
GLenum fb_format;
GLenum fb_type;
+ int i;
/* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
* enough to add support. Basically, if a context is created with an
@@ -277,7 +279,7 @@ radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
depth_bits_array[0] = depth_bits;
depth_bits_array[1] = depth_bits;
-
+
/* Just like with the accumulation buffer, always provide some modes
* with a stencil buffer. It will be a sw fallback, but some apps won't
* care about that.
@@ -288,8 +290,6 @@ radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
back_buffer_factor = (have_back_buffer) ? 2 : 1;
- num_modes = depth_buffer_factor * back_buffer_factor * 4;
-
if ( pixel_bits == 16 ) {
fb_format = GL_RGB;
fb_type = GL_UNSIGNED_SHORT_5_6_5;
@@ -299,21 +299,11 @@ radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
}
- modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
- m = modes;
- if ( ! driFillInModes( & m, fb_format, fb_type,
- depth_bits_array, stencil_bits_array, depth_buffer_factor,
- back_buffer_modes, back_buffer_factor,
- GLX_TRUE_COLOR ) ) {
- fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
- __func__, __LINE__ );
- return NULL;
- }
-
- if ( ! driFillInModes( & m, fb_format, fb_type,
- depth_bits_array, stencil_bits_array, depth_buffer_factor,
- back_buffer_modes, back_buffer_factor,
- GLX_DIRECT_COLOR ) ) {
+ configs = driCreateConfigs(fb_format, fb_type,
+ depth_bits_array, stencil_bits_array,
+ depth_buffer_factor,
+ back_buffer_modes, back_buffer_factor);
+ if (configs == NULL) {
fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
__func__, __LINE__ );
return NULL;
@@ -321,15 +311,43 @@ radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
/* Mark the visual as slow if there are "fake" stencil bits.
*/
- for ( m = modes ; m != NULL ; m = m->next ) {
- if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
+ for (i = 0; configs[i]; i++) {
+ m = &configs[i]->modes;
+ if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
m->visualRating = GLX_SLOW_CONFIG;
}
}
- return modes;
+ return (const __DRIconfig **) configs;
}
+#if !RADEON_COMMON
+static const __DRItexOffsetExtension radeonTexOffsetExtension = {
+ { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
+ radeonSetTexOffset,
+};
+#endif
+
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+static const __DRIallocateExtension r200AllocateExtension = {
+ { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
+ r200AllocateMemoryMESA,
+ r200FreeMemoryMESA,
+ r200GetMemoryOffsetMESA
+};
+
+static const __DRItexOffsetExtension r200texOffsetExtension = {
+ { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
+ r200SetTexOffset,
+};
+#endif
+
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+static const __DRItexOffsetExtension r300texOffsetExtension = {
+ { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
+ r300SetTexOffset,
+};
+#endif
/* Create the device specific screen private data struct.
*/
@@ -339,9 +357,9 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
radeonScreenPtr screen;
RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
unsigned char *RADEONMMIO;
- PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
- (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
- void * const psc = sPriv->psc->screenConfigs;
+ int i;
+ int ret;
+ uint32_t temp;
if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
@@ -372,7 +390,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
int ret;
ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
&screen->gart_buffer_offset);
-
+
if (ret) {
FREE( screen );
fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
@@ -394,13 +412,13 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
return NULL;
}
- screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7);
- screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
- screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
- screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
- screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
- screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15);
- screen->drmSupportsVertexProgram = (sPriv->drmMinor >= 25);
+ screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
+ screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
+ screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
+ screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
+ screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
+ screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
+ screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
}
screen->mmio.handle = dri_priv->registerHandle;
@@ -534,7 +552,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->chip_family = CHIP_FAMILY_RS300;
break;
+ /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
case PCI_CHIP_R300_AD:
+ screen->chip_family = CHIP_FAMILY_RV350;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
case PCI_CHIP_R300_AE:
case PCI_CHIP_R300_AF:
case PCI_CHIP_R300_AG:
@@ -632,17 +654,18 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
+ case PCI_CHIP_RV410_5E4C:
+ case PCI_CHIP_RV410_5E4F:
case PCI_CHIP_RV410_564A:
case PCI_CHIP_RV410_564B:
case PCI_CHIP_RV410_564F:
case PCI_CHIP_RV410_5652:
case PCI_CHIP_RV410_5653:
+ case PCI_CHIP_RV410_5657:
case PCI_CHIP_RV410_5E48:
case PCI_CHIP_RV410_5E4A:
case PCI_CHIP_RV410_5E4B:
- case PCI_CHIP_RV410_5E4C:
case PCI_CHIP_RV410_5E4D:
- case PCI_CHIP_RV410_5E4F:
screen->chip_family = CHIP_FAMILY_RV410;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
@@ -656,7 +679,132 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
case PCI_CHIP_RC410_5A61:
case PCI_CHIP_RC410_5A62:
screen->chip_family = CHIP_FAMILY_RS400;
- fprintf(stderr, "Warning, xpress200 detected.\n");
+ break;
+
+ case PCI_CHIP_RS690_791E:
+ case PCI_CHIP_RS690_791F:
+ screen->chip_family = CHIP_FAMILY_RS690;
+ break;
+ case PCI_CHIP_RS740_796C:
+ case PCI_CHIP_RS740_796D:
+ case PCI_CHIP_RS740_796E:
+ case PCI_CHIP_RS740_796F:
+ screen->chip_family = CHIP_FAMILY_RS740;
+ break;
+
+ case PCI_CHIP_R520_7100:
+ case PCI_CHIP_R520_7101:
+ case PCI_CHIP_R520_7102:
+ case PCI_CHIP_R520_7103:
+ case PCI_CHIP_R520_7104:
+ case PCI_CHIP_R520_7105:
+ case PCI_CHIP_R520_7106:
+ case PCI_CHIP_R520_7108:
+ case PCI_CHIP_R520_7109:
+ case PCI_CHIP_R520_710A:
+ case PCI_CHIP_R520_710B:
+ case PCI_CHIP_R520_710C:
+ case PCI_CHIP_R520_710E:
+ case PCI_CHIP_R520_710F:
+ screen->chip_family = CHIP_FAMILY_R520;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV515_7140:
+ case PCI_CHIP_RV515_7141:
+ case PCI_CHIP_RV515_7142:
+ case PCI_CHIP_RV515_7143:
+ case PCI_CHIP_RV515_7144:
+ case PCI_CHIP_RV515_7145:
+ case PCI_CHIP_RV515_7146:
+ case PCI_CHIP_RV515_7147:
+ case PCI_CHIP_RV515_7149:
+ case PCI_CHIP_RV515_714A:
+ case PCI_CHIP_RV515_714B:
+ case PCI_CHIP_RV515_714C:
+ case PCI_CHIP_RV515_714D:
+ case PCI_CHIP_RV515_714E:
+ case PCI_CHIP_RV515_714F:
+ case PCI_CHIP_RV515_7151:
+ case PCI_CHIP_RV515_7152:
+ case PCI_CHIP_RV515_7153:
+ case PCI_CHIP_RV515_715E:
+ case PCI_CHIP_RV515_715F:
+ case PCI_CHIP_RV515_7180:
+ case PCI_CHIP_RV515_7181:
+ case PCI_CHIP_RV515_7183:
+ case PCI_CHIP_RV515_7186:
+ case PCI_CHIP_RV515_7187:
+ case PCI_CHIP_RV515_7188:
+ case PCI_CHIP_RV515_718A:
+ case PCI_CHIP_RV515_718B:
+ case PCI_CHIP_RV515_718C:
+ case PCI_CHIP_RV515_718D:
+ case PCI_CHIP_RV515_718F:
+ case PCI_CHIP_RV515_7193:
+ case PCI_CHIP_RV515_7196:
+ case PCI_CHIP_RV515_719B:
+ case PCI_CHIP_RV515_719F:
+ case PCI_CHIP_RV515_7200:
+ case PCI_CHIP_RV515_7210:
+ case PCI_CHIP_RV515_7211:
+ screen->chip_family = CHIP_FAMILY_RV515;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV530_71C0:
+ case PCI_CHIP_RV530_71C1:
+ case PCI_CHIP_RV530_71C2:
+ case PCI_CHIP_RV530_71C3:
+ case PCI_CHIP_RV530_71C4:
+ case PCI_CHIP_RV530_71C5:
+ case PCI_CHIP_RV530_71C6:
+ case PCI_CHIP_RV530_71C7:
+ case PCI_CHIP_RV530_71CD:
+ case PCI_CHIP_RV530_71CE:
+ case PCI_CHIP_RV530_71D2:
+ case PCI_CHIP_RV530_71D4:
+ case PCI_CHIP_RV530_71D5:
+ case PCI_CHIP_RV530_71D6:
+ case PCI_CHIP_RV530_71DA:
+ case PCI_CHIP_RV530_71DE:
+ screen->chip_family = CHIP_FAMILY_RV530;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_R580_7240:
+ case PCI_CHIP_R580_7243:
+ case PCI_CHIP_R580_7244:
+ case PCI_CHIP_R580_7245:
+ case PCI_CHIP_R580_7246:
+ case PCI_CHIP_R580_7247:
+ case PCI_CHIP_R580_7248:
+ case PCI_CHIP_R580_7249:
+ case PCI_CHIP_R580_724A:
+ case PCI_CHIP_R580_724B:
+ case PCI_CHIP_R580_724C:
+ case PCI_CHIP_R580_724D:
+ case PCI_CHIP_R580_724E:
+ case PCI_CHIP_R580_724F:
+ case PCI_CHIP_R580_7284:
+ screen->chip_family = CHIP_FAMILY_R580;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV570_7280:
+ case PCI_CHIP_RV560_7281:
+ case PCI_CHIP_RV560_7283:
+ case PCI_CHIP_RV560_7287:
+ case PCI_CHIP_RV570_7288:
+ case PCI_CHIP_RV570_7289:
+ case PCI_CHIP_RV570_728B:
+ case PCI_CHIP_RV570_728C:
+ case PCI_CHIP_RV560_7290:
+ case PCI_CHIP_RV560_7291:
+ case PCI_CHIP_RV560_7293:
+ case PCI_CHIP_RV560_7297:
+ screen->chip_family = CHIP_FAMILY_RV560;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
break;
default:
@@ -665,11 +813,19 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
return NULL;
}
if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
- sPriv->ddxMinor < 2) {
+ sPriv->ddx_version.minor < 2) {
fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
return NULL;
}
+ if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
+ fprintf(stderr, "R500 support requires a newer drm.\n");
+ return NULL;
+ }
+
+ if (getenv("R300_NO_TCL"))
+ screen->chip_flags &= ~RADEON_CHIPSET_TCL;
+
if (screen->chip_family <= CHIP_FAMILY_RS200)
screen->chip_flags |= RADEON_CLASS_R100;
else if (screen->chip_family <= CHIP_FAMILY_RV280)
@@ -680,9 +836,51 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
- screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
+ ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
+ &temp);
+ if (ret) {
+ if (screen->chip_family < CHIP_FAMILY_RS690)
+ screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
+ else {
+ FREE( screen );
+ fprintf(stderr, "Unable to get fb location need newer drm\n");
+ return NULL;
+ }
+ } else {
+ screen->fbLocation = (temp & 0xffff) << 16;
+ }
+
+ if (screen->chip_family >= CHIP_FAMILY_RV515) {
+ ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
+ &temp);
+ if (ret) {
+ fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
+ switch (screen->chip_family) {
+ case CHIP_FAMILY_R300:
+ case CHIP_FAMILY_R350:
+ screen->num_gb_pipes = 2;
+ break;
+ case CHIP_FAMILY_R420:
+ case CHIP_FAMILY_R520:
+ case CHIP_FAMILY_R580:
+ case CHIP_FAMILY_RV560:
+ case CHIP_FAMILY_RV570:
+ screen->num_gb_pipes = 4;
+ break;
+ case CHIP_FAMILY_RV350:
+ case CHIP_FAMILY_RV515:
+ case CHIP_FAMILY_RV530:
+ case CHIP_FAMILY_RV410:
+ default:
+ screen->num_gb_pipes = 1;
+ break;
+ }
+ } else {
+ screen->num_gb_pipes = temp;
+ }
+ }
- if ( sPriv->drmMinor >= 10 ) {
+ if ( sPriv->drm_version.minor >= 10 ) {
drm_radeon_setparam_t sp;
sp.param = RADEON_SETPARAM_FB_LOCATION;
@@ -700,8 +898,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->depthPitch = dri_priv->depthPitch;
/* Check if ddx has set up a surface reg to cover depth buffer */
- screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
- (screen->chip_flags & RADEON_CHIPSET_TCL));
+ screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
+ /* these chips don't use tiled z without hyperz. So always pretend
+ we have set up a surface which will cause linear reads/writes */
+ ((screen->chip_family & RADEON_CLASS_R100) &&
+ !(screen->chip_flags & RADEON_CHIPSET_TCL));
if ( dri_priv->textureSize == 0 ) {
screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
@@ -730,29 +931,34 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
dri_priv->log2GARTTexGran;
}
- if ( glx_enable_extension != NULL ) {
- if ( screen->irq != 0 ) {
- (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
- (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
- (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
- }
-
- (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
- if (IS_R200_CLASS(screen))
- (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
+ i = 0;
+ screen->extensions[i++] = &driCopySubBufferExtension.base;
+ screen->extensions[i++] = &driFrameTrackingExtension.base;
+ screen->extensions[i++] = &driReadDrawableExtension;
- (*glx_enable_extension)( psc, "GLX_MESA_copy_sub_buffer" );
- (*glx_enable_extension)( psc, "GLX_SGI_make_current_read" );
+ if ( screen->irq != 0 ) {
+ screen->extensions[i++] = &driSwapControlExtension.base;
+ screen->extensions[i++] = &driMediaStreamCounterExtension.base;
}
+#if !RADEON_COMMON
+ screen->extensions[i++] = &radeonTexOffsetExtension.base;
+#endif
+
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
- if (IS_R200_CLASS(screen)) {
- sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
- sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA;
- sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA;
- }
+ if (IS_R200_CLASS(screen))
+ screen->extensions[i++] = &r200AllocateExtension.base;
+
+ screen->extensions[i++] = &r200texOffsetExtension.base;
#endif
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+ screen->extensions[i++] = &r300texOffsetExtension.base;
+#endif
+
+ screen->extensions[i++] = NULL;
+ sPriv->extensions = screen->extensions;
+
screen->driScreen = sPriv;
screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
return screen;
@@ -935,71 +1141,16 @@ static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
#endif
-#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
-static struct __DriverAPIRec radeonAPI = {
- .InitDriver = radeonInitDriver,
- .DestroyScreen = radeonDestroyScreen,
- .CreateContext = radeonCreateContext,
- .DestroyContext = radeonDestroyContext,
- .CreateBuffer = radeonCreateBuffer,
- .DestroyBuffer = radeonDestroyBuffer,
- .SwapBuffers = radeonSwapBuffers,
- .MakeCurrent = radeonMakeCurrent,
- .UnbindContext = radeonUnbindContext,
- .GetSwapInfo = getSwapInfo,
- .GetMSC = driGetMSC32,
- .WaitForMSC = driWaitForMSC32,
- .WaitForSBC = NULL,
- .SwapBuffersMSC = NULL,
- .CopySubBuffer = radeonCopySubBuffer,
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
- .setTexOffset = r300SetTexOffset,
-#endif
-};
-#else
-static const struct __DriverAPIRec r200API = {
- .InitDriver = radeonInitDriver,
- .DestroyScreen = radeonDestroyScreen,
- .CreateContext = r200CreateContext,
- .DestroyContext = r200DestroyContext,
- .CreateBuffer = radeonCreateBuffer,
- .DestroyBuffer = radeonDestroyBuffer,
- .SwapBuffers = r200SwapBuffers,
- .MakeCurrent = r200MakeCurrent,
- .UnbindContext = r200UnbindContext,
- .GetSwapInfo = getSwapInfo,
- .GetMSC = driGetMSC32,
- .WaitForMSC = driWaitForMSC32,
- .WaitForSBC = NULL,
- .SwapBuffersMSC = NULL,
- .CopySubBuffer = r200CopySubBuffer
-};
-#endif
-
/**
- * This is the bootstrap function for the driver. libGL supplies all of the
- * requisite information about the system, and the driver initializes itself.
- * This routine also fills in the linked list pointed to by \c driver_modes
- * with the \c __GLcontextModes that the driver can support for windows or
- * pbuffers.
+ * This is the driver specific part of the createNewScreen entry point.
*
- * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
- * failure.
+ * \todo maybe fold this into intelInitDriver
+ *
+ * \return the __GLcontextModes supported by this driver
*/
-PUBLIC void *
-__driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
- int scrn, __DRIscreen *psc,
- const __GLcontextModes * modes,
- const __DRIversion * ddx_version,
- const __DRIversion * dri_version,
- const __DRIversion * drm_version,
- const __DRIframebuffer * frame_buffer,
- drmAddress pSAREA, int fd,
- int internal_api_version,
- const __DRIinterfaceMethods * interface,
- __GLcontextModes ** driver_modes )
+static const __DRIconfig **
+radeonInitScreen(__DRIscreenPrivate *psp)
{
- __DRIscreenPrivate *psp;
#if !RADEON_COMMON
static const char *driver_name = "Radeon";
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
@@ -1016,57 +1167,42 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 24, 0 };
#endif
-
- dri_interface = interface;
+ RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
if ( ! driCheckDriDdxDrmVersions3( driver_name,
- dri_version, & dri_expected,
- ddx_version, & ddx_expected,
- drm_version, & drm_expected ) ) {
+ &psp->dri_version, & dri_expected,
+ &psp->ddx_version, & ddx_expected,
+ &psp->drm_version, & drm_expected ) ) {
return NULL;
}
-#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
- psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
- ddx_version, dri_version, drm_version,
- frame_buffer, pSAREA, fd,
- internal_api_version, &radeonAPI);
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
- psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
- ddx_version, dri_version, drm_version,
- frame_buffer, pSAREA, fd,
- internal_api_version, &r200API);
-#endif
- if ( psp != NULL ) {
- RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
- if (driver_modes) {
- *driver_modes = radeonFillInModes( dri_priv->bpp,
- (dri_priv->bpp == 16) ? 16 : 24,
- (dri_priv->bpp == 16) ? 0 : 8,
- (dri_priv->backOffset != dri_priv->depthOffset) );
- }
-
- /* Calling driInitExtensions here, with a NULL context pointer,
- * does not actually enable the extensions. It just makes sure
- * that all the dispatch offsets for all the extensions that
- * *might* be enables are known. This is needed because the
- * dispatch offsets need to be known when _mesa_context_create
- * is called, but we can't enable the extensions until we have a
- * context pointer.
- *
- * Hello chicken. Hello egg. How are you two today?
- */
- driInitExtensions( NULL, card_extensions, GL_FALSE );
+ /* Calling driInitExtensions here, with a NULL context pointer,
+ * does not actually enable the extensions. It just makes sure
+ * that all the dispatch offsets for all the extensions that
+ * *might* be enables are known. This is needed because the
+ * dispatch offsets need to be known when _mesa_context_create
+ * is called, but we can't enable the extensions until we have a
+ * context pointer.
+ *
+ * Hello chicken. Hello egg. How are you two today?
+ */
+ driInitExtensions( NULL, card_extensions, GL_FALSE );
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
- driInitExtensions( NULL, blend_extensions, GL_FALSE );
- driInitSingleExtension( NULL, ARB_vp_extension );
- driInitSingleExtension( NULL, NV_vp_extension );
- driInitSingleExtension( NULL, ATI_fs_extension );
- driInitExtensions( NULL, point_extensions, GL_FALSE );
+ driInitExtensions( NULL, blend_extensions, GL_FALSE );
+ driInitSingleExtension( NULL, ARB_vp_extension );
+ driInitSingleExtension( NULL, NV_vp_extension );
+ driInitSingleExtension( NULL, ATI_fs_extension );
+ driInitExtensions( NULL, point_extensions, GL_FALSE );
#endif
- }
- return (void *) psp;
+ if (!radeonInitDriver(psp))
+ return NULL;
+
+ return radeonFillInModes( psp,
+ dri_priv->bpp,
+ (dri_priv->bpp == 16) ? 16 : 24,
+ (dri_priv->bpp == 16) ? 0 : 8,
+ (dri_priv->backOffset != dri_priv->depthOffset) );
}
@@ -1099,3 +1235,41 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
return 0;
}
+
+#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
+const struct __DriverAPIRec driDriverAPI = {
+ .InitScreen = radeonInitScreen,
+ .DestroyScreen = radeonDestroyScreen,
+ .CreateContext = radeonCreateContext,
+ .DestroyContext = radeonDestroyContext,
+ .CreateBuffer = radeonCreateBuffer,
+ .DestroyBuffer = radeonDestroyBuffer,
+ .SwapBuffers = radeonSwapBuffers,
+ .MakeCurrent = radeonMakeCurrent,
+ .UnbindContext = radeonUnbindContext,
+ .GetSwapInfo = getSwapInfo,
+ .GetDrawableMSC = driDrawableGetMSC32,
+ .WaitForMSC = driWaitForMSC32,
+ .WaitForSBC = NULL,
+ .SwapBuffersMSC = NULL,
+ .CopySubBuffer = radeonCopySubBuffer,
+};
+#else
+const struct __DriverAPIRec driDriverAPI = {
+ .InitScreen = radeonInitScreen,
+ .DestroyScreen = radeonDestroyScreen,
+ .CreateContext = r200CreateContext,
+ .DestroyContext = r200DestroyContext,
+ .CreateBuffer = radeonCreateBuffer,
+ .DestroyBuffer = radeonDestroyBuffer,
+ .SwapBuffers = r200SwapBuffers,
+ .MakeCurrent = r200MakeCurrent,
+ .UnbindContext = r200UnbindContext,
+ .GetSwapInfo = getSwapInfo,
+ .GetDrawableMSC = driDrawableGetMSC32,
+ .WaitForMSC = driWaitForMSC32,
+ .WaitForSBC = NULL,
+ .SwapBuffersMSC = NULL,
+ .CopySubBuffer = r200CopySubBuffer,
+};
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index c9b0c3af12..b84c70bfae 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -102,6 +102,10 @@ typedef struct {
/* Configuration cache with default values for all contexts */
driOptionCache optionCache;
+
+ const __DRIextension *extensions[8];
+
+ int num_gb_pipes;
} radeonScreenRec, *radeonScreenPtr;
#define IS_R100_CLASS(screen) \
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 732a85ecf0..e7ab3677b3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -173,6 +173,8 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
/* 16-bit depth buffer functions
*/
+#define VALUE_TYPE GLushort
+
#define WRITE_DEPTH( _x, _y, d ) \
*(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
@@ -187,6 +189,8 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
* Careful: It looks like the R300 uses ZZZS byte order while the R200
* uses SZZZ for 24 bit depth, 8 bit stencil mode.
*/
+#define VALUE_TYPE GLuint
+
#ifdef COMPILE_R300
#define WRITE_DEPTH( _x, _y, d ) \
do { \
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 1fe5c244cd..3437de16bb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -1639,8 +1639,7 @@ void radeonSetCliprects( radeonContextPtr rmesa )
GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate;
GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate;
- if (draw_fb->_ColorDrawBufferMask[0]
- == BUFFER_BIT_BACK_LEFT) {
+ if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
/* Can't ignore 2d windows if we are page flipping.
*/
if ( drawable->numBackClipRects == 0 || rmesa->doPageFlip ) {
@@ -1692,17 +1691,18 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */
- /*
- * _ColorDrawBufferMask is easier to cope with than <mode>.
- * Check for software fallback, update cliprects.
- */
- switch ( ctx->DrawBuffer->_ColorDrawBufferMask[0] ) {
- case BUFFER_BIT_FRONT_LEFT:
- case BUFFER_BIT_BACK_LEFT:
+ if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) {
+ /* 0 (GL_NONE) buffers or multiple color drawing buffers */
+ FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE );
+ return;
+ }
+
+ switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) {
+ case BUFFER_FRONT_LEFT:
+ case BUFFER_BACK_LEFT:
FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE );
break;
default:
- /* 0 (GL_NONE) buffers or multiple color drawing buffers */
FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE );
return;
}
@@ -2221,11 +2221,11 @@ radeonUpdateDrawBuffer(GLcontext *ctx)
struct gl_framebuffer *fb = ctx->DrawBuffer;
driRenderbuffer *drb;
- if (fb->_ColorDrawBufferMask[0] == BUFFER_BIT_FRONT_LEFT) {
+ if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
/* draw to front */
drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
}
- else if (fb->_ColorDrawBufferMask[0] == BUFFER_BIT_BACK_LEFT) {
+ else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
/* draw to back */
drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c
index d35be1ca88..4c11ff7ab4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c
@@ -417,7 +417,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx,
for (i = 0 ; i < VB->PrimitiveCount ; i++)
{
- GLuint prim = VB->Primitive[i].mode;
+ GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
GLuint start = VB->Primitive[i].start;
GLuint length = VB->Primitive[i].count;
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h
index bdf086dfee..8000880828 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.h
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.h
@@ -37,6 +37,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __RADEON_TEX_H__
#define __RADEON_TEX_H__
+extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
+ unsigned long long offset, GLint depth,
+ GLuint pitch);
+
extern void radeonUpdateTextureState( GLcontext *ctx );
extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t,
diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c
index f7520f1dea..523c597271 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c
@@ -333,7 +333,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
{
int numLevels;
- if ( !t || t->base.totalSize == 0 )
+ if ( !t || t->base.totalSize == 0 || t->image_override )
return 0;
if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index ae8d527cf4..90c6379eae 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -39,6 +39,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "context.h"
#include "macros.h"
#include "texformat.h"
+#include "texobj.h"
#include "enums.h"
#include "radeon_context.h"
@@ -83,7 +84,7 @@ tx_table[] =
_ALPHA_REV(RGBA8888),
_ALPHA(ARGB8888),
_ALPHA_REV(ARGB8888),
- _INVALID(RGB888),
+ [ MESA_FORMAT_RGB888 ] = { RADEON_TXFORMAT_ARGB8888, 0 },
_COLOR(RGB565),
_COLOR_REV(RGB565),
_ALPHA(ARGB4444),
@@ -133,18 +134,19 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
/* Set the hardware texture format
*/
-
- t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
- RADEON_TXFORMAT_ALPHA_IN_MAP);
- t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
-
- if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) {
- t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format;
- t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter;
- }
- else {
- _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__);
- return;
+ if ( !t->image_override ) {
+ t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
+ RADEON_TXFORMAT_ALPHA_IN_MAP);
+ t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
+
+ if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) {
+ t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format;
+ t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter;
+ }
+ else {
+ _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__);
+ return;
+ }
}
texelBytes = baseImage->TexFormat->TexelBytes;
@@ -340,11 +342,13 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
* requires 64-byte aligned pitches, and we may/may not need the
* blitter. NPOT only!
*/
- if (baseImage->IsCompressed)
- t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63);
- else
- t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63);
- t->pp_txpitch -= 32;
+ if ( !t->image_override ) {
+ if (baseImage->IsCompressed)
+ t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63);
+ else
+ t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63);
+ t->pp_txpitch -= 32;
+ }
t->dirty_state = TEX_ALL;
@@ -839,6 +843,44 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
return GL_TRUE;
}
+void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
+ unsigned long long offset, GLint depth, GLuint pitch)
+{
+ radeonContextPtr rmesa = pDRICtx->driverPrivate;
+ struct gl_texture_object *tObj =
+ _mesa_lookup_texture(rmesa->glCtx, texname);
+ radeonTexObjPtr t;
+
+ if (tObj == NULL)
+ return;
+
+ t = (radeonTexObjPtr) tObj->DriverData;
+
+ t->image_override = GL_TRUE;
+
+ if (!offset)
+ return;
+
+ t->pp_txoffset = offset;
+ t->pp_txpitch = pitch - 32;
+
+ switch (depth) {
+ case 32:
+ t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
+ t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
+ break;
+ case 24:
+ default:
+ t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
+ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
+ break;
+ case 16:
+ t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
+ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
+ break;
+ }
+}
+
#define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
RADEON_MIN_FILTER_MASK | \
RADEON_MAG_FILTER_MASK | \
@@ -1135,7 +1177,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit )
RADEON_FIREVERTICES( rmesa );
radeonSetTexImages( rmesa, tObj );
radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
- if ( !t->base.memBlock )
+ if ( !t->base.memBlock && !t->image_override )
return GL_FALSE;
}
@@ -1202,7 +1244,8 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
RADEON_FIREVERTICES( rmesa );
radeonSetTexImages( rmesa, tObj );
radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
- if ( !t->base.memBlock /* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
+ if ( !t->base.memBlock &&
+ !t->image_override /* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
fprintf(stderr, "%s: upload failed\n", __FUNCTION__);
return GL_FALSE;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-23 03:34:33 +0000