diff options
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/Makefile | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_chipset.h | 135 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_context.c | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_ioctl.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 438 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.h | 25 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state_init.c | 4 |
8 files changed, 544 insertions, 71 deletions
diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 8a942cb480..34dc58e2dc 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -32,6 +32,7 @@ C_SOURCES = \ $(COMMON_SOURCES) \ $(DRIVER_SOURCES) +DEFINES += -DRADEON_COMMON=0 X86_SOURCES = \ radeon_vtxtmp_x86.S diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h new file mode 100644 index 0000000000..b82606441c --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h @@ -0,0 +1,135 @@ +#ifndef _RADEON_CHIPSET_H +#define _RADEON_CHIPSET_H +/* Including xf86PciInfo.h introduces a bunch of errors... + */ + +/* General chip classes: + * r100 includes R100, RV100, RV200, RS100, RS200, RS250. + * r200 includes R200, RV250, RV280, RS300. + * r300 includes R300, RV350, RV370. + * (RS* denotes IGP) + */ +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV350_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AU 0x4155 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JO 0x4A4F +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_RADEON_QY 0x5159 +#define PCI_CHIP_RADEON_QZ 0x515A +#define PCI_CHIP_RN50_515E 0x515E +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5965 0x5965 +#define PCI_CHIP_RN50_5969 0x5969 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 + +enum { + CHIP_FAMILY_R100, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, + CHIP_FAMILY_R420, + CHIP_FAMILY_LAST +}; + +/* General classes of Radeons, as described above the device ID section */ +#define RADEON_CLASS_R100 (0 << 0) +#define RADEON_CLASS_R200 (1 << 0) +#define RADEON_CLASS_R300 (2 << 0) +#define RADEON_CLASS_MASK (3 << 0) + +#define RADEON_CHIPSET_TCL (1 << 2) /* tcl support - any radeon */ +#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 3) /* r100 stencil bug */ +#define R200_CHIPSET_YCBCR_BROKEN (1 << 4) /* r200 ycbcr bug */ + +#endif /* _RADEON_CHIPSET_H */ diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 4b81b53980..e819566c01 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -464,15 +464,15 @@ radeonCreateContext( const __GLcontextModes *glVisual, fprintf(stderr, "disabling 3D acceleration\n"); FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1); } else if (tcl_mode == DRI_CONF_TCL_SW || - !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) { - if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) { - rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL; + !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; fprintf(stderr, "Disabling HW TCL support\n"); } TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); } - if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) { + if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { if (tcl_mode >= DRI_CONF_TCL_VTXFMT) radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN ); diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 37a619c245..fa22cbd6f9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -210,7 +210,7 @@ void radeonEmitState( radeonContextPtr rmesa ) foreach(atom, &rmesa->hw.atomlist) { if (rmesa->hw.all_dirty) atom->dirty = GL_TRUE; - if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) && + if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) && atom->is_tcl) atom->dirty = GL_FALSE; if (atom->dirty) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 9a552c2c12..3b78972820 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -43,10 +43,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "renderbuffer.h" #define STANDALONE_MMIO -#include "radeon_context.h" -#include "radeon_screen.h" +#include "radeon_chipset.h" #include "radeon_macros.h" +#include "radeon_screen.h" +#if !RADEON_COMMON +#include "radeon_context.h" +#include "radeon_span.h" +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) +#include "r200_context.h" +#include "r200_ioctl.h" +#include "r200_span.h" +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +#include "r300_context.h" #include "radeon_span.h" +#endif #include "utils.h" #include "context.h" @@ -59,6 +69,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "xmlpool.h" +#if !RADEON_COMMON /* R100 */ PUBLIC const char __driConfigOptions[] = DRI_CONF_BEGIN DRI_CONF_SECTION_PERFORMANCE @@ -84,40 +95,117 @@ DRI_CONF_BEGIN DRI_CONF_END; static const GLuint __driNConfigOptions = 14; -extern const struct dri_extension card_extensions[]; - -#if 1 -/* Including xf86PciInfo.h introduces a bunch of errors... - */ -#define PCI_CHIP_RADEON_QD 0x5144 -#define PCI_CHIP_RADEON_QE 0x5145 -#define PCI_CHIP_RADEON_QF 0x5146 -#define PCI_CHIP_RADEON_QG 0x5147 - -#define PCI_CHIP_RADEON_QY 0x5159 -#define PCI_CHIP_RADEON_QZ 0x515A +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) -#define PCI_CHIP_RN50_515E 0x515E -#define PCI_CHIP_RN50_5969 0x5969 - -#define PCI_CHIP_RADEON_LW 0x4C57 /* mobility 7 - has tcl */ -#define PCI_CHIP_RADEON_LX 0x4C58 /* mobility FireGL 7800 m7 */ - -#define PCI_CHIP_RADEON_LY 0x4C59 -#define PCI_CHIP_RADEON_LZ 0x4C5A +PUBLIC const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_UNITS(4,2,6) + DRI_CONF_HYPERZ(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_TEXTURE_LEVEL_HACK(false) + DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_SOFTWARE + DRI_CONF_ARB_VERTEX_PROGRAM(false) + DRI_CONF_NV_VERTEX_PROGRAM(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 17; + +extern const struct dri_extension blend_extensions[]; +extern const struct dri_extension ARB_vp_extension[]; +extern const struct dri_extension NV_vp_extension[]; +extern const struct dri_extension ATI_fs_extension[]; + +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + +/* TODO: integrate these into xmlpool.h! */ +#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Number of texture image units") \ + DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ +DRI_CONF_OPT_END + +#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Number of texture coordinate units") \ + DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ +DRI_CONF_OPT_END + +#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ + DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ +DRI_CONF_OPT_END + +const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(16, 2, 16) + DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 14; -#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */ -#define PCI_CHIP_RV200_QX 0x5158 +#ifndef RADEON_DEBUG +int RADEON_DEBUG = 0; + +static const struct dri_debug_control debug_control[] = { + {"fall", DEBUG_FALLBACKS}, + {"tex", DEBUG_TEXTURE}, + {"ioctl", DEBUG_IOCTL}, + {"prim", DEBUG_PRIMS}, + {"vert", DEBUG_VERTS}, + {"state", DEBUG_STATE}, + {"code", DEBUG_CODEGEN}, + {"vfmt", DEBUG_VFMT}, + {"vtxf", DEBUG_VFMT}, + {"verb", DEBUG_VERBOSE}, + {"dri", DEBUG_DRI}, + {"dma", DEBUG_DMA}, + {"san", DEBUG_SANITY}, + {"sync", DEBUG_SYNC}, + {"pix", DEBUG_PIXEL}, + {"mem", DEBUG_MEMORY}, + {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ + {NULL, 0} +}; +#endif /* RADEON_DEBUG */ -/* IGP Chipsets */ -#define PCI_CHIP_RS100_4136 0x4136 -#define PCI_CHIP_RS200_4137 0x4137 -#define PCI_CHIP_RS250_4237 0x4237 -#define PCI_CHIP_RS100_4336 0x4336 -#define PCI_CHIP_RS200_4337 0x4337 -#define PCI_CHIP_RS250_4437 0x4437 -#endif +#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ +extern const struct dri_extension card_extensions[]; static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); @@ -227,6 +315,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return NULL; } +#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); +#endif + /* parse information in __driConfigOptions */ driParseOptionInfo (&screen->optionCache, __driConfigOptions, __driNConfigOptions); @@ -252,6 +344,17 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) } if (sPriv->drmMinor >= 6) { + gp.param = RADEON_PARAM_GART_BASE; + gp.value = &screen->gart_base; + + ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (ret) { + FREE( screen ); + fprintf(stderr, "drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n", ret); + return NULL; + } + gp.param = RADEON_PARAM_IRQ_NR; gp.value = &screen->irq; @@ -262,7 +365,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); return NULL; } - screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 15); + screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 7); + screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11); + screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16); + screen->drmSupportsFragShader = (sPriv->drmMinor >= 18); + screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13); } } @@ -322,36 +429,168 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) ); } - screen->chipset = 0; + screen->chip_flags = 0; + /* XXX: add more chipsets */ switch ( dri_priv->deviceID ) { - default: - fprintf(stderr, "unknown chip id, assuming full radeon support\n"); + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + case PCI_CHIP_RN50_515E: + case PCI_CHIP_RN50_5969: + screen->chip_family = CHIP_FAMILY_RV100; + break; + + case PCI_CHIP_RS100_4136: + case PCI_CHIP_RS100_4336: + screen->chip_family = CHIP_FAMILY_RS100; + break; + + case PCI_CHIP_RS200_4137: + case PCI_CHIP_RS200_4337: + case PCI_CHIP_RS250_4237: + case PCI_CHIP_RS250_4437: + screen->chip_family = CHIP_FAMILY_RS200; + break; + case PCI_CHIP_RADEON_QD: case PCI_CHIP_RADEON_QE: case PCI_CHIP_RADEON_QF: case PCI_CHIP_RADEON_QG: /* all original radeons (7200) presumably have a stencil op bug */ - screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL; + screen->chip_family = CHIP_FAMILY_R100; + screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; + break; + case PCI_CHIP_RV200_QW: case PCI_CHIP_RV200_QX: case PCI_CHIP_RADEON_LW: case PCI_CHIP_RADEON_LX: - screen->chipset |= RADEON_CHIPSET_TCL; - case PCI_CHIP_RADEON_QY: - case PCI_CHIP_RADEON_QZ: - case PCI_CHIP_RN50_515E: - case PCI_CHIP_RN50_5969: - case PCI_CHIP_RADEON_LY: - case PCI_CHIP_RADEON_LZ: - case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */ - case PCI_CHIP_RS200_4137: - case PCI_CHIP_RS250_4237: - case PCI_CHIP_RS100_4336: - case PCI_CHIP_RS200_4337: - case PCI_CHIP_RS250_4437: + screen->chip_family = CHIP_FAMILY_RV200; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R200_BB: + case PCI_CHIP_R200_BC: + case PCI_CHIP_R200_QH: + case PCI_CHIP_R200_QI: + case PCI_CHIP_R200_QJ: + case PCI_CHIP_R200_QK: + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QM: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + screen->chip_family = CHIP_FAMILY_R200; + screen->chip_flags = RADEON_CHIPSET_TCL; break; + + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + screen->chip_family = CHIP_FAMILY_RV250; + screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV280_5960: + case PCI_CHIP_RV280_5961: + case PCI_CHIP_RV280_5962: + case PCI_CHIP_RV280_5964: + case PCI_CHIP_RV280_5965: + case PCI_CHIP_RV280_5C61: + case PCI_CHIP_RV280_5C63: + screen->chip_family = CHIP_FAMILY_RV280; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RS300_5834: + case PCI_CHIP_RS300_5835: + case PCI_CHIP_RS300_5836: + case PCI_CHIP_RS300_5837: + screen->chip_family = CHIP_FAMILY_RS300; + break; + + case PCI_CHIP_R300_AD: + case PCI_CHIP_R300_AE: + case PCI_CHIP_R300_AF: + case PCI_CHIP_R300_AG: + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + screen->chip_family = CHIP_FAMILY_R300; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV350_AP: + case PCI_CHIP_RV350_AQ: + case PCI_CHIP_RV350_AR: + case PCI_CHIP_RV350_AS: + case PCI_CHIP_RV350_AT: + case PCI_CHIP_RV350_AV: + case PCI_CHIP_RV350_AU: + case PCI_CHIP_RV350_NP: + case PCI_CHIP_RV350_NQ: + case PCI_CHIP_RV350_NR: + case PCI_CHIP_RV350_NS: + case PCI_CHIP_RV350_NT: + case PCI_CHIP_RV350_NV: + screen->chip_family = CHIP_FAMILY_RV350; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R350_AH: + case PCI_CHIP_R350_AI: + case PCI_CHIP_R350_AJ: + case PCI_CHIP_R350_AK: + case PCI_CHIP_R350_NH: + case PCI_CHIP_R350_NI: + case PCI_CHIP_R360_NJ: + case PCI_CHIP_R350_NK: + screen->chip_family = CHIP_FAMILY_R350; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV370_5460: + case PCI_CHIP_RV370_5464: + case PCI_CHIP_RV370_5B60: + case PCI_CHIP_RV370_5B62: + case PCI_CHIP_RV370_5B64: + case PCI_CHIP_RV370_5B65: + screen->chip_family = CHIP_FAMILY_RV380; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R420_JN: + case PCI_CHIP_R420_JH: + case PCI_CHIP_R420_JI: + case PCI_CHIP_R420_JJ: + case PCI_CHIP_R420_JK: + case PCI_CHIP_R420_JL: + case PCI_CHIP_R420_JM: + case PCI_CHIP_R420_JO: + case PCI_CHIP_R420_JP: + screen->chip_family = CHIP_FAMILY_R420; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + default: + fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", + dri_priv->deviceID); + return NULL; } + if (screen->chip_family <= CHIP_FAMILY_RS200) + screen->chip_flags |= RADEON_CLASS_R200; + else if (screen->chip_family <= CHIP_FAMILY_RV280) + screen->chip_flags |= RADEON_CLASS_R200; + else + screen->chip_flags |= RADEON_CLASS_R300; + screen->cpp = dri_priv->bpp / 8; screen->AGPMode = dri_priv->AGPMode; @@ -376,7 +615,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) /* Check if ddx has set up a surface reg to cover depth buffer */ screen->depthHasSurface = ((sPriv->ddxMajor > 4) && - (screen->chipset & RADEON_CHIPSET_TCL)); + (screen->chip_flags & RADEON_CHIPSET_TCL)); screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset + screen->fbLocation; @@ -406,8 +645,18 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) } (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" ); + if (IS_R200_CLASS(screen)) + (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" ); } +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) { + sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA; + sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA; + sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA; + } +#endif + screen->driScreen = sPriv; screen->sarea_priv_offset = dri_priv->sarea_priv_offset; return screen; @@ -559,6 +808,38 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate)); } +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +/** + * Choose the appropriate CreateContext function based on the chipset. + * Eventually, all drivers will go through this process. + */ +static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPriv) +{ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + + if (IS_R300_CLASS(screen)) + return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); + return GL_FALSE; +} + +/** + * Choose the appropriate DestroyContext function based on the chipset. + */ +static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) +{ + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + + if (IS_R300_CLASS(radeon->radeonScreen)) + return r300DestroyContext(driContextPriv); +} + + +#endif + +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) static struct __DriverAPIRec radeonAPI = { .InitDriver = radeonInitDriver, .DestroyScreen = radeonDestroyScreen, @@ -575,7 +856,24 @@ static struct __DriverAPIRec radeonAPI = { .WaitForSBC = NULL, .SwapBuffersMSC = NULL }; - +#else +static const struct __DriverAPIRec r200API = { + .InitDriver = radeonInitDriver, + .DestroyScreen = radeonDestroyScreen, + .CreateContext = r200CreateContext, + .DestroyContext = r200DestroyContext, + .CreateBuffer = radeonCreateBuffer, + .DestroyBuffer = radeonDestroyBuffer, + .SwapBuffers = r200SwapBuffers, + .MakeCurrent = r200MakeCurrent, + .UnbindContext = r200UnbindContext, + .GetSwapInfo = getSwapInfo, + .GetMSC = driGetMSC32, + .WaitForMSC = driWaitForMSC32, + .WaitForSBC = NULL, + .SwapBuffersMSC = NULL +}; +#endif /** * This is the bootstrap function for the driver. libGL supplies all of the @@ -601,23 +899,43 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, __GLcontextModes ** driver_modes ) { __DRIscreenPrivate *psp; +#if !RADEON_COMMON + static const char *driver_name = "Radeon"; static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; static const __DRIversion dri_expected = { 4, 0, 0 }; static const __DRIversion drm_expected = { 1, 3, 0 }; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + static const char *driver_name = "R200"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 5, 0 }; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + static const char *driver_name = "R300"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 17, 0 }; +#endif dri_interface = interface; - if ( ! driCheckDriDdxDrmVersions3( "Radeon", + if ( ! driCheckDriDdxDrmVersions3( driver_name, dri_version, & dri_expected, ddx_version, & ddx_expected, drm_version, & drm_expected ) ) { return NULL; } - +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, ddx_version, dri_version, drm_version, frame_buffer, pSAREA, fd, internal_api_version, &radeonAPI); +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, + ddx_version, dri_version, drm_version, + frame_buffer, pSAREA, fd, + internal_api_version, &r200API); +#endif + if ( psp != NULL ) { RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; *driver_modes = radeonFillInModes( dri_priv->bpp, @@ -636,6 +954,12 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, * Hello chicken. Hello egg. How are you two today? */ driInitExtensions( NULL, card_extensions, GL_FALSE ); +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + driInitExtensions( NULL, blend_extensions, GL_FALSE ); + driInitSingleExtension( NULL, ARB_vp_extension ); + driInitSingleExtension( NULL, NV_vp_extension ); + driInitSingleExtension( NULL, ATI_fs_extension ); +#endif } return (void *) psp; @@ -648,7 +972,11 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) { +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) radeonContextPtr rmesa; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + r200ContextPtr rmesa; +#endif if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) || (dPriv->driContextPriv->driverPrivate == NULL) @@ -656,7 +984,7 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) return -1; } - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rmesa = dPriv->driContextPriv->driverPrivate; sInfo->swap_count = rmesa->swap_count; sInfo->swap_ust = rmesa->swap_ust; sInfo->swap_missed_count = rmesa->swap_missed_count; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 0bf88d9841..e8c58568a6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -41,8 +41,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * IMPORTS: these headers contain all the DRI, X and kernel-related * definitions that we need. */ -/* #include "dri_util.h" */ +#include "dri_util.h" #include "radeon_dri.h" +#include "radeon_chipset.h" #include "radeon_reg.h" #include "drm_sarea.h" #include "xmlconfig.h" @@ -54,13 +55,9 @@ typedef struct { drmAddress map; /* Mapping of the DRM region */ } radeonRegionRec, *radeonRegionPtr; -/* chipset features */ -#define RADEON_CHIPSET_TCL (1 << 0) -#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 1) - typedef struct { - - int chipset; + int chip_family; + int chip_flags; int cpp; int IsPCI; /* Current card is a PCI card */ int AGPMode; @@ -93,12 +90,24 @@ typedef struct { unsigned int sarea_priv_offset; unsigned int gart_buffer_offset; /* offset in card memory space */ unsigned int gart_texture_offset; /* offset in card memory space */ + unsigned int gart_base; + GLboolean drmSupportsCubeMaps; /* need radeon kernel module >= 1.7 */ + GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */ + GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */ + GLboolean drmSupportsFragShader; /* need radeon kernel module >= 1.18 */ + GLboolean drmSupportsPointSprites; /* need radeon kernel module >= 1.13 */ GLboolean depthHasSurface; /* Configuration cache with default values for all contexts */ driOptionCache optionCache; - GLboolean drmSupportsCubeMaps; } radeonScreenRec, *radeonScreenPtr; +#define IS_R100_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R100) +#define IS_R200_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200) +#define IS_R300_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300) + #endif /* __RADEON_SCREEN_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index e0c3286195..b1019601d2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1348,7 +1348,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP; GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP; - if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_BROKEN_STENCIL) { + if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) { tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC; tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC; tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 6c0298a6f7..a2e3d1e5ea 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -376,7 +376,7 @@ void radeonInitState( radeonContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | RADEON_Z_DECOMPRESSION_ENABLE; - if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) { + if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { /* works for q3, but slight rendering errors with glxgears ? */ /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ /* need this otherwise get lots of lockups with q3 ??? */ @@ -446,7 +446,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_VC_NO_SWAP; #endif - if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) { + if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; } |