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-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.h669
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_lock.c117
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_lock.h26
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c7
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_span.c217
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_span.h14
7 files changed, 540 insertions, 512 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index d7c2d1407d..9451ec4aa5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -604,7 +604,6 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
newCtx->dri.drawable = driDrawPriv;
radeonSetCliprects(newCtx);
- radeonUpdateWindow( newCtx->glCtx );
radeonUpdateViewportOffset( newCtx->glCtx );
}
@@ -612,6 +611,7 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
(GLframebuffer *) driDrawPriv->driverPrivate,
(GLframebuffer *) driReadPriv->driverPrivate );
+ _mesa_update_state( newCtx->glCtx );
} else {
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 02cea2f4e3..8dedd66f56 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -1,8 +1,12 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
All Rights Reserved.
@@ -30,9 +34,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
- * Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
+ * Kevin E. Martin <martin@valinux.com>
+ * Nicolai Haehnle <prefect_@gmx.net>
*/
#ifndef __RADEON_CONTEXT_H__
@@ -54,7 +59,10 @@ typedef struct radeon_context *radeonContextPtr;
/* This union is used to avoid warnings/miscompilation
with float to uint32_t casts due to strict-aliasing */
-typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
+typedef union {
+ GLfloat f;
+ uint32_t ui32;
+} float_ui32_type;
#include "radeon_lock.h"
#include "radeon_screen.h"
@@ -62,8 +70,13 @@ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
#include "math/m_vector.h"
-/* Flags for software fallback cases */
-/* See correponding strings in radeon_swtcl.c */
+#define TEX_0 0x1
+#define TEX_1 0x2
+#define TEX_2 0x4
+#define TEX_ALL 0x7
+
+/* Rasterizing fallbacks */
+/* See correponding strings in r200_swtcl.c */
#define RADEON_FALLBACK_TEXTURE 0x0001
#define RADEON_FALLBACK_DRAW_BUFFER 0x0002
#define RADEON_FALLBACK_STENCIL 0x0004
@@ -84,46 +97,41 @@ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
#include "tnl_dd/t_dd_vertex.h"
#undef TAG
-typedef void (*radeon_tri_func)( radeonContextPtr,
+typedef void (*radeon_tri_func) (radeonContextPtr,
radeonVertex *,
- radeonVertex *,
- radeonVertex * );
-
-typedef void (*radeon_line_func)( radeonContextPtr,
- radeonVertex *,
- radeonVertex * );
+ radeonVertex *, radeonVertex *);
-typedef void (*radeon_point_func)( radeonContextPtr,
- radeonVertex * );
+typedef void (*radeon_line_func) (radeonContextPtr,
+ radeonVertex *, radeonVertex *);
+typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
struct radeon_colorbuffer_state {
- GLuint clear;
- int roundEnable;
+ GLuint clear;
+ int roundEnable;
};
-
struct radeon_depthbuffer_state {
- GLuint clear;
- GLfloat scale;
+ GLuint clear;
+ GLfloat scale;
};
struct radeon_scissor_state {
- drm_clip_rect_t rect;
- GLboolean enabled;
+ drm_clip_rect_t rect;
+ GLboolean enabled;
- GLuint numClipRects; /* Cliprects active */
- GLuint numAllocedClipRects; /* Cliprects available */
- drm_clip_rect_t *pClipRects;
+ GLuint numClipRects; /* Cliprects active */
+ GLuint numAllocedClipRects; /* Cliprects available */
+ drm_clip_rect_t *pClipRects;
};
struct radeon_stencilbuffer_state {
- GLboolean hwBuffer;
- GLuint clear; /* rb3d_stencilrefmask value */
+ GLboolean hwBuffer;
+ GLuint clear; /* rb3d_stencilrefmask value */
};
struct radeon_stipple_state {
- GLuint mask[32];
+ GLuint mask[32];
};
/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */
@@ -133,70 +141,61 @@ struct radeon_stipple_state {
#define RADEON_Q_BIT(unit) \
(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit))
-#define TEX_0 0x1
-#define TEX_1 0x2
-#define TEX_2 0x4
-#define TEX_ALL 0x7
-
typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
/* Texture object in locally shared texture space.
*/
struct radeon_tex_obj {
- driTextureObject base;
+ driTextureObject base;
- GLuint bufAddr; /* Offset to start of locally
- shared texture block */
+ GLuint bufAddr; /* Offset to start of locally
+ shared texture block */
- GLuint dirty_state; /* Flags (1 per texunit) for
- whether or not this texobj
- has dirty hardware state
- (pp_*) that needs to be
- brought into the
- texunit. */
+ GLuint dirty_state; /* Flags (1 per texunit) for
+ whether or not this texobj
+ has dirty hardware state
+ (pp_*) that needs to be
+ brought into the
+ texunit. */
- drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
- /* Six, for the cube faces */
+ drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
+ /* Six, for the cube faces */
- GLuint pp_txfilter; /* hardware register values */
- GLuint pp_txformat;
- GLuint pp_txoffset; /* Image location in texmem.
- All cube faces follow. */
- GLuint pp_txsize; /* npot only */
- GLuint pp_txpitch; /* npot only */
- GLuint pp_border_color;
- GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
+ GLuint pp_txfilter; /* hardware register values */
+ GLuint pp_txformat;
+ GLuint pp_txoffset; /* Image location in texmem.
+ All cube faces follow. */
+ GLuint pp_txsize; /* npot only */
+ GLuint pp_txpitch; /* npot only */
+ GLuint pp_border_color;
+ GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
- GLboolean border_fallback;
+ GLboolean border_fallback;
- GLuint tile_bits; /* hw texture tile bits used on this texture */
+ GLuint tile_bits; /* hw texture tile bits used on this texture */
};
-
struct radeon_texture_env_state {
- radeonTexObjPtr texobj;
- GLenum format;
- GLenum envMode;
+ radeonTexObjPtr texobj;
+ GLenum format;
+ GLenum envMode;
};
struct radeon_texture_state {
- struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS];
+ struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS];
};
-
struct radeon_state_atom {
- struct radeon_state_atom *next, *prev;
- const char *name; /* for debug */
- int cmd_size; /* size in bytes */
- GLuint is_tcl;
- int *cmd; /* one or more cmd's */
- int *lastcmd; /* one or more cmd's */
- GLboolean dirty; /* dirty-mark in emit_state_list */
- GLboolean (*check)( GLcontext * ); /* is this state active? */
+ struct radeon_state_atom *next, *prev;
+ const char *name; /* for debug */
+ int cmd_size; /* size in bytes */
+ GLuint is_tcl;
+ int *cmd; /* one or more cmd's */
+ int *lastcmd; /* one or more cmd's */
+ GLboolean dirty; /* dirty-mark in emit_state_list */
+ GLboolean(*check) (GLcontext *); /* is this state active? */
};
-
-
/* Trying to keep these relatively short as the variables are becoming
* extravagently long. Drop the driver name prefix off the front of
* everything - I think we know which driver we're in by now, and keep the
@@ -263,9 +262,9 @@ struct radeon_state_atom {
#define TEX_PP_BORDER_COLOR 8
#define TEX_STATE_SIZE 9
-#define TXR_CMD_0 0 /* rectangle textures */
-#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
-#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
+#define TXR_CMD_0 0 /* rectangle textures */
+#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
+#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
#define TXR_STATE_SIZE 3
#define CUBE_CMD_0 0
@@ -297,11 +296,11 @@ struct radeon_state_atom {
#define TCL_PER_LIGHT_CTL_3 11
#define TCL_STATE_SIZE 12
-#define MTL_CMD_0 0
-#define MTL_EMMISSIVE_RED 1
-#define MTL_EMMISSIVE_GREEN 2
-#define MTL_EMMISSIVE_BLUE 3
-#define MTL_EMMISSIVE_ALPHA 4
+#define MTL_CMD_0 0
+#define MTL_EMMISSIVE_RED 1
+#define MTL_EMMISSIVE_GREEN 2
+#define MTL_EMMISSIVE_BLUE 3
+#define MTL_EMMISSIVE_ALPHA 4
#define MTL_AMBIENT_RED 5
#define MTL_AMBIENT_GREEN 6
#define MTL_AMBIENT_BLUE 7
@@ -365,7 +364,7 @@ struct radeon_state_atom {
#define LIT_SPOT_EXPONENT 27
#define LIT_SPOT_CUTOFF 28
#define LIT_SPECULAR_THRESH 29
-#define LIT_RANGE_CUTOFF 30 /* ? */
+#define LIT_RANGE_CUTOFF 30 /* ? */
#define LIT_ATTEN_CONST_INV 31
#define LIT_STATE_SIZE 32
@@ -409,59 +408,54 @@ struct radeon_state_atom {
#define SHN_SHININESS 1
#define SHN_STATE_SIZE 2
-
-
-
-
struct radeon_hw_state {
- /* Head of the linked list of state atoms. */
- struct radeon_state_atom atomlist;
-
- /* Hardware state, stored as cmdbuf commands:
- * -- Need to doublebuffer for
- * - eliding noop statechange loops? (except line stipple count)
- */
- struct radeon_state_atom ctx;
- struct radeon_state_atom set;
- struct radeon_state_atom lin;
- struct radeon_state_atom msk;
- struct radeon_state_atom vpt;
- struct radeon_state_atom tcl;
- struct radeon_state_atom msc;
- struct radeon_state_atom tex[3];
- struct radeon_state_atom cube[3];
- struct radeon_state_atom zbs;
- struct radeon_state_atom mtl;
- struct radeon_state_atom mat[6];
- struct radeon_state_atom lit[8]; /* includes vec, scl commands */
- struct radeon_state_atom ucp[6];
- struct radeon_state_atom eye; /* eye pos */
- struct radeon_state_atom grd; /* guard band clipping */
- struct radeon_state_atom fog;
- struct radeon_state_atom glt;
- struct radeon_state_atom txr[3]; /* for NPOT */
-
- int max_state_size; /* Number of bytes necessary for a full state emit. */
- GLboolean is_dirty, all_dirty;
+ /* Head of the linked list of state atoms. */
+ struct radeon_state_atom atomlist;
+
+ /* Hardware state, stored as cmdbuf commands:
+ * -- Need to doublebuffer for
+ * - eliding noop statechange loops? (except line stipple count)
+ */
+ struct radeon_state_atom ctx;
+ struct radeon_state_atom set;
+ struct radeon_state_atom lin;
+ struct radeon_state_atom msk;
+ struct radeon_state_atom vpt;
+ struct radeon_state_atom tcl;
+ struct radeon_state_atom msc;
+ struct radeon_state_atom tex[3];
+ struct radeon_state_atom cube[3];
+ struct radeon_state_atom zbs;
+ struct radeon_state_atom mtl;
+ struct radeon_state_atom mat[6];
+ struct radeon_state_atom lit[8]; /* includes vec, scl commands */
+ struct radeon_state_atom ucp[6];
+ struct radeon_state_atom eye; /* eye pos */
+ struct radeon_state_atom grd; /* guard band clipping */
+ struct radeon_state_atom fog;
+ struct radeon_state_atom glt;
+ struct radeon_state_atom txr[3]; /* for NPOT */
+
+ int max_state_size; /* Number of bytes necessary for a full state emit. */
+ GLboolean is_dirty, all_dirty;
};
struct radeon_state {
- /* Derived state for internal purposes:
- */
- struct radeon_colorbuffer_state color;
- struct radeon_depthbuffer_state depth;
- struct radeon_scissor_state scissor;
- struct radeon_stencilbuffer_state stencil;
- struct radeon_stipple_state stipple;
- struct radeon_texture_state texture;
+ /* Derived state for internal purposes:
+ */
+ struct radeon_colorbuffer_state color;
+ struct radeon_depthbuffer_state depth;
+ struct radeon_scissor_state scissor;
+ struct radeon_stencilbuffer_state stencil;
+ struct radeon_stipple_state stipple;
+ struct radeon_texture_state texture;
};
-
/* Need refcounting on dma buffers:
*/
struct radeon_dma_buffer {
- int refcount; /* the number of retained regions in buf */
- drmBufPtr buf;
+ int refcount; /* the number of retained regions in buf */
+ drmBufPtr buf;
};
#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
@@ -471,139 +465,130 @@ struct radeon_dma_buffer {
/* A retained region, eg vertices for indexed vertices.
*/
struct radeon_dma_region {
- struct radeon_dma_buffer *buf;
- char *address; /* == buf->address */
- int start, end, ptr; /* offsets from start of buf */
- int aos_start;
- int aos_stride;
- int aos_size;
+ struct radeon_dma_buffer *buf;
+ char *address; /* == buf->address */
+ int start, end, ptr; /* offsets from start of buf */
+ int aos_start;
+ int aos_stride;
+ int aos_size;
};
-
struct radeon_dma {
- /* Active dma region. Allocations for vertices and retained
- * regions come from here. Also used for emitting random vertices,
- * these may be flushed by calling flush_current();
- */
- struct radeon_dma_region current;
-
- void (*flush)( radeonContextPtr );
+ /* Active dma region. Allocations for vertices and retained
+ * regions come from here. Also used for emitting random vertices,
+ * these may be flushed by calling flush_current();
+ */
+ struct radeon_dma_region current;
- char *buf0_address; /* start of buf[0], for index calcs */
- GLuint nr_released_bufs; /* flush after so many buffers released */
+ void (*flush) (radeonContextPtr);
+
+ char *buf0_address; /* start of buf[0], for index calcs */
+ GLuint nr_released_bufs; /* flush after so many buffers released */
};
struct radeon_dri_mirror {
- __DRIcontextPrivate *context; /* DRI context */
- __DRIscreenPrivate *screen; /* DRI screen */
+ __DRIcontextPrivate *context; /* DRI context */
+ __DRIscreenPrivate *screen; /* DRI screen */
/**
* DRI drawable bound to this context for drawing.
*/
- __DRIdrawablePrivate *drawable;
+ __DRIdrawablePrivate *drawable;
/**
* DRI drawable bound to this context for reading.
*/
- __DRIdrawablePrivate *readable;
+ __DRIdrawablePrivate *readable;
- drm_context_t hwContext;
- drm_hw_lock_t *hwLock;
- int fd;
- int drmMinor;
+ drm_context_t hwContext;
+ drm_hw_lock_t *hwLock;
+ int fd;
+ int drmMinor;
};
-
-#define RADEON_CMD_BUF_SZ (8*1024)
+#define RADEON_CMD_BUF_SZ (8*1024)
struct radeon_store {
- GLuint statenr;
- GLuint primnr;
- char cmd_buf[RADEON_CMD_BUF_SZ];
- int cmd_used;
- int elts_start;
+ GLuint statenr;
+ GLuint primnr;
+ char cmd_buf[RADEON_CMD_BUF_SZ];
+ int cmd_used;
+ int elts_start;
};
-
/* radeon_tcl.c
*/
struct radeon_tcl_info {
- GLuint vertex_format;
- GLuint hw_primitive;
-
- /* Temporary for cases where incoming vertex data is incompatible
- * with maos code.
- */
- GLvector4f ObjClean;
-
- struct radeon_dma_region *aos_components[8];
- GLuint nr_aos_components;
-
- GLuint *Elts;
-
- struct radeon_dma_region indexed_verts;
- struct radeon_dma_region obj;
- struct radeon_dma_region rgba;
- struct radeon_dma_region spec;
- struct radeon_dma_region fog;
- struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
- struct radeon_dma_region norm;
+ GLuint vertex_format;
+ GLuint hw_primitive;
+
+ /* Temporary for cases where incoming vertex data is incompatible
+ * with maos code.
+ */
+ GLvector4f ObjClean;
+
+ struct radeon_dma_region *aos_components[8];
+ GLuint nr_aos_components;
+
+ GLuint *Elts;
+
+ struct radeon_dma_region indexed_verts;
+ struct radeon_dma_region obj;
+ struct radeon_dma_region rgba;
+ struct radeon_dma_region spec;
+ struct radeon_dma_region fog;
+ struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
+ struct radeon_dma_region norm;
};
-
/* radeon_swtcl.c
*/
struct radeon_swtcl_info {
- GLuint RenderIndex;
- GLuint vertex_size;
- GLuint vertex_format;
+ GLuint RenderIndex;
+ GLuint vertex_size;
+ GLuint vertex_format;
- struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
- GLuint vertex_attr_count;
+ struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
+ GLuint vertex_attr_count;
- GLubyte *verts;
+ GLubyte *verts;
- /* Fallback rasterization functions
- */
- radeon_point_func draw_point;
- radeon_line_func draw_line;
- radeon_tri_func draw_tri;
+ /* Fallback rasterization functions
+ */
+ radeon_point_func draw_point;
+ radeon_line_func draw_line;
+ radeon_tri_func draw_tri;
- GLuint hw_primitive;
- GLenum render_primitive;
- GLuint numverts;
+ GLuint hw_primitive;
+ GLenum render_primitive;
+ GLuint numverts;
/**
* Offset of the 4UB color data within a hardware (swtcl) vertex.
*/
- GLuint coloroffset;
+ GLuint coloroffset;
/**
* Offset of the 3UB specular color data within a hardware (swtcl) vertex.
*/
- GLuint specoffset;
+ GLuint specoffset;
- GLboolean needproj;
+ GLboolean needproj;
- struct radeon_dma_region indexed_verts;
+ struct radeon_dma_region indexed_verts;
};
-
struct radeon_ioctl {
- GLuint vertex_offset;
- GLuint vertex_size;
+ GLuint vertex_offset;
+ GLuint vertex_size;
};
-
-
#define RADEON_MAX_PRIMS 64
-
-
struct radeon_prim {
- GLuint start;
- GLuint end;
- GLuint prim;
+ GLuint start;
+ GLuint end;
+ GLuint prim;
};
/* A maximum total of 20 elements per vertex: 3 floats for position, 3
@@ -615,145 +600,141 @@ struct radeon_prim {
*/
#define RADEON_MAX_VERTEX_SIZE 20
-
struct radeon_context {
- GLcontext *glCtx; /* Mesa context */
-
- /* Driver and hardware state management
- */
- struct radeon_hw_state hw;
- struct radeon_state state;
-
- /* Texture object bookkeeping
- */
- unsigned nr_heaps;
- driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ];
- driTextureObject swapped;
- int texture_depth;
- float initialMaxAnisotropy;
-
- /* Rasterization and vertex state:
- */
- GLuint TclFallback;
- GLuint Fallback;
- GLuint NewGLState;
- DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
-
- /* Vertex buffers
- */
- struct radeon_ioctl ioctl;
- struct radeon_dma dma;
- struct radeon_store store;
- /* A full state emit as of the first state emit in the main store, in case
- * the context is lost.
- */
- struct radeon_store backup_store;
-
- /* Page flipping
- */
- GLuint doPageFlip;
-
- /* Busy waiting
- */
- GLuint do_usleeps;
- GLuint do_irqs;
- GLuint irqsEmitted;
- drm_radeon_irq_wait_t iw;
-
- /* Drawable, cliprect and scissor information
- */
- GLuint numClipRects; /* Cliprects for the draw buffer */
- drm_clip_rect_t *pClipRects;
- unsigned int lastStamp;
- GLboolean lost_context;
- GLboolean save_on_next_emit;
- radeonScreenPtr radeonScreen; /* Screen private DRI data */
- drm_radeon_sarea_t *sarea; /* Private SAREA data */
-
- /* TCL stuff
- */
- GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS];
- GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS];
- GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS];
- GLuint TexGenEnabled;
- GLuint NeedTexMatrix;
- GLuint TexMatColSwap;
- GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
- GLuint last_ReallyEnabled;
-
- /* VBI
- */
- GLuint vbl_seq;
- GLuint vblank_flags;
-
- int64_t swap_ust;
- int64_t swap_missed_ust;
-
- GLuint swap_count;
- GLuint swap_missed_count;
-
-
- /* radeon_tcl.c
- */
- struct radeon_tcl_info tcl;
-
- /* radeon_swtcl.c
- */
- struct radeon_swtcl_info swtcl;
-
- /* Mirrors of some DRI state
- */
- struct radeon_dri_mirror dri;
-
- /* Configuration cache
- */
- driOptionCache optionCache;
-
- GLboolean using_hyperz;
- GLboolean texmicrotile;
-
- /* Performance counters
- */
- GLuint boxes; /* Draw performance boxes */
- GLuint hardwareWentIdle;
- GLuint c_clears;
- GLuint c_drawWaits;
- GLuint c_textureSwaps;
- GLuint c_textureBytes;
- GLuint c_vertexBuffers;
+ GLcontext *glCtx; /* Mesa context */
+
+ /* Driver and hardware state management
+ */
+ struct radeon_hw_state hw;
+ struct radeon_state state;
+
+ /* Texture object bookkeeping
+ */
+ unsigned nr_heaps;
+ driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
+ driTextureObject swapped;
+ int texture_depth;
+ float initialMaxAnisotropy;
+
+ /* Rasterization and vertex state:
+ */
+ GLuint TclFallback;
+ GLuint Fallback;
+ GLuint NewGLState;
+ DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
+
+ /* Vertex buffers
+ */
+ struct radeon_ioctl ioctl;
+ struct radeon_dma dma;
+ struct radeon_store store;
+ /* A full state emit as of the first state emit in the main store, in case
+ * the context is lost.
+ */
+ struct radeon_store backup_store;
+
+ /* Page flipping
+ */
+ GLuint doPageFlip;
+
+ /* Busy waiting
+ */
+ GLuint do_usleeps;
+ GLuint do_irqs;
+ GLuint irqsEmitted;
+ drm_radeon_irq_wait_t iw;
+
+ /* Drawable, cliprect and scissor information
+ */
+ GLuint numClipRects; /* Cliprects for the draw buffer */
+ drm_clip_rect_t *pClipRects;
+ unsigned int lastStamp;
+ GLboolean lost_context;
+ GLboolean save_on_next_emit;
+ radeonScreenPtr radeonScreen; /* Screen private DRI data */
+ drm_radeon_sarea_t *sarea; /* Private SAREA data */
+
+ /* TCL stuff
+ */
+ GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS];
+ GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS];
+ GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS];
+ GLuint TexGenEnabled;
+ GLuint NeedTexMatrix;
+ GLuint TexMatColSwap;
+ GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
+ GLuint last_ReallyEnabled;
+
+ /* VBI
+ */
+ GLuint vbl_seq;
+ GLuint vblank_flags;
+
+ int64_t swap_ust;
+ int64_t swap_missed_ust;
+
+ GLuint swap_count;
+ GLuint swap_missed_count;
+
+ /* radeon_tcl.c
+ */
+ struct radeon_tcl_info tcl;
+
+ /* radeon_swtcl.c
+ */
+ struct radeon_swtcl_info swtcl;
+
+ /* Mirrors of some DRI state
+ */
+ struct radeon_dri_mirror dri;
+
+ /* Configuration cache
+ */
+ driOptionCache optionCache;
+
+ GLboolean using_hyperz;
+ GLboolean texmicrotile;
+
+ /* Performance counters
+ */
+ GLuint boxes; /* Draw performance boxes */
+ GLuint hardwareWentIdle;
+ GLuint c_clears;
+ GLuint c_drawWaits;
+ GLuint c_textureSwaps;
+ GLuint c_textureBytes;
+ GLuint c_vertexBuffers;
};
#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
-
-static __inline GLuint radeonPackColor( GLuint cpp,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a )
+static __inline GLuint radeonPackColor(GLuint cpp,
+ GLubyte r, GLubyte g,
+ GLubyte b, GLubyte a)
{
- switch ( cpp ) {
- case 2:
- return PACK_COLOR_565( r, g, b );
- case 4:
- return PACK_COLOR_8888( a, r, g, b );
- default:
- return 0;
- }
+ switch (cpp) {
+ case 2:
+ return PACK_COLOR_565(r, g, b);
+ case 4:
+ return PACK_COLOR_8888(a, r, g, b);
+ default:
+ return 0;
+ }
}
#define RADEON_OLD_PACKETS 1
-
-extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv );
-extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual,
- __DRIcontextPrivate *driContextPriv,
+extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
+extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
+ __DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate);
-extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv );
+extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv);
extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
int x, int y, int w, int h);
-extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv );
-extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv );
+extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
+ __DRIdrawablePrivate * driDrawPriv,
+ __DRIdrawablePrivate * driReadPriv);
+extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
/* ================================================================
* Debugging:
@@ -766,18 +747,18 @@ extern int RADEON_DEBUG;
#define RADEON_DEBUG 0
#endif
-#define DEBUG_TEXTURE 0x001
-#define DEBUG_STATE 0x002
-#define DEBUG_IOCTL 0x004
-#define DEBUG_PRIMS 0x008
-#define DEBUG_VERTS 0x010
-#define DEBUG_FALLBACKS 0x020
-#define DEBUG_VFMT 0x040
-#define DEBUG_CODEGEN 0x080
-#define DEBUG_VERBOSE 0x100
-#define DEBUG_DRI 0x200
-#define DEBUG_DMA 0x400
-#define DEBUG_SANITY 0x800
-#define DEBUG_SYNC 0x1000
-
-#endif /* __RADEON_CONTEXT_H__ */
+#define DEBUG_TEXTURE 0x0001
+#define DEBUG_STATE 0x0002
+#define DEBUG_IOCTL 0x0004
+#define DEBUG_PRIMS 0x0008
+#define DEBUG_VERTS 0x0010
+#define DEBUG_FALLBACKS 0x0020
+#define DEBUG_VFMT 0x0040
+#define DEBUG_CODEGEN 0x0080
+#define DEBUG_VERBOSE 0x0100
+#define DEBUG_DRI 0x0200
+#define DEBUG_DMA 0x0400
+#define DEBUG_SANITY 0x0800
+#define DEBUG_SYNC 0x1000
+
+#endif /* __RADEON_CONTEXT_H__ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index 312041e035..30a0c3863c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -1,8 +1,12 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_lock.c,v 1.5 2002/10/30 12:51:55 alanh Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
All Rights Reserved.
@@ -30,8 +34,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
- * Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
+ * Keith Whitwell <keith@tungstengraphics.com>
+ * Kevin E. Martin <martin@valinux.com>
*/
#include "glheader.h"
@@ -44,7 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drirenderbuffer.h"
-
#if DEBUG_LOCKING
char *prevLockFile = NULL;
int prevLockLine = 0;
@@ -52,17 +56,15 @@ int prevLockLine = 0;
/* Turn on/off page flipping according to the flags in the sarea:
*/
-static void
-radeonUpdatePageFlipping( radeonContextPtr rmesa )
+static void radeonUpdatePageFlipping(radeonContextPtr rmesa)
{
- rmesa->doPageFlip = rmesa->sarea->pfState;
- if (rmesa->glCtx->WinSysDrawBuffer) {
- driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
- rmesa->sarea->pfCurrentPage);
- }
+ rmesa->doPageFlip = rmesa->sarea->pfState;
+ if (rmesa->glCtx->WinSysDrawBuffer) {
+ driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
+ rmesa->sarea->pfCurrentPage);
+ }
}
-
/* Update the hardware state. This is called if another context has
* grabbed the hardware lock, which includes the X server. This
* function also updates the driver's window state after the X server
@@ -71,51 +73,52 @@ radeonUpdatePageFlipping( radeonContextPtr rmesa )
* the hardware lock when it changes the window state, this routine will
* automatically be called after such a change.
*/
-void radeonGetLock( radeonContextPtr rmesa, GLuint flags )
+void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
{
- __DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
- __DRIdrawablePrivate *const readable = rmesa->dri.readable;
- __DRIscreenPrivate *sPriv = rmesa->dri.screen;
- drm_radeon_sarea_t *sarea = rmesa->sarea;
-
- drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags );
-
- /* The window might have moved, so we might need to get new clip
- * rects.
- *
- * NOTE: This releases and regrabs the hw lock to allow the X server
- * to respond to the DRI protocol request for new drawable info.
- * Since the hardware state depends on having the latest drawable
- * clip rects, all state checking must be done _after_ this call.
- */
- DRI_VALIDATE_DRAWABLE_INFO( sPriv, drawable );
- if (drawable != readable) {
- DRI_VALIDATE_DRAWABLE_INFO( sPriv, readable );
- }
-
- if ( rmesa->lastStamp != drawable->lastStamp ) {
- radeonUpdatePageFlipping( rmesa );
- radeonSetCliprects( rmesa );
- radeonUpdateViewportOffset( rmesa->glCtx );
- driUpdateFramebufferSize(rmesa->glCtx, drawable);
- }
-
- RADEON_STATECHANGE( rmesa, ctx );
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
- }
- else {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~RADEON_COLOR_TILE_ENABLE;
- }
-
- if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
- int i;
- sarea->ctx_owner = rmesa->dri.hwContext;
-
- for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
- DRI_AGE_TEXTURES( rmesa->texture_heaps[ i ] );
- }
- }
-
- rmesa->lost_context = GL_TRUE;
+ __DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
+ __DRIdrawablePrivate *const readable = rmesa->dri.readable;
+ __DRIscreenPrivate *sPriv = rmesa->dri.screen;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
+
+ drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags);
+
+ /* The window might have moved, so we might need to get new clip
+ * rects.
+ *
+ * NOTE: This releases and regrabs the hw lock to allow the X server
+ * to respond to the DRI protocol request for new drawable info.
+ * Since the hardware state depends on having the latest drawable
+ * clip rects, all state checking must be done _after_ this call.
+ */
+ DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable);
+ if (drawable != readable) {
+ DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable);
+ }
+
+ if (rmesa->lastStamp != drawable->lastStamp) {
+ radeonUpdatePageFlipping(rmesa);
+ radeonSetCliprects(rmesa);
+ radeonUpdateViewportOffset(rmesa->glCtx);
+ driUpdateFramebufferSize(rmesa->glCtx, drawable);
+ }
+
+ RADEON_STATECHANGE(rmesa, ctx);
+ if (rmesa->sarea->tiling_enabled) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
+ RADEON_COLOR_TILE_ENABLE;
+ } else {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
+ ~RADEON_COLOR_TILE_ENABLE;
+ }
+
+ if (sarea->ctx_owner != rmesa->dri.hwContext) {
+ int i;
+ sarea->ctx_owner = rmesa->dri.hwContext;
+
+ for (i = 0; i < rmesa->nr_heaps; i++) {
+ DRI_AGE_TEXTURES(rmesa->texture_heaps[i]);
+ }
+ }
+
+ rmesa->lost_context = GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h
index 4e8617eb8f..86e96aa7d2 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.h
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.h
@@ -1,8 +1,12 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_lock.h,v 1.3 2002/10/30 12:51:55 alanh Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
All Rights Reserved.
@@ -30,14 +34,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
- * Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
+ * Keith Whitwell <keith@tungstengraphics.com>
+ * Kevin E. Martin <martin@valinux.com>
*/
#ifndef __RADEON_LOCK_H__
#define __RADEON_LOCK_H__
-extern void radeonGetLock( radeonContextPtr rmesa, GLuint flags );
+extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags);
/* Turn DEBUG_LOCKING on to find locking conflicts.
*/
@@ -83,26 +88,25 @@ extern int prevLockLine;
* do not do any drawing !!!
*/
-
/* Lock the hardware and validate our state.
*/
#define LOCK_HARDWARE( rmesa ) \
do { \
char __ret = 0; \
DEBUG_CHECK_LOCK(); \
- DRM_CAS( rmesa->dri.hwLock, rmesa->dri.hwContext, \
- (DRM_LOCK_HELD | rmesa->dri.hwContext), __ret ); \
+ DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \
+ (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \
if ( __ret ) \
- radeonGetLock( rmesa, 0 ); \
+ radeonGetLock( (rmesa), 0 ); \
DEBUG_LOCK(); \
} while (0)
#define UNLOCK_HARDWARE( rmesa ) \
do { \
- DRM_UNLOCK( rmesa->dri.fd, \
- rmesa->dri.hwLock, \
- rmesa->dri.hwContext ); \
+ DRM_UNLOCK( (rmesa)->dri.fd, \
+ (rmesa)->dri.hwLock, \
+ (rmesa)->dri.hwContext ); \
DEBUG_RESET(); \
} while (0)
-#endif /* __RADEON_LOCK_H__ */
+#endif /* __RADEON_LOCK_H__ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index b0c8fae285..aa7fb633dd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -56,6 +56,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
#include "r300_context.h"
#include "r300_fragprog.h"
+#include "r300_tex.h"
#include "radeon_span.h"
#endif
@@ -656,8 +657,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
case PCI_CHIP_RC410_5A61:
case PCI_CHIP_RC410_5A62:
screen->chip_family = CHIP_FAMILY_RS400;
- fprintf(stderr, "Warning, xpress200 detected. Won't work.\n");
- return NULL;
+ fprintf(stderr, "Warning, xpress200 detected.\n");
break;
default:
@@ -953,6 +953,9 @@ static struct __DriverAPIRec radeonAPI = {
.WaitForSBC = NULL,
.SwapBuffersMSC = NULL,
.CopySubBuffer = radeonCopySubBuffer,
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+ .setTexOffset = r300SetTexOffset,
+#endif
};
#else
static const struct __DriverAPIRec r200API = {
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index c49f5870c6..732a85ecf0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -1,9 +1,13 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
/**************************************************************************
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
+
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining
@@ -47,10 +51,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drirenderbuffer.h"
-
#define DBG 0
-
/*
* Note that all information needed to access pixels in a renderbuffer
* should be obtained through the gl_renderbuffer parameter, not per-context
@@ -81,8 +83,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define HW_UNLOCK()
-
-
/* ================================================================
* Color buffer
*/
@@ -97,7 +97,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
#include "spantmp2.h"
-
/* 32 bit, ARGB8888 color spanline and pixel functions
*/
#define SPANTMP_PIXEL_FMT GL_BGRA
@@ -108,7 +107,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
#include "spantmp2.h"
-
/* ================================================================
* Depth buffer
*/
@@ -123,59 +121,56 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* too...
*/
-static GLuint
-radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
+static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
{
- GLuint pitch = drb->pitch;
- if (drb->depthHasSurface) {
- return 4 * (x + y * pitch);
- }
- else {
- GLuint ba, address = 0; /* a[0..1] = 0 */
-
- ba = (y / 16) * (pitch / 16) + (x / 16);
-
- address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
- address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
- address |=
- (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
-
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |=
- (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
- address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
-
- return address;
- }
+ GLuint pitch = drb->pitch;
+ if (drb->depthHasSurface) {
+ return 4 * (x + y * pitch);
+ } else {
+ GLuint ba, address = 0; /* a[0..1] = 0 */
+
+#ifdef COMPILE_R300
+ ba = (y / 8) * (pitch / 8) + (x / 8);
+#else
+ ba = (y / 16) * (pitch / 16) + (x / 16);
+#endif
+
+ address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
+ address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
+ address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
+ address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
+
+ address |= (y & 0x8) << 7; /* a[10] = y[3] */
+ address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
+ address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
+
+ return address;
+ }
}
-
static INLINE GLuint
-radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
+radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
{
- GLuint pitch = drb->pitch;
- if (drb->depthHasSurface) {
- return 2 * (x + y * pitch);
- }
- else {
- GLuint ba, address = 0; /* a[0] = 0 */
-
- ba = (y / 16) * (pitch / 32) + (x / 32);
-
- address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
- address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
- address |= (x & 0x8) << 4; /* a[7] = x[3] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
- address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
-
- return address;
- }
+ GLuint pitch = drb->pitch;
+ if (drb->depthHasSurface) {
+ return 2 * (x + y * pitch);
+ } else {
+ GLuint ba, address = 0; /* a[0] = 0 */
+
+ ba = (y / 16) * (pitch / 32) + (x / 32);
+
+ address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
+ address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
+ address |= (x & 0x8) << 4; /* a[7] = x[3] */
+ address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
+ address |= (y & 0x8) << 7; /* a[10] = y[3] */
+ address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
+ address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
+
+ return address;
+ }
}
-
/* 16-bit depth buffer functions
*/
#define WRITE_DEPTH( _x, _y, d ) \
@@ -187,9 +182,21 @@ radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
#define TAG(x) radeon##x##_z16
#include "depthtmp.h"
-
/* 24 bit depth, 8 bit stencil depthbuffer functions
+ *
+ * Careful: It looks like the R300 uses ZZZS byte order while the R200
+ * uses SZZZ for 24 bit depth, 8 bit stencil mode.
*/
+#ifdef COMPILE_R300
+#define WRITE_DEPTH( _x, _y, d ) \
+do { \
+ GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
+ GLuint tmp = *(GLuint *)(buf + offset); \
+ tmp &= 0x000000ff; \
+ tmp |= ((d << 8) & 0xffffff00); \
+ *(GLuint *)(buf + offset) = tmp; \
+} while (0)
+#else
#define WRITE_DEPTH( _x, _y, d ) \
do { \
GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
@@ -198,21 +205,39 @@ do { \
tmp |= ((d) & 0x00ffffff); \
*(GLuint *)(buf + offset) = tmp; \
} while (0)
+#endif
+#ifdef COMPILE_R300
+#define READ_DEPTH( d, _x, _y ) \
+ do { \
+ d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
+ _y + yo )) & 0xffffff00) >> 8; \
+ }while(0)
+#else
#define READ_DEPTH( d, _x, _y ) \
d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
_y + yo )) & 0x00ffffff;
+#endif
#define TAG(x) radeon##x##_z24_s8
#include "depthtmp.h"
-
/* ================================================================
* Stencil buffer
*/
/* 24 bit depth, 8 bit stencil depthbuffer functions
*/
+#ifdef COMPILE_R300
+#define WRITE_STENCIL( _x, _y, d ) \
+do { \
+ GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
+ GLuint tmp = *(GLuint *)(buf + offset); \
+ tmp &= 0xffffff00; \
+ tmp |= (d) & 0xff; \
+ *(GLuint *)(buf + offset) = tmp; \
+} while (0)
+#else
#define WRITE_STENCIL( _x, _y, d ) \
do { \
GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
@@ -221,69 +246,77 @@ do { \
tmp |= (((d) & 0xff) << 24); \
*(GLuint *)(buf + offset) = tmp; \
} while (0)
+#endif
+#ifdef COMPILE_R300
#define READ_STENCIL( d, _x, _y ) \
do { \
GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
GLuint tmp = *(GLuint *)(buf + offset); \
- tmp &= 0xff000000; \
- d = tmp >> 24; \
+ d = tmp & 0x000000ff; \
} while (0)
+#else
+#define READ_STENCIL( d, _x, _y ) \
+do { \
+ GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
+ GLuint tmp = *(GLuint *)(buf + offset); \
+ d = (tmp & 0xff000000) >> 24; \
+} while (0)
+#endif
#define TAG(x) radeon##x##_z24_s8
#include "stenciltmp.h"
-
-
/* Move locking out to get reasonable span performance (10x better
* than doing this in HW_LOCK above). WaitForIdle() is the main
* culprit.
*/
-static void radeonSpanRenderStart( GLcontext *ctx )
+static void radeonSpanRenderStart(GLcontext * ctx)
{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
- radeonWaitForIdleLocked( rmesa );
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+#ifdef COMPILE_R300
+ r300ContextPtr r300 = (r300ContextPtr) rmesa;
+ R300_FIREVERTICES(r300);
+#else
+ RADEON_FIREVERTICES(rmesa);
+#endif
+ LOCK_HARDWARE(rmesa);
+ radeonWaitForIdleLocked(rmesa);
}
-static void radeonSpanRenderFinish( GLcontext *ctx )
+static void radeonSpanRenderFinish(GLcontext * ctx)
{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- _swrast_flush( ctx );
- UNLOCK_HARDWARE( rmesa );
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ _swrast_flush(ctx);
+ UNLOCK_HARDWARE(rmesa);
}
-void radeonInitSpanFuncs( GLcontext *ctx )
+void radeonInitSpanFuncs(GLcontext * ctx)
{
- struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
- swdd->SpanRenderStart = radeonSpanRenderStart;
- swdd->SpanRenderFinish = radeonSpanRenderFinish;
+ struct swrast_device_driver *swdd =
+ _swrast_GetDeviceDriverReference(ctx);
+ swdd->SpanRenderStart = radeonSpanRenderStart;
+ swdd->SpanRenderFinish = radeonSpanRenderFinish;
}
-
/**
* Plug in the Get/Put routines for the given driRenderbuffer.
*/
-void
-radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
+void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
{
- if (drb->Base.InternalFormat == GL_RGBA) {
- if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
- radeonInitPointers_RGB565(&drb->Base);
- }
- else {
- radeonInitPointers_ARGB8888(&drb->Base);
- }
- }
- else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
- radeonInitDepthPointers_z16(&drb->Base);
- }
- else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
- radeonInitDepthPointers_z24_s8(&drb->Base);
- }
- else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
- radeonInitStencilPointers_z24_s8(&drb->Base);
- }
+ if (drb->Base.InternalFormat == GL_RGBA) {
+ if (vis->redBits == 5 && vis->greenBits == 6
+ && vis->blueBits == 5) {
+ radeonInitPointers_RGB565(&drb->Base);
+ } else {
+ radeonInitPointers_ARGB8888(&drb->Base);
+ }
+ } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
+ radeonInitDepthPointers_z16(&drb->Base);
+ } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
+ radeonInitDepthPointers_z24_s8(&drb->Base);
+ } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
+ radeonInitStencilPointers_z24_s8(&drb->Base);
+ }
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h
index 13b308e1c4..9abe0864b1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.h
+++ b/src/mesa/drivers/dri/radeon/radeon_span.h
@@ -1,8 +1,12 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.h,v 1.2 2002/02/22 21:45:01 dawes Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
All Rights Reserved.
@@ -30,8 +34,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
- * Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
+ * Keith Whitwell <keith@tungstengraphics.com>
+ * Kevin E. Martin <martin@valinux.com>
*/
#ifndef __RADEON_SPAN_H__
@@ -39,8 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drirenderbuffer.h"
-extern void radeonInitSpanFuncs( GLcontext *ctx );
-
-extern void radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
+extern void radeonInitSpanFuncs(GLcontext * ctx);
+extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis);
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-18 12:36:28 +0000