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-rw-r--r--src/mesa/drivers/dri/r200/r200_context.h6
-rw-r--r--src/mesa/drivers/dri/r200/r200_state.c17
-rw-r--r--src/mesa/drivers/dri/r200/r200_state_init.c9
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common.c25
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common.h1
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.h7
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state.c16
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state_init.c10
8 files changed, 62 insertions, 29 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index c5dccf0a75..246f98c6dc 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -479,6 +479,11 @@ struct r200_texture_state {
#define R200_QUERYOBJ_DATA_0 1
#define R200_QUERYOBJ_CMDSIZE 2
+#define STP_CMD_0 0
+#define STP_DATA_0 1
+#define STP_CMD_1 2
+#define STP_STATE_SIZE 35
+
struct r200_hw_state {
/* Hardware state, stored as cmdbuf commands:
* -- Need to doublebuffer for
@@ -521,6 +526,7 @@ struct r200_hw_state {
struct radeon_state_atom atf;
struct radeon_state_atom spr;
struct radeon_state_atom ptp;
+ struct radeon_state_atom stp;
};
struct r200_state {
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index fea7681c8a..76852e315c 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -2466,6 +2466,21 @@ static void r200WrapRunPipeline( GLcontext *ctx )
}
+static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask )
+{
+ r200ContextPtr r200 = R200_CONTEXT(ctx);
+ GLint i;
+
+ radeon_firevertices(&r200->radeon);
+
+ R200_STATECHANGE(r200, stp);
+
+ /* Must flip pattern upside down.
+ */
+ for ( i = 31 ; i >= 0; i--) {
+ r200->hw.stp.cmd[3 + i] = ((GLuint *) mask)[i];
+ }
+}
/* Initialize the driver's state functions.
*/
void r200InitStateFuncs( struct dd_function_table *functions, GLboolean dri2 )
@@ -2503,7 +2518,7 @@ void r200InitStateFuncs( struct dd_function_table *functions, GLboolean dri2 )
functions->PolygonMode = r200PolygonMode;
functions->PolygonOffset = r200PolygonOffset;
if (dri2)
- functions->PolygonStipple = radeonPolygonStipple;
+ functions->PolygonStipple = r200PolygonStipple;
else
functions->PolygonStipple = radeonPolygonStipplePreKMS;
functions->PointParameterfv = r200PointParameter;
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 3e0cebaa07..7697306d88 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -885,6 +885,10 @@ void r200InitState( r200ContextPtr rmesa )
}
}
}
+ /* polygon stipple is done with irq for non-kms */
+ if (rmesa->radeon.radeonScreen->kernel_mm) {
+ ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
+ }
for (i = 0; i < 6; i++)
if (rmesa->radeon.radeonScreen->kernel_mm)
@@ -1117,6 +1121,11 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
if (rmesa->radeon.radeonScreen->kernel_mm) {
+
+ rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
+ rmesa->hw.stp.cmd[STP_DATA_0] = 0;
+ rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
+
rmesa->hw.mtl[0].emit = mtl_emit;
rmesa->hw.mtl[1].emit = mtl_emit;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index aaa5165bc8..1836dbc79a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -312,31 +312,6 @@ void radeonPolygonStipplePreKMS( GLcontext *ctx, const GLubyte *mask )
UNLOCK_HARDWARE( radeon );
}
-void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- GLint i;
- BATCH_LOCALS(radeon);
-
- radeon_firevertices(radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(35);
-
- OUT_BATCH(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
- OUT_BATCH(0x00000000);
-
- OUT_BATCH(CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31));
-
- /* Must flip pattern upside down.
- */
- for ( i = 31 ; i >= 0; i--) {
- OUT_BATCH(((GLuint *) mask)[i]);
- }
-
- END_BATCH();
-}
-
-
/* ================================================================
* SwapBuffers with client-side throttling
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index ba983e5ab6..f3201911ac 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -10,7 +10,6 @@ void radeonRecalcScissorRects(radeonContextPtr radeon);
void radeonSetCliprects(radeonContextPtr radeon);
void radeonUpdateScissor( GLcontext *ctx );
void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h);
-void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask );
void radeonPolygonStipplePreKMS( GLcontext *ctx, const GLubyte *mask );
void radeonWaitForIdleLocked(radeonContextPtr radeon);
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 572acbb006..4e2c52c835 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -299,6 +299,11 @@ struct radeon_texture_state {
#define R100_QUERYOBJ_DATA_0 1
#define R100_QUERYOBJ_CMDSIZE 2
+#define STP_CMD_0 0
+#define STP_DATA_0 1
+#define STP_CMD_1 2
+#define STP_STATE_SIZE 35
+
struct r100_hw_state {
/* Hardware state, stored as cmdbuf commands:
* -- Need to doublebuffer for
@@ -323,7 +328,7 @@ struct r100_hw_state {
struct radeon_state_atom fog;
struct radeon_state_atom glt;
struct radeon_state_atom txr[3]; /* for NPOT */
-
+ struct radeon_state_atom stp;
};
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index c8cc7f9bcf..4d0d35ee0c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -2197,6 +2197,22 @@ static void radeonWrapRunPipeline( GLcontext *ctx )
}
}
+static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
+{
+ r100ContextPtr r100 = R100_CONTEXT(ctx);
+ GLint i;
+
+ radeon_firevertices(&r100->radeon);
+
+ RADEON_STATECHANGE(r100, stp);
+
+ /* Must flip pattern upside down.
+ */
+ for ( i = 31 ; i >= 0; i--) {
+ r100->hw.stp.cmd[3 + i] = ((GLuint *) mask)[i];
+ }
+}
+
/* Initialize the driver's state functions.
* Many of the ctx->Driver functions might have been initialized to
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 8236199b9b..f3ad0dd17a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -781,6 +781,10 @@ void radeonInitState( r100ContextPtr rmesa )
ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
}
+ if (rmesa->radeon.radeonScreen->kernel_mm) {
+ ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
+ }
+
for (i = 0; i < 3; i++) {
if (rmesa->radeon.radeonScreen->kernel_mm)
rmesa->hw.tex[i].emit = tex_emit_cs;
@@ -873,6 +877,10 @@ void radeonInitState( r100ContextPtr rmesa )
}
if (rmesa->radeon.radeonScreen->kernel_mm) {
+ rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
+ rmesa->hw.stp.cmd[STP_DATA_0] = 0;
+ rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
+
rmesa->hw.grd.emit = scl_emit;
rmesa->hw.fog.emit = vec_emit;
rmesa->hw.glt.emit = vec_emit;
@@ -1143,7 +1151,7 @@ void radeonInitState( r100ContextPtr rmesa )
rmesa->hw.eye.cmd[EYE_Y] = 0;
rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
-
+
if (rmesa->radeon.radeonScreen->kernel_mm) {
radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE);
rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-02 04:47:45 +0000