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-rw-r--r--src/mesa/drivers/dri/common/dri_util.c31
-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c18
-rw-r--r--src/mesa/drivers/dri/i915/i915_program.c22
-rw-r--r--src/mesa/drivers/dri/i915/i915_tex_layout.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c34
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c80
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_emit.c90
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_sampler_state.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.h2
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.c4
-rw-r--r--src/mesa/drivers/dri/r600/r600_context.c2
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.c48
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.h2
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c259
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_queryobj.c4
16 files changed, 501 insertions, 113 deletions
diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
index 11c189a660..d2ffa5da64 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -153,19 +153,24 @@ static int driBindContext(__DRIcontext *pcp,
{
__DRIscreen *psp = NULL;
- /* Bind the drawable to the context */
+ /*
+ ** Assume error checking is done properly in glXMakeCurrent before
+ ** calling driUnbindContext.
+ */
- if (pcp) {
- psp = pcp->driScreenPriv;
- pcp->driDrawablePriv = pdp;
- pcp->driReadablePriv = prp;
- if (pdp) {
- pdp->driContextPriv = pcp;
- dri_get_drawable(pdp);
- }
- if ( prp && pdp != prp ) {
- dri_get_drawable(prp);
- }
+ if (!pcp)
+ return GL_FALSE;
+
+ /* Bind the drawable to the context */
+ psp = pcp->driScreenPriv;
+ pcp->driDrawablePriv = pdp;
+ pcp->driReadablePriv = prp;
+ if (pdp) {
+ pdp->driContextPriv = pcp;
+ dri_get_drawable(pdp);
+ }
+ if (prp && pdp != prp) {
+ dri_get_drawable(prp);
}
/*
@@ -173,7 +178,6 @@ static int driBindContext(__DRIcontext *pcp,
** initialize the drawable information if has not been done before.
*/
- assert(psp);
if (!psp->dri2.enabled) {
if (pdp && !pdp->pStamp) {
DRM_SPINLOCK(&psp->pSAREA->drawable_lock, psp->drawLockID);
@@ -188,7 +192,6 @@ static int driBindContext(__DRIcontext *pcp,
}
/* Call device-specific MakeCurrent */
-
return (*psp->DriverAPI.MakeCurrent)(pcp, pdp, prp);
}
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 9f12e2c632..e60157f377 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -359,9 +359,10 @@ upload_program(struct i915_fragment_program *p)
}
if (program->Base.NumInstructions > I915_MAX_INSN) {
- i915_program_error( p, "Exceeded max instructions" );
- return;
- }
+ i915_program_error(p, "Exceeded max instructions (%d out of %d)",
+ program->Base.NumInstructions, I915_MAX_INSN);
+ return;
+ }
/* Not always needed:
*/
@@ -1099,12 +1100,23 @@ translate_program(struct i915_fragment_program *p)
{
struct i915_context *i915 = I915_CONTEXT(p->ctx);
+ if (INTEL_DEBUG & DEBUG_WM) {
+ printf("fp:\n");
+ _mesa_print_program(&p->ctx->FragmentProgram._Current->Base);
+ printf("\n");
+ }
+
i915_init_program(i915, p);
check_wpos(p);
upload_program(p);
fixup_depth_write(p);
i915_fini_program(p);
+ if (INTEL_DEBUG & DEBUG_WM) {
+ printf("i915:\n");
+ i915_disassemble_program(i915->state.Program, i915->state.ProgramSize);
+ }
+
p->translated = 1;
}
diff --git a/src/mesa/drivers/dri/i915/i915_program.c b/src/mesa/drivers/dri/i915/i915_program.c
index 3902c69097..670c713785 100644
--- a/src/mesa/drivers/dri/i915/i915_program.c
+++ b/src/mesa/drivers/dri/i915/i915_program.c
@@ -494,17 +494,25 @@ i915_fini_program(struct i915_fragment_program *p)
GLuint program_size = p->csr - p->program;
GLuint decl_size = p->decl - p->declarations;
- if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
- i915_program_error(p, "Exceeded max nr indirect texture lookups");
+ if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT) {
+ i915_program_error(p, "Exceeded max nr indirect texture lookups "
+ "(%d out of %d)",
+ p->nr_tex_indirect, I915_MAX_TEX_INDIRECT);
+ }
- if (p->nr_tex_insn > I915_MAX_TEX_INSN)
- i915_program_error(p, "Exceeded max TEX instructions");
+ if (p->nr_tex_insn > I915_MAX_TEX_INSN) {
+ i915_program_error(p, "Exceeded max TEX instructions (%d out of %d)",
+ p->nr_tex_insn, I915_MAX_TEX_INSN);
+ }
if (p->nr_alu_insn > I915_MAX_ALU_INSN)
- i915_program_error(p, "Exceeded max ALU instructions");
+ i915_program_error(p, "Exceeded max ALU instructions (%d out of %d)",
+ p->nr_alu_insn, I915_MAX_ALU_INSN);
- if (p->nr_decl_insn > I915_MAX_DECL_INSN)
- i915_program_error(p, "Exceeded max DECL instructions");
+ if (p->nr_decl_insn > I915_MAX_DECL_INSN) {
+ i915_program_error(p, "Exceeded max DECL instructions (%d out of %d)",
+ p->nr_decl_insn, I915_MAX_DECL_INSN);
+ }
if (p->error) {
p->FragProg.Base.NumNativeInstructions = 0;
diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index af9c7ee9b6..6e4512129c 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -483,7 +483,7 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
case GL_TEXTURE_1D:
case GL_TEXTURE_2D:
case GL_TEXTURE_RECTANGLE_ARB:
- i945_miptree_layout_2d(intel, mt, tiling);
+ i945_miptree_layout_2d(intel, mt, tiling, 1);
break;
default:
_mesa_problem(NULL, "Unexpected tex target in i945_miptree_layout()");
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 1fd957b3ad..41a1f438df 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -34,6 +34,7 @@
#include "shader/prog_parameter.h"
#include "shader/program.h"
#include "shader/programopt.h"
+#include "shader/shader_api.h"
#include "tnl/tnl.h"
#include "brw_context.h"
@@ -119,12 +120,28 @@ static GLboolean brwIsProgramNative( GLcontext *ctx,
return GL_TRUE;
}
+static void
+shader_error(GLcontext *ctx, struct gl_program *prog, const char *msg)
+{
+ struct gl_shader_program *shader;
+
+ shader = _mesa_lookup_shader_program(ctx, prog->Id);
+
+ if (shader) {
+ if (shader->InfoLog) {
+ free(shader->InfoLog);
+ }
+ shader->InfoLog = _mesa_strdup(msg);
+ shader->LinkStatus = GL_FALSE;
+ }
+}
static GLboolean brwProgramStringNotify( GLcontext *ctx,
GLenum target,
struct gl_program *prog )
{
struct brw_context *brw = brw_context(ctx);
+ int i;
if (target == GL_FRAGMENT_PROGRAM_ARB) {
struct gl_fragment_program *fprog = (struct gl_fragment_program *) prog;
@@ -160,7 +177,22 @@ static GLboolean brwProgramStringNotify( GLcontext *ctx,
_tnl_program_string(ctx, target, prog);
}
- /* XXX check if program is legal, within limits */
+ /* Reject programs with subroutines, which are totally broken at the moment
+ * (all program flows return when any program flow returns, and
+ * the VS also hangs if a function call calls a function.
+ *
+ * See piglit glsl-{vs,fs}-functions-[23] tests.
+ */
+ for (i = 0; i < prog->NumInstructions; i++) {
+ if (prog->Instructions[i].Opcode == OPCODE_CAL) {
+ shader_error(ctx, prog,
+ "i965 driver doesn't yet support uninlined function "
+ "calls. Move to using a single return statement at "
+ "the end of the function to work around it.");
+ return GL_FALSE;
+ }
+ }
+
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 9a215ab8a4..768ccfd79c 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -49,74 +49,30 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (intel->gen == 5) {
- GLuint align_h = 2, align_w = 4;
+ GLuint align_h = 2;
GLuint level;
- GLuint x = 0;
- GLuint y = 0;
- GLuint width = mt->width0;
- GLuint height = mt->height0;
GLuint qpitch = 0;
- GLuint y_pitch = 0;
+ int h0, h1, q;
- mt->total_width = mt->width0;
- intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
- y_pitch = ALIGN(height, align_h);
+ /* On Ironlake, cube maps are finally represented as just a series
+ * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
+ * by a pitch of qpitch rows, where qpitch is defined by the equation
+ * given in Volume 1 of the BSpec.
+ */
+ h0 = ALIGN(mt->height0, align_h);
+ h1 = ALIGN(minify(h0), align_h);
+ qpitch = (h0 + h1 + 11 * align_h);
+ if (mt->compressed)
+ qpitch /= 4;
- if (mt->compressed) {
- mt->total_width = ALIGN(mt->width0, align_w);
- }
-
- if (mt->first_level != mt->last_level) {
- GLuint mip1_width;
-
- if (mt->compressed) {
- mip1_width = ALIGN(minify(mt->width0), align_w)
- + ALIGN(minify(minify(mt->width0)), align_w);
- } else {
- mip1_width = ALIGN(minify(mt->width0), align_w)
- + minify(minify(mt->width0));
- }
-
- if (mip1_width > mt->total_width) {
- mt->total_width = mip1_width;
- }
- }
-
- if (mt->compressed) {
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4;
- mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
- } else {
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h);
- mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
- }
+ i945_miptree_layout_2d(intel, mt, tiling, 6);
for (level = mt->first_level; level <= mt->last_level; level++) {
- GLuint img_height;
- GLuint nr_images = 6;
- GLuint q = 0;
-
- intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
- height, 1);
-
- for (q = 0; q < nr_images; q++)
- intel_miptree_set_image_offset(mt, level, q,
- x, y + q * qpitch);
-
- if (mt->compressed)
- img_height = MAX2(1, height/4);
- else
- img_height = ALIGN(height, align_h);
-
- if (level == mt->first_level + 1) {
- x += ALIGN(width, align_w);
- }
- else {
- y += img_height;
- }
-
- width = minify(width);
- height = minify(height);
+ for (q = 0; q < 6; q++) {
+ intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
+ }
}
+ mt->total_height = qpitch * 6;
break;
}
@@ -206,7 +162,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
}
default:
- i945_miptree_layout_2d(intel, mt, tiling);
+ i945_miptree_layout_2d(intel, mt, tiling, 1);
break;
}
DBG("%s: %dx%dx%d\n", __FUNCTION__,
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index eeb3f366a4..dc6ab81c4a 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -37,6 +37,43 @@
#include "brw_context.h"
#include "brw_vs.h"
+/* Return the SrcReg index of the channels that can be immediate float operands
+ * instead of usage of PROGRAM_CONSTANT values through push/pull.
+ */
+static GLboolean
+brw_vs_arg_can_be_immediate(enum prog_opcode opcode, int arg)
+{
+ int opcode_array[] = {
+ [OPCODE_ADD] = 2,
+ [OPCODE_CMP] = 3,
+ [OPCODE_DP3] = 2,
+ [OPCODE_DP4] = 2,
+ [OPCODE_DPH] = 2,
+ [OPCODE_MAX] = 2,
+ [OPCODE_MIN] = 2,
+ [OPCODE_MUL] = 2,
+ [OPCODE_SEQ] = 2,
+ [OPCODE_SGE] = 2,
+ [OPCODE_SGT] = 2,
+ [OPCODE_SLE] = 2,
+ [OPCODE_SLT] = 2,
+ [OPCODE_SNE] = 2,
+ [OPCODE_XPD] = 2,
+ };
+
+ /* These opcodes get broken down in a way that allow two
+ * args to be immediates.
+ */
+ if (opcode == OPCODE_MAD || opcode == OPCODE_LRP) {
+ if (arg == 1 || arg == 2)
+ return GL_TRUE;
+ }
+
+ if (opcode > ARRAY_SIZE(opcode_array))
+ return GL_FALSE;
+
+ return arg == opcode_array[opcode] - 1;
+}
static struct brw_reg get_tmp( struct brw_vs_compile *c )
{
@@ -453,8 +490,8 @@ static void emit_max( struct brw_compile *p,
struct brw_reg arg0,
struct brw_reg arg1 )
{
- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1);
- brw_SEL(p, dst, arg1, arg0);
+ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1);
+ brw_SEL(p, dst, arg0, arg1);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
@@ -983,6 +1020,55 @@ get_src_reg( struct brw_vs_compile *c,
const GLint index = inst->SrcReg[argIndex].Index;
const GLboolean relAddr = inst->SrcReg[argIndex].RelAddr;
+ if (brw_vs_arg_can_be_immediate(inst->Opcode, argIndex)) {
+ const struct prog_src_register *src = &inst->SrcReg[argIndex];
+
+ if (src->Swizzle == MAKE_SWIZZLE4(SWIZZLE_ZERO,
+ SWIZZLE_ZERO,
+ SWIZZLE_ZERO,
+ SWIZZLE_ZERO)) {
+ return brw_imm_f(0.0f);
+ } else if (src->Swizzle == MAKE_SWIZZLE4(SWIZZLE_ONE,
+ SWIZZLE_ONE,
+ SWIZZLE_ONE,
+ SWIZZLE_ONE)) {
+ if (src->Negate)
+ return brw_imm_f(-1.0F);
+ else
+ return brw_imm_f(1.0F);
+ } else if (src->File == PROGRAM_CONSTANT) {
+ const struct gl_program_parameter_list *params;
+ float f;
+ int component = -1;
+
+ switch (src->Swizzle) {
+ case SWIZZLE_XXXX:
+ component = 0;
+ break;
+ case SWIZZLE_YYYY:
+ component = 1;
+ break;
+ case SWIZZLE_ZZZZ:
+ component = 2;
+ break;
+ case SWIZZLE_WWWW:
+ component = 3;
+ break;
+ }
+
+ if (component >= 0) {
+ params = c->vp->program.Base.Parameters;
+ f = params->ParameterValues[src->Index][component];
+
+ if (src->Abs)
+ f = fabs(f);
+ if (src->Negate)
+ f = -f;
+ return brw_imm_f(f);
+ }
+ }
+ }
+
switch (file) {
case PROGRAM_TEMPORARY:
case PROGRAM_INPUT:
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index d7650af3d9..1582ff1ab6 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -228,6 +228,8 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
{
GLcontext *ctx = &brw->intel.ctx;
int unit;
+ char *last_entry_end = ((char*)&key->sampler_count) +
+ sizeof(key->sampler_count);
key->sampler_count = 0;
@@ -240,7 +242,9 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
struct gl_texture_image *firstImage =
texObj->Image[0][intelObj->firstLevel];
- memset(entry, 0, sizeof(*entry));
+ memset(last_entry_end, 0,
+ (char*)entry - last_entry_end + sizeof(*entry));
+ last_entry_end = ((char*)entry) + sizeof(*entry);
entry->tex_target = texObj->Target;
@@ -280,6 +284,8 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
key->sampler_count = unit + 1;
}
}
+ struct wm_sampler_entry *entry = &key->sampler[key->sampler_count];
+ memset(last_entry_end, 0, (char*)entry - last_entry_end);
}
/* All samplers must be uploaded in a single contiguous array, which
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index d132e19e83..d39733b6c5 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -63,9 +63,9 @@ void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *
}
}
-void i945_miptree_layout_2d( struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- uint32_t tiling )
+void i945_miptree_layout_2d(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ uint32_t tiling, int nr_images)
{
GLuint align_h = 2, align_w = 4;
GLuint level;
@@ -107,7 +107,7 @@ void i945_miptree_layout_2d( struct intel_context *intel,
for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
GLuint img_height;
- intel_miptree_set_level_info(mt, level, 1, x, y, width,
+ intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
height, 1);
if (mt->compressed)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index a9ac9e7eb4..1c8c53e545 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h
@@ -40,5 +40,5 @@ static INLINE GLuint minify( GLuint d )
extern void i945_miptree_layout_2d(struct intel_context *intel,
struct intel_mipmap_tree *mt,
- uint32_t tiling);
+ uint32_t tiling, int nr_images);
extern void intel_get_texture_alignment_unit(GLenum, GLuint *, GLuint *);
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 244fdc4ffb..172f85eb26 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -344,6 +344,10 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
return;
}
+ /* must be 0 on r7xx */
+ if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+ CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
+
SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
CB_COLOR0_INFO__FORMAT_mask);
SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index fddac2f9bd..ab6b617235 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -239,7 +239,7 @@ static void r600_init_vtbl(radeonContextPtr radeon)
radeon->vtbl.emit_query_finish = r600_emit_query_finish;
radeon->vtbl.check_blit = r600_check_blit;
radeon->vtbl.blit = r600_blit;
- radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
+ radeon->vtbl.is_format_renderable = r600IsFormatRenderable;
}
static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 36a6e6e0a1..41419f8460 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -392,6 +392,54 @@ static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx,
return &t->base;
}
+unsigned r600IsFormatRenderable(gl_format mesa_format)
+{
+ switch (mesa_format) {
+ case MESA_FORMAT_RGBA8888:
+ case MESA_FORMAT_SIGNED_RGBA8888:
+ case MESA_FORMAT_RGBA8888_REV:
+ case MESA_FORMAT_SIGNED_RGBA8888_REV:
+ case MESA_FORMAT_ARGB8888:
+ case MESA_FORMAT_XRGB8888:
+ case MESA_FORMAT_ARGB8888_REV:
+ case MESA_FORMAT_XRGB8888_REV:
+ case MESA_FORMAT_RGB565:
+ case MESA_FORMAT_RGB565_REV:
+ case MESA_FORMAT_ARGB4444:
+ case MESA_FORMAT_ARGB4444_REV:
+ case MESA_FORMAT_ARGB1555:
+ case MESA_FORMAT_ARGB1555_REV:
+ case MESA_FORMAT_AL88:
+ case MESA_FORMAT_AL88_REV:
+ case MESA_FORMAT_RGB332:
+ case MESA_FORMAT_A8:
+ case MESA_FORMAT_I8:
+ case MESA_FORMAT_CI8:
+ case MESA_FORMAT_L8:
+ case MESA_FORMAT_RGBA_FLOAT32:
+ case MESA_FORMAT_RGBA_FLOAT16:
+ case MESA_FORMAT_ALPHA_FLOAT32:
+ case MESA_FORMAT_ALPHA_FLOAT16:
+ case MESA_FORMAT_LUMINANCE_FLOAT32:
+ case MESA_FORMAT_LUMINANCE_FLOAT16:
+ case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
+ case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
+ case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
+ case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
+ case MESA_FORMAT_X8_Z24:
+ case MESA_FORMAT_S8_Z24:
+ case MESA_FORMAT_Z24_S8:
+ case MESA_FORMAT_Z16:
+ case MESA_FORMAT_Z32:
+ case MESA_FORMAT_SRGBA8:
+ case MESA_FORMAT_SLA8:
+ case MESA_FORMAT_SL8:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
void r600InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
{
/* Note: we only plug in the functions we implement in the driver
diff --git a/src/mesa/drivers/dri/r600/r600_tex.h b/src/mesa/drivers/dri/r600/r600_tex.h
index 1d75a2ecd6..771affdfa6 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.h
+++ b/src/mesa/drivers/dri/r600/r600_tex.h
@@ -60,4 +60,6 @@ extern GLboolean r600ValidateBuffers(GLcontext * ctx);
extern void r600InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
+unsigned r600IsFormatRenderable(gl_format mesa_format);
+
#endif /* __r600_TEX_H__ */
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 63614b160c..cefda3ac4b 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -290,7 +290,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
static void r700SetRenderTarget(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
+ uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
@@ -312,22 +312,251 @@ static void r700SetRenderTarget(context_t *context, int id)
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- if(4 == rrb->cpp)
- {
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
- CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
- }
- else
- {
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
- CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
- COMP_SWAP_shift, COMP_SWAP_mask);
+
+ switch (rrb->base.Format) {
+ case MESA_FORMAT_RGBA8888:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_SIGNED_RGBA8888:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_SNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_RGBA8888_REV:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_SIGNED_RGBA8888_REV:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_SNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ARGB8888:
+ case MESA_FORMAT_XRGB8888:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_ALT;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ARGB8888_REV:
+ case MESA_FORMAT_XRGB8888_REV:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_RGB565:
+ format = COLOR_5_6_5;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_RGB565_REV:
+ format = COLOR_5_6_5;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ARGB4444:
+ format = COLOR_4_4_4_4;
+ comp_swap = SWAP_ALT;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ARGB4444_REV:
+ format = COLOR_4_4_4_4;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ARGB1555:
+ format = COLOR_1_5_5_5;
+ comp_swap = SWAP_ALT;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ARGB1555_REV:
+ format = COLOR_1_5_5_5;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_AL88:
+ format = COLOR_8_8;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_AL88_REV:
+ format = COLOR_8_8;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_RGB332:
+ format = COLOR_3_3_2;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_A8:
+ format = COLOR_8;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_I8:
+ case MESA_FORMAT_CI8:
+ format = COLOR_8;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_L8:
+ format = COLOR_8;
+ comp_swap = SWAP_ALT;
+ number_type = NUMBER_UNORM;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_RGBA_FLOAT32:
+ format = COLOR_32_32_32_32_FLOAT;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_FLOAT;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_RGBA_FLOAT16:
+ format = COLOR_16_16_16_16_FLOAT;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_FLOAT;
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ALPHA_FLOAT32:
+ format = COLOR_32_FLOAT;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_FLOAT;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_ALPHA_FLOAT16:
+ format = COLOR_16_FLOAT;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_FLOAT;
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_LUMINANCE_FLOAT32:
+ format = COLOR_32_FLOAT;
+ comp_swap = SWAP_ALT;
+ number_type = NUMBER_FLOAT;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_LUMINANCE_FLOAT16:
+ format = COLOR_16_FLOAT;
+ comp_swap = SWAP_ALT;
+ number_type = NUMBER_FLOAT;
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
+ format = COLOR_32_32_FLOAT;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_FLOAT;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
+ format = COLOR_16_16_FLOAT;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_FLOAT;
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
+ format = COLOR_32_FLOAT;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_FLOAT;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
+ format = COLOR_16_FLOAT;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_X8_Z24:
+ case MESA_FORMAT_S8_Z24:
+ format = COLOR_8_24;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
+ CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_Z24_S8:
+ format = COLOR_24_8;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
+ CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_Z16:
+ format = COLOR_16;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
+ CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_Z32:
+ format = COLOR_32;
+ comp_swap = SWAP_STD;
+ number_type = NUMBER_UNORM;
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
+ CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_SRGBA8:
+ format = COLOR_8_8_8_8;
+ comp_swap = SWAP_STD_REV;
+ number_type = NUMBER_SRGB;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_SLA8:
+ format = COLOR_8_8;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_SRGB;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ case MESA_FORMAT_SL8:
+ format = COLOR_8;
+ comp_swap = SWAP_ALT_REV;
+ number_type = NUMBER_SRGB;
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ break;
+ default:
+ _mesa_problem(context->radeon.glCtx, "unexpected format in r700SetRenderTarget()");
+ break;
}
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+
+ /* must be 0 on r7xx */
+ if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+ CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
+
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, format,
+ CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, comp_swap,
+ COMP_SWAP_shift, COMP_SWAP_mask);
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, number_type,
+ NUMBER_TYPE_shift, NUMBER_TYPE_mask);
SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
r700->render_target[id].enabled = GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
index 04ce12493e..ab6d02e56b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c
+++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
@@ -31,6 +31,8 @@
#include "main/imports.h"
#include "main/simple_list.h"
+#include <inttypes.h>
+
static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
@@ -65,7 +67,7 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
}
radeon_print(RADEON_STATE, RADEON_TRACE,
- "%d start: %llx, end: %llx %lld\n", i, start, end, end - start);
+ "%d start: %" PRIu64 ", end: %" PRIu64 " %" PRIu64 "\n", i, start, end, end - start);
}
} else {
for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-06 10:35:28 +0000