diff options
Diffstat (limited to 'src/mesa/drivers/dri')
83 files changed, 9519 insertions, 2153 deletions
diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index a581c6663f..f07c3da4bb 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -635,6 +635,7 @@ dri2CreateNewContextForAPI(__DRIscreen *screen, int api, __DRIcontext *shared, void *data) { __DRIcontext *context; + const __GLcontextModes *modes = (config != NULL) ? &config->modes : NULL; void *shareCtx = (shared != NULL) ? shared->driverPrivate : NULL; gl_api mesa_api; @@ -651,6 +652,8 @@ dri2CreateNewContextForAPI(__DRIscreen *screen, int api, case __DRI_API_GLES2: mesa_api = API_OPENGLES2; break; + default: + return NULL; } context = malloc(sizeof *context); @@ -661,7 +664,7 @@ dri2CreateNewContextForAPI(__DRIscreen *screen, int api, context->driDrawablePriv = NULL; context->loaderPrivate = data; - if (!(*screen->DriverAPI.CreateContext)(api, &config->modes, + if (!(*screen->DriverAPI.CreateContext)(mesa_api, modes, context, shareCtx) ) { free(context); return NULL; diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index d8715cf026..450e66e0d3 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -174,7 +174,12 @@ i915CreateContext(int api, ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; - ctx->Shader.EmitNoIfs = GL_TRUE; + /* FINISHME: Are there other options that should be enabled for software + * FINISHME: vertex shaders? + */ + ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitCondCodes = GL_TRUE; + ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoIfs = GL_TRUE; + ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoNoise = GL_TRUE; ctx->Const.MaxDrawBuffers = 1; diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c index 4a2e6209d0..31988f3d81 100644 --- a/src/mesa/drivers/dri/i915/i915_fragprog.c +++ b/src/mesa/drivers/dri/i915/i915_fragprog.c @@ -680,21 +680,6 @@ upload_program(struct i915_fragment_program *p) EMIT_2ARG_ARITH(A0_MUL); break; - case OPCODE_NOISE1: - case OPCODE_NOISE2: - case OPCODE_NOISE3: - case OPCODE_NOISE4: - /* Don't implement noise because we just don't have the instructions - * to spare. We aren't the first vendor to do so. - */ - i915_program_error(p, "Stubbed-out noise functions"); - i915_emit_arith(p, - A0_MOV, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(tmp, ZERO, ZERO, ZERO, ZERO), 0, 0); - break; - case OPCODE_POW: src0 = src_vector(p, &inst->SrcReg[0], program); src1 = src_vector(p, &inst->SrcReg[1], program); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index d2b20165f9..de78400d42 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -66,6 +66,7 @@ GLboolean brwCreateContext( int api, struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context); struct intel_context *intel = &brw->intel; GLcontext *ctx = &intel->ctx; + unsigned i; if (!brw) { printf("%s: failed to alloc context\n", __FUNCTION__); @@ -110,8 +111,12 @@ GLboolean brwCreateContext( int api, ctx->Const.MaxPointSizeAA = 255.0; /* We want the GLSL compiler to emit code that uses condition codes */ - ctx->Shader.EmitCondCodes = GL_TRUE; - ctx->Shader.EmitNVTempInitialization = GL_TRUE; + for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) { + ctx->ShaderCompilerOptions[i].EmitCondCodes = GL_TRUE; + ctx->ShaderCompilerOptions[i].EmitNVTempInitialization = GL_TRUE; + ctx->ShaderCompilerOptions[i].EmitNoNoise = GL_TRUE; + ctx->ShaderCompilerOptions[i].EmitNoMainReturn = GL_TRUE; + } ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024); ctx->Const.VertexProgram.MaxAluInstructions = 0; diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 0906150613..ddd3a94eb0 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -103,12 +103,92 @@ static void brw_set_dest( struct brw_instruction *insn, guess_execution_size(insn, dest); } +extern int reg_type_size[]; + +static void +validate_reg(struct brw_instruction *insn, struct brw_reg reg) +{ + int hstride_for_reg[] = {0, 1, 2, 4}; + int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256}; + int width_for_reg[] = {1, 2, 4, 8, 16}; + int execsize_for_reg[] = {1, 2, 4, 8, 16}; + int width, hstride, vstride, execsize; + + if (reg.file == BRW_IMMEDIATE_VALUE) { + /* 3.3.6: Region Parameters. Restriction: Immediate vectors + * mean the destination has to be 128-bit aligned and the + * destination horiz stride has to be a word. + */ + if (reg.type == BRW_REGISTER_TYPE_V) { + assert(hstride_for_reg[insn->bits1.da1.dest_horiz_stride] * + reg_type_size[insn->bits1.da1.dest_reg_type] == 2); + } + + return; + } + + if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && + reg.file == BRW_ARF_NULL) + return; + + assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg)); + hstride = hstride_for_reg[reg.hstride]; + + if (reg.vstride == 0xf) { + vstride = -1; + } else { + assert(reg.vstride >= 0 && reg.vstride < Elements(vstride_for_reg)); + vstride = vstride_for_reg[reg.vstride]; + } + + assert(reg.width >= 0 && reg.width < Elements(width_for_reg)); + width = width_for_reg[reg.width]; + + assert(insn->header.execution_size >= 0 && + insn->header.execution_size < Elements(execsize_for_reg)); + execsize = execsize_for_reg[insn->header.execution_size]; + + /* Restrictions from 3.3.10: Register Region Restrictions. */ + /* 3. */ + assert(execsize >= width); + + /* 4. */ + if (execsize == width && hstride != 0) { + assert(vstride == -1 || vstride == width * hstride); + } + + /* 5. */ + if (execsize == width && hstride == 0) { + /* no restriction on vstride. */ + } + + /* 6. */ + if (width == 1) { + assert(hstride == 0); + } + + /* 7. */ + if (execsize == 1 && width == 1) { + assert(hstride == 0); + assert(vstride == 0); + } + + /* 8. */ + if (vstride == 0 && hstride == 0) { + assert(width == 1); + } + + /* 10. Check destination issues. */ +} + static void brw_set_src0( struct brw_instruction *insn, struct brw_reg reg ) { if (reg.type != BRW_ARCHITECTURE_REGISTER_FILE) assert(reg.nr < 128); + validate_reg(insn, reg); + insn->bits1.da1.src0_reg_file = reg.file; insn->bits1.da1.src0_reg_type = reg.type; insn->bits2.da1.src0_abs = reg.abs; @@ -184,6 +264,8 @@ void brw_set_src1( struct brw_instruction *insn, assert(reg.nr < 128); + validate_reg(insn, reg); + insn->bits1.da1.src1_reg_file = reg.file; insn->bits1.da1.src1_reg_type = reg.type; insn->bits3.da1.src1_abs = reg.abs; @@ -579,8 +661,6 @@ ALU2(SHL) ALU2(RSR) ALU2(RSL) ALU2(ASR) -ALU2(ADD) -ALU2(MUL) ALU1(FRC) ALU1(RNDD) ALU1(RNDZ) @@ -594,6 +674,63 @@ ALU2(DP2) ALU2(LINE) ALU2(PLN) +struct brw_instruction *brw_ADD(struct brw_compile *p, + struct brw_reg dest, + struct brw_reg src0, + struct brw_reg src1) +{ + /* 6.2.2: add */ + if (src0.type == BRW_REGISTER_TYPE_F || + (src0.file == BRW_IMMEDIATE_VALUE && + src0.type == BRW_REGISTER_TYPE_VF)) { + assert(src1.type != BRW_REGISTER_TYPE_UD); + assert(src1.type != BRW_REGISTER_TYPE_D); + } + + if (src1.type == BRW_REGISTER_TYPE_F || + (src1.file == BRW_IMMEDIATE_VALUE && + src1.type == BRW_REGISTER_TYPE_VF)) { + assert(src0.type != BRW_REGISTER_TYPE_UD); + assert(src0.type != BRW_REGISTER_TYPE_D); + } + + return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1); +} + +struct brw_instruction *brw_MUL(struct brw_compile *p, + struct brw_reg dest, + struct brw_reg src0, + struct brw_reg src1) +{ + /* 6.32.38: mul */ + if (src0.type == BRW_REGISTER_TYPE_D || + src0.type == BRW_REGISTER_TYPE_UD || + src1.type == BRW_REGISTER_TYPE_D || + src1.type == BRW_REGISTER_TYPE_UD) { + assert(dest.type != BRW_REGISTER_TYPE_F); + } + + if (src0.type == BRW_REGISTER_TYPE_F || + (src0.file == BRW_IMMEDIATE_VALUE && + src0.type == BRW_REGISTER_TYPE_VF)) { + assert(src1.type != BRW_REGISTER_TYPE_UD); + assert(src1.type != BRW_REGISTER_TYPE_D); + } + + if (src1.type == BRW_REGISTER_TYPE_F || + (src1.file == BRW_IMMEDIATE_VALUE && + src1.type == BRW_REGISTER_TYPE_VF)) { + assert(src0.type != BRW_REGISTER_TYPE_UD); + assert(src0.type != BRW_REGISTER_TYPE_D); + } + + assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE || + src0.nr != BRW_ARF_ACCUMULATOR); + assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE || + src1.nr != BRW_ARF_ACCUMULATOR); + + return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1); +} void brw_NOP(struct brw_compile *p) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 34c5d5262f..cf5c52119a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -141,7 +141,7 @@ brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog) do { progress = false; - progress = do_common_optimization(shader->ir, true) || progress; + progress = do_common_optimization(shader->ir, true, 32) || progress; } while (progress); validate_ir_tree(shader->ir); @@ -202,63 +202,56 @@ public: return node; } - /** Generic unset register constructor. */ - fs_reg() + void init() { - this->file = BAD_FILE; this->reg = 0; this->reg_offset = 0; - this->hw_reg = -1; this->negate = 0; this->abs = 0; + this->hw_reg = -1; + } + + /** Generic unset register constructor. */ + fs_reg() + { + init(); + this->file = BAD_FILE; } /** Immediate value constructor. */ fs_reg(float f) { + init(); this->file = IMM; - this->reg = 0; - this->hw_reg = 0; this->type = BRW_REGISTER_TYPE_F; this->imm.f = f; - this->negate = 0; - this->abs = 0; } /** Immediate value constructor. */ fs_reg(int32_t i) { + init(); this->file = IMM; - this->reg = 0; - this->hw_reg = 0; this->type = BRW_REGISTER_TYPE_D; this->imm.i = i; - this->negate = 0; - this->abs = 0; } /** Immediate value constructor. */ fs_reg(uint32_t u) { + init(); this->file = IMM; - this->reg = 0; - this->hw_reg = 0; this->type = BRW_REGISTER_TYPE_UD; this->imm.u = u; - this->negate = 0; - this->abs = 0; } /** Fixed brw_reg Immediate value constructor. */ fs_reg(struct brw_reg fixed_hw_reg) { + init(); this->file = FIXED_HW_REG; this->fixed_hw_reg = fixed_hw_reg; - this->reg = 0; - this->hw_reg = 0; this->type = fixed_hw_reg.type; - this->negate = 0; - this->abs = 0; } fs_reg(enum register_file file, int hw_reg); @@ -482,25 +475,21 @@ public: /** Fixed HW reg constructor. */ fs_reg::fs_reg(enum register_file file, int hw_reg) { + init(); this->file = file; - this->reg = 0; - this->reg_offset = 0; this->hw_reg = hw_reg; this->type = BRW_REGISTER_TYPE_F; - this->negate = 0; - this->abs = 0; } /** Automatic reg constructor. */ fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) { + init(); + this->file = GRF; this->reg = v->next_abstract_grf; this->reg_offset = 0; v->next_abstract_grf += type_size(type); - this->hw_reg = -1; - this->negate = 0; - this->abs = 0; switch (type->base_type) { case GLSL_TYPE_FLOAT: @@ -764,6 +753,10 @@ fs_visitor::visit(ir_expression *ir) assert(!"not reached: should be handled by brw_channel_expressions"); break; + case ir_unop_noise: + assert(!"not reached: should be handled by lower_noise"); + break; + case ir_unop_sqrt: emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0])); break; @@ -778,7 +771,7 @@ fs_visitor::visit(ir_expression *ir) emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); break; case ir_unop_f2i: - emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0])); + emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); break; case ir_unop_f2b: case ir_unop_i2b: @@ -1222,6 +1215,8 @@ fs_visitor::emit_interpolation() this->current_annotation = "compute pixel centers"; this->pixel_x = fs_reg(this, glsl_type::uint_type); this->pixel_y = fs_reg(this, glsl_type::uint_type); + this->pixel_x.type = BRW_REGISTER_TYPE_UW; + this->pixel_y.type = BRW_REGISTER_TYPE_UW; emit(fs_inst(BRW_OPCODE_ADD, this->pixel_x, fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), @@ -1525,6 +1520,14 @@ fs_visitor::assign_curb_setup() c->prog_data.first_curbe_grf = c->key.nr_payload_regs; c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8; + if (intel->gen == 5 && (c->prog_data.first_curbe_grf + + c->prog_data.curb_read_length) & 1) { + /* Align the start of the interpolation coefficients so that we can use + * the PLN instruction. + */ + c->prog_data.first_curbe_grf++; + } + /* Map the offsets in the UNIFORM file to fixed HW regs. */ foreach_iter(exec_list_iterator, iter, this->instructions) { fs_inst *inst = (fs_inst *)iter.get(); @@ -1882,9 +1885,6 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) ir->accept(&v); } - if (v.fail) - return GL_FALSE; - v.emit_fb_writes(); v.assign_curb_setup(); v.assign_urb_setup(); @@ -1893,6 +1893,11 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) v.generate_code(); + assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */ + + if (v.fail) + return GL_FALSE; + if (INTEL_DEBUG & DEBUG_WM) { const char *last_annotation_string = NULL; ir_instruction *last_annotation_ir = NULL; diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp index d8d58a9467..478614090a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp @@ -356,6 +356,9 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir) assign(ir, 0, last); break; } + case ir_unop_noise: + assert(!"noise should have been broken down to function call"); + break; } ir->remove(); diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index bc152204a4..3e52be5d4b 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -132,6 +132,7 @@ static GLboolean brwProgramStringNotify( GLcontext *ctx, struct brw_fragment_program *newFP = brw_fragment_program(fprog); const struct brw_fragment_program *curFP = brw_fragment_program_const(brw->fragment_program); + struct gl_shader_program *shader_program; if (fprog->FogOption) { _mesa_append_fog_code(ctx, fprog); @@ -142,6 +143,21 @@ static GLboolean brwProgramStringNotify( GLcontext *ctx, brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; newFP->id = brw->program_id++; newFP->isGLSL = brw_wm_is_glsl(fprog); + + /* Don't reject fragment shaders for their Mesa IR state when we're + * using the new FS backend. + */ + shader_program = _mesa_lookup_shader_program(ctx, prog->Id); + if (shader_program) { + for (i = 0; i < shader_program->_NumLinkedShaders; i++) { + struct brw_shader *shader; + + shader = (struct brw_shader *)shader_program->_LinkedShaders[i]; + if (shader->base.Type == GL_FRAGMENT_SHADER && shader->ir) { + return GL_TRUE; + } + } + } } else if (target == GL_VERTEX_PROGRAM_ARB) { struct gl_vertex_program *vprog = (struct gl_vertex_program *) prog; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 1d88c6b5a4..ad0d00b87c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -954,7 +954,7 @@ get_reladdr_constant(struct brw_vs_compile *c, struct brw_compile *p = &c->func; struct brw_reg const_reg = c->current_const[argIndex].reg; struct brw_reg addrReg = c->regs[PROGRAM_ADDRESS][0]; - struct brw_reg byte_addr_reg = get_tmp(c); + struct brw_reg byte_addr_reg = retype(get_tmp(c), BRW_REGISTER_TYPE_D); assert(argIndex < 3); @@ -1069,6 +1069,12 @@ move_to_reladdr_dst(struct brw_vs_compile *c, struct brw_reg indirect = brw_vec4_indirect(0,0); struct brw_reg acc = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UW); + /* Because destination register indirect addressing can only use + * one index, we'll write each vertex's vec4 value separately. + */ + val.width = BRW_WIDTH_4; + val.vstride = BRW_VERTICAL_STRIDE_4; + brw_push_insn_state(p); brw_set_access_mode(p, BRW_ALIGN_1); diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index c1083c5942..7d6724dc1c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -6,10 +6,6 @@ #include "brw_eu.h" #include "brw_wm.h" -enum _subroutine { - SUB_NOISE1, SUB_NOISE2, SUB_NOISE3, SUB_NOISE4 -}; - static struct brw_reg get_dst_reg(struct brw_wm_compile *c, const struct prog_instruction *inst, GLuint component); @@ -35,10 +31,6 @@ GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp) case OPCODE_CAL: case OPCODE_BRK: case OPCODE_RET: - case OPCODE_NOISE1: - case OPCODE_NOISE2: - case OPCODE_NOISE3: - case OPCODE_NOISE4: case OPCODE_BGNLOOP: return GL_TRUE; default: @@ -167,11 +159,6 @@ static int mark_tmps(struct brw_wm_compile *c) return c->tmp_index; } -static struct brw_reg lookup_tmp( struct brw_wm_compile *c, int index ) -{ - return brw_vec8_grf( c->tmp_regs[ index ], 0 ); -} - static void release_tmps(struct brw_wm_compile *c, int mark) { c->tmp_index = mark; @@ -614,70 +601,6 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, } } -/** - * Subroutines are minimal support for resusable instruction sequences. - * They are implemented as simply as possible to minimise overhead: there - * is no explicit support for communication between the caller and callee - * other than saving the return address in a temporary register, nor is - * there any automatic local storage. This implies that great care is - * required before attempting reentrancy or any kind of nested - * subroutine invocations. - */ -static void invoke_subroutine( struct brw_wm_compile *c, - enum _subroutine subroutine, - void (*emit)( struct brw_wm_compile * ) ) -{ - struct brw_compile *p = &c->func; - - assert( subroutine < BRW_WM_MAX_SUBROUTINE ); - - if( c->subroutines[ subroutine ] ) { - /* subroutine previously emitted: reuse existing instructions */ - - int mark = mark_tmps( c ); - struct brw_reg return_address = retype( alloc_tmp( c ), - BRW_REGISTER_TYPE_UD ); - int here = p->nr_insn; - - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_ADD( p, return_address, brw_ip_reg(), brw_imm_ud( 2 << 4 ) ); - - brw_ADD( p, brw_ip_reg(), brw_ip_reg(), - brw_imm_d( ( c->subroutines[ subroutine ] - - here - 1 ) << 4 ) ); - brw_pop_insn_state(p); - - release_tmps( c, mark ); - } else { - /* previously unused subroutine: emit, and mark for later reuse */ - - int mark = mark_tmps( c ); - struct brw_reg return_address = retype( alloc_tmp( c ), - BRW_REGISTER_TYPE_UD ); - struct brw_instruction *calc; - int base = p->nr_insn; - - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - calc = brw_ADD( p, return_address, brw_ip_reg(), brw_imm_ud( 0 ) ); - brw_pop_insn_state(p); - - c->subroutines[ subroutine ] = p->nr_insn; - - emit( c ); - - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_MOV( p, brw_ip_reg(), return_address ); - brw_pop_insn_state(p); - - brw_set_src1( calc, brw_imm_ud( ( p->nr_insn - base ) << 4 ) ); - - release_tmps( c, mark ); - } -} - static void emit_arl(struct brw_wm_compile *c, const struct prog_instruction *inst) { @@ -728,1037 +651,6 @@ static INLINE struct brw_reg odd_bytes( struct brw_reg reg ) 0, 16, 2 ); } -/* One-, two- and three-dimensional Perlin noise, similar to the description - in _Improving Noise_, Ken Perlin, Computer Graphics vol. 35 no. 3. */ -static void noise1_sub( struct brw_wm_compile *c ) { - - struct brw_compile *p = &c->func; - struct brw_reg param, - x0, x1, /* gradients at each end */ - t, tmp[ 2 ], /* float temporaries */ - itmp[ 5 ]; /* unsigned integer temporaries (aliases of floats above) */ - int i; - int mark = mark_tmps( c ); - - x0 = alloc_tmp( c ); - x1 = alloc_tmp( c ); - t = alloc_tmp( c ); - tmp[ 0 ] = alloc_tmp( c ); - tmp[ 1 ] = alloc_tmp( c ); - itmp[ 0 ] = retype( tmp[ 0 ], BRW_REGISTER_TYPE_UD ); - itmp[ 1 ] = retype( tmp[ 1 ], BRW_REGISTER_TYPE_UD ); - itmp[ 2 ] = retype( x0, BRW_REGISTER_TYPE_UD ); - itmp[ 3 ] = retype( x1, BRW_REGISTER_TYPE_UD ); - itmp[ 4 ] = retype( t, BRW_REGISTER_TYPE_UD ); - - param = lookup_tmp( c, mark - 2 ); - - brw_set_access_mode( p, BRW_ALIGN_1 ); - - brw_MOV( p, itmp[ 2 ], brw_imm_ud( 0xBA97 ) ); /* constant used later */ - - /* Arrange the two end coordinates into scalars (itmp0/itmp1) to - be hashed. Also compute the remainder (offset within the unit - length), interleaved to reduce register dependency penalties. */ - brw_RNDD( p, retype( itmp[ 0 ], BRW_REGISTER_TYPE_D ), param ); - brw_FRC( p, param, param ); - brw_ADD( p, itmp[ 1 ], itmp[ 0 ], brw_imm_ud( 1 ) ); - brw_MOV( p, itmp[ 3 ], brw_imm_ud( 0x79D9 ) ); /* constant used later */ - brw_MOV( p, itmp[ 4 ], brw_imm_ud( 0xD5B1 ) ); /* constant used later */ - - /* We're now ready to perform the hashing. The two hashes are - interleaved for performance. The hash function used is - designed to rapidly achieve avalanche and require only 32x16 - bit multiplication, and 16-bit swizzles (which we get for - free). We can't use immediate operands in the multiplies, - because immediates are permitted only in src1 and the 16-bit - factor is permitted only in src0. */ - for( i = 0; i < 2; i++ ) - brw_MUL( p, itmp[ i ], itmp[ 2 ], itmp[ i ] ); - for( i = 0; i < 2; i++ ) - brw_XOR( p, low_words( itmp[ i ] ), low_words( itmp[ i ] ), - high_words( itmp[ i ] ) ); - for( i = 0; i < 2; i++ ) - brw_MUL( p, itmp[ i ], itmp[ 3 ], itmp[ i ] ); - for( i = 0; i < 2; i++ ) - brw_XOR( p, low_words( itmp[ i ] ), low_words( itmp[ i ] ), - high_words( itmp[ i ] ) ); - for( i = 0; i < 2; i++ ) - brw_MUL( p, itmp[ i ], itmp[ 4 ], itmp[ i ] ); - for( i = 0; i < 2; i++ ) - brw_XOR( p, low_words( itmp[ i ] ), low_words( itmp[ i ] ), - high_words( itmp[ i ] ) ); - - /* Now we want to initialise the two gradients based on the - hashes. Format conversion from signed integer to float leaves - everything scaled too high by a factor of pow( 2, 31 ), but - we correct for that right at the end. */ - brw_ADD( p, t, param, brw_imm_f( -1.0 ) ); - brw_MOV( p, x0, retype( tmp[ 0 ], BRW_REGISTER_TYPE_D ) ); - brw_MOV( p, x1, retype( tmp[ 1 ], BRW_REGISTER_TYPE_D ) ); - - brw_MUL( p, x0, x0, param ); - brw_MUL( p, x1, x1, t ); - - /* We interpolate between the gradients using the polynomial - 6t^5 - 15t^4 + 10t^3 (Perlin). */ - brw_MUL( p, tmp[ 0 ], param, brw_imm_f( 6.0 ) ); - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], brw_imm_f( -15.0 ) ); - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param ); - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], brw_imm_f( 10.0 ) ); - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param ); - brw_ADD( p, x1, x1, negate( x0 ) ); /* unrelated work to fill the - pipeline */ - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param ); - brw_MUL( p, param, tmp[ 0 ], param ); - brw_MUL( p, x1, x1, param ); - brw_ADD( p, x0, x0, x1 ); - /* scale by pow( 2, -30 ), to compensate for the format conversion - above and an extra factor of 2 so that a single gradient covers - the [-1,1] range */ - brw_MUL( p, param, x0, brw_imm_f( 0.000000000931322574615478515625 ) ); - - release_tmps( c, mark ); -} - -static void emit_noise1( struct brw_wm_compile *c, - const struct prog_instruction *inst ) -{ - struct brw_compile *p = &c->func; - struct brw_reg src, param, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - int mark = mark_tmps( c ); - - assert( mark == 0 ); - - src = get_src_reg( c, inst, 0, 0 ); - - param = alloc_tmp( c ); - - brw_MOV( p, param, src ); - - invoke_subroutine( c, SUB_NOISE1, noise1_sub ); - - /* Fill in the result: */ - brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); - for (i = 0 ; i < 4; i++) { - if (mask & (1<<i)) { - dst = get_dst_reg(c, inst, i); - brw_MOV( p, dst, param ); - } - } - if( inst->SaturateMode == SATURATE_ZERO_ONE ) - brw_set_saturate( p, 0 ); - - release_tmps( c, mark ); -} - -static void noise2_sub( struct brw_wm_compile *c ) { - - struct brw_compile *p = &c->func; - struct brw_reg param0, param1, - x0y0, x0y1, x1y0, x1y1, /* gradients at each corner */ - t, tmp[ 4 ], /* float temporaries */ - itmp[ 7 ]; /* unsigned integer temporaries (aliases of floats above) */ - int i; - int mark = mark_tmps( c ); - - x0y0 = alloc_tmp( c ); - x0y1 = alloc_tmp( c ); - x1y0 = alloc_tmp( c ); - x1y1 = alloc_tmp( c ); - t = alloc_tmp( c ); - for( i = 0; i < 4; i++ ) { - tmp[ i ] = alloc_tmp( c ); - itmp[ i ] = retype( tmp[ i ], BRW_REGISTER_TYPE_UD ); - } - itmp[ 4 ] = retype( x0y0, BRW_REGISTER_TYPE_UD ); - itmp[ 5 ] = retype( x0y1, BRW_REGISTER_TYPE_UD ); - itmp[ 6 ] = retype( x1y0, BRW_REGISTER_TYPE_UD ); - - param0 = lookup_tmp( c, mark - 3 ); - param1 = lookup_tmp( c, mark - 2 ); - - brw_set_access_mode( p, BRW_ALIGN_1 ); - - /* Arrange the four corner coordinates into scalars (itmp0..itmp3) to - be hashed. Also compute the remainders (offsets within the unit - square), interleaved to reduce register dependency penalties. */ - brw_RNDD( p, retype( itmp[ 0 ], BRW_REGISTER_TYPE_D ), param0 ); - brw_RNDD( p, retype( itmp[ 1 ], BRW_REGISTER_TYPE_D ), param1 ); - brw_FRC( p, param0, param0 ); - brw_FRC( p, param1, param1 ); - brw_MOV( p, itmp[ 4 ], brw_imm_ud( 0xBA97 ) ); /* constant used later */ - brw_ADD( p, high_words( itmp[ 0 ] ), high_words( itmp[ 0 ] ), - low_words( itmp[ 1 ] ) ); - brw_MOV( p, itmp[ 5 ], brw_imm_ud( 0x79D9 ) ); /* constant used later */ - brw_MOV( p, itmp[ 6 ], brw_imm_ud( 0xD5B1 ) ); /* constant used later */ - brw_ADD( p, itmp[ 1 ], itmp[ 0 ], brw_imm_ud( 0x10000 ) ); - brw_ADD( p, itmp[ 2 ], itmp[ 0 ], brw_imm_ud( 0x1 ) ); - brw_ADD( p, itmp[ 3 ], itmp[ 0 ], brw_imm_ud( 0x10001 ) ); - - /* We're now ready to perform the hashing. The four hashes are - interleaved for performance. The hash function used is - designed to rapidly achieve avalanche and require only 32x16 - bit multiplication, and 16-bit swizzles (which we get for - free). We can't use immediate operands in the multiplies, - because immediates are permitted only in src1 and the 16-bit - factor is permitted only in src0. */ - for( i = 0; i < 4; i++ ) - brw_MUL( p, itmp[ i ], itmp[ 4 ], itmp[ i ] ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, low_words( itmp[ i ] ), low_words( itmp[ i ] ), - high_words( itmp[ i ] ) ); - for( i = 0; i < 4; i++ ) - brw_MUL( p, itmp[ i ], itmp[ 5 ], itmp[ i ] ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, low_words( itmp[ i ] ), low_words( itmp[ i ] ), - high_words( itmp[ i ] ) ); - for( i = 0; i < 4; i++ ) - brw_MUL( p, itmp[ i ], itmp[ 6 ], itmp[ i ] ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, low_words( itmp[ i ] ), low_words( itmp[ i ] ), - high_words( itmp[ i ] ) ); - - /* Now we want to initialise the four gradients based on the - hashes. Format conversion from signed integer to float leaves - everything scaled too high by a factor of pow( 2, 15 ), but - we correct for that right at the end. */ - brw_ADD( p, t, param0, brw_imm_f( -1.0 ) ); - brw_MOV( p, x0y0, low_words( tmp[ 0 ] ) ); - brw_MOV( p, x0y1, low_words( tmp[ 1 ] ) ); - brw_MOV( p, x1y0, low_words( tmp[ 2 ] ) ); - brw_MOV( p, x1y1, low_words( tmp[ 3 ] ) ); - - brw_MOV( p, tmp[ 0 ], high_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 1 ], high_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 2 ], high_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 3 ], high_words( tmp[ 3 ] ) ); - - brw_MUL( p, x1y0, x1y0, t ); - brw_MUL( p, x1y1, x1y1, t ); - brw_ADD( p, t, param1, brw_imm_f( -1.0 ) ); - brw_MUL( p, x0y0, x0y0, param0 ); - brw_MUL( p, x0y1, x0y1, param0 ); - - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param1 ); - brw_MUL( p, tmp[ 2 ], tmp[ 2 ], param1 ); - brw_MUL( p, tmp[ 1 ], tmp[ 1 ], t ); - brw_MUL( p, tmp[ 3 ], tmp[ 3 ], t ); - - brw_ADD( p, x0y0, x0y0, tmp[ 0 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 2 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 1 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 3 ] ); - - /* We interpolate between the gradients using the polynomial - 6t^5 - 15t^4 + 10t^3 (Perlin). */ - brw_MUL( p, tmp[ 0 ], param0, brw_imm_f( 6.0 ) ); - brw_MUL( p, tmp[ 1 ], param1, brw_imm_f( 6.0 ) ); - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], brw_imm_f( -15.0 ) ); - brw_ADD( p, tmp[ 1 ], tmp[ 1 ], brw_imm_f( -15.0 ) ); - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param0 ); - brw_MUL( p, tmp[ 1 ], tmp[ 1 ], param1 ); - brw_ADD( p, x0y1, x0y1, negate( x0y0 ) ); /* unrelated work to fill the - pipeline */ - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], brw_imm_f( 10.0 ) ); - brw_ADD( p, tmp[ 1 ], tmp[ 1 ], brw_imm_f( 10.0 ) ); - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param0 ); - brw_MUL( p, tmp[ 1 ], tmp[ 1 ], param1 ); - brw_ADD( p, x1y1, x1y1, negate( x1y0 ) ); /* unrelated work to fill the - pipeline */ - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], param0 ); - brw_MUL( p, tmp[ 1 ], tmp[ 1 ], param1 ); - brw_MUL( p, param0, tmp[ 0 ], param0 ); - brw_MUL( p, param1, tmp[ 1 ], param1 ); - - /* Here we interpolate in the y dimension... */ - brw_MUL( p, x0y1, x0y1, param1 ); - brw_MUL( p, x1y1, x1y1, param1 ); - brw_ADD( p, x0y0, x0y0, x0y1 ); - brw_ADD( p, x1y0, x1y0, x1y1 ); - - /* And now in x. There are horrible register dependencies here, - but we have nothing else to do. */ - brw_ADD( p, x1y0, x1y0, negate( x0y0 ) ); - brw_MUL( p, x1y0, x1y0, param0 ); - brw_ADD( p, x0y0, x0y0, x1y0 ); - - /* scale by pow( 2, -15 ), as described above */ - brw_MUL( p, param0, x0y0, brw_imm_f( 0.000030517578125 ) ); - - release_tmps( c, mark ); -} - -static void emit_noise2( struct brw_wm_compile *c, - const struct prog_instruction *inst ) -{ - struct brw_compile *p = &c->func; - struct brw_reg src0, src1, param0, param1, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - int mark = mark_tmps( c ); - - assert( mark == 0 ); - - src0 = get_src_reg( c, inst, 0, 0 ); - src1 = get_src_reg( c, inst, 0, 1 ); - - param0 = alloc_tmp( c ); - param1 = alloc_tmp( c ); - - brw_MOV( p, param0, src0 ); - brw_MOV( p, param1, src1 ); - - invoke_subroutine( c, SUB_NOISE2, noise2_sub ); - - /* Fill in the result: */ - brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); - for (i = 0 ; i < 4; i++) { - if (mask & (1<<i)) { - dst = get_dst_reg(c, inst, i); - brw_MOV( p, dst, param0 ); - } - } - if( inst->SaturateMode == SATURATE_ZERO_ONE ) - brw_set_saturate( p, 0 ); - - release_tmps( c, mark ); -} - -/** - * The three-dimensional case is much like the one- and two- versions above, - * but since the number of corners is rapidly growing we now pack 16 16-bit - * hashes into each register to extract more parallelism from the EUs. - */ -static void noise3_sub( struct brw_wm_compile *c ) { - - struct brw_compile *p = &c->func; - struct brw_reg param0, param1, param2, - x0y0, x0y1, x1y0, x1y1, /* gradients at four of the corners */ - xi, yi, zi, /* interpolation coefficients */ - t, tmp[ 8 ], /* float temporaries */ - itmp[ 8 ], /* unsigned integer temporaries (aliases of floats above) */ - wtmp[ 8 ]; /* 16-way unsigned word temporaries (aliases of above) */ - int i; - int mark = mark_tmps( c ); - - x0y0 = alloc_tmp( c ); - x0y1 = alloc_tmp( c ); - x1y0 = alloc_tmp( c ); - x1y1 = alloc_tmp( c ); - xi = alloc_tmp( c ); - yi = alloc_tmp( c ); - zi = alloc_tmp( c ); - t = alloc_tmp( c ); - for( i = 0; i < 8; i++ ) { - tmp[ i ] = alloc_tmp( c ); - itmp[ i ] = retype( tmp[ i ], BRW_REGISTER_TYPE_UD ); - wtmp[ i ] = brw_uw16_grf( tmp[ i ].nr, 0 ); - } - - param0 = lookup_tmp( c, mark - 4 ); - param1 = lookup_tmp( c, mark - 3 ); - param2 = lookup_tmp( c, mark - 2 ); - - brw_set_access_mode( p, BRW_ALIGN_1 ); - - /* Arrange the eight corner coordinates into scalars (itmp0..itmp3) to - be hashed. Also compute the remainders (offsets within the unit - cube), interleaved to reduce register dependency penalties. */ - brw_RNDD( p, retype( itmp[ 0 ], BRW_REGISTER_TYPE_D ), param0 ); - brw_RNDD( p, retype( itmp[ 1 ], BRW_REGISTER_TYPE_D ), param1 ); - brw_RNDD( p, retype( itmp[ 2 ], BRW_REGISTER_TYPE_D ), param2 ); - brw_FRC( p, param0, param0 ); - brw_FRC( p, param1, param1 ); - brw_FRC( p, param2, param2 ); - /* Since we now have only 16 bits of precision in the hash, we must - be more careful about thorough mixing to maintain entropy as we - squash the input vector into a small scalar. */ - brw_MUL( p, brw_null_reg(), low_words( itmp[ 0 ] ), brw_imm_uw( 0xBC8F ) ); - brw_MAC( p, brw_null_reg(), low_words( itmp[ 1 ] ), brw_imm_uw( 0xD0BD ) ); - brw_MAC( p, low_words( itmp[ 0 ] ), low_words( itmp[ 2 ] ), - brw_imm_uw( 0x9B93 ) ); - brw_ADD( p, high_words( itmp[ 0 ] ), low_words( itmp[ 0 ] ), - brw_imm_uw( 0xBC8F ) ); - - /* Temporarily disable the execution mask while we work with ExecSize=16 - channels (the mask is set for ExecSize=8 and is probably incorrect). - Although this might cause execution of unwanted channels, the code - writes only to temporary registers and has no side effects, so - disabling the mask is harmless. */ - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_ADD( p, wtmp[ 1 ], wtmp[ 0 ], brw_imm_uw( 0xD0BD ) ); - brw_ADD( p, wtmp[ 2 ], wtmp[ 0 ], brw_imm_uw( 0x9B93 ) ); - brw_ADD( p, wtmp[ 3 ], wtmp[ 1 ], brw_imm_uw( 0x9B93 ) ); - - /* We're now ready to perform the hashing. The eight hashes are - interleaved for performance. The hash function used is - designed to rapidly achieve avalanche and require only 16x16 - bit multiplication, and 8-bit swizzles (which we get for - free). */ - for( i = 0; i < 4; i++ ) - brw_MUL( p, wtmp[ i ], wtmp[ i ], brw_imm_uw( 0x28D9 ) ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, even_bytes( wtmp[ i ] ), even_bytes( wtmp[ i ] ), - odd_bytes( wtmp[ i ] ) ); - for( i = 0; i < 4; i++ ) - brw_MUL( p, wtmp[ i ], wtmp[ i ], brw_imm_uw( 0xC6D5 ) ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, even_bytes( wtmp[ i ] ), even_bytes( wtmp[ i ] ), - odd_bytes( wtmp[ i ] ) ); - brw_pop_insn_state( p ); - - /* Now we want to initialise the four rear gradients based on the - hashes. Format conversion from signed integer to float leaves - everything scaled too high by a factor of pow( 2, 15 ), but - we correct for that right at the end. */ - /* x component */ - brw_ADD( p, t, param0, brw_imm_f( -1.0 ) ); - brw_MOV( p, x0y0, low_words( tmp[ 0 ] ) ); - brw_MOV( p, x0y1, low_words( tmp[ 1 ] ) ); - brw_MOV( p, x1y0, high_words( tmp[ 0 ] ) ); - brw_MOV( p, x1y1, high_words( tmp[ 1 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 0 ], wtmp[ 0 ], brw_imm_uw( 5 ) ); - brw_SHL( p, wtmp[ 1 ], wtmp[ 1 ], brw_imm_uw( 5 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, x1y0, x1y0, t ); - brw_MUL( p, x1y1, x1y1, t ); - brw_ADD( p, t, param1, brw_imm_f( -1.0 ) ); - brw_MUL( p, x0y0, x0y0, param0 ); - brw_MUL( p, x0y1, x0y1, param0 ); - - /* y component */ - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 0 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 0 ], wtmp[ 0 ], brw_imm_uw( 5 ) ); - brw_SHL( p, wtmp[ 1 ], wtmp[ 1 ], brw_imm_uw( 5 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - brw_ADD( p, t, param0, brw_imm_f( -1.0 ) ); - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], param1 ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], param1 ); - - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - - /* z component */ - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 1 ] ) ); - - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], param2 ); - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], param2 ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], param2 ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], param2 ); - - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - - /* We interpolate between the gradients using the polynomial - 6t^5 - 15t^4 + 10t^3 (Perlin). */ - brw_MUL( p, xi, param0, brw_imm_f( 6.0 ) ); - brw_MUL( p, yi, param1, brw_imm_f( 6.0 ) ); - brw_MUL( p, zi, param2, brw_imm_f( 6.0 ) ); - brw_ADD( p, xi, xi, brw_imm_f( -15.0 ) ); - brw_ADD( p, yi, yi, brw_imm_f( -15.0 ) ); - brw_ADD( p, zi, zi, brw_imm_f( -15.0 ) ); - brw_MUL( p, xi, xi, param0 ); - brw_MUL( p, yi, yi, param1 ); - brw_MUL( p, zi, zi, param2 ); - brw_ADD( p, xi, xi, brw_imm_f( 10.0 ) ); - brw_ADD( p, yi, yi, brw_imm_f( 10.0 ) ); - brw_ADD( p, zi, zi, brw_imm_f( 10.0 ) ); - brw_ADD( p, x0y1, x0y1, negate( x0y0 ) ); /* unrelated work */ - brw_ADD( p, x1y1, x1y1, negate( x1y0 ) ); /* unrelated work */ - brw_MUL( p, xi, xi, param0 ); - brw_MUL( p, yi, yi, param1 ); - brw_MUL( p, zi, zi, param2 ); - brw_MUL( p, xi, xi, param0 ); - brw_MUL( p, yi, yi, param1 ); - brw_MUL( p, zi, zi, param2 ); - brw_MUL( p, xi, xi, param0 ); - brw_MUL( p, yi, yi, param1 ); - brw_MUL( p, zi, zi, param2 ); - - /* Here we interpolate in the y dimension... */ - brw_MUL( p, x0y1, x0y1, yi ); - brw_MUL( p, x1y1, x1y1, yi ); - brw_ADD( p, x0y0, x0y0, x0y1 ); - brw_ADD( p, x1y0, x1y0, x1y1 ); - - /* And now in x. Leave the result in tmp[ 0 ] (see below)... */ - brw_ADD( p, x1y0, x1y0, negate( x0y0 ) ); - brw_MUL( p, x1y0, x1y0, xi ); - brw_ADD( p, tmp[ 0 ], x0y0, x1y0 ); - - /* Now do the same thing for the front four gradients... */ - /* x component */ - brw_MOV( p, x0y0, low_words( tmp[ 2 ] ) ); - brw_MOV( p, x0y1, low_words( tmp[ 3 ] ) ); - brw_MOV( p, x1y0, high_words( tmp[ 2 ] ) ); - brw_MOV( p, x1y1, high_words( tmp[ 3 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 2 ], wtmp[ 2 ], brw_imm_uw( 5 ) ); - brw_SHL( p, wtmp[ 3 ], wtmp[ 3 ], brw_imm_uw( 5 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, x1y0, x1y0, t ); - brw_MUL( p, x1y1, x1y1, t ); - brw_ADD( p, t, param1, brw_imm_f( -1.0 ) ); - brw_MUL( p, x0y0, x0y0, param0 ); - brw_MUL( p, x0y1, x0y1, param0 ); - - /* y component */ - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 2 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 2 ], wtmp[ 2 ], brw_imm_uw( 5 ) ); - brw_SHL( p, wtmp[ 3 ], wtmp[ 3 ], brw_imm_uw( 5 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - brw_ADD( p, t, param2, brw_imm_f( -1.0 ) ); - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], param1 ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], param1 ); - - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - - /* z component */ - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 3 ] ) ); - - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], t ); - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - - /* The interpolation coefficients are still around from last time, so - again interpolate in the y dimension... */ - brw_ADD( p, x0y1, x0y1, negate( x0y0 ) ); - brw_ADD( p, x1y1, x1y1, negate( x1y0 ) ); - brw_MUL( p, x0y1, x0y1, yi ); - brw_MUL( p, x1y1, x1y1, yi ); - brw_ADD( p, x0y0, x0y0, x0y1 ); - brw_ADD( p, x1y0, x1y0, x1y1 ); - - /* And now in x. The rear face is in tmp[ 0 ] (see above), so this - time put the front face in tmp[ 1 ] and we're nearly there... */ - brw_ADD( p, x1y0, x1y0, negate( x0y0 ) ); - brw_MUL( p, x1y0, x1y0, xi ); - brw_ADD( p, tmp[ 1 ], x0y0, x1y0 ); - - /* The final interpolation, in the z dimension: */ - brw_ADD( p, tmp[ 1 ], tmp[ 1 ], negate( tmp[ 0 ] ) ); - brw_MUL( p, tmp[ 1 ], tmp[ 1 ], zi ); - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], tmp[ 1 ] ); - - /* scale by pow( 2, -15 ), as described above */ - brw_MUL( p, param0, tmp[ 0 ], brw_imm_f( 0.000030517578125 ) ); - - release_tmps( c, mark ); -} - -static void emit_noise3( struct brw_wm_compile *c, - const struct prog_instruction *inst ) -{ - struct brw_compile *p = &c->func; - struct brw_reg src0, src1, src2, param0, param1, param2, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - int mark = mark_tmps( c ); - - assert( mark == 0 ); - - src0 = get_src_reg( c, inst, 0, 0 ); - src1 = get_src_reg( c, inst, 0, 1 ); - src2 = get_src_reg( c, inst, 0, 2 ); - - param0 = alloc_tmp( c ); - param1 = alloc_tmp( c ); - param2 = alloc_tmp( c ); - - brw_MOV( p, param0, src0 ); - brw_MOV( p, param1, src1 ); - brw_MOV( p, param2, src2 ); - - invoke_subroutine( c, SUB_NOISE3, noise3_sub ); - - /* Fill in the result: */ - brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); - for (i = 0 ; i < 4; i++) { - if (mask & (1<<i)) { - dst = get_dst_reg(c, inst, i); - brw_MOV( p, dst, param0 ); - } - } - if( inst->SaturateMode == SATURATE_ZERO_ONE ) - brw_set_saturate( p, 0 ); - - release_tmps( c, mark ); -} - -/** - * For the four-dimensional case, the little micro-optimisation benefits - * we obtain by unrolling all the loops aren't worth the massive bloat it - * now causes. Instead, we loop twice around performing a similar operation - * to noise3, once for the w=0 cube and once for the w=1, with a bit more - * code to glue it all together. - */ -static void noise4_sub( struct brw_wm_compile *c ) -{ - struct brw_compile *p = &c->func; - struct brw_reg param[ 4 ], - x0y0, x0y1, x1y0, x1y1, /* gradients at four of the corners */ - w0, /* noise for the w=0 cube */ - floors[ 2 ], /* integer coordinates of base corner of hypercube */ - interp[ 4 ], /* interpolation coefficients */ - t, tmp[ 8 ], /* float temporaries */ - itmp[ 8 ], /* unsigned integer temporaries (aliases of floats above) */ - wtmp[ 8 ]; /* 16-way unsigned word temporaries (aliases of above) */ - int i, j; - int mark = mark_tmps( c ); - GLuint loop, origin; - - x0y0 = alloc_tmp( c ); - x0y1 = alloc_tmp( c ); - x1y0 = alloc_tmp( c ); - x1y1 = alloc_tmp( c ); - t = alloc_tmp( c ); - w0 = alloc_tmp( c ); - floors[ 0 ] = retype( alloc_tmp( c ), BRW_REGISTER_TYPE_UD ); - floors[ 1 ] = retype( alloc_tmp( c ), BRW_REGISTER_TYPE_UD ); - - for( i = 0; i < 4; i++ ) { - param[ i ] = lookup_tmp( c, mark - 5 + i ); - interp[ i ] = alloc_tmp( c ); - } - - for( i = 0; i < 8; i++ ) { - tmp[ i ] = alloc_tmp( c ); - itmp[ i ] = retype( tmp[ i ], BRW_REGISTER_TYPE_UD ); - wtmp[ i ] = brw_uw16_grf( tmp[ i ].nr, 0 ); - } - - brw_set_access_mode( p, BRW_ALIGN_1 ); - - /* We only want 16 bits of precision from the integral part of each - co-ordinate, but unfortunately the RNDD semantics would saturate - at 16 bits if we performed the operation directly to a 16-bit - destination. Therefore, we round to 32-bit temporaries where - appropriate, and then store only the lower 16 bits. */ - brw_RNDD( p, retype( floors[ 0 ], BRW_REGISTER_TYPE_D ), param[ 0 ] ); - brw_RNDD( p, retype( itmp[ 0 ], BRW_REGISTER_TYPE_D ), param[ 1 ] ); - brw_RNDD( p, retype( floors[ 1 ], BRW_REGISTER_TYPE_D ), param[ 2 ] ); - brw_RNDD( p, retype( itmp[ 1 ], BRW_REGISTER_TYPE_D ), param[ 3 ] ); - brw_MOV( p, high_words( floors[ 0 ] ), low_words( itmp[ 0 ] ) ); - brw_MOV( p, high_words( floors[ 1 ] ), low_words( itmp[ 1 ] ) ); - - /* Modify the flag register here, because the side effect is useful - later (see below). We know for certain that all flags will be - cleared, since the FRC instruction cannot possibly generate - negative results. Even for exceptional inputs (infinities, denormals, - NaNs), the architecture guarantees that the L conditional is false. */ - brw_set_conditionalmod( p, BRW_CONDITIONAL_L ); - brw_FRC( p, param[ 0 ], param[ 0 ] ); - brw_set_predicate_control( p, BRW_PREDICATE_NONE ); - for( i = 1; i < 4; i++ ) - brw_FRC( p, param[ i ], param[ i ] ); - - /* Calculate the interpolation coefficients (6t^5 - 15t^4 + 10t^3) first - of all. */ - for( i = 0; i < 4; i++ ) - brw_MUL( p, interp[ i ], param[ i ], brw_imm_f( 6.0 ) ); - for( i = 0; i < 4; i++ ) - brw_ADD( p, interp[ i ], interp[ i ], brw_imm_f( -15.0 ) ); - for( i = 0; i < 4; i++ ) - brw_MUL( p, interp[ i ], interp[ i ], param[ i ] ); - for( i = 0; i < 4; i++ ) - brw_ADD( p, interp[ i ], interp[ i ], brw_imm_f( 10.0 ) ); - for( j = 0; j < 3; j++ ) - for( i = 0; i < 4; i++ ) - brw_MUL( p, interp[ i ], interp[ i ], param[ i ] ); - - /* Mark the current address, as it will be a jump destination. The - following code will be executed twice: first, with the flag - register clear indicating the w=0 case, and second with flags - set for w=1. */ - loop = p->nr_insn; - - /* Arrange the eight corner coordinates into scalars (itmp0..itmp3) to - be hashed. Since we have only 16 bits of precision in the hash, we - must be careful about thorough mixing to maintain entropy as we - squash the input vector into a small scalar. */ - brw_MUL( p, brw_null_reg(), low_words( floors[ 0 ] ), - brw_imm_uw( 0xBC8F ) ); - brw_MAC( p, brw_null_reg(), high_words( floors[ 0 ] ), - brw_imm_uw( 0xD0BD ) ); - brw_MAC( p, brw_null_reg(), low_words( floors[ 1 ] ), - brw_imm_uw( 0x9B93 ) ); - brw_MAC( p, low_words( itmp[ 0 ] ), high_words( floors[ 1 ] ), - brw_imm_uw( 0xA359 ) ); - brw_ADD( p, high_words( itmp[ 0 ] ), low_words( itmp[ 0 ] ), - brw_imm_uw( 0xBC8F ) ); - - /* Temporarily disable the execution mask while we work with ExecSize=16 - channels (the mask is set for ExecSize=8 and is probably incorrect). - Although this might cause execution of unwanted channels, the code - writes only to temporary registers and has no side effects, so - disabling the mask is harmless. */ - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_ADD( p, wtmp[ 1 ], wtmp[ 0 ], brw_imm_uw( 0xD0BD ) ); - brw_ADD( p, wtmp[ 2 ], wtmp[ 0 ], brw_imm_uw( 0x9B93 ) ); - brw_ADD( p, wtmp[ 3 ], wtmp[ 1 ], brw_imm_uw( 0x9B93 ) ); - - /* We're now ready to perform the hashing. The eight hashes are - interleaved for performance. The hash function used is - designed to rapidly achieve avalanche and require only 16x16 - bit multiplication, and 8-bit swizzles (which we get for - free). */ - for( i = 0; i < 4; i++ ) - brw_MUL( p, wtmp[ i ], wtmp[ i ], brw_imm_uw( 0x28D9 ) ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, even_bytes( wtmp[ i ] ), even_bytes( wtmp[ i ] ), - odd_bytes( wtmp[ i ] ) ); - for( i = 0; i < 4; i++ ) - brw_MUL( p, wtmp[ i ], wtmp[ i ], brw_imm_uw( 0xC6D5 ) ); - for( i = 0; i < 4; i++ ) - brw_XOR( p, even_bytes( wtmp[ i ] ), even_bytes( wtmp[ i ] ), - odd_bytes( wtmp[ i ] ) ); - brw_pop_insn_state( p ); - - /* Now we want to initialise the four rear gradients based on the - hashes. Format conversion from signed integer to float leaves - everything scaled too high by a factor of pow( 2, 15 ), but - we correct for that right at the end. */ - /* x component */ - brw_ADD( p, t, param[ 0 ], brw_imm_f( -1.0 ) ); - brw_MOV( p, x0y0, low_words( tmp[ 0 ] ) ); - brw_MOV( p, x0y1, low_words( tmp[ 1 ] ) ); - brw_MOV( p, x1y0, high_words( tmp[ 0 ] ) ); - brw_MOV( p, x1y1, high_words( tmp[ 1 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 0 ], wtmp[ 0 ], brw_imm_uw( 4 ) ); - brw_SHL( p, wtmp[ 1 ], wtmp[ 1 ], brw_imm_uw( 4 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, x1y0, x1y0, t ); - brw_MUL( p, x1y1, x1y1, t ); - brw_ADD( p, t, param[ 1 ], brw_imm_f( -1.0 ) ); - brw_MUL( p, x0y0, x0y0, param[ 0 ] ); - brw_MUL( p, x0y1, x0y1, param[ 0 ] ); - - /* y component */ - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 0 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 0 ], wtmp[ 0 ], brw_imm_uw( 4 ) ); - brw_SHL( p, wtmp[ 1 ], wtmp[ 1 ], brw_imm_uw( 4 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - /* prepare t for the w component (used below): w the first time through - the loop; w - 1 the second time) */ - brw_set_predicate_control( p, BRW_PREDICATE_NORMAL ); - brw_ADD( p, t, param[ 3 ], brw_imm_f( -1.0 ) ); - p->current->header.predicate_inverse = 1; - brw_MOV( p, t, param[ 3 ] ); - p->current->header.predicate_inverse = 0; - brw_set_predicate_control( p, BRW_PREDICATE_NONE ); - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], param[ 1 ] ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], param[ 1 ] ); - - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - - /* z component */ - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 1 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 0 ], wtmp[ 0 ], brw_imm_uw( 4 ) ); - brw_SHL( p, wtmp[ 1 ], wtmp[ 1 ], brw_imm_uw( 4 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], param[ 2 ] ); - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], param[ 2 ] ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], param[ 2 ] ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], param[ 2 ] ); - - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - - /* w component */ - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 1 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 0 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 1 ] ) ); - - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], t ); - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - brw_ADD( p, t, param[ 0 ], brw_imm_f( -1.0 ) ); - - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - - /* Here we interpolate in the y dimension... */ - brw_ADD( p, x0y1, x0y1, negate( x0y0 ) ); - brw_ADD( p, x1y1, x1y1, negate( x1y0 ) ); - brw_MUL( p, x0y1, x0y1, interp[ 1 ] ); - brw_MUL( p, x1y1, x1y1, interp[ 1 ] ); - brw_ADD( p, x0y0, x0y0, x0y1 ); - brw_ADD( p, x1y0, x1y0, x1y1 ); - - /* And now in x. Leave the result in tmp[ 0 ] (see below)... */ - brw_ADD( p, x1y0, x1y0, negate( x0y0 ) ); - brw_MUL( p, x1y0, x1y0, interp[ 0 ] ); - brw_ADD( p, tmp[ 0 ], x0y0, x1y0 ); - - /* Now do the same thing for the front four gradients... */ - /* x component */ - brw_MOV( p, x0y0, low_words( tmp[ 2 ] ) ); - brw_MOV( p, x0y1, low_words( tmp[ 3 ] ) ); - brw_MOV( p, x1y0, high_words( tmp[ 2 ] ) ); - brw_MOV( p, x1y1, high_words( tmp[ 3 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 2 ], wtmp[ 2 ], brw_imm_uw( 4 ) ); - brw_SHL( p, wtmp[ 3 ], wtmp[ 3 ], brw_imm_uw( 4 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, x1y0, x1y0, t ); - brw_MUL( p, x1y1, x1y1, t ); - brw_ADD( p, t, param[ 1 ], brw_imm_f( -1.0 ) ); - brw_MUL( p, x0y0, x0y0, param[ 0 ] ); - brw_MUL( p, x0y1, x0y1, param[ 0 ] ); - - /* y component */ - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 2 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 2 ], wtmp[ 2 ], brw_imm_uw( 4 ) ); - brw_SHL( p, wtmp[ 3 ], wtmp[ 3 ], brw_imm_uw( 4 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - brw_ADD( p, t, param[ 2 ], brw_imm_f( -1.0 ) ); - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], param[ 1 ] ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], param[ 1 ] ); - - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - - /* z component */ - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 3 ] ) ); - - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_SHL( p, wtmp[ 2 ], wtmp[ 2 ], brw_imm_uw( 4 ) ); - brw_SHL( p, wtmp[ 3 ], wtmp[ 3 ], brw_imm_uw( 4 ) ); - brw_pop_insn_state( p ); - - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], t ); - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - /* prepare t for the w component (used below): w the first time through - the loop; w - 1 the second time) */ - brw_set_predicate_control( p, BRW_PREDICATE_NORMAL ); - brw_ADD( p, t, param[ 3 ], brw_imm_f( -1.0 ) ); - p->current->header.predicate_inverse = 1; - brw_MOV( p, t, param[ 3 ] ); - p->current->header.predicate_inverse = 0; - brw_set_predicate_control( p, BRW_PREDICATE_NONE ); - - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - - /* w component */ - brw_MOV( p, tmp[ 4 ], low_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 5 ], low_words( tmp[ 3 ] ) ); - brw_MOV( p, tmp[ 6 ], high_words( tmp[ 2 ] ) ); - brw_MOV( p, tmp[ 7 ], high_words( tmp[ 3 ] ) ); - - brw_MUL( p, tmp[ 4 ], tmp[ 4 ], t ); - brw_MUL( p, tmp[ 5 ], tmp[ 5 ], t ); - brw_MUL( p, tmp[ 6 ], tmp[ 6 ], t ); - brw_MUL( p, tmp[ 7 ], tmp[ 7 ], t ); - - brw_ADD( p, x0y0, x0y0, tmp[ 4 ] ); - brw_ADD( p, x0y1, x0y1, tmp[ 5 ] ); - brw_ADD( p, x1y0, x1y0, tmp[ 6 ] ); - brw_ADD( p, x1y1, x1y1, tmp[ 7 ] ); - - /* Interpolate in the y dimension: */ - brw_ADD( p, x0y1, x0y1, negate( x0y0 ) ); - brw_ADD( p, x1y1, x1y1, negate( x1y0 ) ); - brw_MUL( p, x0y1, x0y1, interp[ 1 ] ); - brw_MUL( p, x1y1, x1y1, interp[ 1 ] ); - brw_ADD( p, x0y0, x0y0, x0y1 ); - brw_ADD( p, x1y0, x1y0, x1y1 ); - - /* And now in x. The rear face is in tmp[ 0 ] (see above), so this - time put the front face in tmp[ 1 ] and we're nearly there... */ - brw_ADD( p, x1y0, x1y0, negate( x0y0 ) ); - brw_MUL( p, x1y0, x1y0, interp[ 0 ] ); - brw_ADD( p, tmp[ 1 ], x0y0, x1y0 ); - - /* Another interpolation, in the z dimension: */ - brw_ADD( p, tmp[ 1 ], tmp[ 1 ], negate( tmp[ 0 ] ) ); - brw_MUL( p, tmp[ 1 ], tmp[ 1 ], interp[ 2 ] ); - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], tmp[ 1 ] ); - - /* Exit the loop if we've computed both cubes... */ - origin = p->nr_insn; - brw_push_insn_state( p ); - brw_set_predicate_control( p, BRW_PREDICATE_NORMAL ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_ADD( p, brw_ip_reg(), brw_ip_reg(), brw_imm_d( 0 ) ); - brw_pop_insn_state( p ); - - /* Save the result for the w=0 case, and increment the w coordinate: */ - brw_MOV( p, w0, tmp[ 0 ] ); - brw_ADD( p, high_words( floors[ 1 ] ), high_words( floors[ 1 ] ), - brw_imm_uw( 1 ) ); - - /* Loop around for the other cube. Explicitly set the flag register - (unfortunately we must spend an extra instruction to do this: we - can't rely on a side effect of the previous MOV or ADD because - conditional modifiers which are normally true might be false in - exceptional circumstances, e.g. given a NaN input; the add to - brw_ip_reg() is not suitable because the IP is not an 8-vector). */ - brw_push_insn_state( p ); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_MOV( p, brw_flag_reg(), brw_imm_uw( 0xFF ) ); - brw_ADD( p, brw_ip_reg(), brw_ip_reg(), - brw_imm_d( ( loop - p->nr_insn ) << 4 ) ); - brw_pop_insn_state( p ); - - /* Patch the previous conditional branch now that we know the - destination address. */ - brw_set_src1( p->store + origin, - brw_imm_d( ( p->nr_insn - origin ) << 4 ) ); - - /* The very last interpolation. */ - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], negate( w0 ) ); - brw_MUL( p, tmp[ 0 ], tmp[ 0 ], interp[ 3 ] ); - brw_ADD( p, tmp[ 0 ], tmp[ 0 ], w0 ); - - /* scale by pow( 2, -15 ), as described above */ - brw_MUL( p, param[ 0 ], tmp[ 0 ], brw_imm_f( 0.000030517578125 ) ); - - release_tmps( c, mark ); -} - -static void emit_noise4( struct brw_wm_compile *c, - const struct prog_instruction *inst ) -{ - struct brw_compile *p = &c->func; - struct brw_reg src0, src1, src2, src3, param0, param1, param2, param3, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - int mark = mark_tmps( c ); - - assert( mark == 0 ); - - src0 = get_src_reg( c, inst, 0, 0 ); - src1 = get_src_reg( c, inst, 0, 1 ); - src2 = get_src_reg( c, inst, 0, 2 ); - src3 = get_src_reg( c, inst, 0, 3 ); - - param0 = alloc_tmp( c ); - param1 = alloc_tmp( c ); - param2 = alloc_tmp( c ); - param3 = alloc_tmp( c ); - - brw_MOV( p, param0, src0 ); - brw_MOV( p, param1, src1 ); - brw_MOV( p, param2, src2 ); - brw_MOV( p, param3, src3 ); - - invoke_subroutine( c, SUB_NOISE4, noise4_sub ); - - /* Fill in the result: */ - brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); - for (i = 0 ; i < 4; i++) { - if (mask & (1<<i)) { - dst = get_dst_reg(c, inst, i); - brw_MOV( p, dst, param0 ); - } - } - if( inst->SaturateMode == SATURATE_ZERO_ONE ) - brw_set_saturate( p, 0 ); - - release_tmps( c, mark ); -} - /** * Resolve subroutine calls after code emit is done. */ @@ -1990,18 +882,6 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) case OPCODE_MAD: emit_mad(p, dst, dst_flags, args[0], args[1], args[2]); break; - case OPCODE_NOISE1: - emit_noise1(c, inst); - break; - case OPCODE_NOISE2: - emit_noise2(c, inst); - break; - case OPCODE_NOISE3: - emit_noise3(c, inst); - break; - case OPCODE_NOISE4: - emit_noise4(c, inst); - break; case OPCODE_TEX: emit_tex(c, dst, dst_flags, args[0], get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index a9ba93d24b..08069d71dd 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -873,6 +873,9 @@ intelDestroyContext(__DRIcontext * driContextPriv) GLboolean intelUnbindContext(__DRIcontext * driContextPriv) { + /* Unset current context and dispath table */ + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_extensions_es2.c b/src/mesa/drivers/dri/intel/intel_extensions_es2.c index de34bbb2ae..24f64045ef 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions_es2.c +++ b/src/mesa/drivers/dri/intel/intel_extensions_es2.c @@ -39,6 +39,7 @@ static const char *es2_extensions[] = { "GL_ARB_window_pos", "GL_EXT_blend_func_separate", "GL_EXT_compiled_vertex_array", + "GL_EXT_framebuffer_blit", "GL_EXT_multi_draw_arrays", "GL_EXT_polygon_offset", "GL_EXT_texture_object", diff --git a/src/mesa/drivers/dri/nouveau/nouveau_class.h b/src/mesa/drivers/dri/nouveau/nouveau_class.h index 5eff4af4d5..32ee8157d5 120000..100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_class.h +++ b/src/mesa/drivers/dri/nouveau/nouveau_class.h @@ -1 +1,4953 @@ -../../../../gallium/drivers/nouveau/nouveau_class.h
\ No newline at end of file +/************************************************************************* + + Autogenerated file, do not edit ! + + This file was generated by renouveau-gen from renouveau.xml, the + XML database of nvidia objects and methods. renouveau-gen and + renouveau.xml can be found in CVS module renouveau of sourceforge.net + project nouveau: + +cvs -z3 -d:pserver:anonymous@nouveau.cvs.sourceforge.net:/cvsroot/nouveau co -P renouveau + +************************************************************************** + + Copyright (C) 2006-2008 : + Dmitry Baryshkov, + Laurent Carlier, + Matthieu Castet, + Dawid Gajownik, + Jeremy Kolb, + Stephane Loeuillet, + Patrice Mandin, + Stephane Marchesin, + Serge Martin, + Sylvain Munaut, + Simon Raffeiner, + Ben Skeggs, + Erik Waling, + koala_br, + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*************************************************************************/ + + +#ifndef NOUVEAU_REG_H +#define NOUVEAU_REG_H 1 + + +#define NV01_ROOT 0x00000001 + + + +#define NV01_CONTEXT_DMA 0x00000002 + + + +#define NV01_DEVICE 0x00000003 + + + +#define NV01_TIMER 0x00000004 + +#define NV01_TIMER_SYNCHRONIZE 0x00000100 +#define NV01_TIMER_STOP_ALARM 0x00000104 +#define NV01_TIMER_DMA_NOTIFY 0x00000180 +#define NV01_TIMER_TIME(x) (0x00000300+((x)*4)) +#define NV01_TIMER_TIME__SIZE 0x00000002 +#define NV01_TIMER_ALARM_NOTIFY 0x00000308 + + +#define NV01_CONTEXT_BETA1 0x00000012 + +#define NV01_CONTEXT_BETA1_NOP 0x00000100 +#define NV01_CONTEXT_BETA1_NOTIFY 0x00000104 +#define NV01_CONTEXT_BETA1_DMA_NOTIFY 0x00000180 +#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300 + + +#define NV01_CONTEXT_COLOR_KEY 0x00000017 + +#define NV01_CONTEXT_COLOR_KEY_NOP 0x00000100 +#define NV01_CONTEXT_COLOR_KEY_NOTIFY 0x00000104 +#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY 0x00000180 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT 0x00000300 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A8Y8 0x00000001 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X24Y8 0x00000002 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5 0x00000003 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X17R5G5B5 0x00000004 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8 0x00000005 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X8R8G8B8 0x00000006 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16Y16 0x00000007 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16Y16 0x00000008 +#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304 + + +#define NV04_CONTEXT_COLOR_KEY 0x00000057 + + + +#define NV01_CONTEXT_PATTERN 0x00000018 + +#define NV01_CONTEXT_PATTERN_NOP 0x00000100 +#define NV01_CONTEXT_PATTERN_NOTIFY 0x00000104 +#define NV01_CONTEXT_PATTERN_DMA_NOTIFY 0x00000180 +#define NV01_CONTEXT_PATTERN_COLOR_FORMAT 0x00000300 +#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT 0x00000304 +#define NV01_CONTEXT_PATTERN_SHAPE 0x00000308 +#define NV01_CONTEXT_PATTERN_COLOR(x) (0x00000310+((x)*4)) +#define NV01_CONTEXT_PATTERN_COLOR__SIZE 0x00000002 +#define NV01_CONTEXT_PATTERN_PATTERN(x) (0x00000318+((x)*4)) +#define NV01_CONTEXT_PATTERN_PATTERN__SIZE 0x00000002 + + +#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019 + +#define NV01_CONTEXT_CLIP_RECTANGLE_NOP 0x00000100 +#define NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY 0x00000104 +#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT 0x00000300 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_SHIFT 0 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_MASK 0x0000ffff +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_SHIFT 16 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_MASK 0xffff0000 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE 0x00000304 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_SHIFT 0 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_MASK 0x0000ffff +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_SHIFT 16 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_MASK 0xffff0000 + + +#define NV01_RENDER_SOLID_LINE 0x0000001c + +#define NV01_RENDER_SOLID_LINE_NOP 0x00000100 +#define NV01_RENDER_SOLID_LINE_NOTIFY 0x00000104 +#define NV01_RENDER_SOLID_LINE_PATCH 0x0000010c +#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY 0x00000180 +#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE 0x00000184 +#define NV01_RENDER_SOLID_LINE_PATTERN 0x00000188 +#define NV01_RENDER_SOLID_LINE_ROP 0x0000018c +#define NV01_RENDER_SOLID_LINE_BETA1 0x00000190 +#define NV01_RENDER_SOLID_LINE_SURFACE 0x00000194 +#define NV01_RENDER_SOLID_LINE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT 0x00000005 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A8Y8 0x00000001 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X24Y8 0x00000002 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5 0x00000003 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X17R5G5B5 0x00000004 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8 0x00000005 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X8R8G8B8 0x00000006 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16Y16 0x00000007 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16Y16 0x00000008 +#define NV01_RENDER_SOLID_LINE_COLOR 0x00000304 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0(x) (0x00000400+((x)*8)) +#define NV01_RENDER_SOLID_LINE_LINE_POINT0__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X_SHIFT 0 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_SHIFT 16 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1(x) (0x00000404+((x)*8)) +#define NV01_RENDER_SOLID_LINE_LINE_POINT1__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X_SHIFT 0 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_SHIFT 16 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(x) (0x00000480+((x)*16)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(x) (0x00000484+((x)*16)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(x) (0x00000488+((x)*16)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(x) (0x0000048c+((x)*16)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_POLYLINE(x) (0x00000500+((x)*4)) +#define NV01_RENDER_SOLID_LINE_POLYLINE__SIZE 0x00000020 +#define NV01_RENDER_SOLID_LINE_POLYLINE_X_SHIFT 0 +#define NV01_RENDER_SOLID_LINE_POLYLINE_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_POLYLINE_Y_SHIFT 16 +#define NV01_RENDER_SOLID_LINE_POLYLINE_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(x) (0x00000580+((x)*8)) +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(x) (0x00000584+((x)*8)) +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(x) (0x00000600+((x)*8)) +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(x) (0x00000604+((x)*8)) +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__SIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_SHIFT 0 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_SHIFT 16 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_MASK 0xffff0000 + + +#define NV04_RENDER_SOLID_LINE 0x0000005c + +#define NV04_RENDER_SOLID_LINE_BETA4 0x00000194 +#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198 + + +#define NV01_RENDER_SOLID_TRIANGLE 0x0000001d + +#define NV01_RENDER_SOLID_TRIANGLE_NOP 0x00000100 +#define NV01_RENDER_SOLID_TRIANGLE_NOTIFY 0x00000104 +#define NV01_RENDER_SOLID_TRIANGLE_PATCH 0x0000010c +#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY 0x00000180 +#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE 0x00000184 +#define NV01_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188 +#define NV01_RENDER_SOLID_TRIANGLE_ROP 0x0000018c +#define NV01_RENDER_SOLID_TRIANGLE_BETA1 0x00000190 +#define NV01_RENDER_SOLID_TRIANGLE_SURFACE 0x00000194 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT 0x00000005 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR 0x00000304 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0 0x00000310 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1 0x00000314 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2 0x00000318 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X 0x00000320 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y 0x00000324 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X 0x00000328 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y 0x0000032c +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X 0x00000330 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y 0x00000334 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(x) (0x00000400+((x)*4)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__SIZE 0x00000020 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(x) (0x00000480+((x)*8)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__SIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(x) (0x00000484+((x)*8)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__SIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(x) (0x00000500+((x)*16)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__SIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(x) (0x00000504+((x)*16)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__SIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(x) (0x00000508+((x)*16)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__SIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(x) (0x0000050c+((x)*16)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__SIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(x) (0x00000580+((x)*8)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__SIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(x) (0x00000584+((x)*8)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__SIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_SHIFT 16 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_MASK 0xffff0000 + + +#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d + +#define NV04_RENDER_SOLID_TRIANGLE_BETA4 0x00000194 +#define NV04_RENDER_SOLID_TRIANGLE_SURFACE 0x00000198 + + +#define NV01_RENDER_SOLID_RECTANGLE 0x0000001e + +#define NV01_RENDER_SOLID_RECTANGLE_NOP 0x00000100 +#define NV01_RENDER_SOLID_RECTANGLE_NOTIFY 0x00000104 +#define NV01_RENDER_SOLID_RECTANGLE_PATCH 0x0000010c +#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY 0x00000180 +#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE 0x00000184 +#define NV01_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188 +#define NV01_RENDER_SOLID_RECTANGLE_ROP 0x0000018c +#define NV01_RENDER_SOLID_RECTANGLE_BETA1 0x00000190 +#define NV01_RENDER_SOLID_RECTANGLE_SURFACE 0x00000194 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT 0x00000005 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR 0x00000304 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(x) (0x00000400+((x)*8)) +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__SIZE 0x00000010 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_SHIFT 0 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_MASK 0x0000ffff +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_SHIFT 16 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_MASK 0xffff0000 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(x) (0x00000404+((x)*8)) +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__SIZE 0x00000010 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_SHIFT 0 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_MASK 0x0000ffff +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_SHIFT 16 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_MASK 0xffff0000 + + +#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e + +#define NV04_RENDER_SOLID_RECTANGLE_BETA4 0x00000194 +#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198 + + +#define NV01_IMAGE_BLIT 0x0000001f + +#define NV01_IMAGE_BLIT_NOP 0x00000100 +#define NV01_IMAGE_BLIT_NOTIFY 0x00000104 +#define NV01_IMAGE_BLIT_PATCH 0x0000010c +#define NV01_IMAGE_BLIT_DMA_NOTIFY 0x00000180 +#define NV01_IMAGE_BLIT_COLOR_KEY 0x00000184 +#define NV01_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188 +#define NV01_IMAGE_BLIT_PATTERN 0x0000018c +#define NV01_IMAGE_BLIT_ROP 0x00000190 +#define NV01_IMAGE_BLIT_BETA1 0x00000194 +#define NV01_IMAGE_BLIT_SURFACE 0x0000019c +#define NV01_IMAGE_BLIT_OPERATION 0x000002fc +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001 +#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002 +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003 +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005 +#define NV01_IMAGE_BLIT_IMAGE_INPUT 0x00000204 +#define NV01_IMAGE_BLIT_POINT_IN 0x00000300 +#define NV01_IMAGE_BLIT_POINT_IN_X_SHIFT 0 +#define NV01_IMAGE_BLIT_POINT_IN_X_MASK 0x0000ffff +#define NV01_IMAGE_BLIT_POINT_IN_Y_SHIFT 16 +#define NV01_IMAGE_BLIT_POINT_IN_Y_MASK 0xffff0000 +#define NV01_IMAGE_BLIT_POINT_OUT 0x00000304 +#define NV01_IMAGE_BLIT_POINT_OUT_X_SHIFT 0 +#define NV01_IMAGE_BLIT_POINT_OUT_X_MASK 0x0000ffff +#define NV01_IMAGE_BLIT_POINT_OUT_Y_SHIFT 16 +#define NV01_IMAGE_BLIT_POINT_OUT_Y_MASK 0xffff0000 +#define NV01_IMAGE_BLIT_SIZE 0x00000308 +#define NV01_IMAGE_BLIT_SIZE_W_SHIFT 0 +#define NV01_IMAGE_BLIT_SIZE_W_MASK 0x0000ffff +#define NV01_IMAGE_BLIT_SIZE_H_SHIFT 16 +#define NV01_IMAGE_BLIT_SIZE_H_MASK 0xffff0000 + + +#define NV04_IMAGE_BLIT 0x0000005f + +#define NV04_IMAGE_BLIT_ROP 0x00000190 +#define NV04_IMAGE_BLIT_BETA4 0x00000198 +#define NV04_IMAGE_BLIT_SURFACE 0x0000019c + + +#define NV12_IMAGE_BLIT 0x0000009f + +#define NV12_IMAGE_BLIT_WAIT_FOR_IDLE 0x00000108 + + +#define NV01_IMAGE_FROM_CPU 0x00000021 + +#define NV01_IMAGE_FROM_CPU_NOP 0x00000100 +#define NV01_IMAGE_FROM_CPU_NOTIFY 0x00000104 +#define NV01_IMAGE_FROM_CPU_PATCH 0x0000010c +#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 +#define NV01_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 +#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188 +#define NV01_IMAGE_FROM_CPU_PATTERN 0x0000018c +#define NV01_IMAGE_FROM_CPU_ROP 0x00000190 +#define NV01_IMAGE_FROM_CPU_BETA1 0x00000194 +#define NV01_IMAGE_FROM_CPU_SURFACE 0x00000198 +#define NV01_IMAGE_FROM_CPU_OPERATION 0x000002fc +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND 0x00000001 +#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND 0x00000002 +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY 0x00000003 +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT 0x00000005 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_Y8 0x00000001 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8 0x00000005 +#define NV01_IMAGE_FROM_CPU_POINT 0x00000304 +#define NV01_IMAGE_FROM_CPU_POINT_X_SHIFT 0 +#define NV01_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_POINT_Y_SHIFT 16 +#define NV01_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W_SHIFT 0 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W_MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H_SHIFT 16 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H_MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_SIZE_IN 0x0000030c +#define NV01_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT 0 +#define NV01_IMAGE_FROM_CPU_SIZE_IN_W_MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT 16 +#define NV01_IMAGE_FROM_CPU_SIZE_IN_H_MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) +#define NV01_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020 + + +#define NV04_IMAGE_FROM_CPU 0x00000061 + +#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198 +#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c + + +#define NV05_IMAGE_FROM_CPU 0x00000065 + +#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 + + +#define NV10_IMAGE_FROM_CPU 0x0000008a + +#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 + + +#define NV30_IMAGE_FROM_CPU 0x0000038a + + + +#define NV40_IMAGE_FROM_CPU 0x0000308a + + + +#define NV01_NULL 0x00000030 + + + +#define NV03_STRETCHED_IMAGE_FROM_CPU 0x00000036 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_NOP 0x00000100 +#define NV03_STRETCHED_IMAGE_FROM_CPU_NOTIFY 0x00000104 +#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH 0x0000010c +#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 +#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188 +#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP 0x0000018c +#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1 0x00000190 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000194 +#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION 0x000002fc +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN 0x00000304 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT 16 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU 0x00000308 +#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV 0x0000030c +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT 0x00000310 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_SHIFT 16 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE 0x00000314 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_SHIFT 16 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4 0x00000318 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_SHIFT 16 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020 + + +#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194 +#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198 + + +#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066 + +#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 + + +#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366 + + + +#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066 + + + +#define NV03_SCALED_IMAGE_FROM_MEMORY 0x00000037 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100 +#define NV03_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104 +#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180 +#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184 +#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 +#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c +#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000194 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318 +#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_MASK 0xffff0000 + + +#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077 + +#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194 +#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 + + +#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063 + +#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc +#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000 +#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001 +#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002 + + +#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089 + +#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108 + + +#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389 + + + +#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089 + + + +#define NV04_DVD_SUBPICTURE 0x00000038 + +#define NV04_DVD_SUBPICTURE_NOP 0x00000100 +#define NV04_DVD_SUBPICTURE_NOTIFY 0x00000104 +#define NV04_DVD_SUBPICTURE_DMA_NOTIFY 0x00000180 +#define NV04_DVD_SUBPICTURE_DMA_OVERLAY 0x00000184 +#define NV04_DVD_SUBPICTURE_DMA_IMAGEIN 0x00000188 +#define NV04_DVD_SUBPICTURE_DMA_IMAGEOUT 0x0000018c +#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT 0x00000300 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_SHIFT 0 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_SHIFT 16 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE 0x00000304 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_SHIFT 0 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_SHIFT 16 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT 0x00000308 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_SHIFT 0 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_SHIFT 16 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_IMAGEOUT_OFFSET 0x0000030c +#define NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DU_DX 0x00000310 +#define NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DV_DY 0x00000314 +#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE 0x00000318 +#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_SHIFT 0 +#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_SHIFT 16 +#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT 0x0000031c +#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_SHIFT 0 +#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_SHIFT 16 +#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_IMAGEIN_OFFSET 0x00000320 +#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT 0x00000324 +#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_SHIFT 0 +#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_SHIFT 16 +#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DU_DX 0x00000328 +#define NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DV_DY 0x0000032c +#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE 0x00000330 +#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_SHIFT 0 +#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_SHIFT 16 +#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT 0x00000334 +#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_SHIFT 0 +#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_SHIFT 16 +#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_MASK 0xffff0000 +#define NV04_DVD_SUBPICTURE_OVERLAY_OFFSET 0x00000338 +#define NV04_DVD_SUBPICTURE_OVERLAY_POINT 0x0000033c +#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_SHIFT 0 +#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_MASK 0x0000ffff +#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_SHIFT 16 +#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_MASK 0xffff0000 + + +#define NV10_DVD_SUBPICTURE 0x00000088 + +#define NV10_DVD_SUBPICTURE_WAIT_FOR_IDLE 0x00000108 + + +#define NV04_MEMORY_TO_MEMORY_FORMAT 0x00000039 + +#define NV04_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 +#define NV04_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 +#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 +#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN 0x00000184 +#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT 0x00000188 +#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c +#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310 +#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314 +#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318 +#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c +#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT 0 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK 0x000000ff +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT 8 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK 0x0000ff00 +#define NV04_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328 + + +#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 + +#define NV50_MEMORY_TO_MEMORY_FORMAT_SERIALIZE 0x00000110 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_IN 0x00000210 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Z 0x00000214 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_SHIFT 0 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_MASK 0x0000ffff +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_SHIFT 16 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_MASK 0xffff0000 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_OUT 0x0000022c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Z 0x00000230 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_SHIFT 0 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_MASK 0x0000ffff +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_SHIFT 16 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_MASK 0xffff0000 +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c + + +#define NV01_MEMORY_LOCAL_BANKED 0x0000003d + + + +#define NV01_MAPPING_SYSTEM 0x0000003e + + + +#define NV03_MEMORY_LOCAL_CURSOR 0x0000003f + + + +#define NV01_MEMORY_LOCAL_LINEAR 0x00000040 + + + +#define NV01_MAPPING_LOCAL 0x00000041 + + + +#define NV04_CONTEXT_SURFACES_2D 0x00000042 + +#define NV04_CONTEXT_SURFACES_2D_NOP 0x00000100 +#define NV04_CONTEXT_SURFACES_2D_NOTIFY 0x00000104 +#define NV04_CONTEXT_SURFACES_2D_PM_TRIGGER 0x00000140 +#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180 +#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE 0x00000184 +#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN 0x00000188 +#define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8 0x00000001 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5 0x00000002 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5 0x00000003 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5 0x00000004 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16 0x00000005 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8 0x00000006 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8 0x00000007 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8 0x00000009 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8 0x0000000a +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32 0x0000000b +#define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304 +#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT 0 +#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT 16 +#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308 +#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c + + +#define NV10_CONTEXT_SURFACES_2D 0x00000062 + + + +#define NV30_CONTEXT_SURFACES_2D 0x00000362 + + + +#define NV40_CONTEXT_SURFACES_2D 0x00003062 + + + +#define NV03_CONTEXT_ROP 0x00000043 + +#define NV03_CONTEXT_ROP_NOP 0x00000100 +#define NV03_CONTEXT_ROP_NOTIFY 0x00000104 +#define NV03_CONTEXT_ROP_DMA_NOTIFY 0x00000180 +#define NV03_CONTEXT_ROP_ROP 0x00000300 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SHIFT 0 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_MASK 0x0000000f +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_CLEAR 0x00000000 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOR 0x00000001 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_INVERTED 0x00000002 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY_INVERTED 0x00000003 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_REVERSE 0x00000004 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_INVERT 0x00000005 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_XOR 0x00000006 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NAND 0x00000007 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND 0x00000008 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_EQUI 0x00000009 +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOOP 0x0000000a +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_INVERTED 0x0000000b +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY 0x0000000c +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_REVERSE 0x0000000d +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR 0x0000000e +#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SET 0x0000000f +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SHIFT 4 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_MASK 0x000000f0 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_CLEAR 0x00000000 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOR 0x00000010 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_INVERTED 0x00000020 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY_INVERTED 0x00000030 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_REVERSE 0x00000040 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_INVERT 0x00000050 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_XOR 0x00000060 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NAND 0x00000070 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND 0x00000080 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_EQUI 0x00000090 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOOP 0x000000a0 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_INVERTED 0x000000b0 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY 0x000000c0 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_REVERSE 0x000000d0 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR 0x000000e0 +#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SET 0x000000f0 + + +#define NV04_IMAGE_PATTERN 0x00000044 + +#define NV04_IMAGE_PATTERN_NOP 0x00000100 +#define NV04_IMAGE_PATTERN_NOTIFY 0x00000104 +#define NV04_IMAGE_PATTERN_DMA_NOTIFY 0x00000180 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT 0x00000304 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6 0x00000001 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE 0x00000002 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8 0x00000000 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1 0x00000001 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64 0x00000002 +#define NV04_IMAGE_PATTERN_PATTERN_SELECT 0x0000030c +#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO 0x00000001 +#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR 0x00000002 +#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310 +#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314 +#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318 +#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c +#define NV04_IMAGE_PATTERN_PATTERN_Y8(x) (0x00000400+((x)*4)) +#define NV04_IMAGE_PATTERN_PATTERN_Y8__SIZE 0x00000010 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_MASK 0x000000ff +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_SHIFT 8 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_MASK 0x0000ff00 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_MASK 0x00ff0000 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_SHIFT 24 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_MASK 0xff000000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(x) (0x00000500+((x)*4)) +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__SIZE 0x00000020 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_MASK 0x0000001f +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_SHIFT 5 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_MASK 0x000007e0 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_SHIFT 11 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_MASK 0x0000f800 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_MASK 0x001f0000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_SHIFT 21 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_MASK 0x07e00000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_SHIFT 27 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_MASK 0xf8000000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(x) (0x00000600+((x)*4)) +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__SIZE 0x00000020 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_MASK 0x0000001f +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_SHIFT 5 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_MASK 0x000003e0 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_SHIFT 10 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_MASK 0x00007c00 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_MASK 0x001f0000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_SHIFT 21 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_MASK 0x03e00000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_SHIFT 26 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_MASK 0x7c000000 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(x) (0x00000700+((x)*4)) +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__SIZE 0x00000040 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_MASK 0x000000ff +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_SHIFT 8 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_MASK 0x0000ff00 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_MASK 0x00ff0000 + + +#define NV03_VIDEO_LUT_CURSOR_DAC 0x00000046 + +#define NV03_VIDEO_LUT_CURSOR_DAC_SYNCHRONIZE 0x00000100 +#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_IMAGE 0x00000104 +#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_CURSOR 0x00000108 +#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_DAC 0x0000010c +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_NOTIFY 0x00000180 +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE(x) (0x00000184+((x)*4)) +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT(x) (0x0000018c+((x)*4)) +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR(x) (0x00000194+((x)*4)) +#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_GET 0x000002fc +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET(x) (0x00000300+((x)*8)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT(x) (0x00000304+((x)*8)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_MASK 0x0fff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_SHIFT 28 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_MASK 0xf0000000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET(x) (0x00000340+((x)*12)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT(x) (0x00000344+((x)*12)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_MASK 0xffff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT(x) (0x00000348+((x)*12)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A 0x00000358 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_MASK 0xffff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE(x) (0x00000380+((x)*16)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_MASK 0xffff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC(x) (0x00000384+((x)*16)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_MASK 0x0fff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_SHIFT 28 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_MASK 0xf0000000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC(x) (0x00000388+((x)*16)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_MASK 0x0fff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_SHIFT 28 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_MASK 0xf0000000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE(x) (0x0000038c+((x)*16)) +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE__SIZE 0x00000002 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_SHIFT 0 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_MASK 0x0000ffff +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_SHIFT 16 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_MASK 0x0fff0000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_SHIFT 28 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_MASK 0xf0000000 +#define NV03_VIDEO_LUT_CURSOR_DAC_SET_PIXEL_CLOCK 0x000003a0 + + +#define NV03_TEXTURED_TRIANGLE 0x00000048 + +#define NV03_TEXTURED_TRIANGLE_NOP 0x00000100 +#define NV03_TEXTURED_TRIANGLE_NOTIFY 0x00000104 +#define NV03_TEXTURED_TRIANGLE_PATCH 0x0000010c +#define NV03_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180 +#define NV03_TEXTURED_TRIANGLE_DMA_TEXTURE 0x00000184 +#define NV03_TEXTURED_TRIANGLE_CLIP_RECTANGLE 0x00000188 +#define NV03_TEXTURED_TRIANGLE_SURFACE 0x0000018c +#define NV03_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT 0 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK 0x0000ffff +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT 16 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK 0x000f0000 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 20 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00f00000 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT 24 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK 0x0f000000 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT 28 +#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK 0xf0000000 +#define NV03_TEXTURED_TRIANGLE_FILTER 0x0000030c +#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT 0 +#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK 0x0000001f +#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT 8 +#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK 0x00001f00 +#define NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT 16 +#define NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK 0x00ff0000 +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR 0x00000310 +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT 0 +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK 0x000000ff +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT 8 +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK 0x0000ff00 +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT 16 +#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK 0x00ff0000 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT 0x00000314 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT 0 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK 0x0000000f +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT 4 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK 0x00000030 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT 6 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK 0x000000c0 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT 8 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK 0x00000f00 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT 12 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK 0x00007000 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE (1 << 15) +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT 16 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK 0x000f0000 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT 20 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK 0x00f00000 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT 24 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK 0x07000000 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT 27 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK 0x18000000 +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_BETA (1 << 29) +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND (1 << 30) +#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND (1 << 31) +#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL 0x00000318 +#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT 0 +#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK 0x000000ff +#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT 8 +#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK 0xffffff00 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00001000+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_SHIFT 0 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_MASK 0x0000000f +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_SHIFT 4 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_MASK 0x000000f0 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_SHIFT 8 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_MASK 0x00000f00 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_SHIFT 12 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_MASK 0x0000f000 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_SHIFT 16 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_MASK 0x000f0000 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_SHIFT 20 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_MASK 0x00f00000 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00001004+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00001008+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x0000100c+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00001010+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x00001014+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00001018+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000080 +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000101c+((x)*32)) +#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000080 + + +#define NV04_GDI_RECTANGLE_TEXT 0x0000004a + +#define NV04_GDI_RECTANGLE_TEXT_NOP 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104 +#define NV04_GDI_RECTANGLE_TEXT_PATCH 0x0000010c +#define NV04_GDI_RECTANGLE_TEXT_PM_TRIGGER 0x00000140 +#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 +#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS 0x00000184 +#define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188 +#define NV04_GDI_RECTANGLE_TEXT_ROP 0x0000018c +#define NV04_GDI_RECTANGLE_TEXT_BETA1 0x00000190 +#define NV04_GDI_RECTANGLE_TEXT_BETA4 0x00000194 +#define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND 0x00000000 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY 0x00000003 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT 0x00000005 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(x) (0x00000400+((x)*8)) +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__SIZE 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(x) (0x00000404+((x)*8)) +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__SIZE 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0 0x000005f4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1 0x000005f8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B 0x000005fc +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(x) (0x00000600+((x)*8)) +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__SIZE 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(x) (0x00000604+((x)*8)) +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__SIZE 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x000007ec +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x000007f0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C 0x000007f4 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C 0x000007f8 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C 0x000007fc +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x) (0x00000800+((x)*4)) +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE 0x00000080 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x00000be4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x00000be8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E 0x00000bec +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E 0x00000bf0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x00000bf4 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x00000bf8 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E 0x00000bfc +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x) (0x00000c00+((x)*4)) +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE 0x00000080 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F 0x00000ff0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_MASK 0x0fffffff +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_SHIFT 28 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_MASK 0xf0000000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0 0x00000ff4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1 0x00000ff8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F 0x00000ffc +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(x) (0x00001000+((x)*4)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__SIZE 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_MASK 0x000000ff +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_SHIFT 8 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_MASK 0x000fff00 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_SHIFT 20 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_MASK 0xfff00000 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G 0x000017f0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_MASK 0x0fffffff +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_SHIFT 28 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_MASK 0xf0000000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0 0x000017f4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1 0x000017f8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G 0x000017fc +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(x) (0x00001800+((x)*8)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__SIZE 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_SHIFT 16 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(x) (0x00001804+((x)*8)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__SIZE 0x00000100 + + +#define NV03_GDI_RECTANGLE_TEXT 0x0000004b + +#define NV03_GDI_RECTANGLE_TEXT_NOP 0x00000100 +#define NV03_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104 +#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 +#define NV03_GDI_RECTANGLE_TEXT_PATTERN 0x00000184 +#define NV03_GDI_RECTANGLE_TEXT_ROP 0x00000188 +#define NV03_GDI_RECTANGLE_TEXT_BETA1 0x0000018c +#define NV03_GDI_RECTANGLE_TEXT_SURFACE 0x00000190 +#define NV03_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc +#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT 0x00000400 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE 0x00000404 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B 0x000007f4 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B 0x000007f8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B 0x000007fc +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0 0x00000800 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1 0x00000804 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x00000bec +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x00000bf0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C 0x00000bf4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C 0x00000bf8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C 0x00000bfc +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x) (0x00000c00+((x)*4)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE 0x00000020 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0 0x00000fe8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1 0x00000fec +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D 0x00000ff0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D 0x00000ff4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D 0x00000ff8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D 0x00000ffc +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(x) (0x00001000+((x)*4)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__SIZE 0x00000020 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x000013e4 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x000013e8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E 0x000013ec +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E 0x000013f0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x000013f4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x000013f8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E 0x000013fc +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X_MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT 16 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x) (0x00001400+((x)*4)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE 0x00000020 + + +#define NV04_SWIZZLED_SURFACE 0x00000052 + +#define NV04_SWIZZLED_SURFACE_NOP 0x00000100 +#define NV04_SWIZZLED_SURFACE_NOTIFY 0x00000104 +#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180 +#define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184 +#define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_SHIFT 0 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x000000ff +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8 0x00000001 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000002 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000003 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5 0x00000004 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16 0x00000005 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000006 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000007 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000009 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8 0x0000000a +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32 0x0000000b +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT 16 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_MASK 0x00ff0000 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT 24 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_MASK 0xff000000 +#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304 + + +#define NV20_SWIZZLED_SURFACE 0x0000009e + + + +#define NV30_SWIZZLED_SURFACE 0x0000039e + + + +#define NV40_SWIZZLED_SURFACE 0x0000309e + + + +#define NV04_CONTEXT_SURFACES_3D 0x00000053 + +#define NV04_CONTEXT_SURFACES_3D_NOP 0x00000100 +#define NV04_CONTEXT_SURFACES_3D_NOTIFY 0x00000104 +#define NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180 +#define NV04_CONTEXT_SURFACES_3D_DMA_COLOR 0x00000184 +#define NV04_CONTEXT_SURFACES_3D_DMA_ZETA 0x00000188 +#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL 0x000002f8 +#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_SHIFT 0 +#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_SHIFT 16 +#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL 0x000002fc +#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_SHIFT 0 +#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_SHIFT 16 +#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_3D_FORMAT 0x00000300 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_SHIFT 0 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK 0x000000ff +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000001 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000002 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5 0x00000003 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000004 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000005 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000006 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000007 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT 8 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK 0x0000ff00 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_PITCH 0x00000100 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SWIZZLE 0x00000200 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_SHIFT 16 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_MASK 0x00ff0000 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_SHIFT 24 +#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_MASK 0xff000000 +#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE 0x00000304 +#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_SHIFT 0 +#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_SHIFT 16 +#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_3D_PITCH 0x00000308 +#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_SHIFT 0 +#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT 16 +#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x0000030c +#define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000310 + + +#define NV10_CONTEXT_SURFACES_3D 0x00000093 + + + +#define NV04_TEXTURED_TRIANGLE 0x00000054 + +#define NV04_TEXTURED_TRIANGLE_NOP 0x00000100 +#define NV04_TEXTURED_TRIANGLE_NOTIFY 0x00000104 +#define NV04_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180 +#define NV04_TEXTURED_TRIANGLE_DMA_A 0x00000184 +#define NV04_TEXTURED_TRIANGLE_DMA_B 0x00000188 +#define NV04_TEXTURED_TRIANGLE_SURFACE 0x0000018c +#define NV04_TEXTURED_TRIANGLE_COLORKEY 0x00000300 +#define NV04_TEXTURED_TRIANGLE_OFFSET 0x00000304 +#define NV04_TEXTURED_TRIANGLE_FORMAT 0x00000308 +#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_A (1 << 0) +#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_B (1 << 1) +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT 2 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK 0x0000000c +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER 0x00000010 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER 0x00000020 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER 0x00000040 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER 0x00000080 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8 0x00000100 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5 0x00000200 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5 0x00000300 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4 0x00000400 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5 0x00000500 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8 0x00000600 +#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8 0x00000700 +#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12 +#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20 +#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT 0x01000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT 0x02000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE 0x03000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER 0x04000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP 0x05000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPU (1 << 27) +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT 0x10000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT 0x20000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE 0x30000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER 0x40000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP 0x50000000 +#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPV (1 << 31) +#define NV04_TEXTURED_TRIANGLE_FILTER 0x0000030c +#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff +#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00 +#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15) +#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT 24 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK 0x07000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST 0x01000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR 0x02000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27) +#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT 28 +#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST 0x10000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR 0x20000000 +#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31) +#define NV04_TEXTURED_TRIANGLE_BLEND 0x00000310 +#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK 0x0000000f +#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT 4 +#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030 +#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6 +#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0 +#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040 +#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080 +#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0 +#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE (1 << 8) +#define NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE (1 << 12) +#define NV04_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE (1 << 16) +#define NV04_TEXTURED_TRIANGLE_BLEND_BLEND_ENABLE (1 << 20) +#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24 +#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000 +#define NV04_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28 +#define NV04_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000 +#define NV04_TEXTURED_TRIANGLE_CONTROL 0x00000314 +#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK 0x000000ff +#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK 0x00000f00 +#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE (1 << 12) +#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN (1 << 13) +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE (1 << 14) +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK 0x000f0000 +#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT 20 +#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK 0x00300000 +#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_BOTH 0x00000000 +#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_NONE 0x00100000 +#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CW 0x00200000 +#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CCW 0x00300000 +#define NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE (1 << 22) +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE (1 << 23) +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE (1 << 24) +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT 30 +#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK 0xc0000000 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR 0x00000318 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT 24 +#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK 0xff000000 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00000400+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x00000404+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00000408+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x0000040c+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00000410+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK 0x000000ff +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK 0x0000ff00 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK 0x00ff0000 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT 24 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK 0xff000000 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00000414+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK 0x000000ff +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK 0x0000ff00 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK 0x00ff0000 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00000418+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000041c+((x)*32)) +#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000010 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(x) (0x00000600+((x)*4)) +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE__SIZE 0x00000040 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT 0 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_MASK 0x0000000f +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT 4 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_MASK 0x000000f0 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT 8 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_MASK 0x00000f00 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT 12 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_MASK 0x0000f000 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT 16 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_MASK 0x000f0000 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT 20 +#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_MASK 0x00f00000 + + +#define NV10_TEXTURED_TRIANGLE 0x00000094 + + + +#define NV04_MULTITEX_TRIANGLE 0x00000055 + +#define NV04_MULTITEX_TRIANGLE_NOP 0x00000100 +#define NV04_MULTITEX_TRIANGLE_NOTIFY 0x00000104 +#define NV04_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180 +#define NV04_MULTITEX_TRIANGLE_DMA_A 0x00000184 +#define NV04_MULTITEX_TRIANGLE_DMA_B 0x00000188 +#define NV04_MULTITEX_TRIANGLE_SURFACE 0x0000018c +#define NV04_MULTITEX_TRIANGLE_OFFSET(x) (0x00000308+((x)*4)) +#define NV04_MULTITEX_TRIANGLE_OFFSET__SIZE 0x00000002 +#define NV04_MULTITEX_TRIANGLE_FORMAT(x) (0x00000310+((x)*4)) +#define NV04_MULTITEX_TRIANGLE_FORMAT__SIZE 0x00000002 +#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_A (1 << 0) +#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_B (1 << 1) +#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4 +#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030 +#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6 +#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0 +#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00 +#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12 +#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000 +#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000 +#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20 +#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000 +#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000 +#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPU (1 << 27) +#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28 +#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000 +#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPV (1 << 31) +#define NV04_MULTITEX_TRIANGLE_FILTER(x) (0x00000318+((x)*4)) +#define NV04_MULTITEX_TRIANGLE_FILTER__SIZE 0x00000002 +#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff +#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00 +#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15) +#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000 +#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK 0x07000000 +#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27) +#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT 28 +#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000 +#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31) +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA(x) (0x00000320+((x)*12)) +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA__SIZE 0x00000002 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE0 (1 << 0) +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_SHIFT 2 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_MASK 0x000000fc +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_ZERO 0x00000004 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_CONSTANT 0x00000008 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PRIMARY_COLOR 0x0000000c +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PREVIOUS 0x00000010 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE0 0x00000014 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE1 0x00000018 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE1 (1 << 8) +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_SHIFT 10 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_MASK 0x0000fc00 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_ZERO 0x00000400 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_CONSTANT 0x00000800 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PRIMARY_COLOR 0x00000c00 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PREVIOUS 0x00001000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE0 0x00001400 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE1 0x00001800 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE2 (1 << 16) +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_SHIFT 18 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_MASK 0x00fc0000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_ZERO 0x00040000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_CONSTANT 0x00080000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PRIMARY_COLOR 0x000c0000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PREVIOUS 0x00100000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE0 0x00140000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE1 0x00180000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE3 (1 << 24) +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_SHIFT 26 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_MASK 0x1c000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_ZERO 0x04000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_CONSTANT 0x08000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PRIMARY_COLOR 0x0c000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PREVIOUS 0x10000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE0 0x14000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE1 0x18000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SHIFT 29 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_MASK 0xe0000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_IDENTITY 0x20000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE2 0x40000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE4 0x60000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS 0x80000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS_SCALE2 0xe0000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR(x) (0x00000324+((x)*12)) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR__SIZE 0x00000002 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE0 (1 << 0) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA0 (1 << 1) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_SHIFT 2 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_MASK 0x000000fc +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_ZERO 0x00000004 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_CONSTANT 0x00000008 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PRIMARY_COLOR 0x0000000c +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PREVIOUS 0x00000010 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE0 0x00000014 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE1 0x00000018 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE1 (1 << 8) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA1 (1 << 9) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_SHIFT 10 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_MASK 0x0000fc00 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_ZERO 0x00000400 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_CONSTANT 0x00000800 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PRIMARY_COLOR 0x00000c00 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PREVIOUS 0x00001000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE0 0x00001400 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE1 0x00001800 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE2 (1 << 16) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA2 (1 << 17) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_SHIFT 18 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_MASK 0x00fc0000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_ZERO 0x00040000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_CONSTANT 0x00080000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PRIMARY_COLOR 0x000c0000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PREVIOUS 0x00100000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE0 0x00140000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE1 0x00180000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE3 (1 << 24) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA3 (1 << 25) +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_SHIFT 26 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_MASK 0x1c000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_ZERO 0x04000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_CONSTANT 0x08000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PRIMARY_COLOR 0x0c000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PREVIOUS 0x10000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE0 0x14000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE1 0x18000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SHIFT 29 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_MASK 0xe0000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_IDENTITY 0x20000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE2 0x40000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE4 0x60000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS 0x80000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS_SCALE2 0xe0000000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK 0x000000ff +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK 0x0000ff00 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK 0x00ff0000 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK 0xff000000 +#define NV04_MULTITEX_TRIANGLE_BLEND 0x00000338 +#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT 4 +#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030 +#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6 +#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0 +#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040 +#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080 +#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0 +#define NV04_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE (1 << 8) +#define NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE (1 << 12) +#define NV04_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE (1 << 16) +#define NV04_MULTITEX_TRIANGLE_BLEND_BLEND_ENABLE (1 << 20) +#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000 +#define NV04_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28 +#define NV04_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0 0x0000033c +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK 0x000000ff +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK 0x00000f00 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_ENABLE (1 << 12) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN (1 << 13) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE (1 << 14) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK 0x000f0000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT 20 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK 0x00300000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_BOTH 0x00000000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_NONE 0x00100000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CW 0x00200000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CCW 0x00300000 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE (1 << 22) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 23) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE (1 << 24) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE (1 << 25) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE (1 << 27) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE (1 << 28) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE (1 << 29) +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT 30 +#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK 0xc0000000 +#define NV04_MULTITEX_TRIANGLE_CONTROL1 0x00000340 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE (1 << 0) +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT 4 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK 0x000000f0 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK 0x0000ff00 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000 +#define NV04_MULTITEX_TRIANGLE_CONTROL2 0x00000344 +#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK 0x0000000f +#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT 4 +#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK 0x000000f0 +#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK 0x00000f00 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR 0x00000348 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK 0xff000000 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x) (0x00000400+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x) (0x00000404+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x) (0x00000408+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x) (0x0000040c+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x) (0x00000410+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK 0x000000ff +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK 0x0000ff00 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK 0x00ff0000 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK 0xff000000 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x) (0x00000414+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK 0x000000ff +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK 0x0000ff00 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK 0x00ff0000 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT 24 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK 0xff000000 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x) (0x00000418+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x) (0x0000041c+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x) (0x00000420+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x) (0x00000424+((x)*40)) +#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE 0x00000008 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE(x) (0x00000540+((x)*4)) +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE__SIZE 0x00000030 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT 0 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_MASK 0x0000000f +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT 4 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_MASK 0x000000f0 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT 8 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_MASK 0x00000f00 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT 12 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_MASK 0x0000f000 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT 16 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_MASK 0x000f0000 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT 20 +#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_MASK 0x00f00000 + + +#define NV10_MULTITEX_TRIANGLE 0x00000095 + + + +#define NV10TCL 0x00000056 + +#define NV10TCL_NOP 0x00000100 +#define NV10TCL_NOTIFY 0x00000104 +#define NV10TCL_DMA_NOTIFY 0x00000180 +#define NV10TCL_DMA_IN_MEMORY0 0x00000184 +#define NV10TCL_DMA_IN_MEMORY1 0x00000188 +#define NV10TCL_DMA_VTXBUF0 0x0000018c +#define NV10TCL_DMA_IN_MEMORY2 0x00000194 +#define NV10TCL_DMA_IN_MEMORY3 0x00000198 +#define NV10TCL_RT_HORIZ 0x00000200 +#define NV10TCL_RT_HORIZ_X_SHIFT 0 +#define NV10TCL_RT_HORIZ_X_MASK 0x0000ffff +#define NV10TCL_RT_HORIZ_W_SHIFT 16 +#define NV10TCL_RT_HORIZ_W_MASK 0xffff0000 +#define NV10TCL_RT_VERT 0x00000204 +#define NV10TCL_RT_VERT_Y_SHIFT 0 +#define NV10TCL_RT_VERT_Y_MASK 0x0000ffff +#define NV10TCL_RT_VERT_H_SHIFT 16 +#define NV10TCL_RT_VERT_H_MASK 0xffff0000 +#define NV10TCL_RT_FORMAT 0x00000208 +#define NV10TCL_RT_FORMAT_TYPE_SHIFT 8 +#define NV10TCL_RT_FORMAT_TYPE_MASK 0x00000f00 +#define NV10TCL_RT_FORMAT_TYPE_LINEAR 0x00000100 +#define NV10TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200 +#define NV10TCL_RT_FORMAT_COLOR_SHIFT 0 +#define NV10TCL_RT_FORMAT_COLOR_MASK 0x0000001f +#define NV10TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003 +#define NV10TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 +#define NV10TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define NV10TCL_RT_FORMAT_COLOR_B8 0x00000009 +#define NV10TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d +#define NV10TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f +#define NV10TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 +#define NV10TCL_RT_PITCH 0x0000020c +#define NV10TCL_RT_PITCH_COLOR_PITCH_SHIFT 0 +#define NV10TCL_RT_PITCH_COLOR_PITCH_MASK 0x0000ffff +#define NV10TCL_RT_PITCH_ZETA_PITCH_SHIFT 16 +#define NV10TCL_RT_PITCH_ZETA_PITCH_MASK 0xffff0000 +#define NV10TCL_COLOR_OFFSET 0x00000210 +#define NV10TCL_ZETA_OFFSET 0x00000214 +#define NV10TCL_TX_OFFSET(x) (0x00000218+((x)*4)) +#define NV10TCL_TX_OFFSET__SIZE 0x00000002 +#define NV10TCL_TX_FORMAT(x) (0x00000220+((x)*4)) +#define NV10TCL_TX_FORMAT__SIZE 0x00000002 +#define NV10TCL_TX_FORMAT_DMA0 (1 << 0) +#define NV10TCL_TX_FORMAT_DMA1 (1 << 1) +#define NV10TCL_TX_FORMAT_CUBE_MAP (1 << 2) +#define NV10TCL_TX_FORMAT_FORMAT_SHIFT 7 +#define NV10TCL_TX_FORMAT_FORMAT_MASK 0x00000f80 +#define NV10TCL_TX_FORMAT_FORMAT_L8 0x00000000 +#define NV10TCL_TX_FORMAT_FORMAT_A8 0x00000080 +#define NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000100 +#define NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000200 +#define NV10TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000280 +#define NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000300 +#define NV10TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000380 +#define NV10TCL_TX_FORMAT_FORMAT_INDEX8 0x00000580 +#define NV10TCL_TX_FORMAT_FORMAT_DXT1 0x00000600 +#define NV10TCL_TX_FORMAT_FORMAT_DXT3 0x00000700 +#define NV10TCL_TX_FORMAT_FORMAT_DXT5 0x00000780 +#define NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00000800 +#define NV10TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00000880 +#define NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00000900 +#define NV10TCL_TX_FORMAT_FORMAT_A8_RECT 0x00000980 +#define NV10TCL_TX_FORMAT_MIPMAP (1 << 15) +#define NV10TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 16 +#define NV10TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x000f0000 +#define NV10TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 20 +#define NV10TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x00f00000 +#define NV10TCL_TX_FORMAT_WRAP_S_SHIFT 24 +#define NV10TCL_TX_FORMAT_WRAP_S_MASK 0x0f000000 +#define NV10TCL_TX_FORMAT_WRAP_S_REPEAT 0x01000000 +#define NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT 0x02000000 +#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE 0x03000000 +#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER 0x04000000 +#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP 0x05000000 +#define NV10TCL_TX_FORMAT_WRAP_T_SHIFT 28 +#define NV10TCL_TX_FORMAT_WRAP_T_MASK 0xf0000000 +#define NV10TCL_TX_FORMAT_WRAP_T_REPEAT 0x10000000 +#define NV10TCL_TX_FORMAT_WRAP_T_MIRRORED_REPEAT 0x20000000 +#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE 0x30000000 +#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER 0x40000000 +#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP 0x50000000 +#define NV10TCL_TX_ENABLE(x) (0x00000228+((x)*4)) +#define NV10TCL_TX_ENABLE__SIZE 0x00000002 +#define NV10TCL_TX_ENABLE_CULL_SHIFT 0 +#define NV10TCL_TX_ENABLE_CULL_MASK 0x0000000f +#define NV10TCL_TX_ENABLE_CULL_DISABLED 0x00000000 +#define NV10TCL_TX_ENABLE_CULL_TEST_ALL 0x00000003 +#define NV10TCL_TX_ENABLE_CULL_TEST_ALPHA 0x00000004 +#define NV10TCL_TX_ENABLE_ANISOTROPY_SHIFT 4 +#define NV10TCL_TX_ENABLE_ANISOTROPY_MASK 0x00000030 +#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14 +#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000 +#define NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26 +#define NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000 +#define NV10TCL_TX_ENABLE_ENABLE (1 << 30) +#define NV10TCL_TX_NPOT_PITCH(x) (0x00000230+((x)*4)) +#define NV10TCL_TX_NPOT_PITCH__SIZE 0x00000002 +#define NV10TCL_TX_NPOT_PITCH_PITCH_SHIFT 16 +#define NV10TCL_TX_NPOT_PITCH_PITCH_MASK 0xffff0000 +#define NV10TCL_TX_NPOT_SIZE(x) (0x00000240+((x)*4)) +#define NV10TCL_TX_NPOT_SIZE__SIZE 0x00000002 +#define NV10TCL_TX_NPOT_SIZE_H_SHIFT 0 +#define NV10TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff +#define NV10TCL_TX_NPOT_SIZE_W_SHIFT 16 +#define NV10TCL_TX_NPOT_SIZE_W_MASK 0xffff0000 +#define NV10TCL_TX_FILTER(x) (0x00000248+((x)*4)) +#define NV10TCL_TX_FILTER__SIZE 0x00000002 +#define NV10TCL_TX_FILTER_LOD_BIAS_SHIFT 8 +#define NV10TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00 +#define NV10TCL_TX_FILTER_MINIFY_SHIFT 24 +#define NV10TCL_TX_FILTER_MINIFY_MASK 0x0f000000 +#define NV10TCL_TX_FILTER_MINIFY_NEAREST 0x01000000 +#define NV10TCL_TX_FILTER_MINIFY_LINEAR 0x02000000 +#define NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000 +#define NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000 +#define NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000 +#define NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000 +#define NV10TCL_TX_FILTER_MAGNIFY_SHIFT 28 +#define NV10TCL_TX_FILTER_MAGNIFY_MASK 0xf0000000 +#define NV10TCL_TX_FILTER_MAGNIFY_NEAREST 0x10000000 +#define NV10TCL_TX_FILTER_MAGNIFY_LINEAR 0x20000000 +#define NV10TCL_TX_PALETTE_OFFSET(x) (0x00000250+((x)*4)) +#define NV10TCL_TX_PALETTE_OFFSET__SIZE 0x00000002 +#define NV10TCL_RC_IN_ALPHA(x) (0x00000260+((x)*4)) +#define NV10TCL_RC_IN_ALPHA__SIZE 0x00000002 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f +#define NV10TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 +#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c +#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d +#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV10TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f +#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a +#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b +#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4) +#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 +#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 +#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 +#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12) +#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 +#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 +#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 +#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20) +#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 +#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 +#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 +#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28) +#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 +#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV10TCL_RC_IN_RGB(x) (0x00000268+((x)*4)) +#define NV10TCL_RC_IN_RGB__SIZE 0x00000002 +#define NV10TCL_RC_IN_RGB_D_INPUT_SHIFT 0 +#define NV10TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f +#define NV10TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV10TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003 +#define NV10TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV10TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 +#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 +#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c +#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d +#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV10TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f +#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a +#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b +#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4) +#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV10TCL_RC_IN_RGB_D_MAPPING_SHIFT 5 +#define NV10TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0 +#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV10TCL_RC_IN_RGB_C_INPUT_SHIFT 8 +#define NV10TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00 +#define NV10TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV10TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300 +#define NV10TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV10TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 +#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 +#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 +#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 +#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV10TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 +#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 +#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 +#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12) +#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_SHIFT 13 +#define NV10TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV10TCL_RC_IN_RGB_B_INPUT_SHIFT 16 +#define NV10TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000 +#define NV10TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV10TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000 +#define NV10TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV10TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 +#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 +#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 +#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 +#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV10TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 +#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 +#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 +#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20) +#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_SHIFT 21 +#define NV10TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV10TCL_RC_IN_RGB_A_INPUT_SHIFT 24 +#define NV10TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 +#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 +#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28) +#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_SHIFT 29 +#define NV10TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV10TCL_RC_COLOR(x) (0x00000270+((x)*4)) +#define NV10TCL_RC_COLOR__SIZE 0x00000002 +#define NV10TCL_RC_COLOR_B_SHIFT 0 +#define NV10TCL_RC_COLOR_B_MASK 0x000000ff +#define NV10TCL_RC_COLOR_G_SHIFT 8 +#define NV10TCL_RC_COLOR_G_MASK 0x0000ff00 +#define NV10TCL_RC_COLOR_R_SHIFT 16 +#define NV10TCL_RC_COLOR_R_MASK 0x00ff0000 +#define NV10TCL_RC_COLOR_A_SHIFT 24 +#define NV10TCL_RC_COLOR_A_MASK 0xff000000 +#define NV10TCL_RC_OUT_ALPHA(x) (0x00000278+((x)*4)) +#define NV10TCL_RC_OUT_ALPHA__SIZE 0x00000002 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV10TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) +#define NV10TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) +#define NV10TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14) +#define NV10TCL_RC_OUT_ALPHA_BIAS (1 << 15) +#define NV10TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000 +#define NV10TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV10TCL_RC_OUT_ALPHA_SCALE_SHIFT 17 +#define NV10TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000 +#define NV10TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000 +#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000 +#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000 +#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000 +#define NV10TCL_RC_OUT_RGB(x) (0x00000280+((x)*4)) +#define NV10TCL_RC_OUT_RGB__SIZE 0x00000002 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV10TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) +#define NV10TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) +#define NV10TCL_RC_OUT_RGB_MUX_SUM (1 << 14) +#define NV10TCL_RC_OUT_RGB_BIAS (1 << 15) +#define NV10TCL_RC_OUT_RGB_BIAS_NONE 0x00000000 +#define NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV10TCL_RC_OUT_RGB_SCALE_SHIFT 17 +#define NV10TCL_RC_OUT_RGB_SCALE_MASK 0x00000000 +#define NV10TCL_RC_OUT_RGB_SCALE_NONE 0x00000000 +#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000 +#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000 +#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000 +#define NV10TCL_RC_OUT_RGB_OPERATION_SHIFT 27 +#define NV10TCL_RC_OUT_RGB_OPERATION_MASK 0x38000000 +#define NV10TCL_RC_FINAL0 0x00000288 +#define NV10TCL_RC_FINAL0_D_INPUT_SHIFT 0 +#define NV10TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f +#define NV10TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV10TCL_RC_FINAL0_D_INPUT_FOG 0x00000003 +#define NV10TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV10TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 +#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 +#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c +#define NV10TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d +#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV10TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f +#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a +#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b +#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4) +#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV10TCL_RC_FINAL0_D_MAPPING_SHIFT 5 +#define NV10TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0 +#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV10TCL_RC_FINAL0_C_INPUT_SHIFT 8 +#define NV10TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00 +#define NV10TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV10TCL_RC_FINAL0_C_INPUT_FOG 0x00000300 +#define NV10TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV10TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 +#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 +#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 +#define NV10TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 +#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV10TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 +#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 +#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 +#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12) +#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV10TCL_RC_FINAL0_C_MAPPING_SHIFT 13 +#define NV10TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000 +#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV10TCL_RC_FINAL0_B_INPUT_SHIFT 16 +#define NV10TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000 +#define NV10TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV10TCL_RC_FINAL0_B_INPUT_FOG 0x00030000 +#define NV10TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV10TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 +#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 +#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 +#define NV10TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 +#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV10TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 +#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 +#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 +#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20) +#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV10TCL_RC_FINAL0_B_MAPPING_SHIFT 21 +#define NV10TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000 +#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV10TCL_RC_FINAL0_A_INPUT_SHIFT 24 +#define NV10TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000 +#define NV10TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV10TCL_RC_FINAL0_A_INPUT_FOG 0x03000000 +#define NV10TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV10TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 +#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 +#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 +#define NV10TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 +#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV10TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 +#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 +#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 +#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28) +#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_SHIFT 29 +#define NV10TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV10TCL_RC_FINAL1 0x0000028c +#define NV10TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) +#define NV10TCL_RC_FINAL1_G_INPUT_SHIFT 8 +#define NV10TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00 +#define NV10TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV10TCL_RC_FINAL1_G_INPUT_FOG 0x00000300 +#define NV10TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 +#define NV10TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 +#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 +#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 +#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 +#define NV10TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 +#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV10TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 +#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 +#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 +#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12) +#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV10TCL_RC_FINAL1_G_MAPPING_SHIFT 13 +#define NV10TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000 +#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV10TCL_RC_FINAL1_F_INPUT_SHIFT 16 +#define NV10TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000 +#define NV10TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV10TCL_RC_FINAL1_F_INPUT_FOG 0x00030000 +#define NV10TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 +#define NV10TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 +#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 +#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 +#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 +#define NV10TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 +#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV10TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 +#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 +#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 +#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20) +#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV10TCL_RC_FINAL1_F_MAPPING_SHIFT 21 +#define NV10TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000 +#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV10TCL_RC_FINAL1_E_INPUT_SHIFT 24 +#define NV10TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000 +#define NV10TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000 +#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV10TCL_RC_FINAL1_E_INPUT_FOG 0x03000000 +#define NV10TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 +#define NV10TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 +#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 +#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 +#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 +#define NV10TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 +#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV10TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 +#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 +#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 +#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28) +#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 +#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_SHIFT 29 +#define NV10TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV10TCL_LIGHT_MODEL 0x00000294 +#define NV10TCL_LIGHT_MODEL_VERTEX_SPECULAR (1 << 0) +#define NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR (1 << 1) +#define NV10TCL_LIGHT_MODEL_LOCAL_VIEWER (1 << 16) +#define NV10TCL_COLOR_MATERIAL 0x00000298 +#define NV10TCL_COLOR_MATERIAL_EMISSION (1 << 0) +#define NV10TCL_COLOR_MATERIAL_AMBIENT (1 << 1) +#define NV10TCL_COLOR_MATERIAL_DIFFUSE (1 << 2) +#define NV10TCL_COLOR_MATERIAL_SPECULAR (1 << 3) +#define NV10TCL_FOG_MODE 0x0000029c +#define NV10TCL_FOG_MODE_LINEAR 0x00002601 +#define NV10TCL_FOG_MODE_EXP 0x00000800 +#define NV10TCL_FOG_MODE_EXP_ABS 0x00000802 +#define NV10TCL_FOG_MODE_EXP2 0x00000803 +#define NV10TCL_FOG_COORD 0x000002a0 +#define NV10TCL_FOG_COORD_FOG 0x00000000 +#define NV10TCL_FOG_COORD_DIST_RADIAL 0x00000001 +#define NV10TCL_FOG_COORD_DIST_ORTHOGONAL 0x00000002 +#define NV10TCL_FOG_COORD_DIST_ORTHOGONAL_ABS 0x00000003 +#define NV10TCL_FOG_ENABLE 0x000002a4 +#define NV10TCL_FOG_COLOR 0x000002a8 +#define NV10TCL_FOG_COLOR_R_SHIFT 0 +#define NV10TCL_FOG_COLOR_R_MASK 0x000000ff +#define NV10TCL_FOG_COLOR_G_SHIFT 8 +#define NV10TCL_FOG_COLOR_G_MASK 0x0000ff00 +#define NV10TCL_FOG_COLOR_B_SHIFT 16 +#define NV10TCL_FOG_COLOR_B_MASK 0x00ff0000 +#define NV10TCL_FOG_COLOR_A_SHIFT 24 +#define NV10TCL_FOG_COLOR_A_MASK 0xff000000 +#define NV10TCL_VIEWPORT_CLIP_MODE 0x000002b4 +#define NV10TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*4)) +#define NV10TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 +#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_SHIFT 0 +#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_MASK 0x000007ff +#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_LEFT_ENABLE (1 << 11) +#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_SHIFT 16 +#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_MASK 0x07ff0000 +#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_RIGHT_ENABLE (1 << 27) +#define NV10TCL_VIEWPORT_CLIP_VERT(x) (0x000002e0+((x)*4)) +#define NV10TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 +#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_SHIFT 0 +#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_MASK 0x000007ff +#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_TOP_ENABLE (1 << 11) +#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_SHIFT 16 +#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_MASK 0x07ff0000 +#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_BOTTOM_ENABLE (1 << 27) +#define NV10TCL_ALPHA_FUNC_ENABLE 0x00000300 +#define NV10TCL_BLEND_FUNC_ENABLE 0x00000304 +#define NV10TCL_CULL_FACE_ENABLE 0x00000308 +#define NV10TCL_DEPTH_TEST_ENABLE 0x0000030c +#define NV10TCL_DITHER_ENABLE 0x00000310 +#define NV10TCL_LIGHTING_ENABLE 0x00000314 +#define NV10TCL_POINT_PARAMETERS_ENABLE 0x00000318 +#define NV10TCL_POINT_SMOOTH_ENABLE 0x0000031c +#define NV10TCL_LINE_SMOOTH_ENABLE 0x00000320 +#define NV10TCL_POLYGON_SMOOTH_ENABLE 0x00000324 +#define NV10TCL_VERTEX_WEIGHT_ENABLE 0x00000328 +#define NV10TCL_STENCIL_ENABLE 0x0000032c +#define NV10TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000330 +#define NV10TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000334 +#define NV10TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000338 +#define NV10TCL_ALPHA_FUNC_FUNC 0x0000033c +#define NV10TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200 +#define NV10TCL_ALPHA_FUNC_FUNC_LESS 0x00000201 +#define NV10TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202 +#define NV10TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 +#define NV10TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204 +#define NV10TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV10TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 +#define NV10TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 +#define NV10TCL_ALPHA_FUNC_REF 0x00000340 +#define NV10TCL_BLEND_FUNC_SRC 0x00000344 +#define NV10TCL_BLEND_FUNC_SRC_ZERO 0x00000000 +#define NV10TCL_BLEND_FUNC_SRC_ONE 0x00000001 +#define NV10TCL_BLEND_FUNC_SRC_SRC_COLOR 0x00000300 +#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA 0x00000302 +#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV10TCL_BLEND_FUNC_SRC_DST_ALPHA 0x00000304 +#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV10TCL_BLEND_FUNC_SRC_DST_COLOR 0x00000306 +#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR 0x00000307 +#define NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE 0x00000308 +#define NV10TCL_BLEND_FUNC_SRC_CONSTANT_COLOR 0x00008001 +#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV10TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA 0x00008003 +#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV10TCL_BLEND_FUNC_DST 0x00000348 +#define NV10TCL_BLEND_FUNC_DST_ZERO 0x00000000 +#define NV10TCL_BLEND_FUNC_DST_ONE 0x00000001 +#define NV10TCL_BLEND_FUNC_DST_SRC_COLOR 0x00000300 +#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV10TCL_BLEND_FUNC_DST_SRC_ALPHA 0x00000302 +#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV10TCL_BLEND_FUNC_DST_DST_ALPHA 0x00000304 +#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV10TCL_BLEND_FUNC_DST_DST_COLOR 0x00000306 +#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR 0x00000307 +#define NV10TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE 0x00000308 +#define NV10TCL_BLEND_FUNC_DST_CONSTANT_COLOR 0x00008001 +#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV10TCL_BLEND_FUNC_DST_CONSTANT_ALPHA 0x00008003 +#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV10TCL_BLEND_COLOR 0x0000034c +#define NV10TCL_BLEND_COLOR_B_SHIFT 0 +#define NV10TCL_BLEND_COLOR_B_MASK 0x000000ff +#define NV10TCL_BLEND_COLOR_G_SHIFT 8 +#define NV10TCL_BLEND_COLOR_G_MASK 0x0000ff00 +#define NV10TCL_BLEND_COLOR_R_SHIFT 16 +#define NV10TCL_BLEND_COLOR_R_MASK 0x00ff0000 +#define NV10TCL_BLEND_COLOR_A_SHIFT 24 +#define NV10TCL_BLEND_COLOR_A_MASK 0xff000000 +#define NV10TCL_BLEND_EQUATION 0x00000350 +#define NV10TCL_BLEND_EQUATION_FUNC_ADD 0x00008006 +#define NV10TCL_BLEND_EQUATION_MIN 0x00008007 +#define NV10TCL_BLEND_EQUATION_MAX 0x00008008 +#define NV10TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a +#define NV10TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b +#define NV10TCL_DEPTH_FUNC 0x00000354 +#define NV10TCL_DEPTH_FUNC_NEVER 0x00000200 +#define NV10TCL_DEPTH_FUNC_LESS 0x00000201 +#define NV10TCL_DEPTH_FUNC_EQUAL 0x00000202 +#define NV10TCL_DEPTH_FUNC_LEQUAL 0x00000203 +#define NV10TCL_DEPTH_FUNC_GREATER 0x00000204 +#define NV10TCL_DEPTH_FUNC_NOTEQUAL 0x00000205 +#define NV10TCL_DEPTH_FUNC_GEQUAL 0x00000206 +#define NV10TCL_DEPTH_FUNC_ALWAYS 0x00000207 +#define NV10TCL_COLOR_MASK 0x00000358 +#define NV10TCL_COLOR_MASK_B (1 << 0) +#define NV10TCL_COLOR_MASK_G (1 << 8) +#define NV10TCL_COLOR_MASK_R (1 << 16) +#define NV10TCL_COLOR_MASK_A (1 << 24) +#define NV10TCL_DEPTH_WRITE_ENABLE 0x0000035c +#define NV10TCL_STENCIL_MASK 0x00000360 +#define NV10TCL_STENCIL_FUNC_FUNC 0x00000364 +#define NV10TCL_STENCIL_FUNC_FUNC_NEVER 0x00000200 +#define NV10TCL_STENCIL_FUNC_FUNC_LESS 0x00000201 +#define NV10TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202 +#define NV10TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203 +#define NV10TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204 +#define NV10TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV10TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206 +#define NV10TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207 +#define NV10TCL_STENCIL_FUNC_REF 0x00000368 +#define NV10TCL_STENCIL_FUNC_MASK 0x0000036c +#define NV10TCL_STENCIL_OP_FAIL 0x00000370 +#define NV10TCL_STENCIL_OP_FAIL_ZERO 0x00000000 +#define NV10TCL_STENCIL_OP_FAIL_INVERT 0x0000150a +#define NV10TCL_STENCIL_OP_FAIL_KEEP 0x00001e00 +#define NV10TCL_STENCIL_OP_FAIL_REPLACE 0x00001e01 +#define NV10TCL_STENCIL_OP_FAIL_INCR 0x00001e02 +#define NV10TCL_STENCIL_OP_FAIL_DECR 0x00001e03 +#define NV10TCL_STENCIL_OP_FAIL_INCR_WRAP 0x00008507 +#define NV10TCL_STENCIL_OP_FAIL_DECR_WRAP 0x00008508 +#define NV10TCL_STENCIL_OP_ZFAIL 0x00000374 +#define NV10TCL_STENCIL_OP_ZFAIL_ZERO 0x00000000 +#define NV10TCL_STENCIL_OP_ZFAIL_INVERT 0x0000150a +#define NV10TCL_STENCIL_OP_ZFAIL_KEEP 0x00001e00 +#define NV10TCL_STENCIL_OP_ZFAIL_REPLACE 0x00001e01 +#define NV10TCL_STENCIL_OP_ZFAIL_INCR 0x00001e02 +#define NV10TCL_STENCIL_OP_ZFAIL_DECR 0x00001e03 +#define NV10TCL_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NV10TCL_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508 +#define NV10TCL_STENCIL_OP_ZPASS 0x00000378 +#define NV10TCL_STENCIL_OP_ZPASS_ZERO 0x00000000 +#define NV10TCL_STENCIL_OP_ZPASS_INVERT 0x0000150a +#define NV10TCL_STENCIL_OP_ZPASS_KEEP 0x00001e00 +#define NV10TCL_STENCIL_OP_ZPASS_REPLACE 0x00001e01 +#define NV10TCL_STENCIL_OP_ZPASS_INCR 0x00001e02 +#define NV10TCL_STENCIL_OP_ZPASS_DECR 0x00001e03 +#define NV10TCL_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507 +#define NV10TCL_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508 +#define NV10TCL_SHADE_MODEL 0x0000037c +#define NV10TCL_SHADE_MODEL_FLAT 0x00001d00 +#define NV10TCL_SHADE_MODEL_SMOOTH 0x00001d01 +#define NV10TCL_LINE_WIDTH 0x00000380 +#define NV10TCL_POLYGON_OFFSET_FACTOR 0x00000384 +#define NV10TCL_POLYGON_OFFSET_UNITS 0x00000388 +#define NV10TCL_POLYGON_MODE_FRONT 0x0000038c +#define NV10TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NV10TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NV10TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 +#define NV10TCL_POLYGON_MODE_BACK 0x00000390 +#define NV10TCL_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NV10TCL_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NV10TCL_POLYGON_MODE_BACK_FILL 0x00001b02 +#define NV10TCL_DEPTH_RANGE_NEAR 0x00000394 +#define NV10TCL_DEPTH_RANGE_FAR 0x00000398 +#define NV10TCL_CULL_FACE 0x0000039c +#define NV10TCL_CULL_FACE_FRONT 0x00000404 +#define NV10TCL_CULL_FACE_BACK 0x00000405 +#define NV10TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 +#define NV10TCL_FRONT_FACE 0x000003a0 +#define NV10TCL_FRONT_FACE_CW 0x00000900 +#define NV10TCL_FRONT_FACE_CCW 0x00000901 +#define NV10TCL_NORMALIZE_ENABLE 0x000003a4 +#define NV10TCL_MATERIAL_FACTOR_R 0x000003a8 +#define NV10TCL_MATERIAL_FACTOR_G 0x000003ac +#define NV10TCL_MATERIAL_FACTOR_B 0x000003b0 +#define NV10TCL_MATERIAL_FACTOR_A 0x000003b4 +#define NV10TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8 +#define NV10TCL_ENABLED_LIGHTS 0x000003bc +#define NV10TCL_ENABLED_LIGHTS_0_SHIFT 0 +#define NV10TCL_ENABLED_LIGHTS_0_MASK 0x00000003 +#define NV10TCL_ENABLED_LIGHTS_0_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_0_NONPOSITIONAL 0x00000001 +#define NV10TCL_ENABLED_LIGHTS_0_POSITIONAL 0x00000002 +#define NV10TCL_ENABLED_LIGHTS_0_DIRECTIONAL 0x00000003 +#define NV10TCL_ENABLED_LIGHTS_1_SHIFT 2 +#define NV10TCL_ENABLED_LIGHTS_1_MASK 0x0000000c +#define NV10TCL_ENABLED_LIGHTS_1_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_1_NONPOSITIONAL 0x00000004 +#define NV10TCL_ENABLED_LIGHTS_1_POSITIONAL 0x00000008 +#define NV10TCL_ENABLED_LIGHTS_1_DIRECTIONAL 0x0000000c +#define NV10TCL_ENABLED_LIGHTS_2_SHIFT 4 +#define NV10TCL_ENABLED_LIGHTS_2_MASK 0x00000030 +#define NV10TCL_ENABLED_LIGHTS_2_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_2_NONPOSITIONAL 0x00000010 +#define NV10TCL_ENABLED_LIGHTS_2_POSITIONAL 0x00000020 +#define NV10TCL_ENABLED_LIGHTS_2_DIRECTIONAL 0x00000030 +#define NV10TCL_ENABLED_LIGHTS_3_SHIFT 6 +#define NV10TCL_ENABLED_LIGHTS_3_MASK 0x000000c0 +#define NV10TCL_ENABLED_LIGHTS_3_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_3_NONPOSITIONAL 0x00000040 +#define NV10TCL_ENABLED_LIGHTS_3_POSITIONAL 0x00000080 +#define NV10TCL_ENABLED_LIGHTS_3_DIRECTIONAL 0x000000c0 +#define NV10TCL_ENABLED_LIGHTS_4_SHIFT 8 +#define NV10TCL_ENABLED_LIGHTS_4_MASK 0x00000300 +#define NV10TCL_ENABLED_LIGHTS_4_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_4_NONPOSITIONAL 0x00000100 +#define NV10TCL_ENABLED_LIGHTS_4_POSITIONAL 0x00000200 +#define NV10TCL_ENABLED_LIGHTS_4_DIRECTIONAL 0x00000300 +#define NV10TCL_ENABLED_LIGHTS_5_SHIFT 10 +#define NV10TCL_ENABLED_LIGHTS_5_MASK 0x00000c00 +#define NV10TCL_ENABLED_LIGHTS_5_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_5_NONPOSITIONAL 0x00000400 +#define NV10TCL_ENABLED_LIGHTS_5_POSITIONAL 0x00000800 +#define NV10TCL_ENABLED_LIGHTS_5_DIRECTIONAL 0x00000c00 +#define NV10TCL_ENABLED_LIGHTS_6_SHIFT 12 +#define NV10TCL_ENABLED_LIGHTS_6_MASK 0x00003000 +#define NV10TCL_ENABLED_LIGHTS_6_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_6_NONPOSITIONAL 0x00001000 +#define NV10TCL_ENABLED_LIGHTS_6_POSITIONAL 0x00002000 +#define NV10TCL_ENABLED_LIGHTS_6_DIRECTIONAL 0x00003000 +#define NV10TCL_ENABLED_LIGHTS_7_SHIFT 14 +#define NV10TCL_ENABLED_LIGHTS_7_MASK 0x0000c000 +#define NV10TCL_ENABLED_LIGHTS_7_DISABLED 0x00000000 +#define NV10TCL_ENABLED_LIGHTS_7_NONPOSITIONAL 0x00004000 +#define NV10TCL_ENABLED_LIGHTS_7_POSITIONAL 0x00008000 +#define NV10TCL_ENABLED_LIGHTS_7_DIRECTIONAL 0x0000c000 +#define NV10TCL_TX_GEN_MODE_S(x) (0x000003c0+((x)*16)) +#define NV10TCL_TX_GEN_MODE_S__SIZE 0x00000002 +#define NV10TCL_TX_GEN_MODE_S_FALSE 0x00000000 +#define NV10TCL_TX_GEN_MODE_S_EYE_LINEAR 0x00002400 +#define NV10TCL_TX_GEN_MODE_S_OBJECT_LINEAR 0x00002401 +#define NV10TCL_TX_GEN_MODE_S_SPHERE_MAP 0x00002402 +#define NV10TCL_TX_GEN_MODE_S_NORMAL_MAP 0x00008511 +#define NV10TCL_TX_GEN_MODE_S_REFLECTION_MAP 0x00008512 +#define NV10TCL_TX_GEN_MODE_T(x) (0x000003c4+((x)*16)) +#define NV10TCL_TX_GEN_MODE_T__SIZE 0x00000002 +#define NV10TCL_TX_GEN_MODE_T_FALSE 0x00000000 +#define NV10TCL_TX_GEN_MODE_T_EYE_LINEAR 0x00002400 +#define NV10TCL_TX_GEN_MODE_T_OBJECT_LINEAR 0x00002401 +#define NV10TCL_TX_GEN_MODE_T_SPHERE_MAP 0x00002402 +#define NV10TCL_TX_GEN_MODE_T_NORMAL_MAP 0x00008511 +#define NV10TCL_TX_GEN_MODE_T_REFLECTION_MAP 0x00008512 +#define NV10TCL_TX_GEN_MODE_R(x) (0x000003c8+((x)*16)) +#define NV10TCL_TX_GEN_MODE_R__SIZE 0x00000002 +#define NV10TCL_TX_GEN_MODE_R_FALSE 0x00000000 +#define NV10TCL_TX_GEN_MODE_R_EYE_LINEAR 0x00002400 +#define NV10TCL_TX_GEN_MODE_R_OBJECT_LINEAR 0x00002401 +#define NV10TCL_TX_GEN_MODE_R_SPHERE_MAP 0x00002402 +#define NV10TCL_TX_GEN_MODE_R_NORMAL_MAP 0x00008511 +#define NV10TCL_TX_GEN_MODE_R_REFLECTION_MAP 0x00008512 +#define NV10TCL_TX_GEN_MODE_Q(x) (0x000003cc+((x)*16)) +#define NV10TCL_TX_GEN_MODE_Q__SIZE 0x00000002 +#define NV10TCL_TX_GEN_MODE_Q_FALSE 0x00000000 +#define NV10TCL_TX_GEN_MODE_Q_EYE_LINEAR 0x00002400 +#define NV10TCL_TX_GEN_MODE_Q_OBJECT_LINEAR 0x00002401 +#define NV10TCL_TX_GEN_MODE_Q_SPHERE_MAP 0x00002402 +#define NV10TCL_TX_GEN_MODE_Q_NORMAL_MAP 0x00008511 +#define NV10TCL_TX_GEN_MODE_Q_REFLECTION_MAP 0x00008512 +#define NV10TCL_TX_MATRIX_ENABLE(x) (0x000003e0+((x)*4)) +#define NV10TCL_TX_MATRIX_ENABLE__SIZE 0x00000002 +#define NV10TCL_VIEW_MATRIX_ENABLE 0x000003e8 +#define NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW1 (1 << 0) +#define NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW0 (1 << 1) +#define NV10TCL_VIEW_MATRIX_ENABLE_PROJECTION (1 << 2) +#define NV10TCL_POINT_SIZE 0x000003ec +#define NV10TCL_MODELVIEW0_MATRIX(x) (0x00000400+((x)*4)) +#define NV10TCL_MODELVIEW0_MATRIX__SIZE 0x00000010 +#define NV10TCL_MODELVIEW1_MATRIX(x) (0x00000440+((x)*4)) +#define NV10TCL_MODELVIEW1_MATRIX__SIZE 0x00000010 +#define NV10TCL_INVERSE_MODELVIEW0_MATRIX(x) (0x00000480+((x)*4)) +#define NV10TCL_INVERSE_MODELVIEW0_MATRIX__SIZE 0x00000010 +#define NV10TCL_INVERSE_MODELVIEW1_MATRIX(x) (0x000004c0+((x)*4)) +#define NV10TCL_INVERSE_MODELVIEW1_MATRIX__SIZE 0x00000010 +#define NV10TCL_PROJECTION_MATRIX(x) (0x00000500+((x)*4)) +#define NV10TCL_PROJECTION_MATRIX__SIZE 0x00000010 +#define NV10TCL_TX0_MATRIX(x) (0x00000540+((x)*4)) +#define NV10TCL_TX0_MATRIX__SIZE 0x00000010 +#define NV10TCL_TX1_MATRIX(x) (0x00000580+((x)*4)) +#define NV10TCL_TX1_MATRIX__SIZE 0x00000010 +#define NV10TCL_TX_GEN_COEFF_S_A(x) (0x00000600+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_S_A__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_S_B(x) (0x00000604+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_S_B__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_S_C(x) (0x00000608+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_S_C__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_S_D(x) (0x0000060c+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_S_D__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_T_A(x) (0x00000610+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_T_A__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_T_B(x) (0x00000614+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_T_B__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_T_C(x) (0x00000618+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_T_C__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_T_D(x) (0x0000061c+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_T_D__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_R_A(x) (0x00000620+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_R_A__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_R_B(x) (0x00000624+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_R_B__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_R_C(x) (0x00000628+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_R_C__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_R_D(x) (0x0000062c+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_R_D__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_Q_A(x) (0x00000630+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_Q_A__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_Q_B(x) (0x00000634+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_Q_B__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_Q_C(x) (0x00000638+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_Q_C__SIZE 0x00000002 +#define NV10TCL_TX_GEN_COEFF_Q_D(x) (0x0000063c+((x)*64)) +#define NV10TCL_TX_GEN_COEFF_Q_D__SIZE 0x00000002 +#define NV10TCL_FOG_EQUATION_CONSTANT 0x00000680 +#define NV10TCL_FOG_EQUATION_LINEAR 0x00000684 +#define NV10TCL_FOG_EQUATION_QUADRATIC 0x00000688 +#define NV10TCL_MATERIAL_SHININESS(x) (0x000006a0+((x)*4)) +#define NV10TCL_MATERIAL_SHININESS__SIZE 0x00000006 +#define NV10TCL_LIGHT_MODEL_AMBIENT_R 0x000006c4 +#define NV10TCL_LIGHT_MODEL_AMBIENT_G 0x000006c8 +#define NV10TCL_LIGHT_MODEL_AMBIENT_B 0x000006cc +#define NV10TCL_VIEWPORT_TRANSLATE_X 0x000006e8 +#define NV10TCL_VIEWPORT_TRANSLATE_Y 0x000006ec +#define NV10TCL_VIEWPORT_TRANSLATE_Z 0x000006f0 +#define NV10TCL_VIEWPORT_TRANSLATE_W 0x000006f4 +#define NV10TCL_POINT_PARAMETER(x) (0x000006f8+((x)*4)) +#define NV10TCL_POINT_PARAMETER__SIZE 0x00000008 +#define NV10TCL_LIGHT_AMBIENT_R(x) (0x00000800+((x)*128)) +#define NV10TCL_LIGHT_AMBIENT_R__SIZE 0x00000008 +#define NV10TCL_LIGHT_AMBIENT_G(x) (0x00000804+((x)*128)) +#define NV10TCL_LIGHT_AMBIENT_G__SIZE 0x00000008 +#define NV10TCL_LIGHT_AMBIENT_B(x) (0x00000808+((x)*128)) +#define NV10TCL_LIGHT_AMBIENT_B__SIZE 0x00000008 +#define NV10TCL_LIGHT_DIFFUSE_R(x) (0x0000080c+((x)*128)) +#define NV10TCL_LIGHT_DIFFUSE_R__SIZE 0x00000008 +#define NV10TCL_LIGHT_DIFFUSE_G(x) (0x00000810+((x)*128)) +#define NV10TCL_LIGHT_DIFFUSE_G__SIZE 0x00000008 +#define NV10TCL_LIGHT_DIFFUSE_B(x) (0x00000814+((x)*128)) +#define NV10TCL_LIGHT_DIFFUSE_B__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPECULAR_R(x) (0x00000818+((x)*128)) +#define NV10TCL_LIGHT_SPECULAR_R__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPECULAR_G(x) (0x0000081c+((x)*128)) +#define NV10TCL_LIGHT_SPECULAR_G__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPECULAR_B(x) (0x00000820+((x)*128)) +#define NV10TCL_LIGHT_SPECULAR_B__SIZE 0x00000008 +#define NV10TCL_LIGHT_HALF_VECTOR_X(x) (0x00000828+((x)*128)) +#define NV10TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008 +#define NV10TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000082c+((x)*128)) +#define NV10TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008 +#define NV10TCL_LIGHT_HALF_VECTOR_Z(x) (0x00000830+((x)*128)) +#define NV10TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008 +#define NV10TCL_LIGHT_DIRECTION_X(x) (0x00000834+((x)*128)) +#define NV10TCL_LIGHT_DIRECTION_X__SIZE 0x00000008 +#define NV10TCL_LIGHT_DIRECTION_Y(x) (0x00000838+((x)*128)) +#define NV10TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008 +#define NV10TCL_LIGHT_DIRECTION_Z(x) (0x0000083c+((x)*128)) +#define NV10TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00000840+((x)*128)) +#define NV10TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00000844+((x)*128)) +#define NV10TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00000848+((x)*128)) +#define NV10TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_DIR_X(x) (0x0000084c+((x)*128)) +#define NV10TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_DIR_Y(x) (0x00000850+((x)*128)) +#define NV10TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_DIR_Z(x) (0x00000854+((x)*128)) +#define NV10TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008 +#define NV10TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00000858+((x)*128)) +#define NV10TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008 +#define NV10TCL_LIGHT_POSITION_X(x) (0x0000085c+((x)*128)) +#define NV10TCL_LIGHT_POSITION_X__SIZE 0x00000008 +#define NV10TCL_LIGHT_POSITION_Y(x) (0x00000860+((x)*128)) +#define NV10TCL_LIGHT_POSITION_Y__SIZE 0x00000008 +#define NV10TCL_LIGHT_POSITION_Z(x) (0x00000864+((x)*128)) +#define NV10TCL_LIGHT_POSITION_Z__SIZE 0x00000008 +#define NV10TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00000868+((x)*128)) +#define NV10TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008 +#define NV10TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000086c+((x)*128)) +#define NV10TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008 +#define NV10TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00000870+((x)*128)) +#define NV10TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008 +#define NV10TCL_VERTEX_POS_3F_X 0x00000c00 +#define NV10TCL_VERTEX_POS_3F_Y 0x00000c04 +#define NV10TCL_VERTEX_POS_3F_Z 0x00000c08 +#define NV10TCL_VERTEX_POS_4F_X 0x00000c18 +#define NV10TCL_VERTEX_POS_4F_Y 0x00000c1c +#define NV10TCL_VERTEX_POS_4F_Z 0x00000c20 +#define NV10TCL_VERTEX_POS_4F_W 0x00000c24 +#define NV10TCL_VERTEX_NOR_3F_X 0x00000c30 +#define NV10TCL_VERTEX_NOR_3F_Y 0x00000c34 +#define NV10TCL_VERTEX_NOR_3F_Z 0x00000c38 +#define NV10TCL_VERTEX_NOR_3I_XY 0x00000c40 +#define NV10TCL_VERTEX_NOR_3I_XY_X_SHIFT 0 +#define NV10TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff +#define NV10TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16 +#define NV10TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 +#define NV10TCL_VERTEX_NOR_3I_Z 0x00000c44 +#define NV10TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0 +#define NV10TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff +#define NV10TCL_VERTEX_COL_4F_R 0x00000c50 +#define NV10TCL_VERTEX_COL_4F_G 0x00000c54 +#define NV10TCL_VERTEX_COL_4F_B 0x00000c58 +#define NV10TCL_VERTEX_COL_4F_A 0x00000c5c +#define NV10TCL_VERTEX_COL_3F_R 0x00000c60 +#define NV10TCL_VERTEX_COL_3F_G 0x00000c64 +#define NV10TCL_VERTEX_COL_3F_B 0x00000c68 +#define NV10TCL_VERTEX_COL_4I 0x00000c6c +#define NV10TCL_VERTEX_COL_4I_R_SHIFT 0 +#define NV10TCL_VERTEX_COL_4I_R_MASK 0x000000ff +#define NV10TCL_VERTEX_COL_4I_G_SHIFT 8 +#define NV10TCL_VERTEX_COL_4I_G_MASK 0x0000ff00 +#define NV10TCL_VERTEX_COL_4I_B_SHIFT 16 +#define NV10TCL_VERTEX_COL_4I_B_MASK 0x00ff0000 +#define NV10TCL_VERTEX_COL_4I_A_SHIFT 24 +#define NV10TCL_VERTEX_COL_4I_A_MASK 0xff000000 +#define NV10TCL_VERTEX_COL2_3F_R 0x00000c80 +#define NV10TCL_VERTEX_COL2_3F_G 0x00000c84 +#define NV10TCL_VERTEX_COL2_3F_B 0x00000c88 +#define NV10TCL_VERTEX_COL2_3I 0x00000c8c +#define NV10TCL_VERTEX_COL2_3I_R_SHIFT 0 +#define NV10TCL_VERTEX_COL2_3I_R_MASK 0x000000ff +#define NV10TCL_VERTEX_COL2_3I_G_SHIFT 8 +#define NV10TCL_VERTEX_COL2_3I_G_MASK 0x0000ff00 +#define NV10TCL_VERTEX_COL2_3I_B_SHIFT 16 +#define NV10TCL_VERTEX_COL2_3I_B_MASK 0x00ff0000 +#define NV10TCL_VERTEX_TX0_2F_S 0x00000c90 +#define NV10TCL_VERTEX_TX0_2F_T 0x00000c94 +#define NV10TCL_VERTEX_TX0_2I 0x00000c98 +#define NV10TCL_VERTEX_TX0_2I_S_SHIFT 0 +#define NV10TCL_VERTEX_TX0_2I_S_MASK 0x0000ffff +#define NV10TCL_VERTEX_TX0_2I_T_SHIFT 16 +#define NV10TCL_VERTEX_TX0_2I_T_MASK 0xffff0000 +#define NV10TCL_VERTEX_TX0_4F_S 0x00000ca0 +#define NV10TCL_VERTEX_TX0_4F_T 0x00000ca4 +#define NV10TCL_VERTEX_TX0_4F_R 0x00000ca8 +#define NV10TCL_VERTEX_TX0_4F_Q 0x00000cac +#define NV10TCL_VERTEX_TX0_4I_ST 0x00000cb0 +#define NV10TCL_VERTEX_TX0_4I_ST_S_SHIFT 0 +#define NV10TCL_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff +#define NV10TCL_VERTEX_TX0_4I_ST_T_SHIFT 16 +#define NV10TCL_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 +#define NV10TCL_VERTEX_TX0_4I_RQ 0x00000cb4 +#define NV10TCL_VERTEX_TX0_4I_RQ_R_SHIFT 0 +#define NV10TCL_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff +#define NV10TCL_VERTEX_TX0_4I_RQ_Q_SHIFT 16 +#define NV10TCL_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 +#define NV10TCL_VERTEX_TX1_2F_S 0x00000cb8 +#define NV10TCL_VERTEX_TX1_2F_T 0x00000cbc +#define NV10TCL_VERTEX_TX1_2I 0x00000cc0 +#define NV10TCL_VERTEX_TX1_2I_S_SHIFT 0 +#define NV10TCL_VERTEX_TX1_2I_S_MASK 0x0000ffff +#define NV10TCL_VERTEX_TX1_2I_T_SHIFT 16 +#define NV10TCL_VERTEX_TX1_2I_T_MASK 0xffff0000 +#define NV10TCL_VERTEX_TX1_4F_S 0x00000cc8 +#define NV10TCL_VERTEX_TX1_4F_T 0x00000ccc +#define NV10TCL_VERTEX_TX1_4F_R 0x00000cd0 +#define NV10TCL_VERTEX_TX1_4F_Q 0x00000cd4 +#define NV10TCL_VERTEX_TX1_4I_ST 0x00000cd8 +#define NV10TCL_VERTEX_TX1_4I_ST_S_SHIFT 0 +#define NV10TCL_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff +#define NV10TCL_VERTEX_TX1_4I_ST_T_SHIFT 16 +#define NV10TCL_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 +#define NV10TCL_VERTEX_TX1_4I_RQ 0x00000cdc +#define NV10TCL_VERTEX_TX1_4I_RQ_R_SHIFT 0 +#define NV10TCL_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff +#define NV10TCL_VERTEX_TX1_4I_RQ_Q_SHIFT 16 +#define NV10TCL_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 +#define NV10TCL_VERTEX_FOG_1F 0x00000ce0 +#define NV10TCL_VERTEX_WGH_1F 0x00000ce4 +#define NV10TCL_EDGEFLAG_ENABLE 0x00000cec +#define NV10TCL_VERTEX_ARRAY_VALIDATE 0x00000cf0 +#define NV10TCL_VTXBUF_ADDRESS(x) (0x00000d00+((x)*8)) +#define NV10TCL_VTXBUF_ADDRESS__SIZE 0x00000008 +#define NV10TCL_VTXFMT(x) (0x00000d04+((x)*8)) +#define NV10TCL_VTXFMT__SIZE 0x00000008 +#define NV10TCL_VTXFMT_TYPE_SHIFT 0 +#define NV10TCL_VTXFMT_TYPE_MASK 0x0000000f +#define NV10TCL_VTXFMT_TYPE_BYTE_BGRA 0x00000000 +#define NV10TCL_VTXFMT_TYPE_SHORT 0x00000001 +#define NV10TCL_VTXFMT_TYPE_FLOAT 0x00000002 +#define NV10TCL_VTXFMT_TYPE_BYTE_RGBA 0x00000004 +#define NV10TCL_VTXFMT_FIELDS_SHIFT 4 +#define NV10TCL_VTXFMT_FIELDS_MASK 0x000000f0 +#define NV10TCL_VTXFMT_STRIDE_SHIFT 8 +#define NV10TCL_VTXFMT_STRIDE_MASK 0x0000ff00 +#define NV10TCL_VTXFMT_POS_HOMOGENEOUS (1 << 24) +#define NV10TCL_VERTEX_BEGIN_END 0x00000dfc +#define NV10TCL_VERTEX_BEGIN_END_STOP 0x00000000 +#define NV10TCL_VERTEX_BEGIN_END_POINTS 0x00000001 +#define NV10TCL_VERTEX_BEGIN_END_LINES 0x00000002 +#define NV10TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 +#define NV10TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 +#define NV10TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005 +#define NV10TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 +#define NV10TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 +#define NV10TCL_VERTEX_BEGIN_END_QUADS 0x00000008 +#define NV10TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 +#define NV10TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a +#define NV10TCL_VB_ELEMENT_U16 0x00000e00 +#define NV10TCL_VB_ELEMENT_U16_I0_SHIFT 0 +#define NV10TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff +#define NV10TCL_VB_ELEMENT_U16_I1_SHIFT 16 +#define NV10TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 +#define NV10TCL_VB_ELEMENT_U32 0x00001100 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END 0x000013fc +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_STOP 0x00000000 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_POINTS 0x00000001 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINES 0x00000002 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_LOOP 0x00000003 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_STRIP 0x00000004 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLES 0x00000005 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_STRIP 0x00000006 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_FAN 0x00000007 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_QUADS 0x00000008 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_QUAD_STRIP 0x00000009 +#define NV10TCL_VERTEX_BUFFER_BEGIN_END_POLYGON 0x0000000a +#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS 0x00001400 +#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_SHIFT 0 +#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK 0x0000ffff +#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_SHIFT 24 +#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_MASK 0xff000000 +#define NV10TCL_VERTEX_ARRAY_DATA 0x00001800 + + +#define NV11TCL 0x00000096 + +#define NV11TCL_COLOR_LOGIC_OP_ENABLE 0x00000d40 +#define NV11TCL_COLOR_LOGIC_OP_OP 0x00000d44 +#define NV11TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 +#define NV11TCL_COLOR_LOGIC_OP_OP_AND 0x00001501 +#define NV11TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 +#define NV11TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503 +#define NV11TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 +#define NV11TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505 +#define NV11TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506 +#define NV11TCL_COLOR_LOGIC_OP_OP_OR 0x00001507 +#define NV11TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508 +#define NV11TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 +#define NV11TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a +#define NV11TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b +#define NV11TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c +#define NV11TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d +#define NV11TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e +#define NV11TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f + + +#define NV17TCL 0x00000099 + +#define NV17TCL_DMA_IN_MEMORY4 0x000001ac +#define NV17TCL_DMA_IN_MEMORY5 0x000001b0 +#define NV17TCL_COLOR_MASK_ENABLE 0x000002bc +#define NV17TCL_LMA_DEPTH_BUFFER_PITCH 0x00000d5c +#define NV17TCL_LMA_DEPTH_BUFFER_OFFSET 0x00000d60 +#define NV17TCL_LMA_DEPTH_FILL_VALUE 0x00000d68 +#define NV17TCL_LMA_DEPTH_BUFFER_CLEAR 0x00000d6c +#define NV17TCL_LMA_DEPTH_WINDOW_X 0x00001638 +#define NV17TCL_LMA_DEPTH_WINDOW_Y 0x0000163c +#define NV17TCL_LMA_DEPTH_WINDOW_Z 0x00001640 +#define NV17TCL_LMA_DEPTH_WINDOW_W 0x00001644 +#define NV17TCL_LMA_DEPTH_ENABLE 0x00001658 + + +#define NV03_CONTEXT_SURFACES_2D 0x00000058 + +#define NV03_CONTEXT_SURFACES_2D_SYNCHRONIZE 0x00000100 +#define NV03_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180 +#define NV03_CONTEXT_SURFACES_2D_DMA_SOURCE 0x00000184 +#define NV03_CONTEXT_SURFACES_2D_DMA_DESTIN 0x00000188 +#define NV03_CONTEXT_SURFACES_2D_COLOR_FORMAT 0x00000300 +#define NV03_CONTEXT_SURFACES_2D_PITCH 0x00000304 +#define NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT 0 +#define NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK 0x0000ffff +#define NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT 16 +#define NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK 0xffff0000 +#define NV03_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308 +#define NV03_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c + + +#define NV03_CONTEXT_SURFACES_3D 0x0000005a + +#define NV03_CONTEXT_SURFACES_3D_SYNCHRONIZE 0x00000100 +#define NV03_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180 +#define NV03_CONTEXT_SURFACES_3D_DMA_SURFACE 0x00000184 +#define NV03_CONTEXT_SURFACES_3D_PITCH 0x00000300 +#define NV03_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x00000304 +#define NV03_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000308 + + +#define NV04_INDEXED_IMAGE_FROM_CPU 0x00000060 + +#define NV04_INDEXED_IMAGE_FROM_CPU_NOP 0x00000100 +#define NV04_INDEXED_IMAGE_FROM_CPU_NOTIFY 0x00000104 +#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c +#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 +#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184 +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188 +#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c +#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190 +#define NV04_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194 +#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198 +#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c +#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0 +#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4 +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8 +#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec +#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0 +#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4 +#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8 +#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000700 + + +#define NV05_INDEXED_IMAGE_FROM_CPU 0x00000064 + +#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0 + + +#define NV03_CHANNEL_PIO 0x0000006a + + + +#define NV03_CHANNEL_DMA 0x0000006b + + + +#define NV04_BETA_SOLID 0x00000072 + +#define NV04_BETA_SOLID_NOP 0x00000100 +#define NV04_BETA_SOLID_NOTIFY 0x00000104 +#define NV04_BETA_SOLID_DMA_NOTIFY 0x00000180 +#define NV04_BETA_SOLID_BETA_OUTPUT 0x00000200 +#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300 + + +#define NV10_TEXTURE_FROM_CPU 0x0000007b + +#define NV10_TEXTURE_FROM_CPU_NOP 0x00000100 +#define NV10_TEXTURE_FROM_CPU_NOTIFY 0x00000104 +#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 +#define NV10_TEXTURE_FROM_CPU_PM_TRIGGER 0x00000140 +#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY 0x00000180 +#define NV10_TEXTURE_FROM_CPU_SURFACE 0x00000184 +#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT 0x00000300 +#define NV10_TEXTURE_FROM_CPU_POINT 0x00000304 +#define NV10_TEXTURE_FROM_CPU_POINT_X_SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_POINT_X_MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_POINT_Y_SHIFT 16 +#define NV10_TEXTURE_FROM_CPU_POINT_Y_MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_SIZE 0x00000308 +#define NV10_TEXTURE_FROM_CPU_SIZE_W_SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_SIZE_W_MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_SIZE_H_SHIFT 16 +#define NV10_TEXTURE_FROM_CPU_SIZE_H_MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL 0x0000030c +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_SHIFT 16 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL 0x00000310 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_SHIFT 16 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) +#define NV10_TEXTURE_FROM_CPU_COLOR__SIZE 0x00000700 + + +#define NV30_TEXTURE_FROM_CPU 0x0000037b + + + +#define NV40_TEXTURE_FROM_CPU 0x0000307b + + + +#define NV10_VIDEO_DISPLAY 0x0000007c + + + +#define NV20TCL 0x00000097 + +#define NV20TCL_NOP 0x00000100 +#define NV20TCL_NOTIFY 0x00000104 +#define NV20TCL_DMA_NOTIFY 0x00000180 +#define NV20TCL_DMA_TEXTURE0 0x00000184 +#define NV20TCL_DMA_TEXTURE1 0x00000188 +#define NV20TCL_DMA_COLOR 0x00000194 +#define NV20TCL_DMA_ZETA 0x00000198 +#define NV20TCL_DMA_VTXBUF0 0x0000019c +#define NV20TCL_DMA_VTXBUF1 0x000001a0 +#define NV20TCL_DMA_FENCE 0x000001a4 +#define NV20TCL_DMA_QUERY 0x000001a8 +#define NV20TCL_RT_HORIZ 0x00000200 +#define NV20TCL_RT_HORIZ_X_SHIFT 0 +#define NV20TCL_RT_HORIZ_X_MASK 0x0000ffff +#define NV20TCL_RT_HORIZ_W_SHIFT 16 +#define NV20TCL_RT_HORIZ_W_MASK 0xffff0000 +#define NV20TCL_RT_VERT 0x00000204 +#define NV20TCL_RT_VERT_Y_SHIFT 0 +#define NV20TCL_RT_VERT_Y_MASK 0x0000ffff +#define NV20TCL_RT_VERT_H_SHIFT 16 +#define NV20TCL_RT_VERT_H_MASK 0xffff0000 +#define NV20TCL_RT_FORMAT 0x00000208 +#define NV20TCL_RT_FORMAT_TYPE_SHIFT 8 +#define NV20TCL_RT_FORMAT_TYPE_MASK 0x00000f00 +#define NV20TCL_RT_FORMAT_TYPE_LINEAR 0x00000100 +#define NV20TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200 +#define NV20TCL_RT_FORMAT_COLOR_SHIFT 0 +#define NV20TCL_RT_FORMAT_COLOR_MASK 0x0000001f +#define NV20TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003 +#define NV20TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 +#define NV20TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define NV20TCL_RT_FORMAT_COLOR_B8 0x00000009 +#define NV20TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d +#define NV20TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f +#define NV20TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 +#define NV20TCL_RT_PITCH 0x0000020c +#define NV20TCL_RT_PITCH_COLOR_PITCH_SHIFT 0 +#define NV20TCL_RT_PITCH_COLOR_PITCH_MASK 0x0000ffff +#define NV20TCL_RT_PITCH_ZETA_PITCH_SHIFT 16 +#define NV20TCL_RT_PITCH_ZETA_PITCH_MASK 0xffff0000 +#define NV20TCL_COLOR_OFFSET 0x00000210 +#define NV20TCL_ZETA_OFFSET 0x00000214 +#define NV20TCL_RC_IN_ALPHA(x) (0x00000260+((x)*4)) +#define NV20TCL_RC_IN_ALPHA__SIZE 0x00000008 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f +#define NV20TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 +#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c +#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d +#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV20TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f +#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a +#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b +#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4) +#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 +#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 +#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 +#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12) +#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 +#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 +#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 +#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20) +#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 +#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 +#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 +#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28) +#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 +#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV20TCL_RC_FINAL0 0x00000288 +#define NV20TCL_RC_FINAL0_D_INPUT_SHIFT 0 +#define NV20TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f +#define NV20TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV20TCL_RC_FINAL0_D_INPUT_FOG 0x00000003 +#define NV20TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV20TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 +#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 +#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c +#define NV20TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d +#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV20TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f +#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a +#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b +#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4) +#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV20TCL_RC_FINAL0_D_MAPPING_SHIFT 5 +#define NV20TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0 +#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV20TCL_RC_FINAL0_C_INPUT_SHIFT 8 +#define NV20TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00 +#define NV20TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV20TCL_RC_FINAL0_C_INPUT_FOG 0x00000300 +#define NV20TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV20TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 +#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 +#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 +#define NV20TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 +#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV20TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 +#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 +#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 +#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12) +#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV20TCL_RC_FINAL0_C_MAPPING_SHIFT 13 +#define NV20TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000 +#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV20TCL_RC_FINAL0_B_INPUT_SHIFT 16 +#define NV20TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000 +#define NV20TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV20TCL_RC_FINAL0_B_INPUT_FOG 0x00030000 +#define NV20TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV20TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 +#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 +#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 +#define NV20TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 +#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV20TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 +#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 +#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 +#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20) +#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV20TCL_RC_FINAL0_B_MAPPING_SHIFT 21 +#define NV20TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000 +#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV20TCL_RC_FINAL0_A_INPUT_SHIFT 24 +#define NV20TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000 +#define NV20TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV20TCL_RC_FINAL0_A_INPUT_FOG 0x03000000 +#define NV20TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV20TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 +#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 +#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 +#define NV20TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 +#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV20TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 +#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 +#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 +#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28) +#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_SHIFT 29 +#define NV20TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV20TCL_RC_FINAL1 0x0000028c +#define NV20TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) +#define NV20TCL_RC_FINAL1_G_INPUT_SHIFT 8 +#define NV20TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00 +#define NV20TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV20TCL_RC_FINAL1_G_INPUT_FOG 0x00000300 +#define NV20TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 +#define NV20TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 +#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 +#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 +#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 +#define NV20TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 +#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV20TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 +#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 +#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 +#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12) +#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV20TCL_RC_FINAL1_G_MAPPING_SHIFT 13 +#define NV20TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000 +#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV20TCL_RC_FINAL1_F_INPUT_SHIFT 16 +#define NV20TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000 +#define NV20TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV20TCL_RC_FINAL1_F_INPUT_FOG 0x00030000 +#define NV20TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 +#define NV20TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 +#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 +#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 +#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 +#define NV20TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 +#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV20TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 +#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 +#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 +#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20) +#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV20TCL_RC_FINAL1_F_MAPPING_SHIFT 21 +#define NV20TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000 +#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV20TCL_RC_FINAL1_E_INPUT_SHIFT 24 +#define NV20TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000 +#define NV20TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV20TCL_RC_FINAL1_E_INPUT_FOG 0x03000000 +#define NV20TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 +#define NV20TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 +#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 +#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 +#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 +#define NV20TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 +#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV20TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 +#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 +#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 +#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28) +#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_SHIFT 29 +#define NV20TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV20TCL_LIGHT_MODEL 0x00000294 +#define NV20TCL_LIGHT_MODEL_VIEWER_SHIFT 16 +#define NV20TCL_LIGHT_MODEL_VIEWER_MASK 0x00030000 +#define NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL 0x00020000 +#define NV20TCL_LIGHT_MODEL_VIEWER_LOCAL 0x00030000 +#define NV20TCL_LIGHT_MODEL_SEPARATE_SPECULAR (1 << 0) +#define NV20TCL_COLOR_MATERIAL 0x00000298 +#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_SHIFT 0 +#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_MASK 0x00000003 +#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL1 0x00000001 +#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL2 0x00000002 +#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_SHIFT 2 +#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_MASK 0x0000000c +#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL1 0x00000004 +#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL2 0x00000008 +#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_SHIFT 4 +#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_MASK 0x00000030 +#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL1 0x00000010 +#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL2 0x00000020 +#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_SHIFT 6 +#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_MASK 0x000000c0 +#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL1 0x00000040 +#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL2 0x00000080 +#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_SHIFT 8 +#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_MASK 0x00000300 +#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL1 0x00000100 +#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL2 0x00000200 +#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_SHIFT 10 +#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_MASK 0x00000c00 +#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL1 0x00000400 +#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL2 0x00000800 +#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_SHIFT 12 +#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_MASK 0x00003000 +#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL1 0x00001000 +#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL2 0x00002000 +#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_SHIFT 14 +#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_MASK 0x0000c000 +#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_OFF 0x00000000 +#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL1 0x00004000 +#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL2 0x00008000 +#define NV20TCL_FOG_MODE 0x0000029c +#define NV20TCL_FOG_MODE_LINEAR_UNSIGNED 0x00000804 +#define NV20TCL_FOG_MODE_LINEAR_SIGNED 0x00002601 +#define NV20TCL_FOG_MODE_EXP_UNSIGNED 0x00000802 +#define NV20TCL_FOG_MODE_EXP_SIGNED 0x00000800 +#define NV20TCL_FOG_MODE_EXP2_UNSIGNED 0x00000803 +#define NV20TCL_FOG_MODE_EXP2_SIGNED 0x00000801 +#define NV20TCL_FOG_COORD 0x000002a0 +#define NV20TCL_FOG_COORD_DIST_RADIAL 0x00000001 +#define NV20TCL_FOG_COORD_DIST_ORTHOGONAL 0x00000002 +#define NV20TCL_FOG_COORD_DIST_ORTHOGONAL_ABS 0x00000003 +#define NV20TCL_FOG_COORD_FOG 0x00000006 +#define NV20TCL_FOG_ENABLE 0x000002a4 +#define NV20TCL_FOG_COLOR 0x000002a8 +#define NV20TCL_FOG_COLOR_R_SHIFT 0 +#define NV20TCL_FOG_COLOR_R_MASK 0x000000ff +#define NV20TCL_FOG_COLOR_G_SHIFT 8 +#define NV20TCL_FOG_COLOR_G_MASK 0x0000ff00 +#define NV20TCL_FOG_COLOR_B_SHIFT 16 +#define NV20TCL_FOG_COLOR_B_MASK 0x00ff0000 +#define NV20TCL_FOG_COLOR_A_SHIFT 24 +#define NV20TCL_FOG_COLOR_A_MASK 0xff000000 +#define NV20TCL_VIEWPORT_CLIP_MODE 0x000002b4 +#define NV20TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*4)) +#define NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 +#define NV20TCL_VIEWPORT_CLIP_VERT(x) (0x000002e0+((x)*4)) +#define NV20TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 +#define NV20TCL_ALPHA_FUNC_ENABLE 0x00000300 +#define NV20TCL_BLEND_FUNC_ENABLE 0x00000304 +#define NV20TCL_CULL_FACE_ENABLE 0x00000308 +#define NV20TCL_DEPTH_TEST_ENABLE 0x0000030c +#define NV20TCL_DITHER_ENABLE 0x00000310 +#define NV20TCL_LIGHTING_ENABLE 0x00000314 +#define NV20TCL_POINT_PARAMETERS_ENABLE 0x00000318 +#define NV20TCL_POINT_SMOOTH_ENABLE 0x0000031c +#define NV20TCL_LINE_SMOOTH_ENABLE 0x00000320 +#define NV20TCL_POLYGON_SMOOTH_ENABLE 0x00000324 +#define NV20TCL_STENCIL_ENABLE 0x0000032c +#define NV20TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000330 +#define NV20TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000334 +#define NV20TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000338 +#define NV20TCL_ALPHA_FUNC_FUNC 0x0000033c +#define NV20TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200 +#define NV20TCL_ALPHA_FUNC_FUNC_LESS 0x00000201 +#define NV20TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202 +#define NV20TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 +#define NV20TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204 +#define NV20TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV20TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 +#define NV20TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 +#define NV20TCL_ALPHA_FUNC_REF 0x00000340 +#define NV20TCL_BLEND_FUNC_SRC 0x00000344 +#define NV20TCL_BLEND_FUNC_SRC_ZERO 0x00000000 +#define NV20TCL_BLEND_FUNC_SRC_ONE 0x00000001 +#define NV20TCL_BLEND_FUNC_SRC_SRC_COLOR 0x00000300 +#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA 0x00000302 +#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV20TCL_BLEND_FUNC_SRC_DST_ALPHA 0x00000304 +#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV20TCL_BLEND_FUNC_SRC_DST_COLOR 0x00000306 +#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR 0x00000307 +#define NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE 0x00000308 +#define NV20TCL_BLEND_FUNC_SRC_CONSTANT_COLOR 0x00008001 +#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV20TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA 0x00008003 +#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV20TCL_BLEND_FUNC_DST 0x00000348 +#define NV20TCL_BLEND_FUNC_DST_ZERO 0x00000000 +#define NV20TCL_BLEND_FUNC_DST_ONE 0x00000001 +#define NV20TCL_BLEND_FUNC_DST_SRC_COLOR 0x00000300 +#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV20TCL_BLEND_FUNC_DST_SRC_ALPHA 0x00000302 +#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV20TCL_BLEND_FUNC_DST_DST_ALPHA 0x00000304 +#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV20TCL_BLEND_FUNC_DST_DST_COLOR 0x00000306 +#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR 0x00000307 +#define NV20TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE 0x00000308 +#define NV20TCL_BLEND_FUNC_DST_CONSTANT_COLOR 0x00008001 +#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV20TCL_BLEND_FUNC_DST_CONSTANT_ALPHA 0x00008003 +#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV20TCL_BLEND_COLOR 0x0000034c +#define NV20TCL_BLEND_COLOR_B_SHIFT 0 +#define NV20TCL_BLEND_COLOR_B_MASK 0x000000ff +#define NV20TCL_BLEND_COLOR_G_SHIFT 8 +#define NV20TCL_BLEND_COLOR_G_MASK 0x0000ff00 +#define NV20TCL_BLEND_COLOR_R_SHIFT 16 +#define NV20TCL_BLEND_COLOR_R_MASK 0x00ff0000 +#define NV20TCL_BLEND_COLOR_A_SHIFT 24 +#define NV20TCL_BLEND_COLOR_A_MASK 0xff000000 +#define NV20TCL_BLEND_EQUATION 0x00000350 +#define NV20TCL_BLEND_EQUATION_FUNC_ADD 0x00008006 +#define NV20TCL_BLEND_EQUATION_MIN 0x00008007 +#define NV20TCL_BLEND_EQUATION_MAX 0x00008008 +#define NV20TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a +#define NV20TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b +#define NV20TCL_DEPTH_FUNC 0x00000354 +#define NV20TCL_DEPTH_FUNC_NEVER 0x00000200 +#define NV20TCL_DEPTH_FUNC_LESS 0x00000201 +#define NV20TCL_DEPTH_FUNC_EQUAL 0x00000202 +#define NV20TCL_DEPTH_FUNC_LEQUAL 0x00000203 +#define NV20TCL_DEPTH_FUNC_GREATER 0x00000204 +#define NV20TCL_DEPTH_FUNC_NOTEQUAL 0x00000205 +#define NV20TCL_DEPTH_FUNC_GEQUAL 0x00000206 +#define NV20TCL_DEPTH_FUNC_ALWAYS 0x00000207 +#define NV20TCL_COLOR_MASK 0x00000358 +#define NV20TCL_COLOR_MASK_B (1 << 0) +#define NV20TCL_COLOR_MASK_G (1 << 8) +#define NV20TCL_COLOR_MASK_R (1 << 16) +#define NV20TCL_COLOR_MASK_A (1 << 24) +#define NV20TCL_DEPTH_WRITE_ENABLE 0x0000035c +#define NV20TCL_STENCIL_MASK 0x00000360 +#define NV20TCL_STENCIL_FUNC_FUNC 0x00000364 +#define NV20TCL_STENCIL_FUNC_FUNC_NEVER 0x00000200 +#define NV20TCL_STENCIL_FUNC_FUNC_LESS 0x00000201 +#define NV20TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202 +#define NV20TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203 +#define NV20TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204 +#define NV20TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV20TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206 +#define NV20TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207 +#define NV20TCL_STENCIL_FUNC_REF 0x00000368 +#define NV20TCL_STENCIL_FUNC_MASK 0x0000036c +#define NV20TCL_STENCIL_OP_FAIL 0x00000370 +#define NV20TCL_STENCIL_OP_FAIL_ZERO 0x00000000 +#define NV20TCL_STENCIL_OP_FAIL_INVERT 0x0000150a +#define NV20TCL_STENCIL_OP_FAIL_KEEP 0x00001e00 +#define NV20TCL_STENCIL_OP_FAIL_REPLACE 0x00001e01 +#define NV20TCL_STENCIL_OP_FAIL_INCR 0x00001e02 +#define NV20TCL_STENCIL_OP_FAIL_DECR 0x00001e03 +#define NV20TCL_STENCIL_OP_FAIL_INCR_WRAP 0x00008507 +#define NV20TCL_STENCIL_OP_FAIL_DECR_WRAP 0x00008508 +#define NV20TCL_STENCIL_OP_ZFAIL 0x00000374 +#define NV20TCL_STENCIL_OP_ZFAIL_ZERO 0x00000000 +#define NV20TCL_STENCIL_OP_ZFAIL_INVERT 0x0000150a +#define NV20TCL_STENCIL_OP_ZFAIL_KEEP 0x00001e00 +#define NV20TCL_STENCIL_OP_ZFAIL_REPLACE 0x00001e01 +#define NV20TCL_STENCIL_OP_ZFAIL_INCR 0x00001e02 +#define NV20TCL_STENCIL_OP_ZFAIL_DECR 0x00001e03 +#define NV20TCL_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NV20TCL_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508 +#define NV20TCL_STENCIL_OP_ZPASS 0x00000378 +#define NV20TCL_STENCIL_OP_ZPASS_ZERO 0x00000000 +#define NV20TCL_STENCIL_OP_ZPASS_INVERT 0x0000150a +#define NV20TCL_STENCIL_OP_ZPASS_KEEP 0x00001e00 +#define NV20TCL_STENCIL_OP_ZPASS_REPLACE 0x00001e01 +#define NV20TCL_STENCIL_OP_ZPASS_INCR 0x00001e02 +#define NV20TCL_STENCIL_OP_ZPASS_DECR 0x00001e03 +#define NV20TCL_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507 +#define NV20TCL_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508 +#define NV20TCL_SHADE_MODEL 0x0000037c +#define NV20TCL_SHADE_MODEL_FLAT 0x00001d00 +#define NV20TCL_SHADE_MODEL_SMOOTH 0x00001d01 +#define NV20TCL_LINE_WIDTH 0x00000380 +#define NV20TCL_POLYGON_OFFSET_FACTOR 0x00000384 +#define NV20TCL_POLYGON_OFFSET_UNITS 0x00000388 +#define NV20TCL_POLYGON_MODE_FRONT 0x0000038c +#define NV20TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NV20TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NV20TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 +#define NV20TCL_POLYGON_MODE_BACK 0x00000390 +#define NV20TCL_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NV20TCL_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NV20TCL_POLYGON_MODE_BACK_FILL 0x00001b02 +#define NV20TCL_DEPTH_RANGE_NEAR 0x00000394 +#define NV20TCL_DEPTH_RANGE_FAR 0x00000398 +#define NV20TCL_CULL_FACE 0x0000039c +#define NV20TCL_CULL_FACE_FRONT 0x00000404 +#define NV20TCL_CULL_FACE_BACK 0x00000405 +#define NV20TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 +#define NV20TCL_FRONT_FACE 0x000003a0 +#define NV20TCL_FRONT_FACE_CW 0x00000900 +#define NV20TCL_FRONT_FACE_CCW 0x00000901 +#define NV20TCL_NORMALIZE_ENABLE 0x000003a4 +#define NV20TCL_MATERIAL_FACTOR_FRONT_R 0x000003a8 +#define NV20TCL_MATERIAL_FACTOR_FRONT_G 0x000003ac +#define NV20TCL_MATERIAL_FACTOR_FRONT_B 0x000003b0 +#define NV20TCL_MATERIAL_FACTOR_FRONT_A 0x000003b4 +#define NV20TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8 +#define NV20TCL_ENABLED_LIGHTS 0x000003bc +#define NV20TCL_ENABLED_LIGHTS_0_SHIFT 0 +#define NV20TCL_ENABLED_LIGHTS_0_MASK 0x00000003 +#define NV20TCL_ENABLED_LIGHTS_0_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_0_NONPOSITIONAL 0x00000001 +#define NV20TCL_ENABLED_LIGHTS_0_POSITIONAL 0x00000002 +#define NV20TCL_ENABLED_LIGHTS_0_DIRECTIONAL 0x00000003 +#define NV20TCL_ENABLED_LIGHTS_1_SHIFT 2 +#define NV20TCL_ENABLED_LIGHTS_1_MASK 0x0000000c +#define NV20TCL_ENABLED_LIGHTS_1_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_1_NONPOSITIONAL 0x00000004 +#define NV20TCL_ENABLED_LIGHTS_1_POSITIONAL 0x00000008 +#define NV20TCL_ENABLED_LIGHTS_1_DIRECTIONAL 0x0000000c +#define NV20TCL_ENABLED_LIGHTS_2_SHIFT 4 +#define NV20TCL_ENABLED_LIGHTS_2_MASK 0x00000030 +#define NV20TCL_ENABLED_LIGHTS_2_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_2_NONPOSITIONAL 0x00000010 +#define NV20TCL_ENABLED_LIGHTS_2_POSITIONAL 0x00000020 +#define NV20TCL_ENABLED_LIGHTS_2_DIRECTIONAL 0x00000030 +#define NV20TCL_ENABLED_LIGHTS_3_SHIFT 6 +#define NV20TCL_ENABLED_LIGHTS_3_MASK 0x000000c0 +#define NV20TCL_ENABLED_LIGHTS_3_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_3_NONPOSITIONAL 0x00000040 +#define NV20TCL_ENABLED_LIGHTS_3_POSITIONAL 0x00000080 +#define NV20TCL_ENABLED_LIGHTS_3_DIRECTIONAL 0x000000c0 +#define NV20TCL_ENABLED_LIGHTS_4_SHIFT 8 +#define NV20TCL_ENABLED_LIGHTS_4_MASK 0x00000300 +#define NV20TCL_ENABLED_LIGHTS_4_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_4_NONPOSITIONAL 0x00000100 +#define NV20TCL_ENABLED_LIGHTS_4_POSITIONAL 0x00000200 +#define NV20TCL_ENABLED_LIGHTS_4_DIRECTIONAL 0x00000300 +#define NV20TCL_ENABLED_LIGHTS_5_SHIFT 10 +#define NV20TCL_ENABLED_LIGHTS_5_MASK 0x00000c00 +#define NV20TCL_ENABLED_LIGHTS_5_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_5_NONPOSITIONAL 0x00000400 +#define NV20TCL_ENABLED_LIGHTS_5_POSITIONAL 0x00000800 +#define NV20TCL_ENABLED_LIGHTS_5_DIRECTIONAL 0x00000c00 +#define NV20TCL_ENABLED_LIGHTS_6_SHIFT 12 +#define NV20TCL_ENABLED_LIGHTS_6_MASK 0x00003000 +#define NV20TCL_ENABLED_LIGHTS_6_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_6_NONPOSITIONAL 0x00001000 +#define NV20TCL_ENABLED_LIGHTS_6_POSITIONAL 0x00002000 +#define NV20TCL_ENABLED_LIGHTS_6_DIRECTIONAL 0x00003000 +#define NV20TCL_ENABLED_LIGHTS_7_SHIFT 14 +#define NV20TCL_ENABLED_LIGHTS_7_MASK 0x0000c000 +#define NV20TCL_ENABLED_LIGHTS_7_DISABLED 0x00000000 +#define NV20TCL_ENABLED_LIGHTS_7_NONPOSITIONAL 0x00004000 +#define NV20TCL_ENABLED_LIGHTS_7_POSITIONAL 0x00008000 +#define NV20TCL_ENABLED_LIGHTS_7_DIRECTIONAL 0x0000c000 +#define NV20TCL_TX_GEN_MODE_S(x) (0x000003c0+((x)*16)) +#define NV20TCL_TX_GEN_MODE_S__SIZE 0x00000004 +#define NV20TCL_TX_GEN_MODE_S_FALSE 0x00000000 +#define NV20TCL_TX_GEN_MODE_S_EYE_LINEAR 0x00002400 +#define NV20TCL_TX_GEN_MODE_S_OBJECT_LINEAR 0x00002401 +#define NV20TCL_TX_GEN_MODE_S_SPHERE_MAP 0x00002402 +#define NV20TCL_TX_GEN_MODE_S_NORMAL_MAP 0x00008511 +#define NV20TCL_TX_GEN_MODE_S_REFLECTION_MAP 0x00008512 +#define NV20TCL_TX_GEN_MODE_T(x) (0x000003c4+((x)*16)) +#define NV20TCL_TX_GEN_MODE_T__SIZE 0x00000004 +#define NV20TCL_TX_GEN_MODE_T_FALSE 0x00000000 +#define NV20TCL_TX_GEN_MODE_T_EYE_LINEAR 0x00002400 +#define NV20TCL_TX_GEN_MODE_T_OBJECT_LINEAR 0x00002401 +#define NV20TCL_TX_GEN_MODE_T_SPHERE_MAP 0x00002402 +#define NV20TCL_TX_GEN_MODE_T_NORMAL_MAP 0x00008511 +#define NV20TCL_TX_GEN_MODE_T_REFLECTION_MAP 0x00008512 +#define NV20TCL_TX_GEN_MODE_R(x) (0x000003c8+((x)*16)) +#define NV20TCL_TX_GEN_MODE_R__SIZE 0x00000004 +#define NV20TCL_TX_GEN_MODE_R_FALSE 0x00000000 +#define NV20TCL_TX_GEN_MODE_R_EYE_LINEAR 0x00002400 +#define NV20TCL_TX_GEN_MODE_R_OBJECT_LINEAR 0x00002401 +#define NV20TCL_TX_GEN_MODE_R_SPHERE_MAP 0x00002402 +#define NV20TCL_TX_GEN_MODE_R_NORMAL_MAP 0x00008511 +#define NV20TCL_TX_GEN_MODE_R_REFLECTION_MAP 0x00008512 +#define NV20TCL_TX_GEN_MODE_Q(x) (0x000003cc+((x)*16)) +#define NV20TCL_TX_GEN_MODE_Q__SIZE 0x00000004 +#define NV20TCL_TX_GEN_MODE_Q_FALSE 0x00000000 +#define NV20TCL_TX_GEN_MODE_Q_EYE_LINEAR 0x00002400 +#define NV20TCL_TX_GEN_MODE_Q_OBJECT_LINEAR 0x00002401 +#define NV20TCL_TX_GEN_MODE_Q_SPHERE_MAP 0x00002402 +#define NV20TCL_TX_GEN_MODE_Q_NORMAL_MAP 0x00008511 +#define NV20TCL_TX_GEN_MODE_Q_REFLECTION_MAP 0x00008512 +#define NV20TCL_TX_MATRIX_ENABLE(x) (0x00000420+((x)*4)) +#define NV20TCL_TX_MATRIX_ENABLE__SIZE 0x00000004 +#define NV20TCL_POINT_SIZE 0x0000043c +#define NV20TCL_MODELVIEW0_MATRIX(x) (0x00000480+((x)*4)) +#define NV20TCL_MODELVIEW0_MATRIX__SIZE 0x00000010 +#define NV20TCL_MODELVIEW1_MATRIX(x) (0x000004c0+((x)*4)) +#define NV20TCL_MODELVIEW1_MATRIX__SIZE 0x00000010 +#define NV20TCL_MODELVIEW2_MATRIX(x) (0x00000500+((x)*4)) +#define NV20TCL_MODELVIEW2_MATRIX__SIZE 0x00000010 +#define NV20TCL_MODELVIEW3_MATRIX(x) (0x00000540+((x)*4)) +#define NV20TCL_MODELVIEW3_MATRIX__SIZE 0x00000010 +#define NV20TCL_INVERSE_MODELVIEW0_MATRIX(x) (0x00000580+((x)*4)) +#define NV20TCL_INVERSE_MODELVIEW0_MATRIX__SIZE 0x00000010 +#define NV20TCL_INVERSE_MODELVIEW1_MATRIX(x) (0x000005c0+((x)*4)) +#define NV20TCL_INVERSE_MODELVIEW1_MATRIX__SIZE 0x00000010 +#define NV20TCL_INVERSE_MODELVIEW2_MATRIX(x) (0x00000600+((x)*4)) +#define NV20TCL_INVERSE_MODELVIEW2_MATRIX__SIZE 0x00000010 +#define NV20TCL_INVERSE_MODELVIEW3_MATRIX(x) (0x00000640+((x)*4)) +#define NV20TCL_INVERSE_MODELVIEW3_MATRIX__SIZE 0x00000010 +#define NV20TCL_PROJECTION_MATRIX(x) (0x00000680+((x)*4)) +#define NV20TCL_PROJECTION_MATRIX__SIZE 0x00000010 +#define NV20TCL_TX0_MATRIX(x) (0x000006c0+((x)*4)) +#define NV20TCL_TX0_MATRIX__SIZE 0x00000010 +#define NV20TCL_TX1_MATRIX(x) (0x00000700+((x)*4)) +#define NV20TCL_TX1_MATRIX__SIZE 0x00000010 +#define NV20TCL_TX2_MATRIX(x) (0x00000740+((x)*4)) +#define NV20TCL_TX2_MATRIX__SIZE 0x00000010 +#define NV20TCL_TX3_MATRIX(x) (0x00000780+((x)*4)) +#define NV20TCL_TX3_MATRIX__SIZE 0x00000010 +#define NV20TCL_TX_GEN_COEFF_S_A(x) (0x00000840+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_S_A__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_S_B(x) (0x00000844+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_S_B__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_S_C(x) (0x00000848+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_S_C__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_S_D(x) (0x0000084c+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_S_D__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_T_A(x) (0x00000850+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_T_A__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_T_B(x) (0x00000854+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_T_B__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_T_C(x) (0x00000858+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_T_C__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_T_D(x) (0x0000085c+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_T_D__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_R_A(x) (0x00000860+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_R_A__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_R_B(x) (0x00000864+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_R_B__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_R_C(x) (0x00000868+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_R_C__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_R_D(x) (0x0000086c+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_R_D__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_Q_A(x) (0x00000870+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_Q_A__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_Q_B(x) (0x00000874+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_Q_B__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_Q_C(x) (0x00000878+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_Q_C__SIZE 0x00000004 +#define NV20TCL_TX_GEN_COEFF_Q_D(x) (0x0000087c+((x)*64)) +#define NV20TCL_TX_GEN_COEFF_Q_D__SIZE 0x00000004 +#define NV20TCL_FOG_EQUATION_CONSTANT 0x000009c0 +#define NV20TCL_FOG_EQUATION_LINEAR 0x000009c4 +#define NV20TCL_FOG_EQUATION_QUADRATIC 0x000009c8 +#define NV20TCL_FRONT_MATERIAL_SHININESS(x) (0x000009e0+((x)*4)) +#define NV20TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006 +#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R 0x00000a10 +#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_G 0x00000a14 +#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_B 0x00000a18 +#define NV20TCL_VIEWPORT_TRANSLATE_X 0x00000a20 +#define NV20TCL_VIEWPORT_TRANSLATE_Y 0x00000a24 +#define NV20TCL_VIEWPORT_TRANSLATE_Z 0x00000a28 +#define NV20TCL_VIEWPORT_TRANSLATE_W 0x00000a2c +#define NV20TCL_POINT_PARAMETER(x) (0x00000a30+((x)*4)) +#define NV20TCL_POINT_PARAMETER__SIZE 0x00000008 +#define NV20TCL_RC_CONSTANT_COLOR0(x) (0x00000a60+((x)*4)) +#define NV20TCL_RC_CONSTANT_COLOR0__SIZE 0x00000008 +#define NV20TCL_RC_CONSTANT_COLOR0_B_SHIFT 0 +#define NV20TCL_RC_CONSTANT_COLOR0_B_MASK 0x000000ff +#define NV20TCL_RC_CONSTANT_COLOR0_G_SHIFT 8 +#define NV20TCL_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00 +#define NV20TCL_RC_CONSTANT_COLOR0_R_SHIFT 16 +#define NV20TCL_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000 +#define NV20TCL_RC_CONSTANT_COLOR0_A_SHIFT 24 +#define NV20TCL_RC_CONSTANT_COLOR0_A_MASK 0xff000000 +#define NV20TCL_RC_CONSTANT_COLOR1(x) (0x00000a80+((x)*4)) +#define NV20TCL_RC_CONSTANT_COLOR1__SIZE 0x00000008 +#define NV20TCL_RC_CONSTANT_COLOR1_B_SHIFT 0 +#define NV20TCL_RC_CONSTANT_COLOR1_B_MASK 0x000000ff +#define NV20TCL_RC_CONSTANT_COLOR1_G_SHIFT 8 +#define NV20TCL_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00 +#define NV20TCL_RC_CONSTANT_COLOR1_R_SHIFT 16 +#define NV20TCL_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000 +#define NV20TCL_RC_CONSTANT_COLOR1_A_SHIFT 24 +#define NV20TCL_RC_CONSTANT_COLOR1_A_MASK 0xff000000 +#define NV20TCL_RC_OUT_ALPHA(x) (0x00000aa0+((x)*4)) +#define NV20TCL_RC_OUT_ALPHA__SIZE 0x00000008 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV20TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) +#define NV20TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) +#define NV20TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14) +#define NV20TCL_RC_OUT_ALPHA_BIAS (1 << 15) +#define NV20TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000 +#define NV20TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV20TCL_RC_OUT_ALPHA_SCALE_SHIFT 17 +#define NV20TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000 +#define NV20TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000 +#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000 +#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000 +#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000 +#define NV20TCL_RC_IN_RGB(x) (0x00000ac0+((x)*4)) +#define NV20TCL_RC_IN_RGB__SIZE 0x00000008 +#define NV20TCL_RC_IN_RGB_D_INPUT_SHIFT 0 +#define NV20TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f +#define NV20TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV20TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003 +#define NV20TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV20TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 +#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 +#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c +#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d +#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV20TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f +#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a +#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b +#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4) +#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV20TCL_RC_IN_RGB_D_MAPPING_SHIFT 5 +#define NV20TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0 +#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV20TCL_RC_IN_RGB_C_INPUT_SHIFT 8 +#define NV20TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00 +#define NV20TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV20TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300 +#define NV20TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV20TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 +#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 +#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 +#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 +#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV20TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 +#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 +#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 +#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12) +#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_SHIFT 13 +#define NV20TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV20TCL_RC_IN_RGB_B_INPUT_SHIFT 16 +#define NV20TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000 +#define NV20TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV20TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000 +#define NV20TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV20TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 +#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 +#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 +#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 +#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV20TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 +#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 +#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 +#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20) +#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_SHIFT 21 +#define NV20TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV20TCL_RC_IN_RGB_A_INPUT_SHIFT 24 +#define NV20TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 +#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 +#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28) +#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_SHIFT 29 +#define NV20TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 +#define NV20TCL_VIEWPORT_SCALE_X 0x00000af0 +#define NV20TCL_VIEWPORT_SCALE_Y 0x00000af4 +#define NV20TCL_VIEWPORT_SCALE_Z 0x00000af8 +#define NV20TCL_VIEWPORT_SCALE_W 0x00000afc +#define NV20TCL_VP_UPLOAD_INST(x) (0x00000b00+((x)*4)) +#define NV20TCL_VP_UPLOAD_INST__SIZE 0x00000004 +#define NV20TCL_VP_UPLOAD_CONST(x) (0x00000b80+((x)*4)) +#define NV20TCL_VP_UPLOAD_CONST__SIZE 0x00000004 +#define NV20TCL_LIGHT_BACK_AMBIENT_R(x) (0x00000c00+((x)*64)) +#define NV20TCL_LIGHT_BACK_AMBIENT_R__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_AMBIENT_G(x) (0x00000c04+((x)*64)) +#define NV20TCL_LIGHT_BACK_AMBIENT_G__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_AMBIENT_B(x) (0x00000c08+((x)*64)) +#define NV20TCL_LIGHT_BACK_AMBIENT_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_DIFFUSE_R(x) (0x00000c0c+((x)*64)) +#define NV20TCL_LIGHT_BACK_DIFFUSE_R__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_DIFFUSE_G(x) (0x00000c10+((x)*64)) +#define NV20TCL_LIGHT_BACK_DIFFUSE_G__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_DIFFUSE_B(x) (0x00000c14+((x)*64)) +#define NV20TCL_LIGHT_BACK_DIFFUSE_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_SPECULAR_R(x) (0x00000c18+((x)*64)) +#define NV20TCL_LIGHT_BACK_SPECULAR_R__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_SPECULAR_G(x) (0x00000c1c+((x)*64)) +#define NV20TCL_LIGHT_BACK_SPECULAR_G__SIZE 0x00000008 +#define NV20TCL_LIGHT_BACK_SPECULAR_B(x) (0x00000c20+((x)*64)) +#define NV20TCL_LIGHT_BACK_SPECULAR_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_AMBIENT_R(x) (0x00001000+((x)*128)) +#define NV20TCL_LIGHT_FRONT_AMBIENT_R__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_AMBIENT_G(x) (0x00001004+((x)*128)) +#define NV20TCL_LIGHT_FRONT_AMBIENT_G__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_AMBIENT_B(x) (0x00001008+((x)*128)) +#define NV20TCL_LIGHT_FRONT_AMBIENT_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_DIFFUSE_R(x) (0x0000100c+((x)*128)) +#define NV20TCL_LIGHT_FRONT_DIFFUSE_R__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_DIFFUSE_G(x) (0x00001010+((x)*128)) +#define NV20TCL_LIGHT_FRONT_DIFFUSE_G__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_DIFFUSE_B(x) (0x00001014+((x)*128)) +#define NV20TCL_LIGHT_FRONT_DIFFUSE_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_SPECULAR_R(x) (0x00001018+((x)*128)) +#define NV20TCL_LIGHT_FRONT_SPECULAR_R__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_SPECULAR_G(x) (0x0000101c+((x)*128)) +#define NV20TCL_LIGHT_FRONT_SPECULAR_G__SIZE 0x00000008 +#define NV20TCL_LIGHT_FRONT_SPECULAR_B(x) (0x00001020+((x)*128)) +#define NV20TCL_LIGHT_FRONT_SPECULAR_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_HALF_VECTOR_X(x) (0x00001028+((x)*128)) +#define NV20TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008 +#define NV20TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000102c+((x)*128)) +#define NV20TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008 +#define NV20TCL_LIGHT_HALF_VECTOR_Z(x) (0x00001030+((x)*128)) +#define NV20TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008 +#define NV20TCL_LIGHT_DIRECTION_X(x) (0x00001034+((x)*128)) +#define NV20TCL_LIGHT_DIRECTION_X__SIZE 0x00000008 +#define NV20TCL_LIGHT_DIRECTION_Y(x) (0x00001038+((x)*128)) +#define NV20TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008 +#define NV20TCL_LIGHT_DIRECTION_Z(x) (0x0000103c+((x)*128)) +#define NV20TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00001040+((x)*128)) +#define NV20TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00001044+((x)*128)) +#define NV20TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00001048+((x)*128)) +#define NV20TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_DIR_X(x) (0x0000104c+((x)*128)) +#define NV20TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_DIR_Y(x) (0x00001050+((x)*128)) +#define NV20TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_DIR_Z(x) (0x00001054+((x)*128)) +#define NV20TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008 +#define NV20TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00001058+((x)*128)) +#define NV20TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008 +#define NV20TCL_LIGHT_POSITION_X(x) (0x0000105c+((x)*128)) +#define NV20TCL_LIGHT_POSITION_X__SIZE 0x00000008 +#define NV20TCL_LIGHT_POSITION_Y(x) (0x00001060+((x)*128)) +#define NV20TCL_LIGHT_POSITION_Y__SIZE 0x00000008 +#define NV20TCL_LIGHT_POSITION_Z(x) (0x00001064+((x)*128)) +#define NV20TCL_LIGHT_POSITION_Z__SIZE 0x00000008 +#define NV20TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00001068+((x)*128)) +#define NV20TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008 +#define NV20TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000106c+((x)*128)) +#define NV20TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008 +#define NV20TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00001070+((x)*128)) +#define NV20TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008 +#define NV20TCL_POLYGON_STIPPLE_ENABLE 0x0000147c +#define NV20TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4)) +#define NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 +#define NV20TCL_VERTEX_POS_3F_X 0x00001500 +#define NV20TCL_VERTEX_POS_3F_Y 0x00001504 +#define NV20TCL_VERTEX_POS_3F_Z 0x00001508 +#define NV20TCL_VERTEX_POS_4F_X 0x00001518 +#define NV20TCL_VERTEX_POS_4F_Y 0x0000151c +#define NV20TCL_VERTEX_POS_4F_Z 0x00001520 +#define NV20TCL_VERTEX_POS_3I_XY 0x00001528 +#define NV20TCL_VERTEX_POS_3I_XY_X_SHIFT 0 +#define NV20TCL_VERTEX_POS_3I_XY_X_MASK 0x0000ffff +#define NV20TCL_VERTEX_POS_3I_XY_Y_SHIFT 16 +#define NV20TCL_VERTEX_POS_3I_XY_Y_MASK 0xffff0000 +#define NV20TCL_VERTEX_POS_3I_Z 0x0000152c +#define NV20TCL_VERTEX_POS_3I_Z_Z_SHIFT 0 +#define NV20TCL_VERTEX_POS_3I_Z_Z_MASK 0x0000ffff +#define NV20TCL_VERTEX_NOR_3F_X 0x00001530 +#define NV20TCL_VERTEX_NOR_3F_Y 0x00001534 +#define NV20TCL_VERTEX_NOR_3F_Z 0x00001538 +#define NV20TCL_VERTEX_NOR_3I_XY 0x00001540 +#define NV20TCL_VERTEX_NOR_3I_XY_X_SHIFT 0 +#define NV20TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff +#define NV20TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16 +#define NV20TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 +#define NV20TCL_VERTEX_NOR_3I_Z 0x00001544 +#define NV20TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0 +#define NV20TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff +#define NV20TCL_VERTEX_COL_4F_X 0x00001550 +#define NV20TCL_VERTEX_COL_4F_Y 0x00001554 +#define NV20TCL_VERTEX_COL_4F_Z 0x00001558 +#define NV20TCL_VERTEX_COL_4F_W 0x0000155c +#define NV20TCL_VERTEX_COL_3F_X 0x00001560 +#define NV20TCL_VERTEX_COL_3F_Y 0x00001564 +#define NV20TCL_VERTEX_COL_3F_Z 0x00001568 +#define NV20TCL_VERTEX_COL_4I 0x0000156c +#define NV20TCL_VERTEX_COL_4I_R_SHIFT 0 +#define NV20TCL_VERTEX_COL_4I_R_MASK 0x000000ff +#define NV20TCL_VERTEX_COL_4I_G_SHIFT 8 +#define NV20TCL_VERTEX_COL_4I_G_MASK 0x0000ff00 +#define NV20TCL_VERTEX_COL_4I_B_SHIFT 16 +#define NV20TCL_VERTEX_COL_4I_B_MASK 0x00ff0000 +#define NV20TCL_VERTEX_COL_4I_A_SHIFT 24 +#define NV20TCL_VERTEX_COL_4I_A_MASK 0xff000000 +#define NV20TCL_VERTEX_COL2_3F_X 0x00001580 +#define NV20TCL_VERTEX_COL2_3F_Y 0x00001584 +#define NV20TCL_VERTEX_COL2_3F_Z 0x00001588 +#define NV20TCL_VERTEX_COL2_4I 0x0000158c +#define NV20TCL_VERTEX_COL2_4I_R_SHIFT 0 +#define NV20TCL_VERTEX_COL2_4I_R_MASK 0x000000ff +#define NV20TCL_VERTEX_COL2_4I_G_SHIFT 8 +#define NV20TCL_VERTEX_COL2_4I_G_MASK 0x0000ff00 +#define NV20TCL_VERTEX_COL2_4I_B_SHIFT 16 +#define NV20TCL_VERTEX_COL2_4I_B_MASK 0x00ff0000 +#define NV20TCL_VERTEX_COL2_4I_A_SHIFT 24 +#define NV20TCL_VERTEX_COL2_4I_A_MASK 0xff000000 +#define NV20TCL_VERTEX_TX0_2F_S 0x00001590 +#define NV20TCL_VERTEX_TX0_2F_T 0x00001594 +#define NV20TCL_VERTEX_TX0_2I 0x00001598 +#define NV20TCL_VERTEX_TX0_2I_S_SHIFT 0 +#define NV20TCL_VERTEX_TX0_2I_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX0_2I_T_SHIFT 16 +#define NV20TCL_VERTEX_TX0_2I_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX0_4F_S 0x000015a0 +#define NV20TCL_VERTEX_TX0_4F_T 0x000015a4 +#define NV20TCL_VERTEX_TX0_4F_R 0x000015a8 +#define NV20TCL_VERTEX_TX0_4F_Q 0x000015ac +#define NV20TCL_VERTEX_TX0_4I_ST 0x000015b0 +#define NV20TCL_VERTEX_TX0_4I_ST_S_SHIFT 0 +#define NV20TCL_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX0_4I_ST_T_SHIFT 16 +#define NV20TCL_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX0_4I_RQ 0x000015b4 +#define NV20TCL_VERTEX_TX0_4I_RQ_R_SHIFT 0 +#define NV20TCL_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX0_4I_RQ_Q_SHIFT 16 +#define NV20TCL_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX1_2F_S 0x000015b8 +#define NV20TCL_VERTEX_TX1_2F_T 0x000015bc +#define NV20TCL_VERTEX_TX1_2I 0x000015c0 +#define NV20TCL_VERTEX_TX1_2I_S_SHIFT 0 +#define NV20TCL_VERTEX_TX1_2I_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX1_2I_T_SHIFT 16 +#define NV20TCL_VERTEX_TX1_2I_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX1_4F_S 0x000015c8 +#define NV20TCL_VERTEX_TX1_4F_T 0x000015cc +#define NV20TCL_VERTEX_TX1_4F_R 0x000015d0 +#define NV20TCL_VERTEX_TX1_4F_Q 0x000015d4 +#define NV20TCL_VERTEX_TX1_4I_ST 0x000015d8 +#define NV20TCL_VERTEX_TX1_4I_ST_S_SHIFT 0 +#define NV20TCL_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX1_4I_ST_T_SHIFT 16 +#define NV20TCL_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX1_4I_RQ 0x000015dc +#define NV20TCL_VERTEX_TX1_4I_RQ_R_SHIFT 0 +#define NV20TCL_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX1_4I_RQ_Q_SHIFT 16 +#define NV20TCL_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX2_2F_S 0x000015e0 +#define NV20TCL_VERTEX_TX2_2F_T 0x000015e4 +#define NV20TCL_VERTEX_TX2_2I 0x000015e8 +#define NV20TCL_VERTEX_TX2_2I_S_SHIFT 0 +#define NV20TCL_VERTEX_TX2_2I_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX2_2I_T_SHIFT 16 +#define NV20TCL_VERTEX_TX2_2I_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX2_4F_S 0x000015f0 +#define NV20TCL_VERTEX_TX2_4F_T 0x000015f4 +#define NV20TCL_VERTEX_TX2_4F_R 0x000015f8 +#define NV20TCL_VERTEX_TX2_4F_Q 0x000015fc +#define NV20TCL_VERTEX_TX2_4I_ST 0x00001600 +#define NV20TCL_VERTEX_TX2_4I_ST_S_SHIFT 0 +#define NV20TCL_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX2_4I_ST_T_SHIFT 16 +#define NV20TCL_VERTEX_TX2_4I_ST_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX2_4I_RQ 0x00001604 +#define NV20TCL_VERTEX_TX2_4I_RQ_R_SHIFT 0 +#define NV20TCL_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX2_4I_RQ_Q_SHIFT 16 +#define NV20TCL_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX3_2F_S 0x00001608 +#define NV20TCL_VERTEX_TX3_2F_T 0x0000160c +#define NV20TCL_VERTEX_TX3_2I 0x00001610 +#define NV20TCL_VERTEX_TX3_2I_S_SHIFT 0 +#define NV20TCL_VERTEX_TX3_2I_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX3_2I_T_SHIFT 16 +#define NV20TCL_VERTEX_TX3_2I_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX3_4F_S 0x00001620 +#define NV20TCL_VERTEX_TX3_4F_T 0x00001624 +#define NV20TCL_VERTEX_TX3_4F_R 0x00001628 +#define NV20TCL_VERTEX_TX3_4F_Q 0x0000162c +#define NV20TCL_VERTEX_TX3_4I_ST 0x00001630 +#define NV20TCL_VERTEX_TX3_4I_ST_S_SHIFT 0 +#define NV20TCL_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX3_4I_ST_T_SHIFT 16 +#define NV20TCL_VERTEX_TX3_4I_ST_T_MASK 0xffff0000 +#define NV20TCL_VERTEX_TX3_4I_RQ 0x00001634 +#define NV20TCL_VERTEX_TX3_4I_RQ_R_SHIFT 0 +#define NV20TCL_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff +#define NV20TCL_VERTEX_TX3_4I_RQ_Q_SHIFT 16 +#define NV20TCL_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000 +#define NV20TCL_VERTEX_FOG_1F 0x00001698 +#define NV20TCL_EDGEFLAG_ENABLE 0x000016bc +#define NV20TCL_VTX_CACHE_INVALIDATE 0x00001710 +#define NV20TCL_VTXBUF_ADDRESS(x) (0x00001720+((x)*4)) +#define NV20TCL_VTXBUF_ADDRESS__SIZE 0x00000010 +#define NV20TCL_VTXBUF_ADDRESS_DMA1 (1 << 31) +#define NV20TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0 +#define NV20TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff +#define NV20TCL_VTXFMT(x) (0x00001760+((x)*4)) +#define NV20TCL_VTXFMT__SIZE 0x00000010 +#define NV20TCL_VTXFMT_TYPE_SHIFT 0 +#define NV20TCL_VTXFMT_TYPE_MASK 0x0000000f +#define NV20TCL_VTXFMT_TYPE_FLOAT 0x00000002 +#define NV20TCL_VTXFMT_TYPE_UBYTE 0x00000004 +#define NV20TCL_VTXFMT_TYPE_USHORT 0x00000005 +#define NV20TCL_VTXFMT_SIZE_SHIFT 4 +#define NV20TCL_VTXFMT_SIZE_MASK 0x000000f0 +#define NV20TCL_VTXFMT_STRIDE_SHIFT 8 +#define NV20TCL_VTXFMT_STRIDE_MASK 0x0000ff00 +#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R 0x000017a0 +#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_G 0x000017a4 +#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_B 0x000017a8 +#define NV20TCL_MATERIAL_FACTOR_BACK_A 0x000017ac +#define NV20TCL_MATERIAL_FACTOR_BACK_R 0x000017b0 +#define NV20TCL_MATERIAL_FACTOR_BACK_G 0x000017b4 +#define NV20TCL_MATERIAL_FACTOR_BACK_B 0x000017b8 +#define NV20TCL_COLOR_LOGIC_OP_ENABLE 0x000017bc +#define NV20TCL_COLOR_LOGIC_OP_OP 0x000017c0 +#define NV20TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 +#define NV20TCL_COLOR_LOGIC_OP_OP_AND 0x00001501 +#define NV20TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 +#define NV20TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503 +#define NV20TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 +#define NV20TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505 +#define NV20TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506 +#define NV20TCL_COLOR_LOGIC_OP_OP_OR 0x00001507 +#define NV20TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508 +#define NV20TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 +#define NV20TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a +#define NV20TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b +#define NV20TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c +#define NV20TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d +#define NV20TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e +#define NV20TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f +#define NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE 0x000017c4 +#define NV20TCL_TX_SHADER_CULL_MODE 0x000017f8 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S (1 << 0) +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S_LESS 0x00000001 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T (1 << 1) +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T_LESS 0x00000002 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R (1 << 2) +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R_LESS 0x00000004 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q (1 << 3) +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_LESS 0x00000008 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S (1 << 4) +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S_LESS 0x00000010 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T (1 << 5) +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T_LESS 0x00000020 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R (1 << 6) +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R_LESS 0x00000040 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q (1 << 7) +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_LESS 0x00000080 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S (1 << 8) +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S_LESS 0x00000100 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T (1 << 9) +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T_LESS 0x00000200 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R (1 << 10) +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R_LESS 0x00000400 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q (1 << 11) +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_LESS 0x00000800 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S (1 << 12) +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S_LESS 0x00001000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T (1 << 13) +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T_LESS 0x00002000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R (1 << 14) +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R_LESS 0x00004000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q (1 << 15) +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_GEQUAL 0x00000000 +#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_LESS 0x00008000 +#define NV20TCL_VERTEX_BEGIN_END 0x000017fc +#define NV20TCL_VERTEX_BEGIN_END_STOP 0x00000000 +#define NV20TCL_VERTEX_BEGIN_END_POINTS 0x00000001 +#define NV20TCL_VERTEX_BEGIN_END_LINES 0x00000002 +#define NV20TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 +#define NV20TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 +#define NV20TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005 +#define NV20TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 +#define NV20TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 +#define NV20TCL_VERTEX_BEGIN_END_QUADS 0x00000008 +#define NV20TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 +#define NV20TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a +#define NV20TCL_VB_ELEMENT_U16 0x00001800 +#define NV20TCL_VB_ELEMENT_U16_I0_SHIFT 0 +#define NV20TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff +#define NV20TCL_VB_ELEMENT_U16_I1_SHIFT 16 +#define NV20TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 +#define NV20TCL_VB_ELEMENT_U32 0x00001808 +#define NV20TCL_VB_VERTEX_BATCH 0x00001810 +#define NV20TCL_VB_VERTEX_BATCH_OFFSET_SHIFT 0 +#define NV20TCL_VB_VERTEX_BATCH_OFFSET_MASK 0x00ffffff +#define NV20TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24 +#define NV20TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000 +#define NV20TCL_VERTEX_DATA 0x00001818 +#define NV20TCL_TX_SHADER_CONST_EYE_X 0x0000181c +#define NV20TCL_TX_SHADER_CONST_EYE_Y 0x00001820 +#define NV20TCL_TX_SHADER_CONST_EYE_Z 0x00001824 +#define NV20TCL_VTX_ATTR_4F_X(x) (0x00001a00+((x)*16)) +#define NV20TCL_VTX_ATTR_4F_X__SIZE 0x00000010 +#define NV20TCL_VTX_ATTR_4F_Y(x) (0x00001a04+((x)*16)) +#define NV20TCL_VTX_ATTR_4F_Y__SIZE 0x00000010 +#define NV20TCL_VTX_ATTR_4F_Z(x) (0x00001a08+((x)*16)) +#define NV20TCL_VTX_ATTR_4F_Z__SIZE 0x00000010 +#define NV20TCL_VTX_ATTR_4F_W(x) (0x00001a0c+((x)*16)) +#define NV20TCL_VTX_ATTR_4F_W__SIZE 0x00000010 +#define NV20TCL_TX_OFFSET(x) (0x00001b00+((x)*64)) +#define NV20TCL_TX_OFFSET__SIZE 0x00000004 +#define NV20TCL_TX_FORMAT(x) (0x00001b04+((x)*64)) +#define NV20TCL_TX_FORMAT__SIZE 0x00000004 +#define NV20TCL_TX_FORMAT_DMA0 (1 << 0) +#define NV20TCL_TX_FORMAT_DMA1 (1 << 1) +#define NV20TCL_TX_FORMAT_CUBIC (1 << 2) +#define NV20TCL_TX_FORMAT_NO_BORDER (1 << 3) +#define NV20TCL_TX_FORMAT_DIMS_SHIFT 4 +#define NV20TCL_TX_FORMAT_DIMS_MASK 0x000000f0 +#define NV20TCL_TX_FORMAT_DIMS_1D 0x00000010 +#define NV20TCL_TX_FORMAT_DIMS_2D 0x00000020 +#define NV20TCL_TX_FORMAT_DIMS_3D 0x00000030 +#define NV20TCL_TX_FORMAT_FORMAT_SHIFT 8 +#define NV20TCL_TX_FORMAT_FORMAT_MASK 0x0000ff00 +#define NV20TCL_TX_FORMAT_FORMAT_L8 0x00000000 +#define NV20TCL_TX_FORMAT_FORMAT_A8 0x00000100 +#define NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000200 +#define NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000400 +#define NV20TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000500 +#define NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000600 +#define NV20TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000700 +#define NV20TCL_TX_FORMAT_FORMAT_INDEX8 0x00000b00 +#define NV20TCL_TX_FORMAT_FORMAT_DXT1 0x00000c00 +#define NV20TCL_TX_FORMAT_FORMAT_DXT3 0x00000e00 +#define NV20TCL_TX_FORMAT_FORMAT_DXT5 0x00000f00 +#define NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000 +#define NV20TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100 +#define NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200 +#define NV20TCL_TX_FORMAT_FORMAT_L8_RECT 0x00001300 +#define NV20TCL_TX_FORMAT_FORMAT_DSDT8_RECT 0x00001700 +#define NV20TCL_TX_FORMAT_FORMAT_A8L8 0x00001a00 +#define NV20TCL_TX_FORMAT_FORMAT_A8_RECT 0x00001b00 +#define NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00 +#define NV20TCL_TX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00 +#define NV20TCL_TX_FORMAT_FORMAT_A8L8_RECT 0x00002000 +#define NV20TCL_TX_FORMAT_FORMAT_DSDT8 0x00002800 +#define NV20TCL_TX_FORMAT_FORMAT_HILO16 0x00003300 +#define NV20TCL_TX_FORMAT_FORMAT_HILO16_RECT 0x00003600 +#define NV20TCL_TX_FORMAT_FORMAT_HILO8 0x00004400 +#define NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500 +#define NV20TCL_TX_FORMAT_FORMAT_HILO8_RECT 0x00004600 +#define NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700 +#define NV20TCL_TX_FORMAT_FORMAT_A16 0x00003200 +#define NV20TCL_TX_FORMAT_FORMAT_A16_RECT 0x00003500 +#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00 +#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00 +#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00 +#define NV20TCL_TX_FORMAT_MIPMAP (1 << 19) +#define NV20TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 20 +#define NV20TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x00f00000 +#define NV20TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 24 +#define NV20TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x0f000000 +#define NV20TCL_TX_FORMAT_BASE_SIZE_W_SHIFT 28 +#define NV20TCL_TX_FORMAT_BASE_SIZE_W_MASK 0xf0000000 +#define NV20TCL_TX_WRAP(x) (0x00001b08+((x)*64)) +#define NV20TCL_TX_WRAP__SIZE 0x00000004 +#define NV20TCL_TX_WRAP_S_SHIFT 0 +#define NV20TCL_TX_WRAP_S_MASK 0x000000ff +#define NV20TCL_TX_WRAP_S_REPEAT 0x00000001 +#define NV20TCL_TX_WRAP_S_MIRRORED_REPEAT 0x00000002 +#define NV20TCL_TX_WRAP_S_CLAMP_TO_EDGE 0x00000003 +#define NV20TCL_TX_WRAP_S_CLAMP_TO_BORDER 0x00000004 +#define NV20TCL_TX_WRAP_S_CLAMP 0x00000005 +#define NV20TCL_TX_WRAP_T_SHIFT 8 +#define NV20TCL_TX_WRAP_T_MASK 0x00000f00 +#define NV20TCL_TX_WRAP_T_REPEAT 0x00000100 +#define NV20TCL_TX_WRAP_T_MIRRORED_REPEAT 0x00000200 +#define NV20TCL_TX_WRAP_T_CLAMP_TO_EDGE 0x00000300 +#define NV20TCL_TX_WRAP_T_CLAMP_TO_BORDER 0x00000400 +#define NV20TCL_TX_WRAP_T_CLAMP 0x00000500 +#define NV20TCL_TX_WRAP_R_SHIFT 16 +#define NV20TCL_TX_WRAP_R_MASK 0x000f0000 +#define NV20TCL_TX_WRAP_R_REPEAT 0x00010000 +#define NV20TCL_TX_WRAP_R_MIRRORED_REPEAT 0x00020000 +#define NV20TCL_TX_WRAP_R_CLAMP_TO_EDGE 0x00030000 +#define NV20TCL_TX_WRAP_R_CLAMP_TO_BORDER 0x00040000 +#define NV20TCL_TX_WRAP_R_CLAMP 0x00050000 +#define NV20TCL_TX_ENABLE(x) (0x00001b0c+((x)*64)) +#define NV20TCL_TX_ENABLE__SIZE 0x00000004 +#define NV20TCL_TX_ENABLE_ANISO_SHIFT 4 +#define NV20TCL_TX_ENABLE_ANISO_MASK 0x00000030 +#define NV20TCL_TX_ENABLE_ANISO_NONE 0x00000000 +#define NV20TCL_TX_ENABLE_ANISO_2X 0x00000010 +#define NV20TCL_TX_ENABLE_ANISO_4X 0x00000020 +#define NV20TCL_TX_ENABLE_ANISO_8X 0x00000030 +#define NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14 +#define NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000 +#define NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26 +#define NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000 +#define NV20TCL_TX_ENABLE_ENABLE (1 << 30) +#define NV20TCL_TX_NPOT_PITCH(x) (0x00001b10+((x)*64)) +#define NV20TCL_TX_NPOT_PITCH__SIZE 0x00000004 +#define NV20TCL_TX_NPOT_PITCH_PITCH_SHIFT 16 +#define NV20TCL_TX_NPOT_PITCH_PITCH_MASK 0xffff0000 +#define NV20TCL_TX_FILTER(x) (0x00001b14+((x)*64)) +#define NV20TCL_TX_FILTER__SIZE 0x00000004 +#define NV20TCL_TX_FILTER_LOD_BIAS_SHIFT 8 +#define NV20TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00 +#define NV20TCL_TX_FILTER_MINIFY_SHIFT 16 +#define NV20TCL_TX_FILTER_MINIFY_MASK 0x000f0000 +#define NV20TCL_TX_FILTER_MINIFY_NEAREST 0x00010000 +#define NV20TCL_TX_FILTER_MINIFY_LINEAR 0x00020000 +#define NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x00030000 +#define NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x00040000 +#define NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x00050000 +#define NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x00060000 +#define NV20TCL_TX_FILTER_MAGNIFY_SHIFT 24 +#define NV20TCL_TX_FILTER_MAGNIFY_MASK 0x0f000000 +#define NV20TCL_TX_FILTER_MAGNIFY_NEAREST 0x01000000 +#define NV20TCL_TX_FILTER_MAGNIFY_LINEAR 0x02000000 +#define NV20TCL_TX_NPOT_SIZE(x) (0x00001b1c+((x)*64)) +#define NV20TCL_TX_NPOT_SIZE__SIZE 0x00000004 +#define NV20TCL_TX_NPOT_SIZE_H_SHIFT 0 +#define NV20TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff +#define NV20TCL_TX_NPOT_SIZE_W_SHIFT 16 +#define NV20TCL_TX_NPOT_SIZE_W_MASK 0xffff0000 +#define NV20TCL_TX_PALETTE_OFFSET(x) (0x00001b20+((x)*64)) +#define NV20TCL_TX_PALETTE_OFFSET__SIZE 0x00000004 +#define NV20TCL_TX_BORDER_COLOR(x) (0x00001b24+((x)*64)) +#define NV20TCL_TX_BORDER_COLOR__SIZE 0x00000004 +#define NV20TCL_TX_BORDER_COLOR_B_SHIFT 0 +#define NV20TCL_TX_BORDER_COLOR_B_MASK 0x000000ff +#define NV20TCL_TX_BORDER_COLOR_G_SHIFT 8 +#define NV20TCL_TX_BORDER_COLOR_G_MASK 0x0000ff00 +#define NV20TCL_TX_BORDER_COLOR_R_SHIFT 16 +#define NV20TCL_TX_BORDER_COLOR_R_MASK 0x00ff0000 +#define NV20TCL_TX_BORDER_COLOR_A_SHIFT 24 +#define NV20TCL_TX_BORDER_COLOR_A_MASK 0xff000000 +#define NV20TCL_TX_SHADER_OFFSET_MATRIX00(x) (0x00001b28+((x)*64)) +#define NV20TCL_TX_SHADER_OFFSET_MATRIX00__SIZE 0x00000004 +#define NV20TCL_TX_SHADER_OFFSET_MATRIX01(x) (0x00001b2c+((x)*64)) +#define NV20TCL_TX_SHADER_OFFSET_MATRIX01__SIZE 0x00000004 +#define NV20TCL_TX_SHADER_OFFSET_MATRIX11(x) (0x00001b30+((x)*64)) +#define NV20TCL_TX_SHADER_OFFSET_MATRIX11__SIZE 0x00000004 +#define NV20TCL_TX_SHADER_OFFSET_MATRIX10(x) (0x00001b34+((x)*64)) +#define NV20TCL_TX_SHADER_OFFSET_MATRIX10__SIZE 0x00000004 +#define NV20TCL_DEPTH_UNK17D8 0x00001d78 +#define NV20TCL_DEPTH_UNK17D8_CLAMP_SHIFT 4 +#define NV20TCL_DEPTH_UNK17D8_CLAMP_MASK 0x000000f0 +#define NV20TCL_MULTISAMPLE_CONTROL 0x00001d7c +#define NV20TCL_CLEAR_DEPTH_VALUE 0x00001d8c +#define NV20TCL_CLEAR_VALUE 0x00001d90 +#define NV20TCL_CLEAR_BUFFERS 0x00001d94 +#define NV20TCL_CLEAR_BUFFERS_COLOR_A (1 << 7) +#define NV20TCL_CLEAR_BUFFERS_COLOR_B (1 << 6) +#define NV20TCL_CLEAR_BUFFERS_COLOR_G (1 << 5) +#define NV20TCL_CLEAR_BUFFERS_COLOR_R (1 << 4) +#define NV20TCL_CLEAR_BUFFERS_STENCIL (1 << 1) +#define NV20TCL_CLEAR_BUFFERS_DEPTH (1 << 0) +#define NV20TCL_RC_COLOR0 0x00001e20 +#define NV20TCL_RC_COLOR0_B_SHIFT 0 +#define NV20TCL_RC_COLOR0_B_MASK 0x000000ff +#define NV20TCL_RC_COLOR0_G_SHIFT 8 +#define NV20TCL_RC_COLOR0_G_MASK 0x0000ff00 +#define NV20TCL_RC_COLOR0_R_SHIFT 16 +#define NV20TCL_RC_COLOR0_R_MASK 0x00ff0000 +#define NV20TCL_RC_COLOR0_A_SHIFT 24 +#define NV20TCL_RC_COLOR0_A_MASK 0xff000000 +#define NV20TCL_RC_COLOR1 0x00001e24 +#define NV20TCL_RC_COLOR1_B_SHIFT 0 +#define NV20TCL_RC_COLOR1_B_MASK 0x000000ff +#define NV20TCL_RC_COLOR1_G_SHIFT 8 +#define NV20TCL_RC_COLOR1_G_MASK 0x0000ff00 +#define NV20TCL_RC_COLOR1_R_SHIFT 16 +#define NV20TCL_RC_COLOR1_R_MASK 0x00ff0000 +#define NV20TCL_RC_COLOR1_A_SHIFT 24 +#define NV20TCL_RC_COLOR1_A_MASK 0xff000000 +#define NV20TCL_BACK_MATERIAL_SHININESS(x) (0x00001e28+((x)*4)) +#define NV20TCL_BACK_MATERIAL_SHININESS__SIZE 0x00000006 +#define NV20TCL_RC_OUT_RGB(x) (0x00001e40+((x)*4)) +#define NV20TCL_RC_OUT_RGB__SIZE 0x00000008 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV20TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) +#define NV20TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) +#define NV20TCL_RC_OUT_RGB_MUX_SUM (1 << 14) +#define NV20TCL_RC_OUT_RGB_BIAS (1 << 15) +#define NV20TCL_RC_OUT_RGB_BIAS_NONE 0x00000000 +#define NV20TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV20TCL_RC_OUT_RGB_SCALE_SHIFT 17 +#define NV20TCL_RC_OUT_RGB_SCALE_MASK 0x00000000 +#define NV20TCL_RC_OUT_RGB_SCALE_NONE 0x00000000 +#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000 +#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000 +#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000 +#define NV20TCL_RC_ENABLE 0x00001e60 +#define NV20TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0 +#define NV20TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f +#define NV20TCL_TX_RCOMP 0x00001e6c +#define NV20TCL_TX_RCOMP_NEVER 0x00000000 +#define NV20TCL_TX_RCOMP_GREATER 0x00000001 +#define NV20TCL_TX_RCOMP_EQUAL 0x00000002 +#define NV20TCL_TX_RCOMP_GEQUAL 0x00000003 +#define NV20TCL_TX_RCOMP_LESS 0x00000004 +#define NV20TCL_TX_RCOMP_NOTEQUAL 0x00000005 +#define NV20TCL_TX_RCOMP_LEQUAL 0x00000006 +#define NV20TCL_TX_RCOMP_ALWAYS 0x00000007 +#define NV20TCL_TX_SHADER_OP 0x00001e70 +#define NV20TCL_TX_SHADER_OP_TX0_SHIFT 0 +#define NV20TCL_TX_SHADER_OP_TX0_MASK 0x0000001f +#define NV20TCL_TX_SHADER_OP_TX0_NONE 0x00000000 +#define NV20TCL_TX_SHADER_OP_TX0_TEXTURE_2D 0x00000001 +#define NV20TCL_TX_SHADER_OP_TX0_PASS_THROUGH 0x00000004 +#define NV20TCL_TX_SHADER_OP_TX0_CULL_FRAGMENT 0x00000005 +#define NV20TCL_TX_SHADER_OP_TX0_OFFSET_TEXTURE_2D 0x00000006 +#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_TEXTURE_2D 0x00000009 +#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_DEPTH_REPLACE 0x0000000a +#define NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_AR_TEXTURE_2D 0x0000000f +#define NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_GB_TEXTURE_2D 0x00000010 +#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT 0x00000011 +#define NV20TCL_TX_SHADER_OP_TX1_SHIFT 5 +#define NV20TCL_TX_SHADER_OP_TX1_MASK 0x000003e0 +#define NV20TCL_TX_SHADER_OP_TX1_NONE 0x00000000 +#define NV20TCL_TX_SHADER_OP_TX1_TEXTURE_2D 0x00000020 +#define NV20TCL_TX_SHADER_OP_TX1_PASS_THROUGH 0x00000080 +#define NV20TCL_TX_SHADER_OP_TX1_CULL_FRAGMENT 0x000000a0 +#define NV20TCL_TX_SHADER_OP_TX1_OFFSET_TEXTURE_2D 0x000000c0 +#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_TEXTURE_2D 0x00000120 +#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_DEPTH_REPLACE 0x00000140 +#define NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_AR_TEXTURE_2D 0x000001e0 +#define NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_GB_TEXTURE_2D 0x00000200 +#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT 0x00000220 +#define NV20TCL_TX_SHADER_OP_TX2_SHIFT 10 +#define NV20TCL_TX_SHADER_OP_TX2_MASK 0x00007c00 +#define NV20TCL_TX_SHADER_OP_TX2_NONE 0x00000000 +#define NV20TCL_TX_SHADER_OP_TX2_TEXTURE_2D 0x00000400 +#define NV20TCL_TX_SHADER_OP_TX2_PASS_THROUGH 0x00001000 +#define NV20TCL_TX_SHADER_OP_TX2_CULL_FRAGMENT 0x00001400 +#define NV20TCL_TX_SHADER_OP_TX2_OFFSET_TEXTURE_2D 0x00001800 +#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_TEXTURE_2D 0x00002400 +#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_DEPTH_REPLACE 0x00002800 +#define NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_AR_TEXTURE_2D 0x00003c00 +#define NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_GB_TEXTURE_2D 0x00004000 +#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT 0x00004400 +#define NV20TCL_TX_SHADER_OP_TX3_SHIFT 15 +#define NV20TCL_TX_SHADER_OP_TX3_MASK 0x000f8000 +#define NV20TCL_TX_SHADER_OP_TX3_NONE 0x00000000 +#define NV20TCL_TX_SHADER_OP_TX3_TEXTURE_2D 0x00008000 +#define NV20TCL_TX_SHADER_OP_TX3_PASS_THROUGH 0x00020000 +#define NV20TCL_TX_SHADER_OP_TX3_CULL_FRAGMENT 0x00028000 +#define NV20TCL_TX_SHADER_OP_TX3_OFFSET_TEXTURE_2D 0x00030000 +#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_TEXTURE_2D 0x00048000 +#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_DEPTH_REPLACE 0x00050000 +#define NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_AR_TEXTURE_2D 0x00078000 +#define NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_GB_TEXTURE_2D 0x00080000 +#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT 0x00088000 +#define NV20TCL_TX_SHADER_DOTMAPPING 0x00001e74 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX0_SHIFT 0 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX0_MASK 0x0000000f +#define NV20TCL_TX_SHADER_DOTMAPPING_TX1_SHIFT 4 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX1_MASK 0x000000f0 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX2_SHIFT 8 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX2_MASK 0x00000f00 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX3_SHIFT 12 +#define NV20TCL_TX_SHADER_DOTMAPPING_TX3_MASK 0x0000f000 +#define NV20TCL_TX_SHADER_PREVIOUS 0x00001e78 +#define NV20TCL_TX_SHADER_PREVIOUS_TX0_SHIFT 8 +#define NV20TCL_TX_SHADER_PREVIOUS_TX0_MASK 0x00000f00 +#define NV20TCL_TX_SHADER_PREVIOUS_TX1_SHIFT 12 +#define NV20TCL_TX_SHADER_PREVIOUS_TX1_MASK 0x0000f000 +#define NV20TCL_TX_SHADER_PREVIOUS_TX2_SHIFT 16 +#define NV20TCL_TX_SHADER_PREVIOUS_TX2_MASK 0x00030000 +#define NV20TCL_TX_SHADER_PREVIOUS_TX3_SHIFT 20 +#define NV20TCL_TX_SHADER_PREVIOUS_TX3_MASK 0x00300000 +#define NV20TCL_ENGINE 0x00001e94 +#define NV20TCL_ENGINE_VP (1 << 1) +#define NV20TCL_ENGINE_FIXED (1 << 2) +#define NV20TCL_VP_UPLOAD_FROM_ID 0x00001e9c +#define NV20TCL_VP_START_FROM_ID 0x00001ea0 +#define NV20TCL_VP_UPLOAD_CONST_ID 0x00001ea4 + + +#define NV25TCL 0x00000597 + +#define NV25TCL_DMA_IN_MEMORY4 0x0000019c +#define NV25TCL_DMA_IN_MEMORY5 0x000001a0 +#define NV25TCL_DMA_IN_MEMORY8 0x000001ac +#define NV25TCL_DMA_IN_MEMORY9 0x000001b0 + +#endif /* NOUVEAU_REG_H */ + diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c index f481161d46..4a1534bee1 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_context.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c @@ -58,8 +58,10 @@ static const struct dri_extension nouveau_extensions[] = { { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions }, { "GL_EXT_stencil_wrap", NULL }, + { "GL_EXT_texture_env_combine", NULL }, { "GL_EXT_texture_lod_bias", NULL }, { "GL_NV_blend_square", NULL }, + { "GL_NV_texture_env_combine4", NULL }, { "GL_SGIS_generate_mipmap", NULL }, { NULL, NULL } }; @@ -306,6 +308,9 @@ nouveau_context_make_current(__DRIcontext *dri_ctx, __DRIdrawable *dri_draw, GLboolean nouveau_context_unbind(__DRIcontext *dri_ctx) { + /* Unset current context and dispath table */ + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/nouveau/nv04_context.c b/src/mesa/drivers/dri/nouveau/nv04_context.c index 6834f7cd3d..1d34c86350 100644 --- a/src/mesa/drivers/dri/nouveau/nv04_context.c +++ b/src/mesa/drivers/dri/nouveau/nv04_context.c @@ -39,6 +39,7 @@ nv04_context_engine(GLcontext *ctx) struct nouveau_grobj *fahrenheit; if (ctx->Texture.Unit[0].EnvMode == GL_COMBINE || + ctx->Texture.Unit[0].EnvMode == GL_COMBINE4_NV || ctx->Texture.Unit[0].EnvMode == GL_BLEND || ctx->Texture.Unit[0].EnvMode == GL_ADD || ctx->Texture.Unit[1]._ReallyEnabled || diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c index d7c86d4178..bb5d7dc20f 100644 --- a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c +++ b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c @@ -44,6 +44,7 @@ struct combiner_state { GLcontext *ctx; int unit; GLboolean alpha; + GLboolean premodulate; /* GL state */ GLenum mode; @@ -66,6 +67,7 @@ struct combiner_state { (rc)->ctx = ctx; \ (rc)->unit = i; \ (rc)->alpha = __INIT_COMBINER_ALPHA_##chan; \ + (rc)->premodulate = c->_NumArgs##chan == 4; \ (rc)->mode = c->Mode##chan; \ (rc)->source = c->Source##chan; \ (rc)->operand = c->Operand##chan; \ @@ -79,6 +81,9 @@ static uint32_t get_input_source(struct combiner_state *rc, int source) { switch (source) { + case GL_ZERO: + return COMBINER_SOURCE(ZERO); + case GL_TEXTURE: return rc->unit ? COMBINER_SOURCE(TEXTURE1) : COMBINER_SOURCE(TEXTURE0); @@ -195,11 +200,24 @@ setup_combiner(struct combiner_state *rc) break; case GL_ADD: - INPUT_ARG(rc, 0, 0, 0); - INPUT_SRC(rc, 1, ZERO, INVERT); - INPUT_ARG(rc, 2, 1, 0); - INPUT_SRC(rc, 3, ZERO, INVERT); - UNSIGNED_OP(rc); + case GL_ADD_SIGNED: + if (rc->premodulate) { + INPUT_ARG(rc, 0, 0, 0); + INPUT_ARG(rc, 1, 1, 0); + INPUT_ARG(rc, 2, 2, 0); + INPUT_ARG(rc, 3, 3, 0); + } else { + INPUT_ARG(rc, 0, 0, 0); + INPUT_SRC(rc, 1, ZERO, INVERT); + INPUT_ARG(rc, 2, 1, 0); + INPUT_SRC(rc, 3, ZERO, INVERT); + } + + if (rc->mode == GL_ADD_SIGNED) + SIGNED_OP(rc); + else + UNSIGNED_OP(rc); + break; case GL_INTERPOLATE: @@ -210,14 +228,6 @@ setup_combiner(struct combiner_state *rc) UNSIGNED_OP(rc); break; - case GL_ADD_SIGNED: - INPUT_ARG(rc, 0, 0, 0); - INPUT_SRC(rc, 1, ZERO, INVERT); - INPUT_ARG(rc, 2, 1, 0); - INPUT_SRC(rc, 3, ZERO, INVERT); - SIGNED_OP(rc); - break; - default: assert(0); } diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c index 76b95fdd51..ab713f9dbf 100644 --- a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c +++ b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c @@ -63,6 +63,7 @@ struct combiner_state { GLcontext *ctx; int unit; + GLboolean premodulate; /* GL state */ GLenum mode; @@ -82,6 +83,7 @@ struct combiner_state { ctx->Texture.Unit[i]._CurrentCombine; \ (rc)->ctx = ctx; \ (rc)->unit = i; \ + (rc)->premodulate = c->_NumArgs##chan == 4; \ (rc)->mode = c->Mode##chan; \ (rc)->source = c->Source##chan; \ (rc)->operand = c->Operand##chan; \ @@ -95,6 +97,9 @@ static uint32_t get_input_source(struct combiner_state *rc, int source) { switch (source) { + case GL_ZERO: + return RC_IN_SOURCE(ZERO); + case GL_TEXTURE: return RC_IN_SOURCE(TEXTURE0) + rc->unit; @@ -228,21 +233,21 @@ setup_combiner(struct combiner_state *rc) break; case GL_ADD: - INPUT_ARG(rc, A, 0, 0); - INPUT_ONE(rc, B, 0); - INPUT_ARG(rc, C, 1, 0); - INPUT_ONE(rc, D, 0); - - rc->out = RC_OUT_SUM; - break; - case GL_ADD_SIGNED: - INPUT_ARG(rc, A, 0, 0); - INPUT_ONE(rc, B, 0); - INPUT_ARG(rc, C, 1, 0); - INPUT_ONE(rc, D, 0); + if (rc->premodulate) { + INPUT_ARG(rc, A, 0, 0); + INPUT_ARG(rc, B, 1, 0); + INPUT_ARG(rc, C, 2, 0); + INPUT_ARG(rc, D, 3, 0); + } else { + INPUT_ARG(rc, A, 0, 0); + INPUT_ONE(rc, B, 0); + INPUT_ARG(rc, C, 1, 0); + INPUT_ONE(rc, D, 0); + } - rc->out = RC_OUT_SUM | RC_OUT_BIAS; + rc->out = RC_OUT_SUM | + (rc->mode == GL_ADD_SIGNED ? RC_OUT_BIAS : 0); break; case GL_INTERPOLATE: diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c index 62efe80fe4..2daaae260c 100644 --- a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c +++ b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c @@ -32,6 +32,28 @@ #include "nv10_driver.h" #include "nv20_driver.h" +#define LIGHT_MODEL_AMBIENT_R(side) \ + ((side) ? NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R : \ + NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R) +#define LIGHT_AMBIENT_R(side, i) \ + ((side) ? NV20TCL_LIGHT_BACK_AMBIENT_R(i) : \ + NV20TCL_LIGHT_FRONT_AMBIENT_R(i)) +#define LIGHT_DIFFUSE_R(side, i) \ + ((side) ? NV20TCL_LIGHT_BACK_DIFFUSE_R(i) : \ + NV20TCL_LIGHT_FRONT_DIFFUSE_R(i)) +#define LIGHT_SPECULAR_R(side, i) \ + ((side) ? NV20TCL_LIGHT_BACK_SPECULAR_R(i) : \ + NV20TCL_LIGHT_FRONT_SPECULAR_R(i)) +#define MATERIAL_FACTOR_R(side) \ + ((side) ? NV20TCL_MATERIAL_FACTOR_BACK_R : \ + NV20TCL_MATERIAL_FACTOR_FRONT_R) +#define MATERIAL_FACTOR_A(side) \ + ((side) ? NV20TCL_MATERIAL_FACTOR_BACK_A : \ + NV20TCL_MATERIAL_FACTOR_FRONT_A) +#define MATERIAL_SHININESS(side) \ + ((side) ? NV20TCL_BACK_MATERIAL_SHININESS(0) : \ + NV20TCL_FRONT_MATERIAL_SHININESS(0)) + void nv20_emit_clip_plane(GLcontext *ctx, int emit) { @@ -210,10 +232,6 @@ nv20_emit_material_ambient(GLcontext *ctx, int emit) struct nouveau_channel *chan = context_chan(ctx); struct nouveau_grobj *kelvin = context_eng3d(ctx); float (*mat)[4] = ctx->Light.Material.Attrib; - uint32_t m_scene[] = { NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R, - NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R }; - uint32_t m_factor[] = { NV20TCL_MATERIAL_FACTOR_FRONT_R, - NV20TCL_MATERIAL_FACTOR_BACK_R }; float c_scene[3], c_factor[3]; struct gl_light *l; @@ -231,23 +249,21 @@ nv20_emit_material_ambient(GLcontext *ctx, int emit) ZERO_3V(c_factor); } - BEGIN_RING(chan, kelvin, m_scene[side], 3); + BEGIN_RING(chan, kelvin, LIGHT_MODEL_AMBIENT_R(side), 3); OUT_RINGp(chan, c_scene, 3); if (ctx->Light.ColorMaterialEnabled) { - BEGIN_RING(chan, kelvin, m_factor[side], 3); + BEGIN_RING(chan, kelvin, MATERIAL_FACTOR_R(side), 3); OUT_RINGp(chan, c_factor, 3); } foreach(l, &ctx->Light.EnabledList) { const int i = l - ctx->Light.Light; - uint32_t m_light[] = { NV20TCL_LIGHT_FRONT_AMBIENT_R(i), - NV20TCL_LIGHT_BACK_AMBIENT_R(i) }; float *c_light = (USE_COLOR_MATERIAL(AMBIENT, side) ? l->Ambient : l->_MatAmbient[side]); - BEGIN_RING(chan, kelvin, m_light[side], 3); + BEGIN_RING(chan, kelvin, LIGHT_AMBIENT_R(side, i), 3); OUT_RINGp(chan, c_light, 3); } } @@ -259,22 +275,18 @@ nv20_emit_material_diffuse(GLcontext *ctx, int emit) struct nouveau_channel *chan = context_chan(ctx); struct nouveau_grobj *kelvin = context_eng3d(ctx); GLfloat (*mat)[4] = ctx->Light.Material.Attrib; - uint32_t m_factor[] = { NV20TCL_MATERIAL_FACTOR_FRONT_A, - NV20TCL_MATERIAL_FACTOR_BACK_A }; struct gl_light *l; - BEGIN_RING(chan, kelvin, m_factor[side], 1); + BEGIN_RING(chan, kelvin, MATERIAL_FACTOR_A(side), 1); OUT_RINGf(chan, mat[MAT_ATTRIB_DIFFUSE(side)][3]); foreach(l, &ctx->Light.EnabledList) { const int i = l - ctx->Light.Light; - uint32_t m_light[] = { NV20TCL_LIGHT_FRONT_DIFFUSE_R(i), - NV20TCL_LIGHT_BACK_DIFFUSE_R(i) }; float *c_light = (USE_COLOR_MATERIAL(DIFFUSE, side) ? l->Diffuse : l->_MatDiffuse[side]); - BEGIN_RING(chan, kelvin, m_light[side], 3); + BEGIN_RING(chan, kelvin, LIGHT_DIFFUSE_R(side, i), 3); OUT_RINGp(chan, c_light, 3); } } @@ -289,13 +301,11 @@ nv20_emit_material_specular(GLcontext *ctx, int emit) foreach(l, &ctx->Light.EnabledList) { const int i = l - ctx->Light.Light; - uint32_t m_light[] = { NV20TCL_LIGHT_FRONT_SPECULAR_R(i), - NV20TCL_LIGHT_BACK_SPECULAR_R(i) }; float *c_light = (USE_COLOR_MATERIAL(SPECULAR, side) ? l->Specular : l->_MatSpecular[side]); - BEGIN_RING(chan, kelvin, m_light[side], 3); + BEGIN_RING(chan, kelvin, LIGHT_SPECULAR_R(side, i), 3); OUT_RINGp(chan, c_light, 3); } } @@ -307,15 +317,13 @@ nv20_emit_material_shininess(GLcontext *ctx, int emit) struct nouveau_channel *chan = context_chan(ctx); struct nouveau_grobj *kelvin = context_eng3d(ctx); float (*mat)[4] = ctx->Light.Material.Attrib; - uint32_t mthd[] = { NV20TCL_FRONT_MATERIAL_SHININESS(0), - NV20TCL_BACK_MATERIAL_SHININESS(0) }; float k[6]; nv10_get_shininess_coeff( CLAMP(mat[MAT_ATTRIB_SHININESS(side)][0], 0, 1024), k); - BEGIN_RING(chan, kelvin, mthd[side], 6); + BEGIN_RING(chan, kelvin, MATERIAL_SHININESS(side), 6); OUT_RINGp(chan, k, 6); } diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index c9c1346c3a..8013768e9f 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -13,6 +13,7 @@ endif RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ + radeon_buffer_objects.c \ radeon_common_context.c \ radeon_common.c \ radeon_cs_legacy.c \ diff --git a/src/mesa/drivers/dri/r200/radeon_buffer_objects.c b/src/mesa/drivers/dri/r200/radeon_buffer_objects.c new file mode 120000 index 0000000000..f6a5f66470 --- /dev/null +++ b/src/mesa/drivers/dri/r200/radeon_buffer_objects.c @@ -0,0 +1 @@ +../radeon/radeon_buffer_objects.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_buffer_objects.h b/src/mesa/drivers/dri/r200/radeon_buffer_objects.h new file mode 120000 index 0000000000..2f134fd17b --- /dev/null +++ b/src/mesa/drivers/dri/r200/radeon_buffer_objects.h @@ -0,0 +1 @@ +../radeon/radeon_buffer_objects.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog.c index 794db8335a..782671bac0 100644 --- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog.c @@ -31,10 +31,29 @@ #include "../r300_reg.h" +static void presub_string(char out[10], unsigned int inst) +{ + switch(inst & 0x600000){ + case R300_ALU_SRCP_1_MINUS_2_SRC0: + sprintf(out, "bias"); + break; + case R300_ALU_SRCP_SRC1_MINUS_SRC0: + sprintf(out, "sub"); + break; + case R300_ALU_SRCP_SRC1_PLUS_SRC0: + sprintf(out, "add"); + break; + case R300_ALU_SRCP_1_MINUS_SRC0: + sprintf(out, "inv "); + break; + } +} + /* just some random things... */ -void r300FragmentProgramDump(struct rX00_fragment_program_code *c) +void r300FragmentProgramDump(struct radeon_compiler *c, void *user) { - struct r300_fragment_program_code *code = &c->code.r300; + struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c; + struct r300_fragment_program_code *code = &compiler->code->code.r300; int n, i, j; static int pc = 0; @@ -97,8 +116,8 @@ void r300FragmentProgramDump(struct rX00_fragment_program_code *c) for (i = alu_offset; i <= alu_offset + alu_end; ++i) { - char srcc[3][10], dstc[20]; - char srca[3][10], dsta[20]; + char srcc[4][10], dstc[20]; + char srca[4][10], dsta[20]; char argc[3][20]; char arga[3][20]; char flags[5], tmp[10]; @@ -141,6 +160,9 @@ void r300FragmentProgramDump(struct rX00_fragment_program_code *c) flags); strcat(dstc, tmp); } + /* Presub */ + presub_string(srcc[3], code->alu.inst[i].rgb_inst); + presub_string(srca[3], code->alu.inst[i].alpha_inst); dsta[0] = 0; if (code->alu.inst[i].alpha_addr & R300_ALU_DSTA_REG) { @@ -159,11 +181,12 @@ void r300FragmentProgramDump(struct rX00_fragment_program_code *c) } fprintf(stderr, - "%3i: xyz: %3s %3s %3s -> %-20s (%08x)\n" - " w: %3s %3s %3s -> %-20s (%08x)\n", i, - srcc[0], srcc[1], srcc[2], dstc, + "%3i: xyz: %3s %3s %3s %5s-> %-20s (%08x)\n" + " w: %3s %3s %3s %5s-> %-20s (%08x)\n", i, + srcc[0], srcc[1], srcc[2], srcc[3], dstc, code->alu.inst[i].rgb_addr, srca[0], srca[1], - srca[2], dsta, code->alu.inst[i].alpha_addr); + srca[2], srca[3], dsta, + code->alu.inst[i].alpha_addr); for (j = 0; j < 3; ++j) { int regc = code->alu.inst[i].rgb_inst >> (j * 7); @@ -193,6 +216,24 @@ void r300FragmentProgramDump(struct rX00_fragment_program_code *c) } } else if (d < 15) { sprintf(buf, "%s.www", srca[d - 12]); + } else if (d < 20 ) { + switch(d) { + case R300_ALU_ARGC_SRCP_XYZ: + sprintf(buf, "srcp.xyz"); + break; + case R300_ALU_ARGC_SRCP_XXX: + sprintf(buf, "srcp.xxx"); + break; + case R300_ALU_ARGC_SRCP_YYY: + sprintf(buf, "srcp.yyy"); + break; + case R300_ALU_ARGC_SRCP_ZZZ: + sprintf(buf, "srcp.zzz"); + break; + case R300_ALU_ARGC_SRCP_WWW: + sprintf(buf, "srcp.www"); + break; + } } else if (d == 20) { sprintf(buf, "0.0"); } else if (d == 21) { @@ -230,6 +271,21 @@ void r300FragmentProgramDump(struct rX00_fragment_program_code *c) 'x' + (char)(d % 3)); } else if (d < 12) { sprintf(buf, "%s.w", srca[d - 9]); + } else if (d < 16) { + switch(d) { + case R300_ALU_ARGA_SRCP_X: + sprintf(buf, "srcp.x"); + break; + case R300_ALU_ARGA_SRCP_Y: + sprintf(buf, "srcp.y"); + break; + case R300_ALU_ARGA_SRCP_Z: + sprintf(buf, "srcp.z"); + break; + case R300_ALU_ARGA_SRCP_W: + sprintf(buf, "srcp.w"); + break; + } } else if (d == 16) { sprintf(buf, "0.0"); } else if (d == 17) { @@ -246,11 +302,14 @@ void r300FragmentProgramDump(struct rX00_fragment_program_code *c) buf, (rega & 64) ? "|" : ""); } - fprintf(stderr, " xyz: %8s %8s %8s op: %08x\n" + fprintf(stderr, " xyz: %8s %8s %8s op: %08x %s\n" " w: %8s %8s %8s op: %08x\n", argc[0], argc[1], argc[2], - code->alu.inst[i].rgb_inst, arga[0], arga[1], - arga[2], code->alu.inst[i].alpha_inst); + code->alu.inst[i].rgb_inst, + code->alu.inst[i].rgb_inst & R300_ALU_INSERT_NOP ? + "NOP" : "", + arga[0], arga[1],arga[2], + code->alu.inst[i].alpha_inst); } } } diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog.h b/src/mesa/drivers/dri/r300/compiler/r300_fragprog.h index 8b755703be..0c88bab2f3 100644 --- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog.h @@ -37,8 +37,8 @@ #include "radeon_program.h" -extern void r300BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler); +extern void r300BuildFragmentProgramHwCode(struct radeon_compiler *c, void *user); -extern void r300FragmentProgramDump(struct rX00_fragment_program_code *c); +extern void r300FragmentProgramDump(struct radeon_compiler *c, void *user); #endif diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c index b27a683c39..3b2b06fc2b 100644 --- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c @@ -135,7 +135,7 @@ static int emit_alu(struct r300_emit_state * emit, struct rc_pair_instruction* i { PROG_CODE; - if (code->alu.length >= R300_PFS_MAX_ALU_INST) { + if (code->alu.length >= c->Base.max_alu_insts) { error("Too many ALU instructions"); return 0; } @@ -164,6 +164,53 @@ static int emit_alu(struct r300_emit_state * emit, struct rc_pair_instruction* i code->alu.inst[ip].alpha_inst |= arg << (7*j); } + /* Presubtract */ + if (inst->RGB.Src[RC_PAIR_PRESUB_SRC].Used) { + switch(inst->RGB.Src[RC_PAIR_PRESUB_SRC].Index) { + case RC_PRESUB_BIAS: + code->alu.inst[ip].rgb_inst |= + R300_ALU_SRCP_1_MINUS_2_SRC0; + break; + case RC_PRESUB_ADD: + code->alu.inst[ip].rgb_inst |= + R300_ALU_SRCP_SRC1_PLUS_SRC0; + break; + case RC_PRESUB_SUB: + code->alu.inst[ip].rgb_inst |= + R300_ALU_SRCP_SRC1_MINUS_SRC0; + break; + case RC_PRESUB_INV: + code->alu.inst[ip].rgb_inst |= + R300_ALU_SRCP_1_MINUS_SRC0; + break; + default: + break; + } + } + + if (inst->Alpha.Src[RC_PAIR_PRESUB_SRC].Used) { + switch(inst->Alpha.Src[RC_PAIR_PRESUB_SRC].Index) { + case RC_PRESUB_BIAS: + code->alu.inst[ip].alpha_inst |= + R300_ALU_SRCP_1_MINUS_2_SRC0; + break; + case RC_PRESUB_ADD: + code->alu.inst[ip].alpha_inst |= + R300_ALU_SRCP_SRC1_PLUS_SRC0; + break; + case RC_PRESUB_SUB: + code->alu.inst[ip].alpha_inst |= + R300_ALU_SRCP_SRC1_MINUS_SRC0; + break; + case RC_PRESUB_INV: + code->alu.inst[ip].alpha_inst |= + R300_ALU_SRCP_1_MINUS_SRC0; + break; + default: + break; + } + } + if (inst->RGB.Saturate) code->alu.inst[ip].rgb_inst |= R300_ALU_OUTC_CLAMP; if (inst->Alpha.Saturate) @@ -198,6 +245,8 @@ static int emit_alu(struct r300_emit_state * emit, struct rc_pair_instruction* i emit->node_flags |= R300_W_OUT; c->code->writes_depth = 1; } + if (inst->Nop) + code->alu.inst[ip].rgb_inst |= R300_ALU_INSERT_NOP; return 1; } @@ -328,8 +377,9 @@ static int emit_tex(struct r300_emit_state * emit, struct rc_instruction * inst) * Final compilation step: Turn the intermediate radeon_program into * machine-readable instructions. */ -void r300BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler) +void r300BuildFragmentProgramHwCode(struct radeon_compiler *c, void *user) { + struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c; struct r300_emit_state emit; struct r300_fragment_program_code *code = &compiler->code->code.r300; diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c index 5d5de2f1b2..caa48fe478 100644 --- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c +++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c @@ -44,25 +44,25 @@ struct swizzle_data { unsigned int hash; /**< swizzle value this matches */ unsigned int base; /**< base value for hw swizzle */ unsigned int stride; /**< difference in base between arg0/1/2 */ + unsigned int srcp_stride; /**< difference in base between arg0/scrp */ }; static const struct swizzle_data native_swizzles[] = { - {MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4}, - {MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4}, - {MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4}, - {MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4}, - {MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1}, - {MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1}, - {MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1}, - {MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1}, - {MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0}, - {MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0}, - {MAKE_SWZ3(HALF, HALF, HALF), R300_ALU_ARGC_HALF, 0} + {MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4, 15}, + {MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4, 15}, + {MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4, 15}, + {MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4, 15}, + {MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1, 7}, + {MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1, 0}, + {MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1, 0}, + {MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1, 0}, + {MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0, 0}, + {MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0, 0}, + {MAKE_SWZ3(HALF, HALF, HALF), R300_ALU_ARGC_HALF, 0, 0} }; static const int num_native_swizzles = sizeof(native_swizzles)/sizeof(native_swizzles[0]); - /** * Find a native RGB swizzle that matches the given swizzle. * Returns 0 if none found. @@ -205,7 +205,11 @@ unsigned int r300FPTranslateRGBSwizzle(unsigned int src, unsigned int swizzle) return 0; } - return sd->base + src*sd->stride; + if (src == RC_PAIR_PRESUB_SRC) { + return sd->base + sd->srcp_stride; + } else { + return sd->base + src*sd->stride; + } } @@ -215,6 +219,9 @@ unsigned int r300FPTranslateRGBSwizzle(unsigned int src, unsigned int swizzle) */ unsigned int r300FPTranslateAlphaSwizzle(unsigned int src, unsigned int swizzle) { + if (src == RC_PAIR_PRESUB_SRC) { + return R300_ALU_ARGA_SRCP_X + swizzle; + } if (swizzle < 3) return swizzle + 3*src; diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c index 8613ec5109..4793f33577 100644 --- a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c @@ -47,8 +47,9 @@ static void dataflow_outputs_mark_use(void * userdata, void * data, callback(data, c->OutputDepth, RC_MASK_W); } -static void rewrite_depth_out(struct r300_fragment_program_compiler * c) +static void rc_rewrite_depth_out(struct radeon_compiler *cc, void *user) { + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc; struct rc_instruction *rci; for (rci = c->Base.Program.Instructions.Next; rci != &c->Base.Program.Instructions; rci = rci->Next) { @@ -89,157 +90,69 @@ static void rewrite_depth_out(struct r300_fragment_program_compiler * c) } } -static void debug_program_log(struct r300_fragment_program_compiler* c, const char * where) -{ - if (c->Base.Debug) { - fprintf(stderr, "Fragment Program: %s\n", where); - rc_print_program(&c->Base.Program); - } -} - void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c) { - struct emulate_loop_state loop_state; - - rewrite_depth_out(c); - - /* This transformation needs to be done before any of the IF - * instructions are modified. */ - radeonTransformKILP(&c->Base); - - debug_program_log(c, "before compilation"); - - if (c->Base.is_r500){ - rc_unroll_loops(&c->Base, R500_PFS_MAX_INST); - debug_program_log(c, "after unroll loops"); - } - else{ - rc_transform_loops(&c->Base, &loop_state, -1); - debug_program_log(c, "after transform loops"); - - rc_emulate_branches(&c->Base); - debug_program_log(c, "after emulate branches"); - } - - if (c->Base.is_r500) { - struct radeon_program_transformation transformations[] = { - { &r500_transform_IF, 0 }, - { &radeonTransformALU, 0 }, - { &radeonTransformDeriv, 0 }, - { &radeonTransformTrigScale, 0 } - }; - radeonLocalTransform(&c->Base, 4, transformations); + int is_r500 = c->Base.is_r500; + int kill_consts = c->Base.remove_unused_constants; + int opt = !c->Base.disable_optimizations; - debug_program_log(c, "after native rewrite part 1"); - - c->Base.SwizzleCaps = &r500_swizzle_caps; - } else { - struct radeon_program_transformation transformations[] = { - { &radeonTransformALU, 0 }, - { &radeonTransformTrigSimple, 0 } - }; - radeonLocalTransform(&c->Base, 2, transformations); - - debug_program_log(c, "after native rewrite part 1"); - - c->Base.SwizzleCaps = &r300_swizzle_caps; - } - - /* Run the common transformations too. - * Remember, lowering comes last! */ - struct radeon_program_transformation common_transformations[] = { + /* Lists of instruction transformations. */ + struct radeon_program_transformation rewrite_tex[] = { { &radeonTransformTEX, c }, + { 0, 0 } }; - radeonLocalTransform(&c->Base, 1, common_transformations); - - common_transformations[0].function = &radeonTransformALU; - radeonLocalTransform(&c->Base, 1, common_transformations); - - if (c->Base.Error) - return; - - debug_program_log(c, "after native rewrite part 2"); - - rc_dataflow_deadcode(&c->Base, &dataflow_outputs_mark_use, c); - if (c->Base.Error) - return; - - debug_program_log(c, "after deadcode"); - - if(!c->Base.is_r500){ - rc_emulate_loops(&loop_state, R300_PFS_MAX_ALU_INST); - debug_program_log(c, "after emulate loops"); - } - rc_optimize(&c->Base); - - debug_program_log(c, "after dataflow optimize"); - - rc_dataflow_swizzles(&c->Base); - if (c->Base.Error) - return; - - debug_program_log(c, "after dataflow passes"); - - if (c->Base.remove_unused_constants) { - rc_remove_unused_constants(&c->Base, - &c->code->constants_remap_table); + struct radeon_program_transformation native_rewrite_r500[] = { + { &r500_transform_IF, 0 }, + { &radeonTransformALU, 0 }, + { &radeonTransformDeriv, 0 }, + { &radeonTransformTrigScale, 0 }, + { 0, 0 } + }; - debug_program_log(c, "after constants cleanup"); - } + struct radeon_program_transformation native_rewrite_r300[] = { + { &radeonTransformALU, 0 }, + { &r300_transform_trig_simple, 0 }, + { 0, 0 } + }; - if(!c->Base.is_r500) { + /* List of compiler passes. */ + struct radeon_compiler_pass fs_list[] = { + /* NAME DUMP PREDICATE FUNCTION PARAM */ + {"rewrite depth out", 1, 1, rc_rewrite_depth_out, NULL}, + /* This transformation needs to be done before any of the IF + * instructions are modified. */ + {"transform KILP", 1, 1, rc_transform_KILP, NULL}, + {"unroll loops", 1, is_r500, rc_unroll_loops, NULL}, + {"transform loops", 1, !is_r500, rc_transform_loops, NULL}, + {"emulate branches", 1, !is_r500, rc_emulate_branches, NULL}, + {"transform TEX", 1, 1, rc_local_transform, rewrite_tex}, + {"native rewrite", 1, is_r500, rc_local_transform, native_rewrite_r500}, + {"native rewrite", 1, !is_r500, rc_local_transform, native_rewrite_r300}, + {"deadcode", 1, opt, rc_dataflow_deadcode, dataflow_outputs_mark_use}, + {"emulate loops", 1, !is_r500, rc_emulate_loops, NULL}, + {"dataflow optimize", 1, opt, rc_optimize, NULL}, + {"dataflow swizzles", 1, 1, rc_dataflow_swizzles, NULL}, + {"dead constants", 1, kill_consts, rc_remove_unused_constants, &c->code->constants_remap_table}, /* This pass makes it easier for the scheduler to group TEX * instructions and reduces the chances of creating too * many texture indirections.*/ - rc_rename_regs(&c->Base); - if (c->Base.Error) - return; - debug_program_log(c, "after register rename"); - } - - rc_pair_translate(c); - if (c->Base.Error) - return; - - debug_program_log(c, "after pair translate"); - - rc_pair_schedule(c); - if (c->Base.Error) - return; - - debug_program_log(c, "after pair scheduling"); - - rc_pair_regalloc(c, c->Base.max_temp_regs); - - if (c->Base.Error) - return; + {"register rename", 1, !is_r500, rc_rename_regs, NULL}, + {"pair translate", 1, 1, rc_pair_translate, NULL}, + {"pair scheduling", 1, 1, rc_pair_schedule, NULL}, + {"register allocation", 1, opt, rc_pair_regalloc, NULL}, + {"dumb register allocation", 1, !opt, rc_pair_regalloc_inputs_only, NULL}, + {"final code validation", 0, 1, rc_validate_final_shader, NULL}, + {"machine code generation", 0, is_r500, r500BuildFragmentProgramHwCode, NULL}, + {"machine code generation", 0, !is_r500, r300BuildFragmentProgramHwCode, NULL}, + {"dump machine code", 0, is_r500 && c->Base.Debug, r500FragmentProgramDump, NULL}, + {"dump machine code", 0, !is_r500 && c->Base.Debug, r300FragmentProgramDump, NULL}, + {NULL, 0, 0, NULL, NULL} + }; - debug_program_log(c, "after register allocation"); + c->Base.SwizzleCaps = c->Base.is_r500 ? &r500_swizzle_caps : &r300_swizzle_caps; - if (c->Base.is_r500) { - r500BuildFragmentProgramHwCode(c); - } else { - r300BuildFragmentProgramHwCode(c); - } + rc_run_compiler(&c->Base, fs_list, "Fragment Program"); rc_constants_copy(&c->code->constants, &c->Base.Program.Constants); - - if (c->Base.Debug) { - if (c->Base.is_r500) { - r500FragmentProgramDump(c->code); - } else { - r300FragmentProgramDump(c->code); - } - } - - /* Check the number of constants. */ - if (!c->Base.Error) { - unsigned max = c->Base.is_r500 ? R500_PFS_NUM_CONST_REGS : R300_PFS_NUM_CONST_REGS; - - if (c->Base.Program.Constants.Count > max) { - rc_error(&c->Base, "Too many constants. Max: %i, Got: %i\n", - max, c->Base.Program.Constants.Count); - } - } } diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c index b05b3aabf3..08785716db 100644 --- a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c @@ -391,7 +391,7 @@ static void ei_if(struct r300_vertex_program_compiler * compiler, /* Reserve a temporary to use as our predicate stack counter, if we * don't already have one. */ if (!compiler->PredicateMask) { - unsigned int writemasks[R300_VS_MAX_TEMPS]; + unsigned int writemasks[RC_REGISTER_MAX_INDEX]; memset(writemasks, 0, sizeof(writemasks)); struct rc_instruction * inst; unsigned int i; @@ -400,7 +400,7 @@ static void ei_if(struct r300_vertex_program_compiler * compiler, inst = inst->Next) { rc_for_all_writes_mask(inst, mark_write, writemasks); } - for(i = 0; i < R300_VS_MAX_TEMPS; i++) { + for(i = 0; i < compiler->Base.max_temp_regs; i++) { unsigned int mask = ~writemasks[i] & RC_MASK_XYZW; /* Only the W component can be used fo the predicate * stack counter. */ @@ -410,7 +410,7 @@ static void ei_if(struct r300_vertex_program_compiler * compiler, break; } } - if (i == R300_VS_MAX_TEMPS) { + if (i == compiler->Base.max_temp_regs) { rc_error(&compiler->Base, "No free temporary to use for" " predicate stack counter.\n"); return; @@ -462,8 +462,9 @@ static void ei_endif(struct r300_vertex_program_compiler *compiler, inst[3] = 0; } -static void translate_vertex_program(struct r300_vertex_program_compiler * compiler) +static void translate_vertex_program(struct radeon_compiler *c, void *user) { + struct r300_vertex_program_compiler *compiler = (struct r300_vertex_program_compiler*)c; struct rc_instruction *rci; struct loop * loops = NULL; @@ -474,18 +475,20 @@ static void translate_vertex_program(struct r300_vertex_program_compiler * compi compiler->code->pos_end = 0; /* Not supported yet */ compiler->code->length = 0; + compiler->code->num_temporaries = 0; compiler->SetHwInputOutput(compiler); for(rci = compiler->Base.Program.Instructions.Next; rci != &compiler->Base.Program.Instructions; rci = rci->Next) { struct rc_sub_instruction *vpi = &rci->U.I; unsigned int *inst = compiler->code->body.d + compiler->code->length; + const struct rc_opcode_info *info = rc_get_opcode_info(vpi->Opcode); /* Skip instructions writing to non-existing destination */ if (!valid_dst(compiler->code, &vpi->DstReg)) continue; - if (rc_get_opcode_info(vpi->Opcode)->HasDstReg) { + if (info->HasDstReg) { /* Relative addressing of destination operands is not supported yet. */ if (vpi->DstReg.RelAddr) { rc_error(&compiler->Base, "Vertex program does not support relative " @@ -500,8 +503,7 @@ static void translate_vertex_program(struct r300_vertex_program_compiler * compi } } - if (compiler->code->length >= R500_VS_MAX_ALU_DWORDS || - (compiler->code->length >= R300_VS_MAX_ALU_DWORDS && !compiler->Base.is_r500)) { + if (compiler->code->length >= c->max_alu_insts * 4) { rc_error(&compiler->Base, "Vertex program has too many instructions\n"); return; } @@ -607,7 +609,7 @@ static void translate_vertex_program(struct r300_vertex_program_compiler * compi } default: - rc_error(&compiler->Base, "Unknown opcode %s\n", rc_get_opcode_info(vpi->Opcode)->Name); + rc_error(&compiler->Base, "Unknown opcode %s\n", info->Name); return; } @@ -624,6 +626,25 @@ static void translate_vertex_program(struct r300_vertex_program_compiler * compi << PVS_DST_PRED_SENSE_SHIFT); } + /* Update the number of temporaries. */ + if (info->HasDstReg && vpi->DstReg.File == RC_FILE_TEMPORARY && + vpi->DstReg.Index >= compiler->code->num_temporaries) + compiler->code->num_temporaries = vpi->DstReg.Index + 1; + + for (unsigned i = 0; i < info->NumSrcRegs; i++) + if (vpi->SrcReg[i].File == RC_FILE_TEMPORARY && + vpi->SrcReg[i].Index >= compiler->code->num_temporaries) + compiler->code->num_temporaries = vpi->SrcReg[i].Index + 1; + + if (compiler->PredicateMask) + if (compiler->PredicateIndex >= compiler->code->num_temporaries) + compiler->code->num_temporaries = compiler->PredicateIndex + 1; + + if (compiler->code->num_temporaries > compiler->Base.max_temp_regs) { + rc_error(&compiler->Base, "Too many temporaries.\n"); + return; + } + compiler->code->length += 4; if (compiler->Base.Error) @@ -637,17 +658,21 @@ struct temporary_allocation { struct rc_instruction * LastRead; }; -static void allocate_temporary_registers(struct r300_vertex_program_compiler * compiler) +static void allocate_temporary_registers(struct radeon_compiler *c, void *user) { + struct r300_vertex_program_compiler *compiler = (struct r300_vertex_program_compiler*)c; struct rc_instruction *inst; struct rc_instruction *end_loop = NULL; unsigned int num_orig_temps = 0; - char hwtemps[R300_VS_MAX_TEMPS]; + char hwtemps[RC_REGISTER_MAX_INDEX]; struct temporary_allocation * ta; unsigned int i, j; + struct rc_instruction *last_inst_src_reladdr = NULL; memset(hwtemps, 0, sizeof(hwtemps)); + rc_recompute_ips(c); + /* Pass 1: Count original temporaries. */ for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); @@ -666,9 +691,9 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c } } } - compiler->code->num_temporaries = num_orig_temps; - /* Pass 2: If there is relative addressing of temporaries, we cannot change register indices. Give up. */ + /* Pass 2: If there is relative addressing of dst temporaries, we cannot change register indices. Give up. + * For src temporaries, save the last instruction which uses relative addressing. */ for (inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) { const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); @@ -679,12 +704,11 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c for (i = 0; i < opcode->NumSrcRegs; ++i) { if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY && inst->U.I.SrcReg[i].RelAddr) { - return; + last_inst_src_reladdr = inst; } } } - compiler->code->num_temporaries = 0; ta = (struct temporary_allocation*)memory_pool_malloc(&compiler->Base.Pool, sizeof(struct temporary_allocation) * num_orig_temps); memset(ta, 0, sizeof(struct temporary_allocation) * num_orig_temps); @@ -718,9 +742,26 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c } for (i = 0; i < opcode->NumSrcRegs; ++i) { - if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) - ta[inst->U.I.SrcReg[i].Index].LastRead = - end_loop ? end_loop : inst; + if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) { + struct rc_instruction *last_read; + + /* From "last_inst_src_reladdr", "end_loop", and "inst", + * select the instruction with the highest instruction index (IP). + * Note that "end_loop", if available, has always a higher index than "inst". */ + if (last_inst_src_reladdr) { + if (end_loop) { + last_read = last_inst_src_reladdr->IP > end_loop->IP ? + last_inst_src_reladdr : end_loop; + } else { + last_read = last_inst_src_reladdr->IP > inst->IP ? + last_inst_src_reladdr : inst; + } + } else { + last_read = end_loop ? end_loop : inst; + } + + ta[inst->U.I.SrcReg[i].Index].LastRead = last_read; + } } } @@ -728,13 +769,15 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); - for (i = 0; i < opcode->NumSrcRegs; ++i) { - if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) { - unsigned int orig = inst->U.I.SrcReg[i].Index; - inst->U.I.SrcReg[i].Index = ta[orig].HwTemp; + if (!last_inst_src_reladdr || last_inst_src_reladdr->IP < inst->IP) { + for (i = 0; i < opcode->NumSrcRegs; ++i) { + if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) { + unsigned int orig = inst->U.I.SrcReg[i].Index; + inst->U.I.SrcReg[i].Index = ta[orig].HwTemp; - if (ta[orig].Allocated && inst == ta[orig].LastRead) - hwtemps[ta[orig].HwTemp] = 0; + if (ta[orig].Allocated && inst == ta[orig].LastRead) + hwtemps[ta[orig].HwTemp] = 0; + } } } @@ -743,19 +786,22 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c unsigned int orig = inst->U.I.DstReg.Index; if (!ta[orig].Allocated) { - for(j = 0; j < R300_VS_MAX_TEMPS; ++j) { + for(j = 0; j < c->max_temp_regs; ++j) { if (!hwtemps[j]) break; } - if (j >= R300_VS_MAX_TEMPS) { - fprintf(stderr, "Out of hw temporaries\n"); + if (j >= c->max_temp_regs) { + rc_error(c, "Too many temporaries\n"); + return; } else { ta[orig].Allocated = 1; - ta[orig].HwTemp = j; - hwtemps[j] = 1; - - if (j >= compiler->code->num_temporaries) - compiler->code->num_temporaries = j + 1; + if (last_inst_src_reladdr && + last_inst_src_reladdr->IP > inst->IP) { + ta[orig].HwTemp = orig; + } else { + ta[orig].HwTemp = j; + } + hwtemps[ta[orig].HwTemp] = 1; } } @@ -849,8 +895,9 @@ static int transform_source_conflicts( return 1; } -static void addArtificialOutputs(struct r300_vertex_program_compiler * compiler) +static void rc_vs_add_artificial_outputs(struct radeon_compiler *c, void *user) { + struct r300_vertex_program_compiler * compiler = (struct r300_vertex_program_compiler*)c; int i; for(i = 0; i < 32; ++i) { @@ -926,8 +973,9 @@ static void transform_negative_addressing(struct r300_vertex_program_compiler *c } } -static void rc_emulate_negative_addressing(struct r300_vertex_program_compiler *c) +static void rc_emulate_negative_addressing(struct radeon_compiler *compiler, void *user) { + struct r300_vertex_program_compiler * c = (struct r300_vertex_program_compiler*)compiler; struct rc_instruction *inst, *lastARL = NULL; int min_offset = 0; @@ -962,145 +1010,72 @@ static void rc_emulate_negative_addressing(struct r300_vertex_program_compiler * transform_negative_addressing(c, lastARL, inst, min_offset); } -static void debug_program_log(struct r300_vertex_program_compiler* c, const char * where) -{ - if (c->Base.Debug) { - fprintf(stderr, "Vertex Program: %s\n", where); - rc_print_program(&c->Base.Program); - } -} - - static struct rc_swizzle_caps r300_vertprog_swizzle_caps = { .IsNative = &swizzle_is_native, .Split = 0 /* should never be called */ }; - void r3xx_compile_vertex_program(struct r300_vertex_program_compiler *c) { - struct emulate_loop_state loop_state; + int is_r500 = c->Base.is_r500; + int kill_consts = c->Base.remove_unused_constants; + int opt = !c->Base.disable_optimizations; + + /* Lists of instruction transformations. */ + struct radeon_program_transformation alu_rewrite_r500[] = { + { &r300_transform_vertex_alu, 0 }, + { &r300_transform_trig_scale_vertex, 0 }, + { 0, 0 } + }; + + struct radeon_program_transformation alu_rewrite_r300[] = { + { &r300_transform_vertex_alu, 0 }, + { &r300_transform_trig_simple, 0 }, + { 0, 0 } + }; + + /* Note: These passes have to be done seperately from ALU rewrite, + * otherwise non-native ALU instructions with source conflits + * or non-native modifiers will not be treated properly. + */ + struct radeon_program_transformation emulate_modifiers[] = { + { &transform_nonnative_modifiers, 0 }, + { 0, 0 } + }; + + struct radeon_program_transformation resolve_src_conflicts[] = { + { &transform_source_conflicts, 0 }, + { 0, 0 } + }; + + /* List of compiler passes. */ + struct radeon_compiler_pass vs_list[] = { + /* NAME DUMP PREDICATE FUNCTION PARAM */ + {"add artificial outputs", 0, 1, rc_vs_add_artificial_outputs, NULL}, + {"transform loops", 1, 1, rc_transform_loops, NULL}, + {"emulate branches", 1, !is_r500, rc_emulate_branches, NULL}, + {"emulate negative addressing", 1, 1, rc_emulate_negative_addressing, NULL}, + {"native rewrite", 1, is_r500, rc_local_transform, alu_rewrite_r500}, + {"native rewrite", 1, !is_r500, rc_local_transform, alu_rewrite_r300}, + {"emulate modifiers", 1, !is_r500, rc_local_transform, emulate_modifiers}, + {"deadcode", 1, opt, rc_dataflow_deadcode, dataflow_outputs_mark_used}, + {"dataflow optimize", 1, opt, rc_optimize, NULL}, + /* This pass must be done after optimizations. */ + {"source conflict resolve", 1, 1, rc_local_transform, resolve_src_conflicts}, + {"dataflow swizzles", 1, 1, rc_dataflow_swizzles, NULL}, + {"register allocation", 1, opt, allocate_temporary_registers, NULL}, + {"dead constants", 1, kill_consts, rc_remove_unused_constants, &c->code->constants_remap_table}, + {"final code validation", 0, 1, rc_validate_final_shader, NULL}, + {"machine code generation", 0, 1, translate_vertex_program, NULL}, + {"dump machine code", 0,c->Base.Debug,r300_vertex_program_dump, NULL}, + {NULL, 0, 0, NULL, NULL} + }; c->Base.SwizzleCaps = &r300_vertprog_swizzle_caps; - addArtificialOutputs(c); - - debug_program_log(c, "before compilation"); - - if (c->Base.is_r500) - rc_transform_loops(&c->Base, &loop_state, R500_VS_MAX_ALU); - else - rc_transform_loops(&c->Base, &loop_state, R300_VS_MAX_ALU); - if (c->Base.Error) - return; - - debug_program_log(c, "after emulate loops"); - - if (!c->Base.is_r500) { - rc_emulate_branches(&c->Base); - if (c->Base.Error) - return; - debug_program_log(c, "after emulate branches"); - } - - rc_emulate_negative_addressing(c); - - debug_program_log(c, "after negative addressing emulation"); - - if (c->Base.is_r500) { - struct radeon_program_transformation transformations[] = { - { &r300_transform_vertex_alu, 0 }, - { &r300_transform_trig_scale_vertex, 0 } - }; - radeonLocalTransform(&c->Base, 2, transformations); - if (c->Base.Error) - return; - - debug_program_log(c, "after native rewrite"); - } else { - struct radeon_program_transformation transformations[] = { - { &r300_transform_vertex_alu, 0 }, - { &radeonTransformTrigSimple, 0 } - }; - radeonLocalTransform(&c->Base, 2, transformations); - if (c->Base.Error) - return; - - debug_program_log(c, "after native rewrite"); - - /* Note: This pass has to be done seperately from ALU rewrite, - * because it needs to check every instruction. - */ - struct radeon_program_transformation transformations2[] = { - { &transform_nonnative_modifiers, 0 }, - }; - radeonLocalTransform(&c->Base, 1, transformations2); - if (c->Base.Error) - return; - - debug_program_log(c, "after emulate modifiers"); - } - - { - /* Note: This pass has to be done seperately from ALU rewrite, - * otherwise non-native ALU instructions with source conflits - * will not be treated properly. - */ - struct radeon_program_transformation transformations[] = { - { &transform_source_conflicts, 0 }, - }; - radeonLocalTransform(&c->Base, 1, transformations); - if (c->Base.Error) - return; - } - - debug_program_log(c, "after source conflict resolve"); - - rc_dataflow_deadcode(&c->Base, &dataflow_outputs_mark_used, c); - if (c->Base.Error) - return; - - debug_program_log(c, "after deadcode"); - - rc_dataflow_swizzles(&c->Base); - if (c->Base.Error) - return; - - debug_program_log(c, "after dataflow"); - - allocate_temporary_registers(c); - if (c->Base.Error) - return; - - debug_program_log(c, "after register allocation"); - - if (c->Base.remove_unused_constants) { - rc_remove_unused_constants(&c->Base, - &c->code->constants_remap_table); - if (c->Base.Error) - return; - - debug_program_log(c, "after constants cleanup"); - } - - translate_vertex_program(c); - if (c->Base.Error) - return; - - rc_constants_copy(&c->code->constants, &c->Base.Program.Constants); + rc_run_compiler(&c->Base, vs_list, "Vertex Program"); c->code->InputsRead = c->Base.Program.InputsRead; c->code->OutputsWritten = c->Base.Program.OutputsWritten; - - if (c->Base.Debug) { - fprintf(stderr, "Final vertex program code:\n"); - r300_vertex_program_dump(c); - } - - /* Check the number of constants. */ - if (!c->Base.Error && - c->Base.Program.Constants.Count > 256) { - rc_error(&c->Base, "Too many constants. Max: 256, Got: %i\n", - c->Base.Program.Constants.Count); - } + rc_constants_copy(&c->code->constants, &c->Base.Program.Constants); } diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog_dump.c b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog_dump.c index e6009338e2..2bc0a87eed 100644 --- a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog_dump.c +++ b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog_dump.c @@ -166,12 +166,15 @@ static void r300_vs_src_dump(uint32_t src) r300_vs_swiz_debug[(src >> 22) & 0x7]); } -void r300_vertex_program_dump(struct r300_vertex_program_compiler * c) +void r300_vertex_program_dump(struct radeon_compiler *compiler, void *user) { + struct r300_vertex_program_compiler *c = (struct r300_vertex_program_compiler*)compiler; struct r300_vertex_program_code * vs = c->code; unsigned instrcount = vs->length / 4; unsigned i; + fprintf(stderr, "Final vertex program code:\n"); + for(i = 0; i < instrcount; i++) { unsigned offset = i*4; unsigned src; diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c index 80a120497e..627ce374ef 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c @@ -247,9 +247,10 @@ static char *to_texop(int val) return NULL; } -void r500FragmentProgramDump(struct rX00_fragment_program_code *c) +void r500FragmentProgramDump(struct radeon_compiler *c, void *user) { - struct r500_fragment_program_code *code = &c->code.r500; + struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c; + struct r500_fragment_program_code *code = &compiler->code->code.r500; fprintf(stderr, "R500 Fragment Program:\n--------\n"); int n, i; diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h index 34173351f8..1e665e2764 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h @@ -36,11 +36,9 @@ #include "radeon_compiler.h" #include "radeon_swizzle.h" -struct emulate_loop_state; +extern void r500BuildFragmentProgramHwCode(struct radeon_compiler *c, void *user); -extern void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler); - -extern void r500FragmentProgramDump(struct rX00_fragment_program_code *c); +extern void r500FragmentProgramDump(struct radeon_compiler *c, void *user); extern struct rc_swizzle_caps r500_swizzle_caps; diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c index 9b60e30f58..54cff9169a 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c @@ -63,7 +63,7 @@ struct branch_info { int Endif; }; -struct loop_info { +struct r500_loop_info { int BgnLoop; int BranchDepth; @@ -84,7 +84,7 @@ struct emit_state { unsigned int CurrentBranchDepth; unsigned int BranchesReserved; - struct loop_info * Loops; + struct r500_loop_info * Loops; unsigned int CurrentLoopDepth; unsigned int LoopsReserved; @@ -229,7 +229,7 @@ static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair { PROG_CODE; - if (code->inst_end >= 511) { + if (code->inst_end >= c->Base.max_alu_insts-1) { error("emit_alu: Too many instructions"); return; } @@ -260,6 +260,9 @@ static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14); code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18); + if (inst->Nop) { + code->inst[ip].inst0 |= R500_INST_NOP; + } if (inst->Alpha.DepthWriteMask) { code->inst[ip].inst4 |= R500_ALPHA_W_OMASK; c->code->writes_depth = 1; @@ -275,6 +278,40 @@ static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair if (inst->Alpha.Saturate) code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP; + /* Set the presubtract operation. */ + switch(inst->RGB.Src[RC_PAIR_PRESUB_SRC].Index) { + case RC_PRESUB_BIAS: + code->inst[ip].inst1 |= R500_RGB_SRCP_OP_1_MINUS_2RGB0; + break; + case RC_PRESUB_SUB: + code->inst[ip].inst1 |= R500_RGB_SRCP_OP_RGB1_MINUS_RGB0; + break; + case RC_PRESUB_ADD: + code->inst[ip].inst1 |= R500_RGB_SRCP_OP_RGB1_PLUS_RGB0; + break; + case RC_PRESUB_INV: + code->inst[ip].inst1 |= R500_RGB_SRCP_OP_1_MINUS_RGB0; + break; + default: + break; + } + switch(inst->Alpha.Src[RC_PAIR_PRESUB_SRC].Index) { + case RC_PRESUB_BIAS: + code->inst[ip].inst2 |= R500_ALPHA_SRCP_OP_1_MINUS_2A0; + break; + case RC_PRESUB_SUB: + code->inst[ip].inst2 |= R500_ALPHA_SRCP_OP_A1_MINUS_A0; + break; + case RC_PRESUB_ADD: + code->inst[ip].inst2 |= R500_ALPHA_SRCP_OP_A1_PLUS_A0; + break; + case RC_PRESUB_INV: + code->inst[ip].inst2 |= R500_ALPHA_SRCP_OP_1_MINUS_A0; + break; + default: + break; + } + code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0])); code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1])); code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2])); @@ -322,7 +359,7 @@ static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_inst { PROG_CODE; - if (code->inst_end >= 511) { + if (code->inst_end >= c->Base.max_alu_insts-1) { error("emit_tex: Too many instructions"); return 0; } @@ -370,7 +407,7 @@ static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_inst static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst) { - if (s->Code->inst_end >= 511) { + if (s->Code->inst_end >= s->C->max_alu_insts-1) { rc_error(s->C, "emit_tex: Too many instructions"); return; } @@ -387,13 +424,13 @@ static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst switch(inst->U.I.Opcode){ struct branch_info * branch; - struct loop_info * loop; + struct r500_loop_info * loop; case RC_OPCODE_BGNLOOP: - memory_pool_array_reserve(&s->C->Pool, struct loop_info, + memory_pool_array_reserve(&s->C->Pool, struct r500_loop_info, s->Loops, s->CurrentLoopDepth, s->LoopsReserved, 1); loop = &s->Loops[s->CurrentLoopDepth++]; - memset(loop, 0, sizeof(struct loop_info)); + memset(loop, 0, sizeof(struct r500_loop_info)); loop->BranchDepth = s->CurrentBranchDepth; loop->BgnLoop = newip; @@ -546,8 +583,9 @@ static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst } } -void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler) +void r500BuildFragmentProgramHwCode(struct radeon_compiler *c, void *user) { + struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c; struct emit_state s; struct r500_fragment_program_code *code = &compiler->code->code.r500; @@ -577,7 +615,7 @@ void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compi } } - if (code->max_temp_idx >= 128) + if (code->max_temp_idx >= compiler->Base.max_temp_regs) rc_error(&compiler->Base, "Too many hardware temporaries used"); if (compiler->Base.Error) @@ -587,7 +625,7 @@ void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compi (code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) { /* This may happen when dead-code elimination is disabled or * when most of the fragment program logic is leading to a KIL */ - if (code->inst_end >= 511) { + if (code->inst_end >= compiler->Base.max_alu_insts-1) { rc_error(&compiler->Base, "Introducing fake OUT: Too many instructions"); return; } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c index 935dc9b0a8..b410b2daf4 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c @@ -350,3 +350,36 @@ void rc_transform_fragment_face(struct radeon_compiler *c, unsigned face) } } } + +/* Executes a list of compiler passes given in the parameter 'list'. */ +void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *list, + const char *shader_name) +{ + if (c->Debug) { + fprintf(stderr, "%s: before compilation\n", shader_name); + rc_print_program(&c->Program); + } + + for (unsigned i = 0; list[i].name; i++) { + if (list[i].predicate) { + list[i].run(c, list[i].user); + + if (c->Error) + return; + + if (c->Debug && list[i].dump) { + fprintf(stderr, "%s: after '%s'\n", shader_name, list[i].name); + rc_print_program(&c->Program); + } + } + } +} + +void rc_validate_final_shader(struct radeon_compiler *c, void *user) +{ + /* Check the number of constants. */ + if (c->Program.Constants.Count > c->max_constants) { + rc_error(c, "Too many constants. Max: 256, Got: %i\n", + c->Program.Constants.Count); + } +} diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h index 5155b912e1..6d96ac9fdd 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h @@ -28,6 +28,7 @@ #include "memory_pool.h" #include "radeon_code.h" #include "radeon_program.h" +#include "radeon_emulate_loops.h" struct rc_swizzle_caps; @@ -40,7 +41,12 @@ struct radeon_compiler { /* Hardware specification. */ unsigned is_r500:1; + unsigned has_half_swizzles:1; + unsigned has_presub:1; + unsigned disable_optimizations:1; unsigned max_temp_regs; + unsigned max_constants; + int max_alu_insts; /* Whether to remove unused constants and empty holes in constant space. */ unsigned remove_unused_constants:1; @@ -52,6 +58,8 @@ struct radeon_compiler { /*@{*/ struct rc_swizzle_caps * SwizzleCaps; /*@}*/ + + struct emulate_loop_state loop_state; }; void rc_init(struct radeon_compiler * c); @@ -106,7 +114,6 @@ struct r300_fragment_program_compiler { void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c); - struct r300_vertex_program_compiler { struct radeon_compiler Base; struct r300_vertex_program_code *code; @@ -120,6 +127,19 @@ struct r300_vertex_program_compiler { }; void r3xx_compile_vertex_program(struct r300_vertex_program_compiler* c); -void r300_vertex_program_dump(struct r300_vertex_program_compiler * c); +void r300_vertex_program_dump(struct radeon_compiler *compiler, void *user); + +struct radeon_compiler_pass { + const char *name; /* Name of the pass. */ + int dump; /* Dump the program if Debug == 1? */ + int predicate; /* Run this pass? */ + void (*run)(struct radeon_compiler *c, void *user); /* The main entrypoint. */ + void *user; /* Optional parameter which is passed to the run function. */ +}; + +/* Executes a list of compiler passes given in the parameter 'list'. */ +void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *list, + const char *shader_name); +void rc_validate_final_shader(struct radeon_compiler *c, void *user); #endif /* RADEON_COMPILER_H */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c index 0e6c62541f..e73700f84a 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c @@ -29,6 +29,25 @@ #include "radeon_program.h" +static void reads_normal_callback( + rc_read_write_chan_fn cb, + struct rc_instruction * fullinst, + struct rc_src_register src, + void * userdata) +{ + unsigned int refmask = 0; + unsigned int chan; + for(chan = 0; chan < 4; chan++) { + refmask |= 1 << GET_SWZ(src.Swizzle, chan); + } + refmask &= RC_MASK_XYZW; + + if (refmask) + cb(userdata, fullinst, src.File, src.Index, refmask); + + if (refmask && src.RelAddr) + cb(userdata, fullinst, RC_FILE_ADDRESS, 0, RC_MASK_X); +} static void reads_normal(struct rc_instruction * fullinst, rc_read_write_chan_fn cb, void * userdata) { @@ -36,47 +55,81 @@ static void reads_normal(struct rc_instruction * fullinst, rc_read_write_chan_fn const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode); for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) { - unsigned int refmask = 0; if (inst->SrcReg[src].File == RC_FILE_NONE) return; - for(unsigned int chan = 0; chan < 4; ++chan) - refmask |= 1 << GET_SWZ(inst->SrcReg[src].Swizzle, chan); - - refmask &= RC_MASK_XYZW; - - if (refmask) - cb(userdata, fullinst, inst->SrcReg[src].File, inst->SrcReg[src].Index, refmask); - - if (refmask && inst->SrcReg[src].RelAddr) - cb(userdata, fullinst, RC_FILE_ADDRESS, 0, RC_MASK_X); + if (inst->SrcReg[src].File == RC_FILE_PRESUB) { + unsigned int i; + unsigned int srcp_regs = rc_presubtract_src_reg_count( + inst->PreSub.Opcode); + for( i = 0; i < srcp_regs; i++) { + reads_normal_callback(cb, fullinst, + inst->PreSub.SrcReg[i], + userdata); + } + } else { + reads_normal_callback(cb, fullinst, + inst->SrcReg[src], userdata); + } } } -static void reads_pair(struct rc_instruction * fullinst, rc_read_write_mask_fn cb, void * userdata) +static void pair_get_src_refmasks(unsigned int * refmasks, + struct rc_pair_instruction * inst, + unsigned int swz, unsigned int src) { - struct rc_pair_instruction * inst = &fullinst->U.P; - unsigned int refmasks[3] = { 0, 0, 0 }; - - if (inst->RGB.Opcode != RC_OPCODE_NOP) { - const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->RGB.Opcode); + if (swz >= 4) + return; + + if (swz == RC_SWIZZLE_X || swz == RC_SWIZZLE_Y || swz == RC_SWIZZLE_Z) { + if(src == RC_PAIR_PRESUB_SRC) { + unsigned int i; + int srcp_regs = + rc_presubtract_src_reg_count( + inst->RGB.Src[src].Index); + for(i = 0; i < srcp_regs; i++) { + refmasks[i] |= 1 << swz; + } + } + else { + refmasks[src] |= 1 << swz; + } + } - for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) { - for(unsigned int chan = 0; chan < 3; ++chan) { - unsigned int swz = GET_SWZ(inst->RGB.Arg[arg].Swizzle, chan); - if (swz < 4) - refmasks[inst->RGB.Arg[arg].Source] |= 1 << swz; + if (swz == RC_SWIZZLE_W) { + if (src == RC_PAIR_PRESUB_SRC) { + unsigned int i; + int srcp_regs = rc_presubtract_src_reg_count( + inst->Alpha.Src[src].Index); + for(i = 0; i < srcp_regs; i++) { + refmasks[i] |= 1 << swz; } } + else { + refmasks[src] |= 1 << swz; + } } +} - if (inst->Alpha.Opcode != RC_OPCODE_NOP) { - const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Alpha.Opcode); +static void reads_pair(struct rc_instruction * fullinst, rc_read_write_mask_fn cb, void * userdata) +{ + struct rc_pair_instruction * inst = &fullinst->U.P; + unsigned int refmasks[3] = { 0, 0, 0 }; - for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) { - if (inst->Alpha.Arg[arg].Swizzle < 4) - refmasks[inst->Alpha.Arg[arg].Source] |= 1 << inst->Alpha.Arg[arg].Swizzle; + unsigned int arg; + + for(arg = 0; arg < 3; ++arg) { + unsigned int chan; + for(chan = 0; chan < 3; ++chan) { + unsigned int swz_rgb = + GET_SWZ(inst->RGB.Arg[arg].Swizzle, chan); + unsigned int swz_alpha = + GET_SWZ(inst->Alpha.Arg[arg].Swizzle, chan); + pair_get_src_refmasks(refmasks, inst, swz_rgb, + inst->RGB.Arg[arg].Source); + pair_get_src_refmasks(refmasks, inst, swz_alpha, + inst->Alpha.Arg[arg].Source); } } @@ -212,10 +265,25 @@ static void remap_normal_instruction(struct rc_instruction * fullinst, rc_register_file file = inst->SrcReg[src].File; unsigned int index = inst->SrcReg[src].Index; - cb(userdata, fullinst, &file, &index); + if (file == RC_FILE_PRESUB) { + unsigned int i; + unsigned int srcp_srcs = rc_presubtract_src_reg_count( + inst->PreSub.Opcode); + for(i = 0; i < srcp_srcs; i++) { + file = inst->PreSub.SrcReg[i].File; + index = inst->PreSub.SrcReg[i].Index; + cb(userdata, fullinst, &file, &index); + inst->PreSub.SrcReg[i].File = file; + inst->PreSub.SrcReg[i].Index = index; + } - inst->SrcReg[src].File = file; - inst->SrcReg[src].Index = index; + } + else { + cb(userdata, fullinst, &file, &index); + + inst->SrcReg[src].File = file; + inst->SrcReg[src].Index = index; + } } } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h index 60a6e192a9..795d9cc2b6 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h @@ -61,10 +61,10 @@ void rc_remap_registers(struct rc_instruction * inst, rc_remap_register_fn cb, v /*@{*/ typedef void (*rc_dataflow_mark_outputs_fn)(void * userdata, void * data, void (*mark_fn)(void * data, unsigned int index, unsigned int mask)); -void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_fn dce, void * userdata); -void rc_dataflow_swizzles(struct radeon_compiler * c); +void rc_dataflow_deadcode(struct radeon_compiler * c, void *user); +void rc_dataflow_swizzles(struct radeon_compiler * c, void *user); /*@}*/ -void rc_optimize(struct radeon_compiler * c); +void rc_optimize(struct radeon_compiler * c, void *user); #endif /* RADEON_DATAFLOW_H */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c index acdb371de9..9d17b4772a 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c @@ -213,11 +213,24 @@ static void mark_output_use(void * data, unsigned int index, unsigned int mask) mark_used(s, RC_FILE_OUTPUT, index, mask); } -void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_fn dce, void * userdata) +void rc_dataflow_deadcode(struct radeon_compiler * c, void *user) { struct deadcode_state s; unsigned int nr_instructions; unsigned has_temp_reladdr_src = 0; + rc_dataflow_mark_outputs_fn dce = (rc_dataflow_mark_outputs_fn)user; + + /* Give up if there is relative addressing of destination operands. */ + for(struct rc_instruction * inst = c->Program.Instructions.Next; + inst != &c->Program.Instructions; + inst = inst->Next) { + const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); + if (opcode->HasDstReg && + inst->U.I.DstReg.WriteMask && + inst->U.I.DstReg.RelAddr) { + return; + } + } memset(&s, 0, sizeof(s)); s.C = c; @@ -226,7 +239,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f s.Instructions = memory_pool_malloc(&c->Pool, sizeof(struct instruction_state)*nr_instructions); memset(s.Instructions, 0, sizeof(struct instruction_state)*nr_instructions); - dce(userdata, &s, &mark_output_use); + dce(c, &s, &mark_output_use); for(struct rc_instruction * inst = c->Program.Instructions.Prev; inst != &c->Program.Instructions; @@ -315,6 +328,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f for (struct rc_instruction *ptr = inst->Prev; ptr != &c->Program.Instructions; ptr = ptr->Prev) { + opcode = rc_get_opcode_info(ptr->U.I.Opcode); if (opcode->HasDstReg && ptr->U.I.DstReg.File == RC_FILE_TEMPORARY && ptr->U.I.DstReg.WriteMask) { @@ -326,6 +340,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f } has_temp_reladdr_src = 1; + break; } } } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c index 33acbd30f4..a0f7bd8174 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c @@ -86,7 +86,7 @@ static void rewrite_source(struct radeon_compiler * c, } } -void rc_dataflow_swizzles(struct radeon_compiler * c) +void rc_dataflow_swizzles(struct radeon_compiler * c, void *user) { struct rc_instruction * inst; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.c b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.c index 863654cf68..222e5b7e02 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.c @@ -296,7 +296,7 @@ static void fix_output_writes(struct emulate_branch_state * s, struct rc_instruc * on different register sets and choose between their results * using CMP instructions in place of the original ENDIF. */ -void rc_emulate_branches(struct radeon_compiler * c) +void rc_emulate_branches(struct radeon_compiler *c, void *user) { struct emulate_branch_state s; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.h b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.h index e07279f093..818ab84d0c 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_branches.h @@ -25,6 +25,6 @@ struct radeon_compiler; -void rc_emulate_branches(struct radeon_compiler * c); +void rc_emulate_branches(struct radeon_compiler *c, void *user); #endif /* RADEON_EMULATE_BRANCHES_H */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.c b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.c index 32d4b45dd6..cd4fcbabb9 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.c @@ -78,12 +78,12 @@ static int src_reg_is_immediate(struct rc_src_register * src, } static unsigned int loop_max_possible_iterations(struct radeon_compiler *c, - struct loop_info * loop, unsigned int prog_inst_limit) + struct loop_info * loop) { unsigned int total_i = rc_recompute_ips(c); unsigned int loop_i = (loop->EndLoop->IP - loop->BeginLoop->IP) - 1; /* +1 because the program already has one iteration of the loop. */ - return 1 + ((prog_inst_limit - total_i) / loop_i); + return 1 + ((c->max_alu_insts - total_i) / loop_i); } static void unroll_loop(struct radeon_compiler * c, struct loop_info * loop, @@ -187,11 +187,10 @@ static void get_incr_amount(void * data, struct rc_instruction * inst, } /** - * If prog_inst_limit is -1, then all eligible loops will be unrolled regardless + * If c->max_alu_inst is -1, then all eligible loops will be unrolled regardless * of how many iterations they have. */ -static int try_unroll_loop(struct radeon_compiler * c, struct loop_info * loop, - unsigned int prog_inst_limit) +static int try_unroll_loop(struct radeon_compiler * c, struct loop_info * loop) { int end_loops; int iterations; @@ -300,9 +299,8 @@ static int try_unroll_loop(struct radeon_compiler * c, struct loop_info * loop, return 0; } - if (prog_inst_limit > 0 - && iterations > loop_max_possible_iterations(c, loop, - prog_inst_limit)) { + if (c->max_alu_insts > 0 + && iterations > loop_max_possible_iterations(c, loop)) { return 0; } @@ -436,7 +434,7 @@ static int transform_loop(struct emulate_loop_state * s, if (!build_loop_info(s->C, loop, inst)) return 0; - if(try_unroll_loop(s->C, loop, s->prog_inst_limit)){ + if(try_unroll_loop(s->C, loop)){ return 1; } @@ -472,14 +470,13 @@ static int transform_loop(struct emulate_loop_state * s, return 1; } -void rc_transform_loops(struct radeon_compiler *c, - struct emulate_loop_state * s, int prog_inst_limit) +void rc_transform_loops(struct radeon_compiler *c, void *user) { + struct emulate_loop_state * s = &c->loop_state; struct rc_instruction * ptr; memset(s, 0, sizeof(struct emulate_loop_state)); s->C = c; - s->prog_inst_limit = prog_inst_limit; for(ptr = s->C->Program.Instructions.Next; ptr != &s->C->Program.Instructions; ptr = ptr->Next) { if(ptr->Type == RC_INSTRUCTION_NORMAL && @@ -490,7 +487,7 @@ void rc_transform_loops(struct radeon_compiler *c, } } -void rc_unroll_loops(struct radeon_compiler *c, int prog_inst_limit) +void rc_unroll_loops(struct radeon_compiler *c, void *user) { struct rc_instruction * inst; struct loop_info loop; @@ -500,14 +497,15 @@ void rc_unroll_loops(struct radeon_compiler *c, int prog_inst_limit) if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP) { if (build_loop_info(c, &loop, inst)) { - try_unroll_loop(c, &loop, prog_inst_limit); + try_unroll_loop(c, &loop); } } } } -void rc_emulate_loops(struct emulate_loop_state *s, int prog_inst_limit) +void rc_emulate_loops(struct radeon_compiler *c, void *user) { + struct emulate_loop_state * s = &c->loop_state; int i; /* Iterate backwards of the list of loops so that loops that nested * loops are unrolled first. @@ -517,7 +515,7 @@ void rc_emulate_loops(struct emulate_loop_state *s, int prog_inst_limit) continue; } unsigned int iterations = loop_max_possible_iterations( - s->C, &s->Loops[i], prog_inst_limit); + s->C, &s->Loops[i]); unroll_loop(s->C, &s->Loops[i], iterations); } } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.h b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.h index bba1f68e30..cd800c059d 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_emulate_loops.h @@ -21,14 +21,12 @@ struct emulate_loop_state { struct loop_info * Loops; unsigned int LoopCount; unsigned int LoopReserved; - int prog_inst_limit; }; -void rc_transform_loops(struct radeon_compiler *c, - struct emulate_loop_state * s, int prog_inst_limit); +void rc_transform_loops(struct radeon_compiler *c, void *user); -void rc_unroll_loops(struct radeon_compiler * c, int prog_inst_limit); +void rc_unroll_loops(struct radeon_compiler * c, void *user); -void rc_emulate_loops(struct emulate_loop_state * s, int prog_inst_limit); +void rc_emulate_loops(struct radeon_compiler * c, void *user); #endif /* RADEON_EMULATE_LOOPS_H */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c index 7a3f35950a..c15a9b1c45 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c @@ -30,6 +30,17 @@ #include "radeon_compiler.h" #include "radeon_swizzle.h" +struct peephole_state { + struct rc_instruction * Inst; + /** Stores a bitmask of the components that are still "alive" (i.e. + * they have not been written to since Inst was executed.) + */ + unsigned int WriteMask; +}; + +typedef void (*rc_presub_replace_fn)(struct peephole_state *, + struct rc_instruction *, + unsigned int); static struct rc_src_register chain_srcregs(struct rc_src_register outer, struct rc_src_register inner) { @@ -54,7 +65,7 @@ static struct rc_src_register chain_srcregs(struct rc_src_register outer, struct return combine; } -struct peephole_state { +struct copy_propagate_state { struct radeon_compiler * C; struct rc_instruction * Mov; unsigned int Conflict:1; @@ -84,10 +95,16 @@ struct peephole_state { * @param index The index of the source register. * @param mask The components of the source register that are being read from. */ -static void peephole_scan_read(void * data, struct rc_instruction * inst, +static void copy_propagate_scan_read(void * data, struct rc_instruction * inst, rc_register_file file, unsigned int index, unsigned int mask) { - struct peephole_state * s = data; + struct copy_propagate_state * s = data; + + /* XXX This could probably be handled better. */ + if (file == RC_FILE_ADDRESS) { + s->Conflict = 1; + return; + } if (file != RC_FILE_TEMPORARY || index != s->Mov->U.I.DstReg.Index) return; @@ -117,10 +134,10 @@ static void peephole_scan_read(void * data, struct rc_instruction * inst, } } -static void peephole_scan_write(void * data, struct rc_instruction * inst, +static void copy_propagate_scan_write(void * data, struct rc_instruction * inst, rc_register_file file, unsigned int index, unsigned int mask) { - struct peephole_state * s = data; + struct copy_propagate_state * s = data; if (s->BranchDepth < 0) return; @@ -140,11 +157,13 @@ static void peephole_scan_write(void * data, struct rc_instruction * inst, } } -static void peephole(struct radeon_compiler * c, struct rc_instruction * inst_mov) +static void copy_propagate(struct radeon_compiler * c, struct rc_instruction * inst_mov) { - struct peephole_state s; + struct copy_propagate_state s; - if (inst_mov->U.I.DstReg.File != RC_FILE_TEMPORARY || inst_mov->U.I.WriteALUResult) + if (inst_mov->U.I.DstReg.File != RC_FILE_TEMPORARY || + inst_mov->U.I.DstReg.RelAddr || + inst_mov->U.I.WriteALUResult) return; memset(&s, 0, sizeof(s)); @@ -162,14 +181,23 @@ static void peephole(struct radeon_compiler * c, struct rc_instruction * inst_mo for(struct rc_instruction * inst = inst_mov->Next; inst != &c->Program.Instructions; inst = inst->Next) { + const struct rc_opcode_info * info = rc_get_opcode_info(inst->U.I.Opcode); /* XXX In the future we might be able to make the optimizer * smart enough to handle loops. */ if(inst->U.I.Opcode == RC_OPCODE_BGNLOOP || inst->U.I.Opcode == RC_OPCODE_ENDLOOP){ return; } - rc_for_all_reads_mask(inst, peephole_scan_read, &s); - rc_for_all_writes_mask(inst, peephole_scan_write, &s); + + /* It is possible to do copy propigation in this situation, + * just not right now, see peephole_add_presub_inv() */ + if (inst_mov->U.I.PreSub.Opcode != RC_PRESUB_NONE && + (info->NumSrcRegs > 2 || info->HasTexture)) { + return; + } + + rc_for_all_reads_mask(inst, copy_propagate_scan_read, &s); + rc_for_all_writes_mask(inst, copy_propagate_scan_write, &s); if (s.Conflict) return; @@ -198,7 +226,6 @@ static void peephole(struct radeon_compiler * c, struct rc_instruction * inst_mo inst != &c->Program.Instructions; inst = inst->Next) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); - for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) { if (inst->U.I.SrcReg[src].File == RC_FILE_TEMPORARY && inst->U.I.SrcReg[src].Index == s.Mov->U.I.DstReg.Index) { @@ -209,8 +236,11 @@ static void peephole(struct radeon_compiler * c, struct rc_instruction * inst_mo refmask |= (1 << swz) & RC_MASK_XYZW; } - if ((refmask & s.MovMask) == refmask) + if ((refmask & s.MovMask) == refmask) { inst->U.I.SrcReg[src] = chain_srcregs(inst->U.I.SrcReg[src], s.Mov->U.I.SrcReg[0]); + if (s.Mov->U.I.SrcReg[0].File == RC_FILE_PRESUB) + inst->U.I.PreSub = s.Mov->U.I.PreSub; + } } } @@ -275,7 +305,6 @@ static int is_src_uniform_constant(struct rc_src_register src, return 1; } - static void constant_folding_mad(struct rc_instruction * inst) { rc_swizzle swz; @@ -371,7 +400,6 @@ static void constant_folding_add(struct rc_instruction * inst) } } - /** * Replace 0.0, 1.0 and 0.5 immediate constants by their * respective swizzles. Simplify instructions like ADD dst, src, 0; @@ -410,7 +438,7 @@ static void constant_folding(struct radeon_compiler * c, struct rc_instruction * newswz = RC_SWIZZLE_ZERO; } else if (baseimm == 1.0) { newswz = RC_SWIZZLE_ONE; - } else if (baseimm == 0.5) { + } else if (baseimm == 0.5 && c->has_half_swizzles) { newswz = RC_SWIZZLE_HALF; } else { have_real_reference = 1; @@ -446,7 +474,301 @@ static void constant_folding(struct radeon_compiler * c, struct rc_instruction * constant_folding_add(inst); } -void rc_optimize(struct radeon_compiler * c) +/** + * This function returns a writemask that indicates wich components are + * read by src and also written by dst. + */ +static unsigned int src_reads_dst_mask(struct rc_src_register src, + struct rc_dst_register dst) +{ + unsigned int mask = 0; + unsigned int i; + if (dst.File != src.File || dst.Index != src.Index) { + return 0; + } + + for(i = 0; i < 4; i++) { + mask |= 1 << GET_SWZ(src.Swizzle, i); + } + mask &= RC_MASK_XYZW; + + return mask; +} + +/* Return 1 if the source registers has a constant swizzle (e.g. 0, 0.5, 1.0) + * in any of its channels. Return 0 otherwise. */ +static int src_has_const_swz(struct rc_src_register src) { + int chan; + for(chan = 0; chan < 4; chan++) { + unsigned int swz = GET_SWZ(src.Swizzle, chan); + if (swz == RC_SWIZZLE_ZERO || swz == RC_SWIZZLE_HALF + || swz == RC_SWIZZLE_ONE) { + return 1; + } + } + return 0; +} + +static void peephole_scan_write(void * data, struct rc_instruction * inst, + rc_register_file file, unsigned int index, unsigned int mask) +{ + struct peephole_state * s = data; + if(s->Inst->U.I.DstReg.File == file + && s->Inst->U.I.DstReg.Index == index) { + unsigned int common_mask = s->WriteMask & mask; + s->WriteMask &= ~common_mask; + } +} + +static int presub_helper( + struct radeon_compiler * c, + struct peephole_state * s, + rc_presubtract_op presub_opcode, + rc_presub_replace_fn presub_replace) +{ + struct rc_instruction * inst; + unsigned int can_remove = 0; + unsigned int cant_sub = 0; + + for(inst = s->Inst->Next; inst != &c->Program.Instructions; + inst = inst->Next) { + unsigned int i; + unsigned char can_use_presub = 1; + const struct rc_opcode_info * info = + rc_get_opcode_info(inst->U.I.Opcode); + /* XXX: There are some situations where instructions + * with more than 2 src registers can use the + * presubtract select, but to keep things simple we + * will disable presubtract on these instructions for + * now. */ + if (info->NumSrcRegs > 2 || info->HasTexture) { + can_use_presub = 0; + } + + /* We can't use more than one presubtract value in an + * instruction, unless the two prsubtract operations + * are the same and read from the same registers. */ + if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE) { + if (inst->U.I.PreSub.Opcode != presub_opcode + || inst->U.I.PreSub.SrcReg[0].File != + s->Inst->U.I.SrcReg[1].File + || inst->U.I.PreSub.SrcReg[0].Index != + s->Inst->U.I.SrcReg[1].Index) { + can_use_presub = 0; + } + } + + /* Even if the instruction can't use a presubtract operation + * we still need to check if the instruction reads from + * s->Inst->U.I.DstReg, because if it does we must not + * remove s->Inst. */ + for(i = 0; i < info->NumSrcRegs; i++) { + if(s->Inst->U.I.DstReg.WriteMask != + src_reads_dst_mask(inst->U.I.SrcReg[i], + s->Inst->U.I.DstReg)) { + continue; + } + if (cant_sub || !can_use_presub) { + can_remove = 0; + break; + } + presub_replace(s, inst, i); + can_remove = 1; + } + if(!can_remove) + break; + rc_for_all_writes_mask(inst, peephole_scan_write, s); + /* If all components of inst_add's destination register have + * been written to by subsequent instructions, the original + * value of the destination register is no longer valid and + * we can't keep doing substitutions. */ + if (!s->WriteMask){ + break; + } + /* Make this instruction doesn't write to the presubtract source. */ + if (inst->U.I.DstReg.WriteMask & + src_reads_dst_mask(s->Inst->U.I.SrcReg[1], + inst->U.I.DstReg) + || src_reads_dst_mask(s->Inst->U.I.SrcReg[0], + inst->U.I.DstReg) + || info->IsFlowControl) { + cant_sub = 1; + } + } + return can_remove; +} + +/* This function assumes that s->Inst->U.I.SrcReg[0] and + * s->Inst->U.I.SrcReg[1] aren't both negative. */ +static void presub_replace_add(struct peephole_state *s, + struct rc_instruction * inst, + unsigned int src_index) +{ + rc_presubtract_op presub_opcode; + if (s->Inst->U.I.SrcReg[1].Negate || s->Inst->U.I.SrcReg[0].Negate) + presub_opcode = RC_PRESUB_SUB; + else + presub_opcode = RC_PRESUB_ADD; + + if (s->Inst->U.I.SrcReg[1].Negate) { + inst->U.I.PreSub.SrcReg[0] = s->Inst->U.I.SrcReg[1]; + inst->U.I.PreSub.SrcReg[1] = s->Inst->U.I.SrcReg[0]; + } else { + inst->U.I.PreSub.SrcReg[0] = s->Inst->U.I.SrcReg[0]; + inst->U.I.PreSub.SrcReg[1] = s->Inst->U.I.SrcReg[1]; + } + inst->U.I.PreSub.SrcReg[0].Negate = 0; + inst->U.I.PreSub.SrcReg[1].Negate = 0; + inst->U.I.PreSub.Opcode = presub_opcode; + inst->U.I.SrcReg[src_index] = chain_srcregs(inst->U.I.SrcReg[src_index], + inst->U.I.PreSub.SrcReg[0]); + inst->U.I.SrcReg[src_index].File = RC_FILE_PRESUB; + inst->U.I.SrcReg[src_index].Index = presub_opcode; +} + +static int peephole_add_presub_add( + struct radeon_compiler * c, + struct rc_instruction * inst_add) +{ + struct rc_src_register * src0 = NULL; + struct rc_src_register * src1 = NULL; + unsigned int i; + struct peephole_state s; + + if (inst_add->U.I.PreSub.Opcode != RC_PRESUB_NONE) + return 0; + + if (inst_add->U.I.SaturateMode) + return 0; + + if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) + return 0; + + /* src0 and src1 can't have absolute values only one can be negative and they must be all negative or all positive. */ + for (i = 0; i < 2; i++) { + if (inst_add->U.I.SrcReg[i].Abs) + return 0; + if ((inst_add->U.I.SrcReg[i].Negate + & inst_add->U.I.DstReg.WriteMask) == + inst_add->U.I.DstReg.WriteMask) { + src0 = &inst_add->U.I.SrcReg[i]; + } else if (!src1) { + src1 = &inst_add->U.I.SrcReg[i]; + } else { + src0 = &inst_add->U.I.SrcReg[i]; + } + } + + if (!src1) + return 0; + + s.Inst = inst_add; + s.WriteMask = inst_add->U.I.DstReg.WriteMask; + if (presub_helper(c, &s, RC_PRESUB_ADD, presub_replace_add)) { + rc_remove_instruction(inst_add); + return 1; + } + return 0; +} + +static void presub_replace_inv(struct peephole_state * s, + struct rc_instruction * inst, + unsigned int src_index) +{ + /* We must be careful not to modify s->Inst, since it + * is possible it will remain part of the program. + * XXX Maybe pass a struct instead of a pointer for s->Inst.*/ + inst->U.I.PreSub.SrcReg[0] = s->Inst->U.I.SrcReg[1]; + inst->U.I.PreSub.SrcReg[0].Negate = 0; + inst->U.I.PreSub.Opcode = RC_PRESUB_INV; + inst->U.I.SrcReg[src_index] = chain_srcregs(inst->U.I.SrcReg[src_index], + inst->U.I.PreSub.SrcReg[0]); + + inst->U.I.SrcReg[src_index].File = RC_FILE_PRESUB; + inst->U.I.SrcReg[src_index].Index = RC_PRESUB_INV; +} + +/** + * PRESUB_INV: ADD TEMP[0], none.1, -TEMP[1] + * Use the presubtract 1 - src0 for all readers of TEMP[0]. The first source + * of the add instruction must have the constatnt 1 swizzle. This function + * does not check const registers to see if their value is 1.0, so it should + * be called after the constant_folding optimization. + * @return + * 0 if the ADD instruction is still part of the program. + * 1 if the ADD instruction is no longer part of the program. + */ +static int peephole_add_presub_inv( + struct radeon_compiler * c, + struct rc_instruction * inst_add) +{ + unsigned int i, swz, mask; + struct peephole_state s; + + if (inst_add->U.I.PreSub.Opcode != RC_PRESUB_NONE) + return 0; + + if (inst_add->U.I.SaturateMode) + return 0; + + mask = inst_add->U.I.DstReg.WriteMask; + + /* Check if src0 is 1. */ + /* XXX It would be nice to use is_src_uniform_constant here, but that + * function only works if the register's file is RC_FILE_NONE */ + for(i = 0; i < 4; i++ ) { + swz = GET_SWZ(inst_add->U.I.SrcReg[0].Swizzle, i); + if(((1 << i) & inst_add->U.I.DstReg.WriteMask) + && swz != RC_SWIZZLE_ONE) { + return 0; + } + } + + /* Check src1. */ + if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != + inst_add->U.I.DstReg.WriteMask + || inst_add->U.I.SrcReg[1].Abs + || (inst_add->U.I.SrcReg[1].File != RC_FILE_TEMPORARY + && inst_add->U.I.SrcReg[1].File != RC_FILE_CONSTANT) + || src_has_const_swz(inst_add->U.I.SrcReg[1])) { + + return 0; + } + + /* Setup the peephole_state information. */ + s.Inst = inst_add; + s.WriteMask = inst_add->U.I.DstReg.WriteMask; + + if (presub_helper(c, &s, RC_PRESUB_INV, presub_replace_inv)) { + rc_remove_instruction(inst_add); + return 1; + } + return 0; +} + +/** + * @return + * 0 if inst is still part of the program. + * 1 if inst is no longer part of the program. + */ +static int peephole(struct radeon_compiler * c, struct rc_instruction * inst) +{ + switch(inst->U.I.Opcode){ + case RC_OPCODE_ADD: + if (c->has_presub) { + if(peephole_add_presub_inv(c, inst)) + return 1; + if(peephole_add_presub_add(c, inst)) + return 1; + } + break; + default: + break; + } + return 0; +} + +void rc_optimize(struct radeon_compiler * c, void *user) { struct rc_instruction * inst = c->Program.Instructions.Next; while(inst != &c->Program.Instructions) { @@ -455,8 +777,11 @@ void rc_optimize(struct radeon_compiler * c) constant_folding(c, cur); + if(peephole(c, cur)) + continue; + if (cur->U.I.Opcode == RC_OPCODE_MOV) { - peephole(c, cur); + copy_propagate(c, cur); /* cur may no longer be part of the program */ } } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c index ce72cd97ab..c73845512f 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c @@ -189,8 +189,17 @@ static void scan_callback(void * data, struct rc_instruction * inst, reg->Live.End = inst->IP; } -static void compute_live_intervals(struct regalloc_state * s) +static void compute_live_intervals(struct radeon_compiler *c, + struct regalloc_state *s) { + memset(s, 0, sizeof(*s)); + s->C = c; + s->NumHwTemporaries = c->max_temp_regs; + s->HwTemporary = + memory_pool_malloc(&c->Pool, + s->NumHwTemporaries * sizeof(struct hardware_register)); + memset(s->HwTemporary, 0, s->NumHwTemporaries * sizeof(struct hardware_register)); + rc_recompute_ips(s->C); for(struct rc_instruction * inst = s->C->Program.Instructions.Next; @@ -207,7 +216,6 @@ static void compute_live_intervals(struct regalloc_state * s) tmp = tmp->Next) { if (tmp->U.I.Opcode == RC_OPCODE_BGNLOOP) { loops++; - break; } else if (tmp->U.I.Opcode == RC_OPCODE_ENDLOOP) { if(!--loops) { @@ -292,19 +300,53 @@ static void alloc_input(void * data, unsigned int input, unsigned int hwreg) } -void rc_pair_regalloc(struct r300_fragment_program_compiler *c, unsigned maxtemps) +void rc_pair_regalloc(struct radeon_compiler *cc, void *user) { + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc; struct regalloc_state s; - memset(&s, 0, sizeof(s)); - s.C = &c->Base; - s.NumHwTemporaries = maxtemps; - s.HwTemporary = memory_pool_malloc(&s.C->Pool, maxtemps*sizeof(struct hardware_register)); - memset(s.HwTemporary, 0, maxtemps*sizeof(struct hardware_register)); - - compute_live_intervals(&s); + compute_live_intervals(cc, &s); c->AllocateHwInputs(c, &alloc_input, &s); do_regalloc(&s); } + +/* This functions offsets the temporary register indices by the number + * of input registers, because input registers are actually temporaries and + * should not occupy the same space. + * + * This pass is supposed to be used to maintain correct allocation of inputs + * if the standard register allocation is disabled. */ +void rc_pair_regalloc_inputs_only(struct radeon_compiler *cc, void *user) +{ + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc; + struct regalloc_state s; + + compute_live_intervals(cc, &s); + + c->AllocateHwInputs(c, &alloc_input, &s); + + int temp_reg_offset = 0; + for (unsigned i = 0; i < RC_REGISTER_MAX_INDEX; i++) { + if (s.Input[i].Allocated && temp_reg_offset <= s.Input[i].Index) + temp_reg_offset = s.Input[i].Index + 1; + } + + if (temp_reg_offset) { + for (unsigned i = 0; i < RC_REGISTER_MAX_INDEX; i++) { + if (s.Temporary[i].Used) { + s.Temporary[i].Allocated = 1; + s.Temporary[i].File = RC_FILE_TEMPORARY; + s.Temporary[i].Index = i + temp_reg_offset; + } + } + + /* Rewrite all registers. */ + for (struct rc_instruction *inst = cc->Program.Instructions.Next; + inst != &cc->Program.Instructions; + inst = inst->Next) { + rc_remap_registers(inst, &remap_register, &s); + } + } +} diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c index fc540496c4..5269d65985 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c @@ -279,11 +279,144 @@ static int destructive_merge_instructions( struct rc_pair_instruction * rgb, struct rc_pair_instruction * alpha) { + const struct rc_opcode_info * opcode; assert(rgb->Alpha.Opcode == RC_OPCODE_NOP); assert(alpha->RGB.Opcode == RC_OPCODE_NOP); + /* Presubtract registers need to be merged first so that registers + * needed by the presubtract operation can be placed in src0 and/or + * src1. */ + + /* Merge the rgb presubtract registers. */ + const struct rc_opcode_info * rgb_info = + rc_get_opcode_info(rgb->RGB.Opcode); + if (alpha->RGB.Src[RC_PAIR_PRESUB_SRC].Used) { + unsigned int srcp_src; + unsigned int srcp_regs; + if (rgb->RGB.Src[RC_PAIR_PRESUB_SRC].Used) + return 0; + srcp_regs = rc_presubtract_src_reg_count( + alpha->RGB.Src[RC_PAIR_PRESUB_SRC].Index); + for(srcp_src = 0; srcp_src < srcp_regs; srcp_src++) { + unsigned int arg; + int free_source; + unsigned int one_way = 0; + struct radeon_pair_instruction_source srcp = + alpha->RGB.Src[srcp_src]; + struct radeon_pair_instruction_source temp; + /* 2nd arg of 1 means this is an rgb source. + * 3rd arg of 0 means this is not an alpha source. */ + free_source = rc_pair_alloc_source(rgb, 1, 0, + srcp.File, srcp.Index); + /* If free_source < 0 then there are no free source + * slots. */ + if (free_source < 0) + return 0; + + temp = rgb->RGB.Src[srcp_src]; + rgb->RGB.Src[srcp_src] = rgb->RGB.Src[free_source]; + /* srcp needs src0 and src1 to be the same */ + if (free_source < srcp_src) { + if (!temp.Used) + continue; + free_source = rc_pair_alloc_source(rgb, 1, 0, + srcp.File, srcp.Index); + one_way = 1; + } else { + rgb->RGB.Src[free_source] = temp; + } + /* If free_source == srcp_src, then the presubtract + * source is already in the correct place. */ + if (free_source == srcp_src) + continue; + /* Shuffle the sources, so we can put the + * presubtract source in the correct place. */ + for (arg = 0; arg < rgb_info->NumSrcRegs; arg++) { + /*If this arg does not read from an rgb source, + * do nothing. */ + if (rc_source_type_that_arg_reads( + rgb->RGB.Arg[arg].Source, + rgb->RGB.Arg[arg].Swizzle, 3) + != RC_PAIR_SOURCE_RGB) { + continue; + } + if (rgb->RGB.Arg[arg].Source == srcp_src) + rgb->RGB.Arg[arg].Source = free_source; + /* We need to do this just in case register + * is one of the sources already, but in the + * wrong spot. */ + else if(rgb->RGB.Arg[arg].Source == free_source + && !one_way) { + rgb->RGB.Arg[arg].Source = srcp_src; + } + } + } + } + + /* Merge the alpha presubtract registers */ + if (alpha->Alpha.Src[RC_PAIR_PRESUB_SRC].Used) { + unsigned int srcp_src; + unsigned int srcp_regs; + if(rgb->Alpha.Src[RC_PAIR_PRESUB_SRC].Used) + return 0; + + srcp_regs = rc_presubtract_src_reg_count( + alpha->Alpha.Src[RC_PAIR_PRESUB_SRC].Index); + for(srcp_src = 0; srcp_src < srcp_regs; srcp_src++) { + unsigned int arg; + int free_source; + unsigned int one_way = 0; + struct radeon_pair_instruction_source srcp = + alpha->Alpha.Src[srcp_src]; + struct radeon_pair_instruction_source temp; + /* 2nd arg of 0 means this is not an rgb source. + * 3rd arg of 1 means this is an alpha source. */ + free_source = rc_pair_alloc_source(rgb, 0, 1, + srcp.File, srcp.Index); + /* If free_source < 0 then there are no free source + * slots. */ + if (free_source < 0) + return 0; + + temp = rgb->Alpha.Src[srcp_src]; + rgb->Alpha.Src[srcp_src] = rgb->Alpha.Src[free_source]; + /* srcp needs src0 and src1 to be the same. */ + if (free_source < srcp_src) { + if (!temp.Used) + continue; + free_source = rc_pair_alloc_source(rgb, 0, 1, + temp.File, temp.Index); + one_way = 1; + } else { + rgb->Alpha.Src[free_source] = temp; + } + /* If free_source == srcp_src, then the presubtract + * source is already in the correct place. */ + if (free_source == srcp_src) + continue; + /* Shuffle the sources, so we can put the + * presubtract source in the correct place. */ + for(arg = 0; arg < rgb_info->NumSrcRegs; arg++) { + /*If this arg does not read from an alpha + * source, do nothing. */ + if (rc_source_type_that_arg_reads( + rgb->RGB.Arg[arg].Source, + rgb->RGB.Arg[arg].Swizzle, 3) + != RC_PAIR_SOURCE_ALPHA) { + continue; + } + if (rgb->RGB.Arg[arg].Source == srcp_src) + rgb->RGB.Arg[arg].Source = free_source; + else if (rgb->RGB.Arg[arg].Source == free_source + && !one_way) { + rgb->RGB.Arg[arg].Source = srcp_src; + } + } + } + } + /* Copy alpha args into rgb */ - const struct rc_opcode_info * opcode = rc_get_opcode_info(alpha->Alpha.Opcode); + opcode = rc_get_opcode_info(alpha->Alpha.Opcode); for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) { unsigned int srcrgb = 0; @@ -351,7 +484,52 @@ static int merge_instructions(struct rc_pair_instruction * rgb, struct rc_pair_i return 0; } +static void presub_nop(struct rc_instruction * emitted) { + int prev_rgb_index, prev_alpha_index, i, num_src; + /* We don't need a nop if the previous instruction is a TEX. */ + if (emitted->Prev->Type != RC_INSTRUCTION_PAIR) { + return; + } + if (emitted->Prev->U.P.RGB.WriteMask) + prev_rgb_index = emitted->Prev->U.P.RGB.DestIndex; + else + prev_rgb_index = -1; + if (emitted->Prev->U.P.Alpha.WriteMask) + prev_alpha_index = emitted->Prev->U.P.Alpha.DestIndex; + else + prev_alpha_index = 1; + + /* Check the previous rgb instruction */ + if (emitted->U.P.RGB.Src[RC_PAIR_PRESUB_SRC].Used) { + num_src = rc_presubtract_src_reg_count( + emitted->U.P.RGB.Src[RC_PAIR_PRESUB_SRC].Index); + for (i = 0; i < num_src; i++) { + unsigned int index = emitted->U.P.RGB.Src[i].Index; + if (emitted->U.P.RGB.Src[i].File == RC_FILE_TEMPORARY + && (index == prev_rgb_index + || index == prev_alpha_index)) { + emitted->Prev->U.P.Nop = 1; + return; + } + } + } + + /* Check the previous alpha instruction. */ + if (!emitted->U.P.Alpha.Src[RC_PAIR_PRESUB_SRC].Used) + return; + + num_src = rc_presubtract_src_reg_count( + emitted->U.P.Alpha.Src[RC_PAIR_PRESUB_SRC].Index); + for (i = 0; i < num_src; i++) { + unsigned int index = emitted->U.P.Alpha.Src[i].Index; + if(emitted->U.P.Alpha.Src[i].File == RC_FILE_TEMPORARY + && (index == prev_rgb_index || index == prev_alpha_index)) { + emitted->Prev->U.P.Nop = 1; + return; + } + } +} /** * Find a good ALU instruction or pair of ALU instruction and emit it. * @@ -408,6 +586,10 @@ static void emit_one_alu(struct schedule_state *s, struct rc_instruction * befor commit_alu_instruction(s, sinst); success: ; } + /* If the instruction we just emitted uses a presubtract value, and + * the presubtract sources were written by the previous intstruction, + * the previous instruction needs a nop. */ + presub_nop(before->Prev); } static void scan_read(void * data, struct rc_instruction * inst, @@ -529,8 +711,9 @@ static int is_controlflow(struct rc_instruction * inst) return 0; } -void rc_pair_schedule(struct r300_fragment_program_compiler *c) +void rc_pair_schedule(struct radeon_compiler *cc, void *user) { + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc; struct rc_instruction * inst = c->Base.Program.Instructions.Next; while(inst != &c->Base.Program.Instructions) { if (is_controlflow(inst)) { diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c index 8327e9aced..ff82584466 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c @@ -127,6 +127,18 @@ static void classify_instruction(struct rc_sub_instruction * inst, } } +static void src_uses(struct rc_src_register src, unsigned int * rgb, + unsigned int * alpha) +{ + int j; + for(j = 0; j < 4; ++j) { + unsigned int swz = GET_SWZ(src.Swizzle, j); + if (swz < 3) + *rgb = 1; + else if (swz < 4) + *alpha = 1; + } +} /** * Fill the given ALU instruction's opcodes and source operands into the given pair, @@ -158,12 +170,51 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c, const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode); int i; + /* Presubtract handling: + * We need to make sure that the values used by the presubtract + * operation end up in src0 or src1. */ + if(inst->PreSub.Opcode != RC_PRESUB_NONE) { + /* rc_pair_alloc_source() will fill in data for + * pair->{RGB,ALPHA}.Src[RC_PAIR_PRESUB_SRC] */ + int j; + for(j = 0; j < 3; j++) { + int src_regs; + if(inst->SrcReg[j].File != RC_FILE_PRESUB) + continue; + + src_regs = rc_presubtract_src_reg_count( + inst->PreSub.Opcode); + for(i = 0; i < src_regs; i++) { + unsigned int rgb = 0; + unsigned int alpha = 0; + src_uses(inst->SrcReg[j], &rgb, &alpha); + if(rgb) { + pair->RGB.Src[i].File = + inst->PreSub.SrcReg[i].File; + pair->RGB.Src[i].Index = + inst->PreSub.SrcReg[i].Index; + pair->RGB.Src[i].Used = 1; + } + if(alpha) { + pair->Alpha.Src[i].File = + inst->PreSub.SrcReg[i].File; + pair->Alpha.Src[i].Index = + inst->PreSub.SrcReg[i].Index; + pair->Alpha.Src[i].Used = 1; + } + } + } + } + for(i = 0; i < opcode->NumSrcRegs; ++i) { int source; if (needrgb && !istranscendent) { unsigned int srcrgb = 0; unsigned int srcalpha = 0; int j; + /* We don't care about the alpha channel here. We only + * want the part of the swizzle that writes to rgb, + * since we are creating an rgb instruction. */ for(j = 0; j < 3; ++j) { unsigned int swz = GET_SWZ(inst->SrcReg[i].Swizzle, j); if (swz < 3) @@ -173,6 +224,11 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c, } source = rc_pair_alloc_source(pair, srcrgb, srcalpha, inst->SrcReg[i].File, inst->SrcReg[i].Index); + if (source < 0) { + rc_error(&c->Base, "Failed to translate " + "rgb instruction.\n"); + return; + } pair->RGB.Arg[i].Source = source; pair->RGB.Arg[i].Swizzle = inst->SrcReg[i].Swizzle & 0x1ff; pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs; @@ -188,6 +244,11 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c, srcalpha = 1; source = rc_pair_alloc_source(pair, srcrgb, srcalpha, inst->SrcReg[i].File, inst->SrcReg[i].Index); + if (source < 0) { + rc_error(&c->Base, "Failed to translate " + "alpha instruction.\n"); + return; + } pair->Alpha.Arg[i].Source = source; pair->Alpha.Arg[i].Swizzle = swz; pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs; @@ -262,8 +323,10 @@ static void check_opcode_support(struct r300_fragment_program_compiler *c, * Translate all ALU instructions into corresponding pair instructions, * performing no other changes. */ -void rc_pair_translate(struct r300_fragment_program_compiler *c) +void rc_pair_translate(struct radeon_compiler *cc, void *user) { + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc; + for(struct rc_instruction * inst = c->Base.Program.Instructions.Next; inst != &c->Base.Program.Instructions; inst = inst->Next) { diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program.c b/src/mesa/drivers/dri/r300/compiler/radeon_program.c index a3c41d7bd4..24b685fbeb 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program.c @@ -47,11 +47,12 @@ * \note The transform is called 'local' because it can only look at * one instruction at a time. */ -void radeonLocalTransform( +void rc_local_transform( struct radeon_compiler * c, - int num_transformations, - struct radeon_program_transformation* transformations) + void *user) { + struct radeon_program_transformation *transformations = + (struct radeon_program_transformation*)user; struct rc_instruction * inst = c->Program.Instructions.Next; while(inst != &c->Program.Instructions) { @@ -60,7 +61,7 @@ void radeonLocalTransform( inst = inst->Next; - for(i = 0; i < num_transformations; ++i) { + for(i = 0; transformations[i].function; ++i) { struct radeon_program_transformation* t = transformations + i; if (t->function(c, current, t->userData)) diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program.h b/src/mesa/drivers/dri/r300/compiler/radeon_program.h index e318867696..f0a77d7b53 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program.h @@ -39,7 +39,7 @@ struct radeon_compiler; struct rc_src_register { - unsigned int File:3; + unsigned int File:4; /** Negative values may be used for relative addressing. */ signed int Index:(RC_REGISTER_INDEX_BITS+1); @@ -64,6 +64,11 @@ struct rc_dst_register { unsigned int WriteMask:4; }; +struct rc_presub_instruction { + rc_presubtract_op Opcode; + struct rc_src_register SrcReg[2]; +}; + /** * Instructions are maintained by the compiler in a doubly linked list * of these structures. @@ -108,6 +113,10 @@ struct rc_sub_instruction { /** True if tex instruction should do shadow comparison */ unsigned int TexShadow:1; /*@}*/ + + /** This holds information about the presubtract operation used by + * this instruction. */ + struct rc_presub_instruction PreSub; }; typedef enum { @@ -150,11 +159,6 @@ struct rc_program { struct rc_constant_list Constants; }; -enum { - OPCODE_REPL_ALPHA = MAX_RC_OPCODE /**< used in paired instructions */ -}; - - static inline rc_swizzle get_swz(unsigned int swz, rc_swizzle idx) { if (idx & 0x4) @@ -197,7 +201,7 @@ static inline void reset_srcreg(struct rc_src_register* reg) /** - * A transformation that can be passed to \ref radeonLocalTransform. + * A transformation that can be passed to \ref rc_local_transform. * * The function will be called once for each instruction. * It has to either emit the appropriate transformed code for the instruction @@ -214,10 +218,9 @@ struct radeon_program_transformation { void *userData; }; -void radeonLocalTransform( +void rc_local_transform( struct radeon_compiler *c, - int num_transformations, - struct radeon_program_transformation* transformations); + void *user); unsigned int rc_find_free_temporary(struct radeon_compiler * c); diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c index 704a7bb2d2..4d3e26f28c 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c @@ -770,7 +770,7 @@ static void transform_r300_vertex_SSG(struct radeon_compiler* c, } /** - * For use with radeonLocalTransform, this transforms non-native ALU + * For use with rc_local_transform, this transforms non-native ALU * instructions of the r300 up to r500 vertex engine. */ int r300_transform_vertex_alu( @@ -870,7 +870,7 @@ static void sin_approx( * using only the basic instructions * MOV, ADD, MUL, MAD, FRC */ -int radeonTransformTrigSimple(struct radeon_compiler* c, +int r300_transform_trig_simple(struct radeon_compiler* c, struct rc_instruction* inst, void* unused) { @@ -1081,7 +1081,7 @@ int radeonTransformDeriv(struct radeon_compiler* c, * This needs to be done in its own pass, because it modifies the instructions * before and after KILP. */ -void radeonTransformKILP(struct radeon_compiler * c) +void rc_transform_KILP(struct radeon_compiler * c, void *user) { struct rc_instruction * inst; for (inst = c->Program.Instructions.Next; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.h b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.h index e6e2cc20c5..b5f361e624 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.h @@ -40,7 +40,7 @@ int r300_transform_vertex_alu( struct rc_instruction * inst, void*); -int radeonTransformTrigSimple( +int r300_transform_trig_simple( struct radeon_compiler * c, struct rc_instruction * inst, void*); @@ -60,6 +60,7 @@ int radeonTransformDeriv( struct rc_instruction * inst, void*); -void radeonTransformKILP(struct radeon_compiler * c); +void rc_transform_KILP(struct radeon_compiler * c, + void *user); #endif /* __RADEON_PROGRAM_ALU_H_ */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h b/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h index 2ddf60b677..9dcd44c522 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h @@ -79,7 +79,13 @@ typedef enum { /** * Indicates a special register, see RC_SPECIAL_xxx. */ - RC_FILE_SPECIAL + RC_FILE_SPECIAL, + + /** + * Indicates this register should use the result of the presubtract + * operation. + */ + RC_FILE_PRESUB } rc_register_file; enum { @@ -147,4 +153,32 @@ typedef enum { RC_ALURESULT_W } rc_write_aluresult; +typedef enum { + RC_PRESUB_NONE = 0, + + /** 1 - 2 * src0 */ + RC_PRESUB_BIAS, + + /** src1 - src0 */ + RC_PRESUB_SUB, + + /** src1 + src0 */ + RC_PRESUB_ADD, + + /** 1 - src0 */ + RC_PRESUB_INV +} rc_presubtract_op; + +static inline int rc_presubtract_src_reg_count(rc_presubtract_op op){ + switch(op){ + case RC_PRESUB_BIAS: + case RC_PRESUB_INV: + return 1; + case RC_PRESUB_ADD: + case RC_PRESUB_SUB: + return 2; + default: + return 0; + } +} #endif /* RADEON_PROGRAM_CONSTANTS_H */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c index ee839596aa..c31efdb059 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c @@ -38,26 +38,45 @@ int rc_pair_alloc_source(struct rc_pair_instruction *pair, { int candidate = -1; int candidate_quality = -1; + unsigned int alpha_used = 0; + unsigned int rgb_used = 0; int i; if ((!rgb && !alpha) || file == RC_FILE_NONE) return 0; + /* Make sure only one presubtract operation is used per instruction. */ + if (file == RC_FILE_PRESUB) { + if (rgb && pair->RGB.Src[RC_PAIR_PRESUB_SRC].Used + && index != pair->RGB.Src[RC_PAIR_PRESUB_SRC].Index) { + return -1; + } + + if (alpha && pair->Alpha.Src[RC_PAIR_PRESUB_SRC].Used + && index != pair->Alpha.Src[RC_PAIR_PRESUB_SRC].Index) { + return -1; + } + } + for(i = 0; i < 3; ++i) { int q = 0; if (rgb) { if (pair->RGB.Src[i].Used) { if (pair->RGB.Src[i].File != file || - pair->RGB.Src[i].Index != index) + pair->RGB.Src[i].Index != index) { + rgb_used++; continue; + } q++; } } if (alpha) { if (pair->Alpha.Src[i].Used) { if (pair->Alpha.Src[i].File != file || - pair->Alpha.Src[i].Index != index) + pair->Alpha.Src[i].Index != index) { + alpha_used++; continue; + } q++; } } @@ -67,18 +86,154 @@ int rc_pair_alloc_source(struct rc_pair_instruction *pair, } } - if (candidate >= 0) { - if (rgb) { - pair->RGB.Src[candidate].Used = 1; - pair->RGB.Src[candidate].File = file; - pair->RGB.Src[candidate].Index = index; + if (file == RC_FILE_PRESUB) { + candidate = RC_PAIR_PRESUB_SRC; + } else if (candidate < 0 || (rgb && rgb_used > 2) + || (alpha && alpha_used > 2)) { + return -1; + } + + /* candidate >= 0 */ + + if (rgb) { + pair->RGB.Src[candidate].Used = 1; + pair->RGB.Src[candidate].File = file; + pair->RGB.Src[candidate].Index = index; + if (candidate == RC_PAIR_PRESUB_SRC) { + /* For registers with the RC_FILE_PRESUB file, + * the index stores the presubtract op. */ + int src_regs = rc_presubtract_src_reg_count(index); + for(i = 0; i < src_regs; i++) { + pair->RGB.Src[i].Used = 1; + } } - if (alpha) { - pair->Alpha.Src[candidate].Used = 1; - pair->Alpha.Src[candidate].File = file; - pair->Alpha.Src[candidate].Index = index; + } + if (alpha) { + pair->Alpha.Src[candidate].Used = 1; + pair->Alpha.Src[candidate].File = file; + pair->Alpha.Src[candidate].Index = index; + if (candidate == RC_PAIR_PRESUB_SRC) { + /* For registers with the RC_FILE_PRESUB file, + * the index stores the presubtract op. */ + int src_regs = rc_presubtract_src_reg_count(index); + for(i=0; i < src_regs; i++) { + pair->Alpha.Src[i].Used = 1; + } } } return candidate; } + +static void pair_foreach_source_callback( + struct rc_pair_instruction * pair, + void * data, + rc_pair_foreach_src_fn cb, + unsigned int swz, + unsigned int src) +{ + /* swz > 3 means that the swizzle is either not used, or a constant + * swizzle (e.g. 0, 1, 0.5). */ + if(swz > 3) + return; + + if(swz == RC_SWIZZLE_W) { + if (src == RC_PAIR_PRESUB_SRC) { + unsigned int i; + unsigned int src_count = rc_presubtract_src_reg_count( + pair->Alpha.Src[RC_PAIR_PRESUB_SRC].Index); + for(i = 0; i < src_count; i++) { + cb(data, &pair->Alpha.Src[i]); + } + } else { + cb(data, &pair->Alpha.Src[src]); + } + } else { + if (src == RC_PAIR_PRESUB_SRC) { + unsigned int i; + unsigned int src_count = rc_presubtract_src_reg_count( + pair->RGB.Src[RC_PAIR_PRESUB_SRC].Index); + for(i = 0; i < src_count; i++) { + cb(data, &pair->RGB.Src[i]); + } + } + else { + cb(data, &pair->RGB.Src[src]); + } + } +} + +void rc_pair_foreach_source_that_alpha_reads( + struct rc_pair_instruction * pair, + void * data, + rc_pair_foreach_src_fn cb) +{ + unsigned int i; + const struct rc_opcode_info * info = + rc_get_opcode_info(pair->Alpha.Opcode); + for(i = 0; i < info->NumSrcRegs; i++) { + pair_foreach_source_callback(pair, data, cb, + GET_SWZ(pair->Alpha.Arg[i].Swizzle, 0), + pair->Alpha.Arg[i].Source); + } +} + +void rc_pair_foreach_source_that_rgb_reads( + struct rc_pair_instruction * pair, + void * data, + rc_pair_foreach_src_fn cb) +{ + unsigned int i; + const struct rc_opcode_info * info = + rc_get_opcode_info(pair->RGB.Opcode); + for(i = 0; i < info->NumSrcRegs; i++) { + unsigned int chan; + unsigned int swz = RC_SWIZZLE_UNUSED; + /* Find a swizzle that is either X,Y,Z,or W. We assume here + * that if one channel swizzles X,Y, or Z, then none of the + * other channels swizzle W, and vice-versa. */ + for(chan = 0; chan < 4; chan++) { + swz = GET_SWZ(pair->RGB.Arg[i].Swizzle, chan); + if(swz == RC_SWIZZLE_X || swz == RC_SWIZZLE_Y + || swz == RC_SWIZZLE_Z || swz == RC_SWIZZLE_W) + continue; + } + pair_foreach_source_callback(pair, data, cb, + swz, + pair->RGB.Arg[i].Source); + } +} + +/*return 0 for rgb, 1 for alpha -1 for error. */ + +rc_pair_source_type rc_source_type_that_arg_reads( + unsigned int source, + unsigned int swizzle, + unsigned int channels) +{ + unsigned int chan; + unsigned int swz = RC_SWIZZLE_UNUSED; + int isRGB = 0; + int isAlpha = 0; + /* Find a swizzle that is either X,Y,Z,or W. We assume here + * that if one channel swizzles X,Y, or Z, then none of the + * other channels swizzle W, and vice-versa. */ + for(chan = 0; chan < channels; chan++) { + swz = GET_SWZ(swizzle, chan); + if (swz == RC_SWIZZLE_W) { + isAlpha = 1; + } else if (swz == RC_SWIZZLE_X || swz == RC_SWIZZLE_Y + || swz == RC_SWIZZLE_Z) { + isRGB = 1; + } + } + assert(!isRGB || !isAlpha); + + if(!isRGB && !isAlpha) + return RC_PAIR_SOURCE_NONE; + + if (isRGB) + return RC_PAIR_SOURCE_RGB; + /*isAlpha*/ + return RC_PAIR_SOURCE_ALPHA; +} diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h index 511cc707a3..e0061e454b 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h @@ -32,7 +32,7 @@ #include "radeon_opcodes.h" #include "radeon_program_constants.h" -struct r300_fragment_program_compiler; +struct radeon_compiler; /** @@ -49,6 +49,11 @@ struct r300_fragment_program_compiler; * see \ref rc_pair_translate */ +/* For rgb and alpha instructions when arg[n].Source = RC_PAIR_PRESUB_SRC, then + * the presubtract value will be used, and + * {RGB,Alpha}.Src[RC_PAIR_PRESUB_SRC].File will be set to RC_FILE_PRESUB. + */ +#define RC_PAIR_PRESUB_SRC 3 struct radeon_pair_instruction_source { unsigned int Used:1; @@ -64,7 +69,7 @@ struct radeon_pair_instruction_rgb { unsigned int OutputWriteMask:3; unsigned int Saturate:1; - struct radeon_pair_instruction_source Src[3]; + struct radeon_pair_instruction_source Src[4]; struct { unsigned int Source:2; @@ -83,7 +88,7 @@ struct radeon_pair_instruction_alpha { unsigned int DepthWriteMask:1; unsigned int Saturate:1; - struct radeon_pair_instruction_source Src[3]; + struct radeon_pair_instruction_source Src[4]; struct { unsigned int Source:2; @@ -99,8 +104,17 @@ struct rc_pair_instruction { unsigned int WriteALUResult:2; unsigned int ALUResultCompare:3; + unsigned int Nop:1; }; +typedef void (*rc_pair_foreach_src_fn) + (void *, struct radeon_pair_instruction_source *); + +typedef enum { + RC_PAIR_SOURCE_NONE = 0, + RC_PAIR_SOURCE_RGB, + RC_PAIR_SOURCE_ALPHA +} rc_pair_source_type; /** * General helper functions for dealing with the paired instruction format. @@ -109,6 +123,21 @@ struct rc_pair_instruction { int rc_pair_alloc_source(struct rc_pair_instruction *pair, unsigned int rgb, unsigned int alpha, rc_register_file file, unsigned int index); + +void rc_pair_foreach_source_that_alpha_reads( + struct rc_pair_instruction * pair, + void * data, + rc_pair_foreach_src_fn cb); + +void rc_pair_foreach_source_that_rgb_reads( + struct rc_pair_instruction * pair, + void * data, + rc_pair_foreach_src_fn cb); + +rc_pair_source_type rc_source_type_that_arg_reads( + unsigned int source, + unsigned int swizzle, + unsigned int channels); /*@}*/ @@ -118,9 +147,10 @@ int rc_pair_alloc_source(struct rc_pair_instruction *pair, /*@{*/ struct radeon_pair_handler; -void rc_pair_translate(struct r300_fragment_program_compiler *c); -void rc_pair_schedule(struct r300_fragment_program_compiler *c); -void rc_pair_regalloc(struct r300_fragment_program_compiler *c, unsigned maxtemps); +void rc_pair_translate(struct radeon_compiler *cc, void *user); +void rc_pair_schedule(struct radeon_compiler *cc, void *user); +void rc_pair_regalloc(struct radeon_compiler *cc, void *user); +void rc_pair_regalloc_inputs_only(struct radeon_compiler *cc, void *user); /*@}*/ #endif /* __RADEON_PROGRAM_PAIR_H_ */ diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c index 28fb9eae92..618ab5a099 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c @@ -38,6 +38,24 @@ static const char * textarget_to_string(rc_texture_target target) } } +static const char * presubtract_op_to_string(rc_presubtract_op op) +{ + switch(op) { + case RC_PRESUB_NONE: + return "NONE"; + case RC_PRESUB_BIAS: + return "(1 - 2 * src0)"; + case RC_PRESUB_SUB: + return "(src1 - src0)"; + case RC_PRESUB_ADD: + return "(src1 + src0)"; + case RC_PRESUB_INV: + return "(1 - src0)"; + default: + return "BAD_PRESUBTRACT_OP"; + } +} + static void rc_print_comparefunc(FILE * f, const char * lhs, rc_compare_func func, const char * rhs) { if (func == RC_COMPARE_FUNC_NEVER) { @@ -125,7 +143,43 @@ static void rc_print_swizzle(FILE * f, unsigned int swizzle, unsigned int negate } } -static void rc_print_src_register(FILE * f, struct rc_src_register src) +static void rc_print_presub_instruction(FILE * f, + struct rc_presub_instruction inst) +{ + fprintf(f,"("); + switch(inst.Opcode){ + case RC_PRESUB_BIAS: + fprintf(f, "1 - 2 * "); + rc_print_register(f, inst.SrcReg[0].File, + inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); + break; + case RC_PRESUB_SUB: + rc_print_register(f, inst.SrcReg[1].File, + inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); + fprintf(f, " - "); + rc_print_register(f, inst.SrcReg[0].File, + inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); + break; + case RC_PRESUB_ADD: + rc_print_register(f, inst.SrcReg[1].File, + inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); + fprintf(f, " + "); + rc_print_register(f, inst.SrcReg[0].File, + inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); + break; + case RC_PRESUB_INV: + fprintf(f, "1 - "); + rc_print_register(f, inst.SrcReg[0].File, + inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); + break; + default: + break; + } + fprintf(f, ")"); +} + +static void rc_print_src_register(FILE * f, struct rc_instruction * inst, + struct rc_src_register src) { int trivial_negate = (src.Negate == RC_MASK_NONE || src.Negate == RC_MASK_XYZW); @@ -134,7 +188,10 @@ static void rc_print_src_register(FILE * f, struct rc_src_register src) if (src.Abs) fprintf(f, "|"); - rc_print_register(f, src.File, src.Index, src.RelAddr); + if(src.File == RC_FILE_PRESUB) + rc_print_presub_instruction(f, inst->U.I.PreSub); + else + rc_print_register(f, src.File, src.Index, src.RelAddr); if (src.Abs && !trivial_negate) fprintf(f, "|"); @@ -148,10 +205,35 @@ static void rc_print_src_register(FILE * f, struct rc_src_register src) fprintf(f, "|"); } -static void rc_print_normal_instruction(FILE * f, struct rc_instruction * inst) +static unsigned update_branch_depth(rc_opcode opcode, unsigned *branch_depth) +{ + switch (opcode) { + case RC_OPCODE_IF: + case RC_OPCODE_BGNLOOP: + return (*branch_depth)++ * 2; + + case RC_OPCODE_ENDIF: + case RC_OPCODE_ENDLOOP: + assert(*branch_depth > 0); + return --(*branch_depth) * 2; + + case RC_OPCODE_ELSE: + assert(*branch_depth > 0); + return (*branch_depth - 1) * 2; + + default: + return *branch_depth * 2; + } +} + +static void rc_print_normal_instruction(FILE * f, struct rc_instruction * inst, unsigned *branch_depth) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); unsigned int reg; + unsigned spaces = update_branch_depth(inst->U.I.Opcode, branch_depth); + + for (unsigned i = 0; i < spaces; i++) + fprintf(f, " "); fprintf(f, "%s", opcode->Name); @@ -173,7 +255,7 @@ static void rc_print_normal_instruction(FILE * f, struct rc_instruction * inst) if (reg > 0) fprintf(f, ","); fprintf(f, " "); - rc_print_src_register(f, inst->U.I.SrcReg[reg]); + rc_print_src_register(f, inst, inst->U.I.SrcReg[reg]); } if (opcode->HasTexture) { @@ -196,10 +278,15 @@ static void rc_print_normal_instruction(FILE * f, struct rc_instruction * inst) fprintf(f, "\n"); } -static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst) +static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst, unsigned *branch_depth) { struct rc_pair_instruction * inst = &fullinst->U.P; int printedsrc = 0; + unsigned spaces = update_branch_depth(inst->RGB.Opcode != RC_OPCODE_NOP ? + inst->RGB.Opcode : inst->Alpha.Opcode, branch_depth); + + for (unsigned i = 0; i < spaces; i++) + fprintf(f, " "); for(unsigned int src = 0; src < 3; ++src) { if (inst->RGB.Src[src].Used) { @@ -217,11 +304,24 @@ static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst printedsrc = 1; } } + if(inst->RGB.Src[RC_PAIR_PRESUB_SRC].Used) { + fprintf(f, ", srcp.xyz = %s", + presubtract_op_to_string( + inst->RGB.Src[RC_PAIR_PRESUB_SRC].Index)); + } + if(inst->Alpha.Src[RC_PAIR_PRESUB_SRC].Used) { + fprintf(f, ", srcp.w = %s", + presubtract_op_to_string( + inst->Alpha.Src[RC_PAIR_PRESUB_SRC].Index)); + } fprintf(f, "\n"); if (inst->RGB.Opcode != RC_OPCODE_NOP) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->RGB.Opcode); + for (unsigned i = 0; i < spaces; i++) + fprintf(f, " "); + fprintf(f, " %s%s", opcode->Name, inst->RGB.Saturate ? "_SAT" : ""); if (inst->RGB.WriteMask) fprintf(f, " temp[%i].%s%s%s", inst->RGB.DestIndex, @@ -239,7 +339,12 @@ static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) { const char* abs = inst->RGB.Arg[arg].Abs ? "|" : ""; const char* neg = inst->RGB.Arg[arg].Negate ? "-" : ""; - fprintf(f, ", %s%ssrc%i.%c%c%c%s", neg, abs, inst->RGB.Arg[arg].Source, + fprintf(f, ", %s%ssrc", neg, abs); + if(inst->RGB.Arg[arg].Source == RC_PAIR_PRESUB_SRC) + fprintf(f,"p"); + else + fprintf(f,"%d", inst->RGB.Arg[arg].Source); + fprintf(f,".%c%c%c%s", rc_swizzle_char(GET_SWZ(inst->RGB.Arg[arg].Swizzle, 0)), rc_swizzle_char(GET_SWZ(inst->RGB.Arg[arg].Swizzle, 1)), rc_swizzle_char(GET_SWZ(inst->RGB.Arg[arg].Swizzle, 2)), @@ -251,6 +356,9 @@ static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst if (inst->Alpha.Opcode != RC_OPCODE_NOP) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Alpha.Opcode); + for (unsigned i = 0; i < spaces; i++) + fprintf(f, " "); + fprintf(f, " %s%s", opcode->Name, inst->Alpha.Saturate ? "_SAT" : ""); if (inst->Alpha.WriteMask) fprintf(f, " temp[%i].w", inst->Alpha.DestIndex); @@ -264,13 +372,21 @@ static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) { const char* abs = inst->Alpha.Arg[arg].Abs ? "|" : ""; const char* neg = inst->Alpha.Arg[arg].Negate ? "-" : ""; - fprintf(f, ", %s%ssrc%i.%c%s", neg, abs, inst->Alpha.Arg[arg].Source, + fprintf(f, ", %s%ssrc", neg, abs); + if(inst->Alpha.Arg[arg].Source == RC_PAIR_PRESUB_SRC) + fprintf(f,"p"); + else + fprintf(f,"%d", inst->Alpha.Arg[arg].Source); + fprintf(f,".%c%s", rc_swizzle_char(inst->Alpha.Arg[arg].Swizzle), abs); } fprintf(f, "\n"); } if (inst->WriteALUResult) { + for (unsigned i = 0; i < spaces; i++) + fprintf(f, " "); + fprintf(f, " [aluresult = ("); rc_print_comparefunc(f, "result", inst->ALUResultCompare, "0"); fprintf(f, ")]\n"); @@ -283,6 +399,7 @@ static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst void rc_print_program(const struct rc_program *prog) { unsigned int linenum = 0; + unsigned branch_depth = 0; struct rc_instruction *inst; fprintf(stderr, "# Radeon Compiler Program\n"); @@ -291,9 +408,9 @@ void rc_print_program(const struct rc_program *prog) fprintf(stderr, "%3d: ", linenum); if (inst->Type == RC_INSTRUCTION_PAIR) - rc_print_pair_instruction(stderr, inst); + rc_print_pair_instruction(stderr, inst, &branch_depth); else - rc_print_normal_instruction(stderr, inst); + rc_print_normal_instruction(stderr, inst, &branch_depth); linenum++; } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c b/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c index be89e9fa5b..d111319d3d 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c @@ -26,10 +26,21 @@ */ #include "radeon_remove_constants.h" +#include "radeon_dataflow.h" -void rc_remove_unused_constants(struct radeon_compiler *c, - unsigned **out_remap_table) +static void remap_regs(void * userdata, struct rc_instruction * inst, + rc_register_file * pfile, unsigned int * pindex) { + unsigned *inv_remap_table = userdata; + + if (*pfile == RC_FILE_CONSTANT) { + *pindex = inv_remap_table[*pindex]; + } +} + +void rc_remove_unused_constants(struct radeon_compiler *c, void *user) +{ + unsigned **out_remap_table = (unsigned**)user; unsigned char *const_used; unsigned *remap_table; unsigned *inv_remap_table; @@ -51,6 +62,10 @@ void rc_remove_unused_constants(struct radeon_compiler *c, inst != &c->Program.Instructions; inst = inst->Next) { const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); + /* XXX: This loop and the if statement after it should be + * replaced by a call to one of the rc_for_all_reads_* functions. + * The reason it does not use one of those functions now is + * because none of them have RelAddr as an argument. */ for (unsigned i = 0; i < opcode->NumSrcRegs; i++) { if (inst->U.I.SrcReg[i].File == RC_FILE_CONSTANT) { if (inst->U.I.SrcReg[i].RelAddr) { @@ -60,6 +75,18 @@ void rc_remove_unused_constants(struct radeon_compiler *c, } } } + if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE) { + unsigned int i; + unsigned int srcp_regs = rc_presubtract_src_reg_count( + inst->U.I.PreSub.Opcode); + for( i = 0; i < srcp_regs; i++) { + if (inst->U.I.PreSub.SrcReg[i].File == + RC_FILE_CONSTANT) { + const_used[ + inst->U.I.PreSub.SrcReg[i].Index] = 1; + } + } + } } /* Pass 2: If there is relative addressing, mark all externals as used. */ @@ -100,13 +127,7 @@ void rc_remove_unused_constants(struct radeon_compiler *c, if (!is_identity) { for (struct rc_instruction *inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) { - const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); - - for (unsigned i = 0; i < opcode->NumSrcRegs; i++) { - if (inst->U.I.SrcReg[i].File == RC_FILE_CONSTANT) { - inst->U.I.SrcReg[i].Index = inv_remap_table[inst->U.I.SrcReg[i].Index]; - } - } + rc_remap_registers(inst, remap_regs, inv_remap_table); } } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.h b/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.h index 0d3a26ca1c..f29113b922 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.h @@ -30,7 +30,6 @@ #include "radeon_compiler.h" -void rc_remove_unused_constants(struct radeon_compiler *c, - unsigned **out_remap_table); +void rc_remove_unused_constants(struct radeon_compiler *c, void *user); #endif diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c b/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c index 31c9866883..31d25f9ab8 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c @@ -87,7 +87,7 @@ static void rename_all( * This function assumes all the instructions are still of type * RC_INSTRUCTION_NORMAL. */ -void rc_rename_regs(struct radeon_compiler * c) +void rc_rename_regs(struct radeon_compiler *c, void *user) { unsigned int cur_index = 0; unsigned int icount; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.h b/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.h index 4323b995d8..3baf29f612 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.h @@ -4,6 +4,6 @@ struct radeon_compiler; -void rc_rename_regs(struct radeon_compiler * c); +void rc_rename_regs(struct radeon_compiler *c, void *user); #endif /* RADEON_RENAME_REGS_H */ diff --git a/src/mesa/drivers/dri/r300/r300_blit.c b/src/mesa/drivers/dri/r300/r300_blit.c index d2c25fb9cd..74aef765e3 100644 --- a/src/mesa/drivers/dri/r300/r300_blit.c +++ b/src/mesa/drivers/dri/r300/r300_blit.c @@ -56,6 +56,7 @@ static void create_vertex_program(struct r300_context *r300) struct r300_vertex_program_compiler compiler; struct rc_instruction *inst; + memset(&compiler, 0, sizeof(compiler)); rc_init(&compiler.Base); inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev); @@ -88,6 +89,12 @@ static void create_vertex_program(struct r300_context *r300) compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0); compiler.SetHwInputOutput = vp_ins_outs; compiler.code = &r300->blit.vp_code; + compiler.Base.is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; + compiler.Base.disable_optimizations = 0; + compiler.Base.has_half_swizzles = 0; + compiler.Base.max_temp_regs = 32; + compiler.Base.max_constants = 256; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256; r3xx_compile_vertex_program(&compiler); } @@ -119,7 +126,11 @@ static void create_fragment_program(struct r300_context *r300) compiler.OutputDepth = FRAG_RESULT_DEPTH; compiler.enable_shadow_ambient = GL_TRUE; compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515); + compiler.Base.disable_optimizations = 0; + compiler.Base.has_half_swizzles = 1; compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32; + compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64; compiler.code = &r300->blit.fp_code; compiler.AllocateHwInputs = fp_allocate_hw_inputs; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c index 7b6521c748..4af91f114d 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c @@ -213,6 +213,7 @@ static void translate_fragment_program(GLcontext *ctx, struct r300_fragment_prog r300ContextPtr r300 = R300_CONTEXT(ctx); struct r300_fragment_program_compiler compiler; + memset(&compiler, 0, sizeof(compiler)); rc_init(&compiler.Base); compiler.Base.Debug = (RADEON_DEBUG & RADEON_PIXEL) ? GL_TRUE : GL_FALSE; @@ -220,7 +221,11 @@ static void translate_fragment_program(GLcontext *ctx, struct r300_fragment_prog compiler.state = fp->state; compiler.enable_shadow_ambient = GL_TRUE; compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) ? GL_TRUE : GL_FALSE; + compiler.Base.disable_optimizations = 0; + compiler.Base.has_half_swizzles = 1; compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32; + compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64; compiler.OutputDepth = FRAG_RESULT_DEPTH; memset(compiler.OutputColor, 0, 4 * sizeof(unsigned)); compiler.OutputColor[0] = FRAG_RESULT_COLOR; diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 67d8b2b328..a160128091 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -238,12 +238,19 @@ static struct r300_vertex_program *build_program(GLcontext *ctx, vp->Base = _mesa_clone_vertex_program(ctx, mesa_vp); memcpy(&vp->key, wanted_key, sizeof(vp->key)); + memset(&compiler, 0, sizeof(compiler)); rc_init(&compiler.Base); compiler.Base.Debug = (RADEON_DEBUG & RADEON_VERTS) ? GL_TRUE : GL_FALSE; compiler.code = &vp->code; compiler.RequiredOutputs = compute_required_outputs(vp->Base, vp->key.FpReads); compiler.SetHwInputOutput = &t_inputs_outputs; + compiler.Base.is_r500 = R300_CONTEXT(ctx)->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; + compiler.Base.disable_optimizations = 0; + compiler.Base.has_half_swizzles = 0; + compiler.Base.max_temp_regs = 32; + compiler.Base.max_constants = 256; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256; if (compiler.Base.Debug) { fprintf(stderr, "Initial vertex program:\n"); diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 03c17540e0..200bc20f64 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -68,6 +68,7 @@ DRIVER_SOURCES = \ evergreen_vertprog.c \ evergreen_fragprog.c \ evergreen_oglprog.c \ + evergreen_blit.c \ $(RADEON_COMMON_SOURCES) \ $(EGL_SOURCES) \ $(CS_SOURCES) diff --git a/src/mesa/drivers/dri/r600/evergreen_blit.c b/src/mesa/drivers/dri/r600/evergreen_blit.c new file mode 100644 index 0000000000..1ed8a08b78 --- /dev/null +++ b/src/mesa/drivers/dri/r600/evergreen_blit.c @@ -0,0 +1,1789 @@ +/* + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "radeon_common.h" +#include "r600_context.h" + +#include "evergreen_off.h" +#include "evergreen_diff.h" + +#include "evergreen_blit.h" +#include "evergreen_blit_shaders.h" +#include "r600_cmdbuf.h" + +/* common formats supported as both textures and render targets */ +unsigned evergreen_check_blit(gl_format mesa_format) +{ + switch (mesa_format) { + case MESA_FORMAT_RGBA8888: + case MESA_FORMAT_SIGNED_RGBA8888: + case MESA_FORMAT_RGBA8888_REV: + case MESA_FORMAT_SIGNED_RGBA8888_REV: + case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: + case MESA_FORMAT_ARGB8888_REV: + case MESA_FORMAT_XRGB8888_REV: + case MESA_FORMAT_RGB565: + case MESA_FORMAT_RGB565_REV: + case MESA_FORMAT_ARGB4444: + case MESA_FORMAT_ARGB4444_REV: + case MESA_FORMAT_ARGB1555: + case MESA_FORMAT_ARGB1555_REV: + case MESA_FORMAT_AL88: + case MESA_FORMAT_AL88_REV: + case MESA_FORMAT_RGB332: + case MESA_FORMAT_A8: + case MESA_FORMAT_I8: + case MESA_FORMAT_CI8: + case MESA_FORMAT_L8: + case MESA_FORMAT_RGBA_FLOAT32: + case MESA_FORMAT_RGBA_FLOAT16: + case MESA_FORMAT_ALPHA_FLOAT32: + case MESA_FORMAT_ALPHA_FLOAT16: + case MESA_FORMAT_LUMINANCE_FLOAT32: + case MESA_FORMAT_LUMINANCE_FLOAT16: + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + case MESA_FORMAT_X8_Z24: + case MESA_FORMAT_S8_Z24: + case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_Z16: + case MESA_FORMAT_Z32: + case MESA_FORMAT_SARGB8: + case MESA_FORMAT_SLA8: + case MESA_FORMAT_SL8: + break; + default: + return 0; + } + + /* ??? */ + /* not sure blit to depth works or not yet */ + if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0) + return 0; + + return 1; +} + +static inline void +eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format, + int nPitchInPixel, int w, int h, intptr_t dst_offset) +{ + uint32_t cb_color0_base, cb_color0_info = 0; + uint32_t cb_color0_pitch = 0, cb_color0_slice = 0, cb_color0_attrib = 0; + int id = 0; + uint32_t comp_swap, format, source_format, number_type; + BATCH_LOCALS(&context->radeon); + + cb_color0_base = dst_offset / 256; + + /* pitch */ + SETfield(cb_color0_pitch, (nPitchInPixel / 8) - 1, + EG_CB_COLOR0_PITCH__TILE_MAX_shift, + EG_CB_COLOR0_PITCH__TILE_MAX_mask); + + /* slice */ + SETfield(cb_color0_slice, + ((nPitchInPixel * h) / 64) - 1, + EG_CB_COLOR0_SLICE__TILE_MAX_shift, + EG_CB_COLOR0_SLICE__TILE_MAX_mask); + + /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */ + SETbit(cb_color0_attrib, + EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit); + + SETfield(cb_color0_info, + ENDIAN_NONE, + EG_CB_COLOR0_INFO__ENDIAN_shift, + EG_CB_COLOR0_INFO__ENDIAN_mask); + SETfield(cb_color0_info, + ARRAY_LINEAR_GENERAL, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + + SETbit(cb_color0_info, EG_CB_COLOR0_INFO__BLEND_BYPASS_bit); + + switch(mesa_format) { + case MESA_FORMAT_RGBA8888: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_SIGNED_RGBA8888: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_SNORM; + source_format = 1; + break; + case MESA_FORMAT_RGBA8888_REV: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_SIGNED_RGBA8888_REV: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD; + number_type = NUMBER_SNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: + format = COLOR_8_8_8_8; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB8888_REV: + case MESA_FORMAT_XRGB8888_REV: + format = COLOR_8_8_8_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGB565: + format = COLOR_5_6_5; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGB565_REV: + format = COLOR_5_6_5; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB4444: + format = COLOR_4_4_4_4; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB4444_REV: + format = COLOR_4_4_4_4; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB1555: + format = COLOR_1_5_5_5; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB1555_REV: + format = COLOR_1_5_5_5; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_AL88: + format = COLOR_8_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_AL88_REV: + format = COLOR_8_8; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGB332: + format = COLOR_3_3_2; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_A8: + format = COLOR_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_I8: + case MESA_FORMAT_CI8: + format = COLOR_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_L8: + format = COLOR_8; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGBA_FLOAT32: + format = COLOR_32_32_32_32_FLOAT; + comp_swap = SWAP_STD; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_RGBA_FLOAT16: + format = COLOR_16_16_16_16_FLOAT; + comp_swap = SWAP_STD; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_ALPHA_FLOAT32: + format = COLOR_32_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_ALPHA_FLOAT16: + format = COLOR_16_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_FLOAT32: + format = COLOR_32_FLOAT; + comp_swap = SWAP_ALT; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_FLOAT16: + format = COLOR_16_FLOAT; + comp_swap = SWAP_ALT; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + format = COLOR_32_32_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + format = COLOR_16_16_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + format = COLOR_32_FLOAT; + comp_swap = SWAP_STD; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + format = COLOR_16_FLOAT; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 0; + break; + case MESA_FORMAT_X8_Z24: + case MESA_FORMAT_S8_Z24: + format = COLOR_8_24; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(cb_color0_info, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_Z24_S8: + format = COLOR_24_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(cb_color0_info, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_Z16: + format = COLOR_16; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(cb_color0_info, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_Z32: + format = COLOR_32; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(cb_color0_info, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_SARGB8: + format = COLOR_8_8_8_8; + comp_swap = SWAP_ALT; + number_type = NUMBER_SRGB; + source_format = 1; + break; + case MESA_FORMAT_SLA8: + format = COLOR_8_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_SRGB; + source_format = 1; + break; + case MESA_FORMAT_SL8: + format = COLOR_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_SRGB; + source_format = 1; + break; + default: + fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format)); + assert("Invalid format for US output\n"); + return; + } + + SETfield(cb_color0_info, + format, + EG_CB_COLOR0_INFO__FORMAT_shift, + EG_CB_COLOR0_INFO__FORMAT_mask); + SETfield(cb_color0_info, + comp_swap, + EG_CB_COLOR0_INFO__COMP_SWAP_shift, + EG_CB_COLOR0_INFO__COMP_SWAP_mask); + SETfield(cb_color0_info, + number_type, + EG_CB_COLOR0_INFO__NUMBER_TYPE_shift, + EG_CB_COLOR0_INFO__NUMBER_TYPE_mask); + SETfield(cb_color0_info, + source_format, + EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift, + EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask); + + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1); + R600_OUT_BATCH(cb_color0_base); + R600_OUT_BATCH_RELOC(cb_color0_base, + bo, + cb_color0_base, + 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, cb_color0_info); + R600_OUT_BATCH_RELOC(cb_color0_info, + bo, + cb_color0_info, + 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(5); + EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3); + R600_OUT_BATCH(cb_color0_pitch); + R600_OUT_BATCH(cb_color0_slice); + R600_OUT_BATCH(0); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(4); + EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2); + R600_OUT_BATCH(cb_color0_attrib); + R600_OUT_BATCH(0); + /* + R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All); + R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All); + R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All); + R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All); + */ + END_BATCH(); + + COMMIT_BATCH(); + +} + +static inline void eg_load_shaders(GLcontext * ctx) +{ + + radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); + context_t *context = EVERGREEN_CONTEXT(ctx); + int i, size; + uint32_t *shader; + + if (context->blit_bo_loaded == 1) + return; + + size = 4096; + context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0, + size, 256, RADEON_GEM_DOMAIN_GTT, 0); + radeon_bo_map(context->blit_bo, 1); + shader = context->blit_bo->ptr; + + for(i=0; i<sizeof(evergreen_vs)/4; i++) { + shader[128+i] = evergreen_vs[i]; + } + for(i=0; i<sizeof(evergreen_ps)/4; i++) { + shader[256+i] = evergreen_ps[i]; + } + + radeon_bo_unmap(context->blit_bo); + context->blit_bo_loaded = 1; + +} + +static inline void +eg_set_shaders(context_t *context) +{ + struct radeon_bo * pbo = context->blit_bo; + uint32_t sq_pgm_start_fs = (512 >> 8); + uint32_t sq_pgm_resources_fs = 0; + + uint32_t sq_pgm_start_vs = (512 >> 8); + uint32_t sq_pgm_resources_vs = (2 << NUM_GPRS_shift); + + uint32_t sq_pgm_start_ps = (1024 >> 8); + uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift); + uint32_t sq_pgm_exports_ps = (1 << 1); + BATCH_LOCALS(&context->radeon); + + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); + + /* FS */ + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_FS, 1); + R600_OUT_BATCH(sq_pgm_start_fs); + R600_OUT_BATCH_RELOC(sq_pgm_start_fs, + pbo, + sq_pgm_start_fs, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(3); + EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs); + END_BATCH(); + + /* VS */ + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1); + R600_OUT_BATCH(sq_pgm_start_vs); + R600_OUT_BATCH_RELOC(sq_pgm_start_vs, + pbo, + sq_pgm_start_vs, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(4); + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2); + R600_OUT_BATCH(sq_pgm_resources_vs); + R600_OUT_BATCH(0); + END_BATCH(); + + /* PS */ + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1); + R600_OUT_BATCH(sq_pgm_start_ps); + R600_OUT_BATCH_RELOC(sq_pgm_start_ps, + pbo, + sq_pgm_start_ps, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(5); + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3); + R600_OUT_BATCH(sq_pgm_resources_ps); + R600_OUT_BATCH(0); + R600_OUT_BATCH(sq_pgm_exports_ps); + END_BATCH(); + + COMMIT_BATCH(); + +} + +static inline void +eg_set_vtx_resource(context_t *context) +{ + struct radeon_bo *bo = context->blit_bo; + uint32_t sq_vtx_constant_word3 = 0; + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); + END_BATCH(); + + if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) + r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit); + else + r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); + + SETfield(sq_vtx_constant_word3, SQ_SEL_X, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask); + SETfield(sq_vtx_constant_word3, SQ_SEL_Y, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask); + SETfield(sq_vtx_constant_word3, SQ_SEL_Z, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask); + SETfield(sq_vtx_constant_word3, SQ_SEL_W, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift, + EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask); + + BEGIN_BATCH_NO_AUTOSTATE(10 + 2); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8)); + R600_OUT_BATCH(EG_SQ_FETCH_RESOURCE_VS_OFFSET * EG_FETCH_RESOURCE_STRIDE); + R600_OUT_BATCH(0); + R600_OUT_BATCH(48 - 1); + R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift); + R600_OUT_BATCH(sq_vtx_constant_word3); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift); + R600_OUT_BATCH_RELOC(0, + bo, + 0, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + COMMIT_BATCH(); + +} + +static inline void +eg_set_tex_resource(context_t * context, + gl_format mesa_format, struct radeon_bo *bo, int w, int h, + int TexelPitch, intptr_t src_offset) +{ + uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource7; + + sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource7 = 0; + BATCH_LOCALS(&context->radeon); + + SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + + switch (mesa_format) { + case MESA_FORMAT_RGBA8888: + case MESA_FORMAT_SIGNED_RGBA8888: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) { + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + } + break; + case MESA_FORMAT_RGBA8888_REV: + case MESA_FORMAT_SIGNED_RGBA8888_REV: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) { + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + } + break; + case MESA_FORMAT_ARGB8888: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_XRGB8888: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ARGB8888_REV: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_XRGB8888_REV: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_RGB565: + SETfield(sq_tex_resource7, FMT_5_6_5, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_RGB565_REV: + SETfield(sq_tex_resource7, FMT_5_6_5, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ARGB4444: + SETfield(sq_tex_resource7, FMT_4_4_4_4, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ARGB4444_REV: + SETfield(sq_tex_resource7, FMT_4_4_4_4, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ARGB1555: + SETfield(sq_tex_resource7, FMT_1_5_5_5, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ARGB1555_REV: + SETfield(sq_tex_resource7, FMT_1_5_5_5, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_AL88: + case MESA_FORMAT_AL88_REV: /* TODO : Check this. */ + SETfield(sq_tex_resource7, FMT_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_RGB332: + SETfield(sq_tex_resource7, FMT_3_3_2, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */ + SETfield(sq_tex_resource7, FMT_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_L8: /* X, X, X, ONE */ + SETfield(sq_tex_resource7, FMT_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_I8: /* X, X, X, X */ + case MESA_FORMAT_CI8: + SETfield(sq_tex_resource7, FMT_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_RGBA_FLOAT32: + SETfield(sq_tex_resource7, FMT_32_32_32_32_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_RGBA_FLOAT16: + SETfield(sq_tex_resource7, FMT_16_16_16_16_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */ + SETfield(sq_tex_resource7, FMT_32_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */ + SETfield(sq_tex_resource7, FMT_16_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */ + SETfield(sq_tex_resource7, FMT_32_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */ + SETfield(sq_tex_resource7, FMT_16_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + SETfield(sq_tex_resource7, FMT_32_32_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + SETfield(sq_tex_resource7, FMT_16_16_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + SETfield(sq_tex_resource7, FMT_32_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + SETfield(sq_tex_resource7, FMT_16_FLOAT, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_Z16: + /* ??? */ + CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit); + SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask); + SETfield(sq_tex_resource7, FMT_16, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_X8_Z24: + /* ??? */ + CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit); + SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask); + SETfield(sq_tex_resource7, FMT_8_24, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_S8_Z24: + /* ??? */ + CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit); + SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask); + SETbit(sq_tex_resource0, TILE_TYPE_bit); + SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + SETfield(sq_tex_resource7, FMT_8_24, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_Z24_S8: + /* ??? */ + CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit); + SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask); + SETbit(sq_tex_resource0, TILE_TYPE_bit); + SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + SETfield(sq_tex_resource7, FMT_24_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_0, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_Z32: + /* ??? */ + CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit); + SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask); + SETbit(sq_tex_resource0, TILE_TYPE_bit); + SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + SETfield(sq_tex_resource7, FMT_32, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_S8: + /* ??? */ + CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit); + SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask); + SETfield(sq_tex_resource7, FMT_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + break; + case MESA_FORMAT_SARGB8: + SETfield(sq_tex_resource7, FMT_8_8_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_Z, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_W, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); + break; + case MESA_FORMAT_SLA8: + SETfield(sq_tex_resource7, FMT_8_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_Y, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); + break; + case MESA_FORMAT_SL8: /* X, X, X, ONE */ + SETfield(sq_tex_resource7, FMT_8, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, + EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); + SETfield(sq_tex_resource4, SQ_SEL_X, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); + SETfield(sq_tex_resource4, SQ_SEL_1, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); + break; + default: + fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format)); + assert("Invalid format for US output\n"); + return; + }; + + SETfield(sq_tex_resource0, (TexelPitch/8)-1, + EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift, + EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask); + SETfield(sq_tex_resource0, w - 1, + EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift, + EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask); + SETfield(sq_tex_resource1, h - 1, + EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift, + EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask); + + sq_tex_resource2 = src_offset / 256; + + SETfield(sq_tex_resource7, SQ_TEX_VTX_VALID_TEXTURE, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, + SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); + + r700SyncSurf(context, bo, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, + 0, TC_ACTION_ENA_bit); + + BEGIN_BATCH_NO_AUTOSTATE(10 + 4); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8)); + R600_OUT_BATCH(0 * 7); + R600_OUT_BATCH(sq_tex_resource0); + R600_OUT_BATCH(sq_tex_resource1); + R600_OUT_BATCH(sq_tex_resource2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(sq_tex_resource4); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(sq_tex_resource7); + R600_OUT_BATCH_RELOC(0, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + R600_OUT_BATCH_RELOC(0, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + END_BATCH(); + COMMIT_BATCH(); +} + +static inline void +eg_set_tex_sampler(context_t * context) +{ + uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0; + int i = 0; + + SETbit(sq_tex_sampler_word2, EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit); + + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(5); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(sq_tex_sampler_word0); + R600_OUT_BATCH(sq_tex_sampler_word1); + R600_OUT_BATCH(sq_tex_sampler_word2); + END_BATCH(); + +} + +static inline void +eg_set_scissors(context_t *context, int x1, int y1, int x2, int y2) +{ + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(17); + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2); + R600_OUT_BATCH((x1 << 0) | (y1 << 16)); + R600_OUT_BATCH((x2 << 0) | (y2 << 16)); + + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 3); + R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET + R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL + R600_OUT_BATCH((x2 << 0) | (y2 << 16)); + + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2); + R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); + R600_OUT_BATCH((x2 << 0) | (y2 << 16)); + + /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */ + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 2); + R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); + R600_OUT_BATCH((x2 << 0) | (y2 << 16)); + END_BATCH(); + + COMMIT_BATCH(); + +} + +static inline void +eg_set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y, + int w, int h, int src_h, unsigned flip_y) +{ + float *vb; + radeon_bo_map(context->blit_bo, 1); + vb = context->blit_bo->ptr; + + vb[0] = (float)(dst_x); + vb[1] = (float)(dst_y); + vb[2] = (float)(src_x); + vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y; + + vb[4] = (float)(dst_x); + vb[5] = (float)(dst_y + h); + vb[6] = (float)(src_x); + vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h); + + vb[8] = (float)(dst_x + w); + vb[9] = (float)(dst_y + h); + vb[10] = (float)(src_x + w); + vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h); + + radeon_bo_unmap(context->blit_bo); + +} + +static inline void +eg_draw_auto(context_t *context) +{ + BATCH_LOCALS(&context->radeon); + uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices; + + SETfield(vgt_primitive_type, DI_PT_RECTLIST, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); + SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, + INDEX_TYPE_mask); + SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, + MAJOR_MODE_mask); + SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, + SOURCE_SELECT_mask); + + vgt_num_indices = 3; + + BEGIN_BATCH_NO_AUTOSTATE(10); + // prim + EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVE_TYPE, 1); + R600_OUT_BATCH(vgt_primitive_type); + // index type + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(vgt_index_type); + // num instances + R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + R600_OUT_BATCH(1); + // + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1)); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + + END_BATCH(); + COMMIT_BATCH(); +} + +static inline void +eg_set_default_state(context_t *context) +{ + int num_ps_gprs; + int num_vs_gprs; + int num_gs_gprs; + int num_es_gprs; + int num_hs_gprs; + int num_ls_gprs; + int num_temp_gprs; + int num_ps_threads; + int num_vs_threads; + int num_gs_threads; + int num_es_threads; + int num_hs_threads; + int num_ls_threads; + int num_ps_stack_entries; + int num_vs_stack_entries; + int num_gs_stack_entries; + int num_es_stack_entries; + int num_hs_stack_entries; + int num_ls_stack_entries; + uint32_t sq_config = 0, sq_gpr_resource_mgmt_1 = 0, sq_gpr_resource_mgmt_2 = 0; + uint32_t sq_gpr_resource_mgmt_3 = 0; + uint32_t sq_thread_resource_mgmt = 0, sq_thread_resource_mgmt_2 = 0; + uint32_t sq_stack_resource_mgmt_1 = 0, sq_stack_resource_mgmt_2 = 0, sq_stack_resource_mgmt_3 = 0; + BATCH_LOCALS(&context->radeon); + + switch (context->radeon.radeonScreen->chip_family) { + case CHIP_FAMILY_CEDAR: + default: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 96; + num_vs_threads = 16; + num_gs_threads = 16; + num_es_threads = 16; + num_hs_threads = 16; + num_ls_threads = 16; + num_ps_stack_entries = 42; + num_vs_stack_entries = 42; + num_gs_stack_entries = 42; + num_es_stack_entries = 42; + num_hs_stack_entries = 42; + num_ls_stack_entries = 42; + break; + case CHIP_FAMILY_REDWOOD: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 42; + num_vs_stack_entries = 42; + num_gs_stack_entries = 42; + num_es_stack_entries = 42; + num_hs_stack_entries = 42; + num_ls_stack_entries = 42; + break; + case CHIP_FAMILY_JUNIPER: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 85; + num_vs_stack_entries = 85; + num_gs_stack_entries = 85; + num_es_stack_entries = 85; + num_hs_stack_entries = 85; + num_ls_stack_entries = 85; + break; + case CHIP_FAMILY_CYPRESS: + case CHIP_FAMILY_HEMLOCK: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 85; + num_vs_stack_entries = 85; + num_gs_stack_entries = 85; + num_es_stack_entries = 85; + num_hs_stack_entries = 85; + num_ls_stack_entries = 85; + break; + } + + if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) + CLEARbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit); + else + SETbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit); + SETbit(sq_config, EG_SQ_CONFIG__EXPORT_SRC_C_bit); + + SETfield(sq_config, 0, + EG_SQ_CONFIG__PS_PRIO_shift, + EG_SQ_CONFIG__PS_PRIO_mask); + SETfield(sq_config, 1, + EG_SQ_CONFIG__VS_PRIO_shift, + EG_SQ_CONFIG__VS_PRIO_mask); + SETfield(sq_config, 2, + EG_SQ_CONFIG__GS_PRIO_shift, + EG_SQ_CONFIG__GS_PRIO_mask); + SETfield(sq_config, 3, + EG_SQ_CONFIG__ES_PRIO_shift, + EG_SQ_CONFIG__ES_PRIO_mask); + + + SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, + NUM_PS_GPRS_shift, NUM_PS_GPRS_mask); + SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, + NUM_VS_GPRS_shift, NUM_VS_GPRS_mask); + SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs, + NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask); + SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, + NUM_GS_GPRS_shift, NUM_GS_GPRS_mask); + SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, + NUM_ES_GPRS_shift, NUM_ES_GPRS_mask); + SETfield(sq_gpr_resource_mgmt_3, num_hs_gprs, + NUM_PS_GPRS_shift, NUM_PS_GPRS_mask); + SETfield(sq_gpr_resource_mgmt_3, num_ls_gprs, + NUM_VS_GPRS_shift, NUM_VS_GPRS_mask); + + SETfield(sq_thread_resource_mgmt, num_ps_threads, + NUM_PS_THREADS_shift, NUM_PS_THREADS_mask); + SETfield(sq_thread_resource_mgmt, num_vs_threads, + NUM_VS_THREADS_shift, NUM_VS_THREADS_mask); + SETfield(sq_thread_resource_mgmt, num_gs_threads, + NUM_GS_THREADS_shift, NUM_GS_THREADS_mask); + SETfield(sq_thread_resource_mgmt, num_es_threads, + NUM_ES_THREADS_shift, NUM_ES_THREADS_mask); + SETfield(sq_thread_resource_mgmt_2, num_hs_threads, + NUM_PS_THREADS_shift, NUM_PS_THREADS_mask); + SETfield(sq_thread_resource_mgmt_2, num_ls_threads, + NUM_VS_THREADS_shift, NUM_VS_THREADS_mask); + + SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries, + NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask); + SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries, + NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask); + SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries, + NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask); + SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries, + NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask); + SETfield(sq_stack_resource_mgmt_3, num_hs_stack_entries, + NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask); + SETfield(sq_stack_resource_mgmt_3, num_ls_stack_entries, + NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask); + + + BEGIN_BATCH_NO_AUTOSTATE(196); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); + //6 + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4); + R600_OUT_BATCH(sq_config); + R600_OUT_BATCH(sq_gpr_resource_mgmt_1); + R600_OUT_BATCH(sq_gpr_resource_mgmt_2); + R600_OUT_BATCH(sq_gpr_resource_mgmt_3); + //7 + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5); + R600_OUT_BATCH(sq_thread_resource_mgmt); + R600_OUT_BATCH(sq_thread_resource_mgmt_2); + R600_OUT_BATCH(sq_stack_resource_mgmt_1); + R600_OUT_BATCH(sq_stack_resource_mgmt_2); + R600_OUT_BATCH(sq_stack_resource_mgmt_3); + //3 + R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); + R600_OUT_BATCH(0x80000000); + R600_OUT_BATCH(0x80000000); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LDS_ALLOC_PS, 0); + //8 + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //6 + EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 4); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, 0); + //7 + EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5); + R600_OUT_BATCH(0x00000060); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0x0000002a); + R600_OUT_BATCH(0); + //4 + EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, 0x0000aa00); + //15 + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_CLIPRECT_RULE, 13); + R600_OUT_BATCH(0x0000ffff); + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(0x20002000); + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(0x20002000); + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(0x20002000); + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(0x20002000); + R600_OUT_BATCH(0xaaaaaaaa); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0x0000000f); + R600_OUT_BATCH(0x0000000f); + //4 + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0x3f800000); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, 0); + //4 + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //18 + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0x00000005); + R600_OUT_BATCH(0x3f800000); + R600_OUT_BATCH(0x3f800000); + R600_OUT_BATCH(0x3f800000); + R600_OUT_BATCH(0x3f800000); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0xffffffff); + //15 + EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR_CONTROL, 13); + R600_OUT_BATCH(0x00cc0010); + R600_OUT_BATCH(0x00000210); + R600_OUT_BATCH(0x00010000); + R600_OUT_BATCH(0x00000004); + R600_OUT_BATCH(0x00000100); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //8 + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //11 + EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 9); + R600_OUT_BATCH(0x00ffffff); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //4 + EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //4 + EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //19 + EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 17); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0x00000008); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_PRIMITIVEID_EN, 0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_MULTI_PRIM_IB_RESET_EN, 0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, 0); + //4 + EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, 0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_CONFIG, 0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_ID_0, 0); + //3 + EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_PS_INPUT_CNTL_0, 0); + //13 + EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_IN_CONTROL_0, 11); + R600_OUT_BATCH(0x20000001); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0x00100000); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + + END_BATCH(); + COMMIT_BATCH(); +} + +static GLboolean eg_validate_buffers(context_t *rmesa, + struct radeon_bo *src_bo, + struct radeon_bo *dst_bo) +{ + int ret; + + radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs); + + ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, + src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); + if (ret) + return GL_FALSE; + + ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, + dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT); + if (ret) + return GL_FALSE; + + ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, + rmesa->blit_bo, + RADEON_GEM_DOMAIN_GTT, 0); + if (ret) + return GL_FALSE; + + return GL_TRUE; +} + +unsigned evergreen_blit(GLcontext *ctx, + struct radeon_bo *src_bo, + intptr_t src_offset, + gl_format src_mesaformat, + unsigned src_pitch, + unsigned src_width, + unsigned src_height, + unsigned src_x, + unsigned src_y, + struct radeon_bo *dst_bo, + intptr_t dst_offset, + gl_format dst_mesaformat, + unsigned dst_pitch, + unsigned dst_width, + unsigned dst_height, + unsigned dst_x, + unsigned dst_y, + unsigned w, + unsigned h, + unsigned flip_y) +{ + context_t *context = EVERGREEN_CONTEXT(ctx); + int id = 0; + + if (!evergreen_check_blit(dst_mesaformat)) + return GL_FALSE; + + if (src_bo == dst_bo) { + return GL_FALSE; + } + + if (src_offset % 256 || dst_offset % 256) { + return GL_FALSE; + } + + if (0) { + fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n", + src_width, src_height, src_pitch, + _mesa_format_row_stride(src_mesaformat, src_width), + _mesa_get_format_name(src_mesaformat)); + fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n", + dst_width, dst_height, + _mesa_format_row_stride(dst_mesaformat, dst_width), + _mesa_get_format_name(dst_mesaformat)); + } + + /* Flush is needed to make sure that source buffer has correct data */ + radeonFlush(ctx); + + rcommonEnsureCmdBufSpace(&context->radeon, 327, __FUNCTION__); + + /* load shaders */ + eg_load_shaders(context->radeon.glCtx); + + if (!eg_validate_buffers(context, src_bo, dst_bo)) + return GL_FALSE; + + /* set clear state */ + /* 196 */ + eg_set_default_state(context); + + /* shaders */ + /* 34 */ + eg_set_shaders(context); + + /* src */ + /* 21 */ + eg_set_tex_resource(context, src_mesaformat, src_bo, + src_width, src_height, src_pitch, src_offset); + + /* 5 */ + eg_set_tex_sampler(context); + + /* dst */ + /* 19 */ + eg_set_render_target(context, dst_bo, dst_mesaformat, + dst_pitch, dst_width, dst_height, dst_offset); + /* scissors */ + /* 17 */ + eg_set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height); + + eg_set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y); + /* Vertex buffer setup */ + /* 18 */ + eg_set_vtx_resource(context); + + /* draw */ + /* 10 */ + eg_draw_auto(context); + + /* 7 */ + r700SyncSurf(context, dst_bo, 0, + RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT, + CB_ACTION_ENA_bit | (1 << (id + 6))); + + radeonFlush(ctx); + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/r600/evergreen_blit.h b/src/mesa/drivers/dri/r600/evergreen_blit.h new file mode 100644 index 0000000000..68d072ecb0 --- /dev/null +++ b/src/mesa/drivers/dri/r600/evergreen_blit.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef EVERGREEN_BLIT_H +#define EVERGREEN_BLIT_H + +unsigned evergreen_check_blit(gl_format mesa_format); + +unsigned evergreen_blit(GLcontext *ctx, + struct radeon_bo *src_bo, + intptr_t src_offset, + gl_format src_mesaformat, + unsigned src_pitch, + unsigned src_width, + unsigned src_height, + unsigned src_x_offset, + unsigned src_y_offset, + struct radeon_bo *dst_bo, + intptr_t dst_offset, + gl_format dst_mesaformat, + unsigned dst_pitch, + unsigned dst_width, + unsigned dst_height, + unsigned dst_x_offset, + unsigned dst_y_offset, + unsigned w, + unsigned h, + unsigned flip_y); + +#endif // EVERGREEN_BLIT_H diff --git a/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h b/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h new file mode 100644 index 0000000000..eb02528073 --- /dev/null +++ b/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +const uint32_t evergreen_vs[] = +{ + 0x00000004, + 0x80800400, + 0x0000a03c, + 0x95000688, + 0x00004000, + 0x15200688, + 0x00000000, + 0x00000000, + 0x3c000000, + 0x67961001, + 0x00080000, + 0x00000000, + 0x1c000000, + 0x67961000, + 0x00000008, + 0x00000000, +}; + +const uint32_t evergreen_ps[] = +{ + 0x00000003, + 0xa00c0000, + 0x00000008, + 0x80400000, + 0x00000000, + 0x95200688, + 0x00380400, + 0x00146b10, + 0x00380000, + 0x20146b10, + 0x00380400, + 0x40146b00, + 0x80380000, + 0x60146b00, + 0x00000000, + 0x00000000, + 0x00000010, + 0x000d1000, + 0xb0800000, + 0x00000000, +}; + diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c index f925f215bc..1050c776bf 100644 --- a/src/mesa/drivers/dri/r600/evergreen_chip.c +++ b/src/mesa/drivers/dri/r600/evergreen_chip.c @@ -60,7 +60,46 @@ do { \ insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \ } while (0) -/* +static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_query_object *query = radeon->query.current; + int count; + + if (!query || query->emitted_begin) + count = 0; + else + count = atom->cmd_size; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); + return count; +} + +static void evergreenSendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_query_object *query = radeon->query.current; + BATCH_LOCALS(radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); + + /* clear the buffer */ + radeon_bo_map(query->bo, GL_FALSE); + memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */ + radeon_bo_unmap(query->bo); + + radeon_cs_space_check_with_bo(radeon->cmdbuf.cs, + query->bo, + 0, RADEON_GEM_DOMAIN_GTT); + + BEGIN_BATCH_NO_AUTOSTATE(4 + 2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); + R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1)); + R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */ + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + query->emitted_begin = GL_TRUE; +} + static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ) { radeon->query.queryobj.cmd_size = (SZ); @@ -69,11 +108,11 @@ static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ) radeon->query.queryobj.idx = 0; radeon->query.queryobj.check = check_queryobj; radeon->query.queryobj.dirty = GL_FALSE; - radeon->query.queryobj.emit = r700SendQueryBegin; + radeon->query.queryobj.emit = evergreenSendQueryBegin; radeon->hw.max_state_size += (SZ); insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj); } -*/ + static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { @@ -107,7 +146,6 @@ static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom } if (bo) { - radeon_bo_unmap(bo); r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, @@ -118,7 +156,7 @@ static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom if( (1<<i) & vp->r700AsmCode.unVetTexBits ) { /* vs texture */ - R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE); } else { @@ -512,8 +550,9 @@ static void evergreenSendPSresource(GLcontext *ctx) context_t *context = EVERGREEN_CONTEXT(ctx); EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); struct radeon_bo * pbo; - - struct radeon_bo * pbo_const; + struct radeon_bo * pbo_const; + /* const size reg is in units of 16 consts */ + int const_size = ((evergreen->ps.num_consts * 4) + 15) & ~15; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); @@ -544,17 +583,8 @@ static void evergreenSendPSresource(GLcontext *ctx) { r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); - - if(evergreen->ps.num_consts < 4) - { - EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, 1); - } - else - { - EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, (evergreen->ps.num_consts * 4)/16 ); - } - + BEGIN_BATCH_NO_AUTOSTATE(3); + EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, const_size / 16); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(3 + 2); @@ -575,8 +605,9 @@ static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *at context_t *context = EVERGREEN_CONTEXT(ctx); EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); struct radeon_bo * pbo; - - struct radeon_bo * pbo_const; + struct radeon_bo * pbo_const; + /* const size reg is in units of 16 consts */ + int const_size = ((evergreen->vs.num_consts * 4) + 15) & ~15; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); @@ -608,17 +639,8 @@ static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *at { r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); - - if(evergreen->vs.num_consts < 4) - { - EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, 1); - } - else - { - EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, (evergreen->vs.num_consts * 4)/16 ); - } - + BEGIN_BATCH_NO_AUTOSTATE(3); + EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, const_size / 16); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(3 + 2); @@ -843,7 +865,7 @@ static void evergreenSetDepthTarget(context_t *context) { EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb) @@ -855,13 +877,24 @@ static void evergreenSetDepthTarget(context_t *context) evergreen->DB_DEPTH_SIZE.u32All = 0; + nPitchInPixel = rrb->pitch/rrb->cpp; + + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift, EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask); - SETfield(evergreen->DB_DEPTH_SIZE.u32All, (context->radeon.radeonScreen->driScreen->fbHeight/8)-1, + SETfield(evergreen->DB_DEPTH_SIZE.u32All, (height/8)-1, EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift, EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask); - evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1; + evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * height)/64 )-1; if(4 == rrb->cpp) { @@ -898,9 +931,6 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All); R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All); R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All); - /* - R600_OUT_BATCH(evergreen->DB_HTILE_DATA_BASE.u32All); - */ END_BATCH(); //4 @@ -943,6 +973,16 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) rrb = radeon_get_depthbuffer(&context->radeon); if( (rrb != NULL) && (rrb->bo != NULL) ) { + + /* make the hw happy */ + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All); + R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All, + rrb->bo, + evergreen->DB_HTILE_DATA_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0); + END_BATCH(); + //5 BEGIN_BATCH_NO_AUTOSTATE(3 + 2); EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All); @@ -1019,9 +1059,9 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) static void evergreenSetRenderTarget(context_t *context, int id) { EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); - + uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1; struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -1036,14 +1076,22 @@ static void evergreenSetRenderTarget(context_t *context, int id) /* pitch */ nPitchInPixel = rrb->pitch/rrb->cpp; + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1, EG_CB_COLOR0_PITCH__TILE_MAX_shift, EG_CB_COLOR0_PITCH__TILE_MAX_mask); - /* skice */ + /* slice */ SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All, - //( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, - ( (nPitchInPixel * 240)/64 )-1, + ( (nPitchInPixel * height)/64 )-1, EG_CB_COLOR0_SLICE__TILE_MAX_shift, EG_CB_COLOR0_SLICE__TILE_MAX_mask); @@ -1060,43 +1108,266 @@ static void evergreenSetRenderTarget(context_t *context, int id) ARRAY_LINEAR_GENERAL, EG_CB_COLOR0_INFO__ARRAY_MODE_shift, EG_CB_COLOR0_INFO__ARRAY_MODE_mask); - if(4 == rrb->cpp) - { - SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, - COLOR_8_8_8_8, - EG_CB_COLOR0_INFO__FORMAT_shift, - EG_CB_COLOR0_INFO__FORMAT_mask); - SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, - SWAP_ALT, //SWAP_STD - EG_CB_COLOR0_INFO__COMP_SWAP_shift, - EG_CB_COLOR0_INFO__COMP_SWAP_mask); - } - else - { - SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, - COLOR_5_6_5, - EG_CB_COLOR0_INFO__FORMAT_shift, - EG_CB_COLOR0_INFO__FORMAT_mask); - SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, - SWAP_ALT_REV, - EG_CB_COLOR0_INFO__COMP_SWAP_shift, - EG_CB_COLOR0_INFO__COMP_SWAP_mask); + + switch (rrb->base.Format) { + case MESA_FORMAT_RGBA8888: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_SIGNED_RGBA8888: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_SNORM; + source_format = 1; + break; + case MESA_FORMAT_RGBA8888_REV: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_SIGNED_RGBA8888_REV: + format = COLOR_8_8_8_8; + comp_swap = SWAP_STD; + number_type = NUMBER_SNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: + format = COLOR_8_8_8_8; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB8888_REV: + case MESA_FORMAT_XRGB8888_REV: + format = COLOR_8_8_8_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGB565: + format = COLOR_5_6_5; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGB565_REV: + format = COLOR_5_6_5; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB4444: + format = COLOR_4_4_4_4; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB4444_REV: + format = COLOR_4_4_4_4; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB1555: + format = COLOR_1_5_5_5; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_ARGB1555_REV: + format = COLOR_1_5_5_5; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_AL88: + format = COLOR_8_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_AL88_REV: + format = COLOR_8_8; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGB332: + format = COLOR_3_3_2; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_A8: + format = COLOR_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_I8: + case MESA_FORMAT_CI8: + format = COLOR_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_L8: + format = COLOR_8; + comp_swap = SWAP_ALT; + number_type = NUMBER_UNORM; + source_format = 1; + break; + case MESA_FORMAT_RGBA_FLOAT32: + format = COLOR_32_32_32_32_FLOAT; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_RGBA_FLOAT16: + format = COLOR_16_16_16_16_FLOAT; + comp_swap = SWAP_STD_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_ALPHA_FLOAT32: + format = COLOR_32_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_ALPHA_FLOAT16: + format = COLOR_16_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_FLOAT32: + format = COLOR_32_FLOAT; + comp_swap = SWAP_ALT; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_FLOAT16: + format = COLOR_16_FLOAT; + comp_swap = SWAP_ALT; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + format = COLOR_32_32_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + format = COLOR_16_16_FLOAT; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + format = COLOR_32_FLOAT; + comp_swap = SWAP_STD; + number_type = NUMBER_FLOAT; + source_format = 0; + break; + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + format = COLOR_16_FLOAT; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + source_format = 0; + break; + case MESA_FORMAT_X8_Z24: + case MESA_FORMAT_S8_Z24: + format = COLOR_8_24; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_Z24_S8: + format = COLOR_24_8; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_Z16: + format = COLOR_16; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_Z32: + format = COLOR_32; + comp_swap = SWAP_STD; + number_type = NUMBER_UNORM; + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + ARRAY_1D_TILED_THIN1, + EG_CB_COLOR0_INFO__ARRAY_MODE_shift, + EG_CB_COLOR0_INFO__ARRAY_MODE_mask); + source_format = 0; + break; + case MESA_FORMAT_SARGB8: + format = COLOR_8_8_8_8; + comp_swap = SWAP_ALT; + number_type = NUMBER_SRGB; + source_format = 1; + break; + case MESA_FORMAT_SLA8: + format = COLOR_8_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_SRGB; + source_format = 1; + break; + case MESA_FORMAT_SL8: + format = COLOR_8; + comp_swap = SWAP_ALT_REV; + number_type = NUMBER_SRGB; + source_format = 1; + break; + default: + _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()"); + break; } - SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, - 1, - EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift, + + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + format, + EG_CB_COLOR0_INFO__FORMAT_shift, + EG_CB_COLOR0_INFO__FORMAT_mask); + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + comp_swap, + EG_CB_COLOR0_INFO__COMP_SWAP_shift, + EG_CB_COLOR0_INFO__COMP_SWAP_mask); + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + number_type, + EG_CB_COLOR0_INFO__NUMBER_TYPE_shift, + EG_CB_COLOR0_INFO__NUMBER_TYPE_mask); + SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + source_format, + EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift, EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask); - SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All, + SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All, EG_CB_COLOR0_INFO__BLEND_CLAMP_bit); - SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, - NUMBER_UNORM, - EG_CB_COLOR0_INFO__NUMBER_TYPE_shift, - EG_CB_COLOR0_INFO__NUMBER_TYPE_mask); evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0; evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0; evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0; - evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0; + evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0; evergreen->render_target[id].enabled = GL_TRUE; } @@ -1162,37 +1433,22 @@ static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All); END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(5); - EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 3); + BEGIN_BATCH_NO_AUTOSTATE(6); + EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 4); R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All); R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All); R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All); + R600_OUT_BATCH(evergreen->CB_BLEND_ALPHA.u32All); END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(9); - EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND_ALPHA, evergreen->CB_BLEND_ALPHA.u32All); + BEGIN_BATCH_NO_AUTOSTATE(6); EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All); EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All); END_BATCH(); COMMIT_BATCH(); } -static void evergreenSendCP(GLcontext *ctx, struct radeon_state_atom *atom) -{ - context_t *context = EVERGREEN_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); - radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - - //first to send - //r700Start3D - BEGIN_BATCH_NO_AUTOSTATE(3); - R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); //IT_CONTEXT_CONTROL 0x28 - R600_OUT_BATCH(0x80000000); - R600_OUT_BATCH(0x80000000); - END_BATCH(); - COMMIT_BATCH(); -} static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = EVERGREEN_CONTEXT(ctx); @@ -1248,13 +1504,6 @@ static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void evergreenSendTIMESTAMP(GLcontext *ctx, struct radeon_state_atom *atom) -{ - context_t *context = EVERGREEN_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); - radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); -} - void evergreenInitAtoms(context_t *context) { radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context); @@ -1265,10 +1514,6 @@ void evergreenInitAtoms(context_t *context) context->radeon.hw.atomlist.name = "atom-list"; EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig); - - //make sure send first - EVERGREEN_ALLOC_STATE(cp, always, 3, evergreenSendCP); - EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX * 12)), evergreenSendVTX); EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA); EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP); @@ -1277,12 +1522,11 @@ void evergreenInitAtoms(context_t *context) EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI); EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX); EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */ - EVERGREEN_ALLOC_STATE(db, always, 60, evergreenSendDB); - EVERGREEN_ALLOC_STATE(cb, always, 35, evergreenSendCB); + EVERGREEN_ALLOC_STATE(db, always, 65, evergreenSendDB); + EVERGREEN_ALLOC_STATE(cb, always, 33, evergreenSendCB); EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT); - EVERGREEN_ALLOC_STATE(timestamp, always, 3, evergreenSendTIMESTAMP); - //evergreen_init_query_stateobj(&context->radeon, 6 * 2); + evergreen_init_query_stateobj(&context->radeon, 6 * 2); context->radeon.hw.is_dirty = GL_TRUE; context->radeon.hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/evergreen_context.c b/src/mesa/drivers/dri/r600/evergreen_context.c index 65b5898efa..fff7c20031 100644 --- a/src/mesa/drivers/dri/r600/evergreen_context.c +++ b/src/mesa/drivers/dri/r600/evergreen_context.c @@ -35,7 +35,9 @@ #include "radeon_common_context.h" #include "evergreen_context.h" #include "evergreen_state.h" -#include "r600_blit.h" +#include "evergreen_blit.h" +#include "r600_cmdbuf.h" +#include "radeon_queryobj.h" static void evergreen_get_lock(radeonContextPtr rmesa) { @@ -56,8 +58,7 @@ static void evergreen_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr static void evergreen_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - //TODO apr.01 - //r700Start3D((context_t *)radeon); + r700Start3D((context_t *)radeon); } static void evergreen_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) @@ -71,20 +72,19 @@ static void evergreen_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) static void evergreen_emit_query_finish(radeonContextPtr radeon) { - //TODO apr.01 - //context_t *context = (context_t*) radeon; - //BATCH_LOCALS(&context->radeon); + context_t *context = (context_t*) radeon; + BATCH_LOCALS(&context->radeon); struct radeon_query_object *query = radeon->query.current; - //BEGIN_BATCH_NO_AUTOSTATE(4 + 2); - //R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); - //R600_OUT_BATCH(ZPASS_DONE); - //R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */ - //R600_OUT_BATCH(0x00000000); - //R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); - //END_BATCH(); - //assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); + BEGIN_BATCH_NO_AUTOSTATE(4 + 2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); + R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1)); + R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */ + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); query->emitted_begin = GL_FALSE; } @@ -97,9 +97,9 @@ void evergreen_init_vtbl(radeonContextPtr radeon) radeon->vtbl.pre_emit_atoms = evergreen_vtbl_pre_emit_atoms; radeon->vtbl.fallback = evergreen_fallback; radeon->vtbl.emit_query_finish = evergreen_emit_query_finish; - radeon->vtbl.check_blit = r600_check_blit; - radeon->vtbl.blit = r600_blit; - radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; + radeon->vtbl.check_blit = evergreen_check_blit; + radeon->vtbl.blit = evergreen_blit; + radeon->vtbl.is_format_renderable = r600IsFormatRenderable; } diff --git a/src/mesa/drivers/dri/r600/evergreen_fragprog.c b/src/mesa/drivers/dri/r600/evergreen_fragprog.c index b53ff424a0..0e7edf4fbe 100644 --- a/src/mesa/drivers/dri/r600/evergreen_fragprog.c +++ b/src/mesa/drivers/dri/r600/evergreen_fragprog.c @@ -99,7 +99,6 @@ void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm, { unsigned int unBit; unsigned int i; - GLuint ui; /* match fp inputs with vp exports. */ struct evergreen_vertex_program_cont *vpc = @@ -246,12 +245,6 @@ void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->pR700Shader->depthIsExported = 1; } - pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); - for(ui=0; ui<pAsm->number_of_exports; ui++) - { - pAsm->pucOutMask[ui] = 0x0; - } - pAsm->flag_reg_index = pAsm->number_used_registers++; pAsm->uFirstHelpReg = pAsm->number_used_registers; @@ -755,6 +748,7 @@ GLboolean evergreenSetupFPconstants(GLcontext * ctx) struct gl_program_parameter_list *paramList; unsigned int unNumParamData; unsigned int ui; + int alloc_size; /* sent out shader constants. */ paramList = fp->mesa_program.Base.Parameters; @@ -778,14 +772,17 @@ GLboolean evergreenSetupFPconstants(GLcontext * ctx) evergreen->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; evergreen->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; } - + + /* alloc multiple of 16 constants */ + alloc_size = ((unNumParamData * 4 * 4) + 255) & ~255; + /* Load fp constants to gpu */ if(unNumParamData > 0) { radeonAllocDmaRegion(&context->radeon, &context->fp_Constbo, &context->fp_bo_offset, - 256, + alloc_size, 256); r600EmitShaderConsts(ctx, context->fp_Constbo, @@ -814,4 +811,7 @@ GLboolean evergreenSetupFPconstants(GLcontext * ctx) } unConstOffset += pCompiledSub->NumParameters; } -}
\ No newline at end of file + + return GL_TRUE; +} + diff --git a/src/mesa/drivers/dri/r600/evergreen_vertprog.c b/src/mesa/drivers/dri/r600/evergreen_vertprog.c index 4f3db00c7d..6840fa3c86 100644 --- a/src/mesa/drivers/dri/r600/evergreen_vertprog.c +++ b/src/mesa/drivers/dri/r600/evergreen_vertprog.c @@ -200,7 +200,6 @@ void evergreen_Map_Vertex_Program(GLcontext *ctx, struct evergreen_vertex_program *vp, struct gl_vertex_program *mesa_vp) { - GLuint ui; r700_AssemblerBase *pAsm = &(vp->r700AsmCode); unsigned int num_inputs; @@ -226,13 +225,6 @@ void evergreen_Map_Vertex_Program(GLcontext *ctx, pAsm->number_used_registers += pAsm->number_of_exports; - pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); - - for(ui=0; ui<pAsm->number_of_exports; ui++) - { - pAsm->pucOutMask[ui] = 0x0; - } - /* Map temporary registers (GPRs) */ pAsm->starting_temp_register_number = pAsm->number_used_registers; @@ -663,6 +655,7 @@ GLboolean evergreenSetupVPconstants(GLcontext * ctx) struct gl_program_parameter_list *paramList; unsigned int unNumParamData; unsigned int ui; + int alloc_size; /* sent out shader constants. */ paramList = vp->mesa_program->Base.Parameters; @@ -685,6 +678,9 @@ GLboolean evergreenSetupVPconstants(GLcontext * ctx) unNumParamData = paramList->NumParameters; + /* alloc multiple of 16 constants */ + alloc_size = ((unNumParamData * 4 * 4) + 255) & ~255; + for(ui=0; ui<unNumParamData; ui++) { if(paramList->Parameters[ui].Type == PROGRAM_UNIFORM) { @@ -705,7 +701,7 @@ GLboolean evergreenSetupVPconstants(GLcontext * ctx) radeonAllocDmaRegion(&context->radeon, &context->vp_Constbo, &context->vp_bo_offset, - 256, + alloc_size, 256); r600EmitShaderConsts(ctx, context->vp_Constbo, @@ -733,4 +729,7 @@ GLboolean evergreenSetupVPconstants(GLcontext * ctx) } unConstOffset += pCompiledSub->NumParameters; } -}
\ No newline at end of file + + return GL_TRUE; +} + diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c index ef47ae1c05..3090c9f613 100644 --- a/src/mesa/drivers/dri/r600/r600_blit.c +++ b/src/mesa/drivers/dri/r600/r600_blit.c @@ -224,14 +224,14 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma break; case MESA_FORMAT_RGBA_FLOAT32: format = COLOR_32_32_32_32_FLOAT; - comp_swap = SWAP_STD_REV; + comp_swap = SWAP_STD; SETbit(cb_color0_info, BLEND_FLOAT32_bit); CLEARbit(cb_color0_info, SOURCE_FORMAT_bit); SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask); break; case MESA_FORMAT_RGBA_FLOAT16: format = COLOR_16_16_16_16_FLOAT; - comp_swap = SWAP_STD_REV; + comp_swap = SWAP_STD; CLEARbit(cb_color0_info, SOURCE_FORMAT_bit); SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask); break; @@ -554,9 +554,9 @@ set_vtx_resource(context_t *context) R600_OUT_BATCH(0); R600_OUT_BATCH(0); R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift); - R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0, + R600_OUT_BATCH_RELOC(0, bo, - SQ_VTX_CONSTANT_WORD0_0, + 0, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); COMMIT_BATCH(); diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 801bb013f6..ffd6c8b092 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -105,6 +105,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R600_IT_ME_INITIALIZE 0x00004400 #define R600_IT_COND_WRITE 0x00004500 #define R600_IT_EVENT_WRITE 0x00004600 +# define R600_EVENT_TYPE(x) ((x) << 0) +# define R600_EVENT_INDEX(x) ((x) << 8) #define R600_IT_EVENT_WRITE_EOP 0x00004700 #define R600_IT_ONE_REG_WRITE 0x00005700 #define R600_IT_SET_CONFIG_REG 0x00006800 diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index bb959e7d2d..9c8fe2a24f 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/extensions.h" #include "main/bufferobj.h" #include "main/texobj.h" +#include "main/points.h" #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" @@ -227,7 +228,7 @@ static void r600_emit_query_finish(radeonContextPtr radeon) BEGIN_BATCH_NO_AUTOSTATE(4 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); - R600_OUT_BATCH(ZPASS_DONE); + R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1)); R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */ R600_OUT_BATCH(0x00000000); R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); @@ -337,6 +338,9 @@ static void r600ParseOptions(context_t *r600, radeonScreenPtr screen) static void r600InitGLExtensions(GLcontext *ctx) { context_t *r600 = R700_CONTEXT(ctx); +#ifdef R600_ENABLE_GLSL_TEST + unsigned i; +#endif driInitExtensions(ctx, card_extensions, GL_TRUE); if (r600->radeon.radeonScreen->kernel_mm) @@ -346,8 +350,9 @@ static void r600InitGLExtensions(GLcontext *ctx) driInitExtensions(ctx, gl_20_extension, GL_TRUE); _mesa_enable_2_0_extensions(ctx); - /* glsl compiler has problem if this is not GL_TRUE */ - ctx->Shader.EmitCondCodes = GL_TRUE; + /* glsl compiler has problem if this is not GL_TRUE */ + for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) + ctx->ShaderCompilerOptions[i].EmitCondCodes = GL_TRUE; #endif /* R600_ENABLE_GLSL_TEST */ if (driQueryOptionb @@ -455,6 +460,9 @@ GLboolean r600CreateContext(gl_api api, r600InitConstValues(ctx, screen); + /* reinit, it depends on consts above */ + _mesa_init_point(ctx); + _mesa_set_mvp_with_dp4( ctx, GL_TRUE ); /* Initialize the software rasterizer and helper modules. diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 45ff9c0624..2bf24096a0 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -619,7 +619,7 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 GLboolean IsTex(gl_inst_opcode Opcode) { if( (OPCODE_TEX==Opcode) || (OPCODE_TXP==Opcode) || (OPCODE_TXB==Opcode) || - (OPCODE_DDX==Opcode) || (OPCODE_DDY==Opcode) ) + (OPCODE_DDX==Opcode) || (OPCODE_DDY==Opcode) || (OPCODE_TXL==Opcode) ) { return GL_TRUE; } @@ -914,7 +914,7 @@ GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, { unsigned int count = GETbits(pAsm->cf_current_tex_clause_ptr->m_Word1.val, EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask) + 1; - SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, count, + SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, count, EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask); } else @@ -923,9 +923,10 @@ GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, } } - // If this clause constains any TEX instruction that is dependent on a previous instruction, - // set the barrier bit - if( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) || pAsm->need_tex_barrier == GL_TRUE ) + // If this clause constains any TEX instruction that is dependent on a + // previous instruction, set the barrier bit, also always set for vert + // programs as tex deps are not(yet) computed for them + if( pAsm->currentShaderType == SPT_VP || pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) || pAsm->need_tex_barrier == GL_TRUE ) { pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x1; } @@ -1413,17 +1414,6 @@ static GLboolean next_ins(r700_AssemblerBase *pAsm) if (pAsm->D.dst.rtype == DST_REG_OUT) { assert(pAsm->D.dst.reg >= pAsm->starting_export_register_number); - - if (pAsm->D.dst.op3) - { - // There is no mask for OP3 instructions, so all channels are written - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; - } - else - { - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] - |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; - } } //reset for next inst. @@ -1645,10 +1635,17 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, } else { + if (1 == pILInst->SrcReg[src].RelAddr) + { + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_RELATIVE_A0); + } + else + { + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); + } switch (pILInst->SrcReg[src].File) { case PROGRAM_TEMPORARY: - setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY; pAsm->S[fld].src.reg = pILInst->SrcReg[src].Index + pAsm->starting_temp_register_number; break; @@ -1657,15 +1654,6 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, case PROGRAM_ENV_PARAM: case PROGRAM_STATE_VAR: case PROGRAM_UNIFORM: - if (1 == pILInst->SrcReg[src].RelAddr) - { - setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_RELATIVE_A0); - } - else - { - setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); - } - pAsm->S[fld].src.rtype = SRC_REG_CONSTANT; if(pILInst->SrcReg[src].Index < 0) { @@ -1678,7 +1666,6 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, } break; case PROGRAM_INPUT: - setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); pAsm->S[fld].src.rtype = SRC_REG_GPR; switch (pAsm->currentShaderType) { @@ -1691,7 +1678,6 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, } break; case PROGRAM_OUTPUT: - setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); pAsm->S[fld].src.rtype = SRC_REG_GPR; switch (pAsm->currentShaderType) { @@ -1728,7 +1714,14 @@ GLboolean assemble_dst(r700_AssemblerBase *pAsm) switch (pILInst->DstReg.File) { case PROGRAM_TEMPORARY: + if (1 == pILInst->DstReg.RelAddr) + { + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_RELATIVE_A0); + } + else + { setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + } pAsm->D.dst.rtype = DST_REG_TEMPORARY; pAsm->D.dst.reg = pILInst->DstReg.Index + pAsm->starting_temp_register_number; break; @@ -1738,7 +1731,14 @@ GLboolean assemble_dst(r700_AssemblerBase *pAsm) pAsm->D.dst.reg = 0; break; case PROGRAM_OUTPUT: + if (1 == pILInst->DstReg.RelAddr) + { + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_RELATIVE_A0); + } + else + { setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + } pAsm->D.dst.rtype = DST_REG_OUT; switch (pAsm->currentShaderType) { @@ -3026,7 +3026,14 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) return GL_FALSE; } - alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype + if ( ADDR_RELATIVE_A0 == addrmode_PVSDST(&(pAsm->D.dst)) ) + { + alu_instruction_ptr->m_Word1.f.dst_rel = SQ_RELATIVE; + } + else + { + alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; + } if ( is_single_scalar_operation == GL_TRUE ) { @@ -3189,6 +3196,9 @@ GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode) return GL_FALSE; } + if( pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_RSQ ) + pAsm->S[0].src.abs = 1; + if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; @@ -4293,8 +4303,6 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) { unsigned int dstReg; unsigned int dstType; - unsigned int srcReg; - unsigned int srcType; checkop1(pAsm); int tmp = gethelpr(pAsm); @@ -4302,182 +4310,178 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) { return GL_FALSE; } - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; - } dstReg = pAsm->D.dst.reg; dstType = pAsm->D.dst.rtype; - srcReg = pAsm->S[0].src.reg; - srcType = pAsm->S[0].src.rtype; /* dst.xw, <- 1.0 */ - pAsm->D.dst.opcode = SQ_OP2_INST_MOV; - pAsm->D.dst.rtype = dstType; - pAsm->D.dst.reg = dstReg; - pAsm->D.dst.writex = 1; - pAsm->D.dst.writey = 0; - pAsm->D.dst.writez = 0; - pAsm->D.dst.writew = 1; - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_1; - pAsm->S[0].src.swizzley = SQ_SEL_1; - pAsm->S[0].src.swizzlez = SQ_SEL_1; - pAsm->S[0].src.swizzlew = SQ_SEL_1; - if( GL_FALSE == next_ins(pAsm) ) + if( pAsm->D.dst.writex || pAsm->D.dst.writew ) { - return GL_FALSE; - } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_1; + pAsm->S[0].src.swizzley = SQ_SEL_1; + pAsm->S[0].src.swizzlez = SQ_SEL_1; + pAsm->S[0].src.swizzlew = SQ_SEL_1; + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } } - /* dst.y = max(src.x, 0.0) */ - pAsm->D.dst.opcode = SQ_OP2_INST_MAX; - pAsm->D.dst.rtype = dstType; - pAsm->D.dst.reg = dstReg; - pAsm->D.dst.writex = 0; - pAsm->D.dst.writey = 1; - pAsm->D.dst.writez = 0; - pAsm->D.dst.writew = 0; - pAsm->S[0].src.rtype = srcType; - pAsm->S[0].src.reg = srcReg; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[1].src.reg = tmp; - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[1].src)); - pAsm->S[1].src.swizzlex = SQ_SEL_0; - pAsm->S[1].src.swizzley = SQ_SEL_0; - pAsm->S[1].src.swizzlez = SQ_SEL_0; - pAsm->S[1].src.swizzlew = SQ_SEL_0; - if( GL_FALSE == next_ins(pAsm) ) + if( GL_FALSE == assemble_dst(pAsm) ) { return GL_FALSE; } - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; - } + if( pAsm->D.dst.writey ) { - swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y); + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } - /* dst.z = log(src.y) */ - if(8 == pAsm->unAsic) - { - pAsm->D.dst.opcode = EG_OP2_INST_LOG_CLAMPED; - } - else - { - pAsm->D.dst.opcode = SQ_OP2_INST_LOG_CLAMPED; - } - pAsm->D.dst.math = 1; - pAsm->D.dst.rtype = dstType; - pAsm->D.dst.reg = dstReg; - pAsm->D.dst.writex = 0; - pAsm->D.dst.writey = 0; - pAsm->D.dst.writez = 1; - pAsm->D.dst.writew = 0; - pAsm->S[0].src.rtype = srcType; - pAsm->S[0].src.reg = srcReg; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; + /* dst.y = max(src.x, 0.0) */ + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_0; + pAsm->S[1].src.swizzley = SQ_SEL_0; + pAsm->S[1].src.swizzlez = SQ_SEL_0; + pAsm->S[1].src.swizzlew = SQ_SEL_0; + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } } - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + if( GL_FALSE == assemble_dst(pAsm) ) { return GL_FALSE; } + if ( pAsm->D.dst.writez) { - if( GL_FALSE == assemble_src(pAsm, 0, 2) ) - { - return GL_FALSE; - } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } - swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W); + /* dst.z = log(src.y) */ + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP2_INST_LOG_CLAMPED; + } + else + { + pAsm->D.dst.opcode = SQ_OP2_INST_LOG_CLAMPED; + } + pAsm->D.dst.math = 1; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 1; + pAsm->D.dst.writew = 0; + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y); + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } - swizzleagain_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } - /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */ - if(8 == pAsm->unAsic) - { - pAsm->D.dst.opcode = EG_OP3_INST_MUL_LIT; - } - else - { - pAsm->D.dst.opcode = SQ_OP3_INST_MUL_LIT; - } - pAsm->D.dst.math = 1; - pAsm->D.dst.op3 = 1; - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp; - pAsm->D.dst.writex = 1; - pAsm->D.dst.writey = 0; - pAsm->D.dst.writez = 0; - pAsm->D.dst.writew = 0; + if( GL_FALSE == assemble_src(pAsm, 0, 2) ) + { + return GL_FALSE; + } - pAsm->S[0].src.rtype = srcType; - pAsm->S[0].src.reg = srcReg; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[1].src.reg = dstReg; - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[1].src)); - pAsm->S[1].src.swizzlex = SQ_SEL_Z; - pAsm->S[1].src.swizzley = SQ_SEL_Z; - pAsm->S[1].src.swizzlez = SQ_SEL_Z; - pAsm->S[1].src.swizzlew = SQ_SEL_Z; + swizzleagain_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); - pAsm->S[2].src.rtype = srcType; - pAsm->S[2].src.reg = srcReg; - setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); + /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */ + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP3_INST_MUL_LIT; + } + else + { + pAsm->D.dst.opcode = SQ_OP3_INST_MUL_LIT; + } + pAsm->D.dst.math = 1; + pAsm->D.dst.op3 = 1; + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } - /* dst.z = exp(tmp.x) */ - if(8 == pAsm->unAsic) - { - pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE; - } - else - { - pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; - } - pAsm->D.dst.math = 1; - pAsm->D.dst.rtype = dstType; - pAsm->D.dst.reg = dstReg; - pAsm->D.dst.writex = 0; - pAsm->D.dst.writey = 0; - pAsm->D.dst.writez = 1; - pAsm->D.dst.writew = 0; + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = dstReg; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_Z; + pAsm->S[1].src.swizzley = SQ_SEL_Z; + pAsm->S[1].src.swizzlez = SQ_SEL_Z; + pAsm->S[1].src.swizzlew = SQ_SEL_Z; - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_X; - pAsm->S[0].src.swizzley = SQ_SEL_X; - pAsm->S[0].src.swizzlez = SQ_SEL_X; - pAsm->S[0].src.swizzlew = SQ_SEL_X; + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + /* dst.z = exp(tmp.x) */ + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + if(8 == pAsm->unAsic) + { + pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE; + } + else + { + pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; + } + pAsm->D.dst.math = 1; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 1; + pAsm->D.dst.writew = 0; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_X; + pAsm->S[0].src.swizzley = SQ_SEL_X; + pAsm->S[0].src.swizzlez = SQ_SEL_X; + pAsm->S[0].src.swizzlew = SQ_SEL_X; + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } return GL_TRUE; } @@ -5274,6 +5278,11 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->D.dst.opcode = SQ_TEX_INST_GET_GRADIENTS_V; break; case OPCODE_TXB: + /* this should actually be SAMPLE_LB but that needs bias to be + * embedded in the instruction - cant do here */ + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_L; + break; + case OPCODE_TXL: pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_L; break; default: @@ -7101,7 +7110,8 @@ GLboolean AssembleInstr(GLuint uiFirstInst, case OPCODE_DDX: case OPCODE_DDY: case OPCODE_TEX: - case OPCODE_TXB: + case OPCODE_TXB: + case OPCODE_TXL: case OPCODE_TXP: if ( GL_FALSE == assemble_TEX(pR700AsmCode) ) return GL_FALSE; @@ -7656,8 +7666,6 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, GLuint starting_register_number, GLboolean is_depth_export) { - unsigned char ucWriteMask; - check_current_clause(pAsm, CF_EMPTY_CLAUSE); check_current_clause(pAsm, CF_EXPORT_CLAUSE); //alloc the cf_current_export_clause_ptr @@ -7737,43 +7745,21 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, { assert(starting_register_number >= pAsm->starting_export_register_number); - ucWriteMask = pAsm->pucOutMask[starting_register_number - pAsm->starting_export_register_number]; /* exports Z as a float into Red channel */ if (GL_TRUE == is_depth_export) - ucWriteMask = 0x1; - - if( (ucWriteMask & 0x1) != 0) { - pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_X; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_Z; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_MASK; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_MASK; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_MASK; } else { - pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_MASK; - } - if( ((ucWriteMask>>1) & 0x1) != 0) - { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_X; pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_Y; - } - else - { - pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_MASK; - } - if( ((ucWriteMask>>2) & 0x1) != 0) - { pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_Z; - } - else - { - pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_MASK; - } - if( ((ucWriteMask>>3) & 0x1) != 0) - { pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_W; } - else - { - pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_MASK; - } } else { @@ -7789,39 +7775,6 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, return GL_TRUE; } -GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm, BITS depth_channel_select) -{ - gl_inst_opcode Opcode_save = pAsm->pILInst[pAsm->uiCurInst].Opcode; //Should be OPCODE_END - pAsm->pILInst[pAsm->uiCurInst].Opcode = OPCODE_MOV; - - // MOV depth_export_register.hw_depth_channel, depth_export_register.depth_channel_select - - pAsm->D.dst.opcode = SQ_OP2_INST_MOV; - - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = pAsm->depth_export_register_number; - - pAsm->D.dst.writex = 1; // depth goes in R channel for HW - - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = DST_REG_TEMPORARY; - pAsm->S[0].src.reg = pAsm->depth_export_register_number; - - setswizzle_PVSSRC(&(pAsm->S[0].src), depth_channel_select); - - noneg_PVSSRC(&(pAsm->S[0].src)); - - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } - - pAsm->pILInst[pAsm->uiCurInst].Opcode = Opcode_save; - - return GL_TRUE; -} - GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten) { @@ -7829,14 +7782,6 @@ GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLuint export_count = 0; unsigned int i; - if(pR700AsmCode->depth_export_register_number >= 0) - { - if( GL_FALSE == Move_Depth_Exports_To_Correct_Channels(pR700AsmCode, SQ_SEL_Z) ) // depth - { - return GL_FALSE; - } - } - for (i = 0; i < FRAG_RESULT_MAX; ++i) { unBit = 1 << i; @@ -8073,21 +8018,27 @@ GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode) { - FREE(pR700AsmCode->pucOutMask); - FREE(pR700AsmCode->pInstDeps); + if(NULL != pR700AsmCode->pInstDeps) + { + FREE(pR700AsmCode->pInstDeps); + pR700AsmCode->pInstDeps = NULL; + } if(NULL != pR700AsmCode->subs) { FREE(pR700AsmCode->subs); + pR700AsmCode->subs = NULL; } if(NULL != pR700AsmCode->callers) { FREE(pR700AsmCode->callers); + pR700AsmCode->callers = NULL; } if(NULL != pR700AsmCode->presubs) { FREE(pR700AsmCode->presubs); + pR700AsmCode->presubs = NULL; } return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index d357b0e3ec..c7c7ab2d4f 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -414,8 +414,6 @@ typedef struct r700_AssemblerBase unsigned char ucVP_AttributeMap[VERT_ATTRIB_MAX]; unsigned char ucVP_OutputMap[VERT_RESULT_MAX]; - unsigned char * pucOutMask; - //----------------------------------------------------------------------------------- // flow control members //----------------------------------------------------------------------------------- diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 71f1af7562..3bb194eb6d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -270,7 +270,7 @@ static void r700SetRenderTarget(context_t *context, int id) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM; struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -283,9 +283,19 @@ static void r700SetRenderTarget(context_t *context, int id) r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256; nPitchInPixel = rrb->pitch/rrb->cpp; + + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, @@ -544,7 +554,7 @@ static void r700SetDepthTarget(context_t *context) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb) @@ -560,9 +570,18 @@ static void r700SetDepthTarget(context_t *context) nPitchInPixel = rrb->pitch/rrb->cpp; + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ if(4 == rrb->cpp) @@ -1416,7 +1435,7 @@ static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom) BEGIN_BATCH_NO_AUTOSTATE(4 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); - R600_OUT_BATCH(ZPASS_DONE); + R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1)); R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */ R600_OUT_BATCH(0x00000000); R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index ebf1840a79..0ca237b1fe 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -38,7 +38,7 @@ #include "r700_chipoffset.h" -#define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | ((val) << (shift)) ) /* u32All */ +#define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | (((val) << (shift)) & (mask)) )/* u32All */ #define CLEARfield(x, mask) ( (x) &= ~(mask) ) #define SETbit(x, bit) ( (x) |= (bit) ) #define CLEARbit(x, bit) ( (x) &= ~(bit) ) diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 6fdd93a330..217b0e27a4 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -99,7 +99,6 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, { unsigned int unBit; unsigned int i; - GLuint ui; /* match fp inputs with vp exports. */ struct r700_vertex_program_cont *vpc = @@ -245,12 +244,6 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, } } - pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); - for(ui=0; ui<pAsm->number_of_exports; ui++) - { - pAsm->pucOutMask[ui] = 0x0; - } - pAsm->flag_reg_index = pAsm->number_used_registers++; pAsm->uFirstHelpReg = pAsm->number_used_registers; diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c index 67b0d40308..8b3ed5cd82 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.c +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -584,7 +584,11 @@ void cleanup_vfetch_shaderinst(R700_Shader *pShader) void Clean_Up_Shader(R700_Shader *pShader) { - FREE(pShader->pProgram); + if(NULL != pShader->pProgram) + { + FREE(pShader->pProgram); + pShader->pProgram = NULL; + } R700ShaderInstruction *pInst; R700ShaderInstruction *pInstToFree; @@ -596,6 +600,8 @@ void Clean_Up_Shader(R700_Shader *pShader) pInst = pInst->pNextInst; FREE(pInstToFree); }; + pShader->lstCFInstructions.pHead = NULL; + pInst = pShader->lstALUInstructions.pHead; while(NULL != pInst) { @@ -603,6 +609,8 @@ void Clean_Up_Shader(R700_Shader *pShader) pInst = pInst->pNextInst; FREE(pInstToFree); }; + pShader->lstALUInstructions.pHead = NULL; + pInst = pShader->lstTEXInstructions.pHead; while(NULL != pInst) { @@ -610,6 +618,8 @@ void Clean_Up_Shader(R700_Shader *pShader) pInst = pInst->pNextInst; FREE(pInstToFree); }; + pShader->lstTEXInstructions.pHead = NULL; + pInst = pShader->lstVTXInstructions.pHead; while(NULL != pInst) { @@ -617,5 +627,6 @@ void Clean_Up_Shader(R700_Shader *pShader) pInst = pInst->pNextInst; FREE(pInstToFree); }; + pShader->lstVTXInstructions.pHead = NULL; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 7ed4b7d238..2fee5b4433 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -201,7 +201,6 @@ void Map_Vertex_Program(GLcontext *ctx, struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp) { - GLuint ui; r700_AssemblerBase *pAsm = &(vp->r700AsmCode); unsigned int num_inputs; @@ -227,13 +226,6 @@ void Map_Vertex_Program(GLcontext *ctx, pAsm->number_used_registers += pAsm->number_of_exports; - pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); - - for(ui=0; ui<pAsm->number_of_exports; ui++) - { - pAsm->pucOutMask[ui] = 0x0; - } - /* Map temporary registers (GPRs) */ pAsm->starting_temp_register_number = pAsm->number_used_registers; diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 19df62742e..93219e40af 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -14,6 +14,7 @@ endif RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ + radeon_buffer_objects.c \ radeon_common_context.c \ radeon_common.c \ radeon_cs_legacy.c \ diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 07f7cba354..b0340cee21 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -363,6 +363,9 @@ GLboolean radeonUnbindContext(__DRIcontext * driContextPriv) fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); + /* Unset current context and dispath table */ + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c index fb741173ca..216eb932db 100644 --- a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c +++ b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c @@ -32,6 +32,7 @@ #include "main/state.h" #include "swrast/swrast.h" +#include "radeon_buffer_objects.h" #include "radeon_common_context.h" #include "radeon_debug.h" #include "radeon_mipmap_tree.h" @@ -96,6 +97,7 @@ do_blit_readpixels(GLcontext * ctx, unsigned dst_rowstride, dst_imagesize, aligned_rowstride, flip_y; struct radeon_bo *dst_buffer; GLint dst_x = 0, dst_y = 0; + intptr_t dst_offset; /* It's not worth if number of pixels to copy is really small */ if (width * height < 100) { @@ -127,10 +129,23 @@ do_blit_readpixels(GLcontext * ctx, assert(x >= 0 && y >= 0); aligned_rowstride = get_texture_image_row_stride(radeon, dst_format, dst_rowstride, 0); + dst_rowstride *= _mesa_get_format_bytes(dst_format); + if (_mesa_is_bufferobj(pack->BufferObj) && aligned_rowstride != dst_rowstride) + return GL_FALSE; dst_imagesize = get_texture_image_size(dst_format, aligned_rowstride, height, 1, 0); - dst_buffer = radeon_bo_open(radeon->radeonScreen->bom, 0, dst_imagesize, 1024, RADEON_GEM_DOMAIN_GTT, 0); + + if (!_mesa_is_bufferobj(pack->BufferObj)) + { + dst_buffer = radeon_bo_open(radeon->radeonScreen->bom, 0, dst_imagesize, 1024, RADEON_GEM_DOMAIN_GTT, 0); + dst_offset = 0; + } + else + { + dst_buffer = get_radeon_buffer_object(pack->BufferObj)->bo; + dst_offset = (intptr_t)pixels; + } /* Disable source Y flipping for FBOs */ flip_y = (ctx->ReadBuffer->Name == 0); @@ -149,7 +164,7 @@ do_blit_readpixels(GLcontext * ctx, x, y, dst_buffer, - 0, /* dst_offset */ + dst_offset, dst_format, aligned_rowstride / _mesa_get_format_bytes(dst_format), width, @@ -160,17 +175,22 @@ do_blit_readpixels(GLcontext * ctx, height, flip_y)) { - radeon_bo_map(dst_buffer, 0); - dst_rowstride *= _mesa_get_format_bytes(dst_format); - copy_rows(pixels, dst_rowstride, dst_buffer->ptr, - aligned_rowstride, height, dst_rowstride); - radeon_bo_unmap(dst_buffer); - radeon_bo_unref(dst_buffer); + if (!_mesa_is_bufferobj(pack->BufferObj)) + { + radeon_bo_map(dst_buffer, 0); + copy_rows(pixels, dst_rowstride, dst_buffer->ptr, + aligned_rowstride, height, dst_rowstride); + radeon_bo_unmap(dst_buffer); + radeon_bo_unref(dst_buffer); + } + return GL_TRUE; - } else { - radeon_bo_unref(dst_buffer); - return GL_FALSE; } + + if (!_mesa_is_bufferobj(pack->BufferObj)) + radeon_bo_unref(dst_buffer); + + return GL_FALSE; } void diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c index ab6d02e56b..5b7178bcca 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c @@ -56,7 +56,7 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) * hw writes zpass end counts to qwords 1, 3, 5, 7. * then we substract. MSB is the valid bit. */ - for (i = 0; i < 16; i += 4) { + for (i = 0; i < 32; i += 4) { uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) | (uint64_t)LE32_TO_CPU(result[i + 1]) << 32; uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) | diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c index f3903c2e38..ff53ffd0de 100644 --- a/src/mesa/drivers/dri/swrast/swrast.c +++ b/src/mesa/drivers/dri/swrast/swrast.c @@ -713,6 +713,10 @@ dri_unbind_context(__DRIcontext * cPriv) { TRACE; (void) cPriv; + + /* Unset current context and dispath table */ + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; } |