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-rw-r--r--src/mesa/drivers/dri/i915/i830_texstate.c6
-rw-r--r--src/mesa/drivers/dri/i915/i915_tex_layout.c27
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c23
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c84
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.h3
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_copy.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_image.c4
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.c14
11 files changed, 47 insertions, 122 deletions
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index e8f7e378ec..a28073919c 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -146,15 +146,15 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
dri_bo_reference(intelObj->mt->region->buffer);
i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
+ pitch = intelObj->mt->region->pitch * intelObj->mt->cpp;
+
/* XXX: This calculation is probably broken for tiled images with
* a non-page-aligned offset.
*/
- i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) *
- intelObj->mt->cpp;
+ i830->state.tex_offset[unit] = dst_x * intelObj->mt->cpp + dst_y * pitch;
format = translate_texture_format(firstImage->TexFormat,
firstImage->InternalFormat);
- pitch = intelObj->mt->pitch * intelObj->mt->cpp;
state[I830_TEXREG_TM0LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
(LOAD_TEXTURE_MAP0 << unit) | 4);
diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index fe3908f580..702655283b 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -123,13 +123,12 @@ i915_miptree_layout_cube(struct intel_context *intel,
assert(lvlWidth == lvlHeight); /* cubemap images are square */
/* double pitch for cube layouts */
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, dim * 2);
+ mt->total_width = dim * 2;
mt->total_height = dim * 4;
for (level = mt->first_level; level <= mt->last_level; level++) {
intel_miptree_set_level_info(mt, level, 6,
0, 0,
- /*OLD: mt->pitch, mt->total_height,*/
lvlWidth, lvlHeight,
1);
lvlWidth /= 2;
@@ -167,7 +166,7 @@ i915_miptree_layout_3d(struct intel_context *intel,
GLint level;
/* Calculate the size of a single slice. */
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+ mt->total_width = mt->width0;
/* XXX: hardware expects/requires 9 levels at minimum. */
for (level = mt->first_level; level <= MAX2(8, mt->last_level); level++) {
@@ -210,7 +209,7 @@ i915_miptree_layout_2d(struct intel_context *intel,
GLuint img_height;
GLint level;
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+ mt->total_width = mt->width0;
mt->total_height = 0;
for (level = mt->first_level; level <= mt->last_level; level++) {
@@ -251,9 +250,8 @@ i915_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
break;
}
- DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
- mt->pitch,
- mt->total_height, mt->cpp, mt->pitch * mt->total_height * mt->cpp);
+ DBG("%s: %dx%dx%d\n", __FUNCTION__,
+ mt->total_width, mt->total_height, mt->cpp);
return GL_TRUE;
}
@@ -336,9 +334,9 @@ i945_miptree_layout_cube(struct intel_context *intel,
* or the final row of 4x4, 2x2 and 1x1 faces below this.
*/
if (dim > 32)
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, dim * 2);
+ mt->total_width = dim * 2;
else
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, 14 * 8);
+ mt->total_width = 14 * 8;
if (dim >= 4)
mt->total_height = dim * 4 + 4;
@@ -423,11 +421,11 @@ i945_miptree_layout_3d(struct intel_context *intel,
GLuint pack_y_pitch;
GLuint level;
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+ mt->total_width = mt->width0;
mt->total_height = 0;
pack_y_pitch = MAX2(mt->height0, 2);
- pack_x_pitch = mt->pitch;
+ pack_x_pitch = mt->total_width;
pack_x_nr = 1;
for (level = mt->first_level; level <= mt->last_level; level++) {
@@ -454,7 +452,7 @@ i945_miptree_layout_3d(struct intel_context *intel,
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
pack_x_nr <<= 1;
- assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+ assert(pack_x_pitch * pack_x_nr <= mt->total_width);
}
if (pack_y_pitch > 2) {
@@ -491,9 +489,8 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
break;
}
- DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
- mt->pitch,
- mt->total_height, mt->cpp, mt->pitch * mt->total_height * mt->cpp);
+ DBG("%s: %dx%dx%d\n", __FUNCTION__,
+ mt->total_width, mt->total_height, mt->cpp);
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index a1ab8f8b6d..ff9ab88c5a 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -165,7 +165,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
format = translate_texture_format(firstImage->TexFormat,
firstImage->InternalFormat,
tObj->DepthMode);
- pitch = intelObj->mt->pitch * intelObj->mt->cpp;
+ pitch = intelObj->mt->region->pitch * intelObj->mt->cpp;
state[I915_TEXREG_MS3] =
(((firstImage->Height - 1) << MS3_HEIGHT_SHIFT) |
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 09edfd81fd..b1f56a8e64 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -58,12 +58,12 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
GLuint qpitch = 0;
GLuint y_pitch = 0;
- mt->pitch = mt->width0;
+ mt->total_width = mt->width0;
intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
y_pitch = ALIGN(height, align_h);
if (mt->compressed) {
- mt->pitch = ALIGN(mt->width0, align_w);
+ mt->total_width = ALIGN(mt->width0, align_w);
}
if (mt->first_level != mt->last_level) {
@@ -77,13 +77,11 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
+ minify(minify(mt->width0));
}
- if (mip1_width > mt->pitch) {
- mt->pitch = mip1_width;
+ if (mip1_width > mt->total_width) {
+ mt->total_width = mip1_width;
}
}
- mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
-
if (mt->compressed) {
qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4;
mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
@@ -137,10 +135,10 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
if (mt->compressed) {
- mt->pitch = ALIGN(width, align_w);
+ mt->total_width = ALIGN(width, align_w);
pack_y_pitch = (height + 3) / 4;
} else {
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+ mt->total_width = mt->width0;
pack_y_pitch = ALIGN(mt->height0, align_h);
}
@@ -184,7 +182,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
pack_x_nr <<= 1;
- assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+ assert(pack_x_pitch * pack_x_nr <= mt->total_width);
}
if (pack_y_pitch > 2) {
@@ -211,11 +209,8 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
i945_miptree_layout_2d(intel, mt, tiling);
break;
}
- DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
- mt->pitch,
- mt->total_height,
- mt->cpp,
- mt->pitch * mt->total_height * mt->cpp );
+ DBG("%s: %dx%dx%d\n", __FUNCTION__,
+ mt->total_width, mt->total_height, mt->cpp);
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ce0bf0b97d..6b9e566886 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -261,7 +261,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
key.format = firstImage->TexFormat;
key.internal_format = firstImage->InternalFormat;
- key.pitch = intelObj->mt->pitch;
+ key.pitch = intelObj->mt->region->pitch;
key.depth = firstImage->Depth;
key.bo = intelObj->mt->region->buffer;
key.offset = 0;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index ba3bb8fdba..8278d12bb9 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -568,7 +568,7 @@ intel_render_texture(GLcontext * ctx,
att->Zoffset,
&dst_x, &dst_y);
- intel_image->mt->region->draw_offset = (dst_y * intel_image->mt->pitch +
+ intel_image->mt->region->draw_offset = (dst_y * intel_image->mt->region->pitch +
dst_x) * intel_image->mt->cpp;
intel_image->mt->region->draw_x = dst_x;
intel_image->mt->region->draw_y = dst_y;
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index e02b188e35..e671355c38 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -83,7 +83,6 @@ intel_miptree_create_internal(struct intel_context *intel,
mt->cpp = compress_byte ? compress_byte : cpp;
mt->compressed = compress_byte ? 1 : 0;
mt->refcount = 1;
- mt->pitch = 0;
#ifdef I915
if (intel->is_945)
@@ -136,7 +135,7 @@ intel_miptree_create(struct intel_context *intel,
/*
* pitch == 0 || height == 0 indicates the null texture
*/
- if (!mt || !mt->pitch || !mt->total_height) {
+ if (!mt || !mt->total_height) {
free(mt);
return NULL;
}
@@ -144,10 +143,9 @@ intel_miptree_create(struct intel_context *intel,
mt->region = intel_region_alloc(intel,
tiling,
mt->cpp,
- mt->pitch,
+ mt->total_width,
mt->total_height,
expect_accelerated_upload);
- mt->pitch = mt->region->pitch;
if (!mt->region) {
free(mt);
@@ -178,71 +176,11 @@ intel_miptree_create_for_region(struct intel_context *intel,
if (!mt)
return mt;
- /* The mipmap tree pitch is aligned to 64 bytes to make sure render
- * to texture works, but we don't need that for texturing from a
- * pixmap. Just override it here. */
- mt->pitch = region->pitch;
-
intel_region_reference(&mt->region, region);
return mt;
}
-
-/**
- * intel_miptree_pitch_align:
- *
- * @intel: intel context pointer
- *
- * @mt: the miptree to compute pitch alignment for
- *
- * @pitch: the natural pitch value
- *
- * Given @pitch, compute a larger value which accounts for
- * any necessary alignment required by the device
- */
-int intel_miptree_pitch_align (struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- uint32_t tiling,
- int pitch)
-{
-#ifdef I915
- GLcontext *ctx = &intel->ctx;
-#endif
-
- if (!mt->compressed) {
- int pitch_align;
-
- /* XXX: Align pitch to multiple of 64 bytes for now to allow
- * render-to-texture to work in all cases. This should probably be
- * replaced at some point by some scheme to only do this when really
- * necessary.
- */
- pitch_align = 64;
-
- if (tiling == I915_TILING_X)
- pitch_align = 512;
- else if (tiling == I915_TILING_Y)
- pitch_align = 128;
-
- pitch = ALIGN(pitch * mt->cpp, pitch_align);
-
-#ifdef I915
- /* Do a little adjustment to linear allocations so that we avoid
- * hitting the same channel of memory for 2 different pages when
- * reading a 2x2 subspan or doing bilinear filtering.
- */
- if (tiling == I915_TILING_NONE && !(pitch & 511) &&
- (pitch + pitch_align) < (1 << ctx->Const.MaxTextureLevels))
- pitch += pitch_align;
-#endif
-
- pitch /= mt->cpp;
- }
- return pitch;
-}
-
-
void
intel_miptree_reference(struct intel_mipmap_tree **dst,
struct intel_mipmap_tree *src)
@@ -414,7 +352,7 @@ intel_miptree_image_map(struct intel_context * intel,
DBG("%s \n", __FUNCTION__);
if (row_stride)
- *row_stride = mt->pitch * mt->cpp;
+ *row_stride = mt->region->pitch * mt->cpp;
if (mt->target == GL_TEXTURE_3D) {
int i;
@@ -423,7 +361,7 @@ intel_miptree_image_map(struct intel_context * intel,
intel_miptree_get_image_offset(mt, level, face, i,
&x, &y);
- image_offsets[i] = x + y * mt->pitch;
+ image_offsets[i] = x + y * mt->region->pitch;
}
return intel_region_map(intel, mt->region);
@@ -434,7 +372,7 @@ intel_miptree_image_map(struct intel_context * intel,
image_offsets[0] = 0;
return intel_region_map(intel, mt->region) +
- (x + y * mt->pitch) * mt->cpp;
+ (x + y * mt->region->pitch) * mt->cpp;
}
}
@@ -524,13 +462,13 @@ intel_miptree_image_copy(struct intel_context *intel,
src_ptr = intel_region_map(intel, src->region);
dst_ptr = intel_region_map(intel, dst->region);
- _mesa_copy_rect(dst_ptr + dst->cpp * (dst_x + dst_y * dst->pitch),
+ _mesa_copy_rect(dst_ptr,
dst->cpp,
- dst->pitch,
- 0, 0, width, height,
- src_ptr + src->cpp * (src_x + src_y * src->pitch),
- src->pitch,
- 0, 0);
+ dst->region->pitch,
+ dst_x, dst_y, width, height,
+ src_ptr,
+ src->region->pitch,
+ src_x, src_y);
intel_region_unmap(intel, src->region);
intel_region_unmap(intel, dst->region);
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 7f3468f115..21db2f4d3b 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -102,8 +102,7 @@ struct intel_mipmap_tree
/* Derived from the above:
*/
- GLuint pitch;
- GLuint depth_pitch; /* per-image on i945? */
+ GLuint total_width;
GLuint total_height;
/* Includes image offset tables:
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 13b8bcfa86..618f690a5f 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -155,7 +155,7 @@ do_copy_texsubimage(struct intel_context *intel,
src->buffer,
0,
src->tiling,
- intelImage->mt->pitch,
+ intelImage->mt->region->pitch,
dst_bo,
0,
intelImage->mt->region->tiling,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index bac36eeb56..9db96acdc0 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -236,7 +236,7 @@ try_pbo_upload(struct intel_context *intel,
intelImage->face, 0,
&dst_x, &dst_y);
- dst_stride = intelImage->mt->pitch;
+ dst_stride = intelImage->mt->region->pitch;
if (drm_intel_bo_references(intel->batch->buf, dst_buffer))
intelFlush(&intel->ctx);
@@ -290,7 +290,7 @@ try_pbo_zcopy(struct intel_context *intel,
intelImage->face, 0,
&dst_x, &dst_y);
- dst_stride = intelImage->mt->pitch;
+ dst_stride = intelImage->mt->region->pitch;
if (src_stride != dst_stride || dst_x != 0 || dst_y != 0 ||
src_offset != 0) {
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 7d69ea4484..d132e19e83 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -74,14 +74,14 @@ void i945_miptree_layout_2d( struct intel_context *intel,
GLuint width = mt->width0;
GLuint height = mt->height0;
- mt->pitch = mt->width0;
+ mt->total_width = mt->width0;
intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
if (mt->compressed) {
- mt->pitch = ALIGN(mt->width0, align_w);
+ mt->total_width = ALIGN(mt->width0, align_w);
}
- /* May need to adjust pitch to accomodate the placement of
+ /* May need to adjust width to accomodate the placement of
* the 2nd mipmap. This occurs when the alignment
* constraints of mipmap placement push the right edge of the
* 2nd mipmap out past the width of its parent.
@@ -97,15 +97,11 @@ void i945_miptree_layout_2d( struct intel_context *intel,
+ minify(minify(mt->width0));
}
- if (mip1_width > mt->pitch) {
- mt->pitch = mip1_width;
+ if (mip1_width > mt->total_width) {
+ mt->total_width = mip1_width;
}
}
- /* Pitch must be a whole number of dwords, even though we
- * express it in texels.
- */
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->pitch);
mt->total_height = 0;
for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 11:15:19 +0000