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-rw-r--r--src/mesa/drivers/dri/common/dri_util.c11
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.h1
-rw-r--r--src/mesa/drivers/dri/i915/i915_state.c32
-rw-r--r--src/mesa/drivers/dri/intel/intel_buffer_objects.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_dma.c9
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_lock.c9
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c85
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h10
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_texture.c56
-rw-r--r--src/mesa/drivers/dri/swrast/swrast_span.c72
10 files changed, 168 insertions, 119 deletions
diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
index e48e10d7c0..da81ec9de5 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -167,11 +167,12 @@ static int driBindContext(__DRIcontext *pcp,
__DRIdrawable *pdp,
__DRIdrawable *prp)
{
- __DRIscreenPrivate *psp = pcp->driScreenPriv;
+ __DRIscreenPrivate *psp;
/* Bind the drawable to the context */
if (pcp) {
+ psp = pcp->driScreenPriv;
pcp->driDrawablePriv = pdp;
pcp->driReadablePriv = prp;
if (pdp) {
@@ -498,11 +499,11 @@ static void dri_put_drawable(__DRIdrawable *pdp)
{
__DRIscreenPrivate *psp;
- pdp->refcount--;
- if (pdp->refcount)
- return;
-
if (pdp) {
+ pdp->refcount--;
+ if (pdp->refcount)
+ return;
+
psp = pdp->driScreenPriv;
(*psp->DriverAPI.DestroyBuffer)(pdp);
if (pdp->pClipRects) {
diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h
index 082d614442..25418d5f7a 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -39,6 +39,7 @@
#define I915_FALLBACK_LOGICOP 0x20000
#define I915_FALLBACK_POLYGON_SMOOTH 0x40000
#define I915_FALLBACK_POINT_SMOOTH 0x80000
+#define I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN 0x100000
#define I915_UPLOAD_CTX 0x1
#define I915_UPLOAD_BUFFERS 0x2
diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c
index b60efea75b..cc98d125db 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -585,7 +585,7 @@ i915PointSize(GLcontext * ctx, GLfloat size)
{
struct i915_context *i915 = I915_CONTEXT(ctx);
int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_POINT_WIDTH_MASK;
- GLint point_size = (int) size;
+ GLint point_size = (int) round(size);
DBG("%s\n", __FUNCTION__);
@@ -599,6 +599,24 @@ i915PointSize(GLcontext * ctx, GLfloat size)
}
+static void
+i915PointParameterfv(GLcontext * ctx, GLenum pname, const GLfloat *params)
+{
+ struct i915_context *i915 = I915_CONTEXT(ctx);
+
+ switch (pname) {
+ case GL_POINT_SPRITE_COORD_ORIGIN:
+ /* This could be supported, but it would require modifying the fragment
+ * program to invert the y component of the texture coordinate by
+ * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
+ */
+ FALLBACK(&i915->intel, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN,
+ (params[0] != GL_UPPER_LEFT));
+ break;
+ }
+}
+
+
/* =============================================================
* Color masks
*/
@@ -939,6 +957,17 @@ i915Enable(GLcontext * ctx, GLenum cap, GLboolean state)
case GL_POLYGON_SMOOTH:
break;
+ case GL_POINT_SPRITE:
+ /* This state change is handled in i915_reduced_primitive_state because
+ * the hardware bit should only be set when rendering points.
+ */
+ I915_STATECHANGE(i915, I915_UPLOAD_CTX);
+ if (state)
+ i915->state.Ctx[I915_CTXREG_LIS4] |= S4_SPRITE_POINT_ENABLE;
+ else
+ i915->state.Ctx[I915_CTXREG_LIS4] &= ~S4_SPRITE_POINT_ENABLE;
+ break;
+
case GL_POINT_SMOOTH:
break;
@@ -1108,6 +1137,7 @@ i915InitStateFunctions(struct dd_function_table *functions)
functions->LineWidth = i915LineWidth;
functions->LogicOpcode = i915LogicOp;
functions->PointSize = i915PointSize;
+ functions->PointParameterfv = i915PointParameterfv;
functions->PolygonStipple = i915PolygonStipple;
functions->Scissor = i915Scissor;
functions->ShadeModel = i915ShadeModel;
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 669becdab4..3b7015b5ad 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -268,6 +268,8 @@ intel_bufferobj_map(GLcontext * ctx,
if (intel_obj->sys_buffer) {
obj->Pointer = intel_obj->sys_buffer;
+ obj->Length = obj->Size;
+ obj->Offset = 0;
return obj->Pointer;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 89a99974e2..b8c65f4ce6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -205,6 +205,7 @@ again_alloc:
counter on unused buffers for later freeing them from
begin of list */
dma_bo = last_elem(&rmesa->dma.free);
+ assert(dma_bo->bo->cref == 1);
remove_from_list(dma_bo);
insert_at_head(&rmesa->dma.reserved, dma_bo);
}
@@ -301,10 +302,6 @@ static int radeon_bo_is_idle(struct radeon_bo* bo)
WARN_ONCE("Your libdrm or kernel doesn't have support for busy query.\n"
"This may cause small performance drop for you.\n");
}
- /* Protect against bug in legacy bo handling that causes bos stay
- * referenced even after they should be freed */
- if (bo->cref != 1)
- return 0;
return ret != -EBUSY;
}
@@ -341,9 +338,7 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa)
foreach_s(dma_bo, temp, &rmesa->dma.wait) {
if (dma_bo->expire_counter == time) {
WARN_ONCE("Leaking dma buffer object!\n");
- /* force free of buffer so we don't realy start
- * leaking stuff now*/
- while ((dma_bo->bo = radeon_bo_unref(dma_bo->bo))) {}
+ radeon_bo_unref(dma_bo->bo);
remove_from_list(dma_bo);
FREE(dma_bo);
continue;
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index 02de8e5fd1..7ad781ba61 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -62,8 +62,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
__DRIdrawablePrivate *const readable = radeon_get_readable(rmesa);
__DRIscreenPrivate *sPriv = rmesa->dri.screen;
- assert(drawable != NULL);
-
drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags);
/* The window might have moved, so we might need to get new clip
@@ -74,12 +72,13 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
* Since the hardware state depends on having the latest drawable
* clip rects, all state checking must be done _after_ this call.
*/
- DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable);
- if (drawable != readable) {
+ if (drawable)
+ DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable);
+ if (readable && drawable != readable) {
DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable);
}
- if (rmesa->lastStamp != drawable->lastStamp) {
+ if (drawable && (rmesa->lastStamp != drawable->lastStamp)) {
radeon_window_moved(rmesa);
rmesa->lastStamp = drawable->lastStamp;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index f2f7b2a9fd..bdbb9460bf 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -140,20 +140,19 @@ static GLuint minify(GLuint size, GLuint levels)
static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
{
- GLuint curOffset;
- GLuint i;
- GLuint face;
+ GLuint curOffset, i, face, level;
assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
curOffset = 0;
for(face = 0; face < mt->faces; face++) {
- for(i = 0; i < mt->numLevels; i++) {
- mt->levels[i].width = minify(mt->width0, i);
- mt->levels[i].height = minify(mt->height0, i);
- mt->levels[i].depth = minify(mt->depth0, i);
- compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
+ for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
+ mt->levels[level].valid = 1;
+ mt->levels[level].width = minify(mt->width0, i);
+ mt->levels[level].height = minify(mt->height0, i);
+ mt->levels[level].depth = minify(mt->depth0, i);
+ compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
}
}
@@ -163,21 +162,21 @@ static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_
static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
{
- GLuint curOffset;
- GLuint i;
+ GLuint curOffset, i, level;
assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
curOffset = 0;
- for(i = 0; i < mt->numLevels; i++) {
+ for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
GLuint face;
- mt->levels[i].width = minify(mt->width0, i);
- mt->levels[i].height = minify(mt->height0, i);
- mt->levels[i].depth = minify(mt->depth0, i);
+ mt->levels[level].valid = 1;
+ mt->levels[level].width = minify(mt->width0, i);
+ mt->levels[level].height = minify(mt->height0, i);
+ mt->levels[level].depth = minify(mt->depth0, i);
for(face = 0; face < mt->faces; face++)
- compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
+ compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
}
/* Note the required size in memory */
@@ -293,18 +292,19 @@ static void calculate_min_max_lod(struct gl_texture_object *tObj,
* given face and level.
*/
GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
- struct gl_texture_image *texImage, GLuint face, GLuint mtLevel)
+ struct gl_texture_image *texImage, GLuint face, GLuint level)
{
radeon_mipmap_level *lvl;
- if (face >= mt->faces || mtLevel > mt->numLevels)
+ if (face >= mt->faces)
return GL_FALSE;
if (texImage->TexFormat != mt->mesaFormat)
return GL_FALSE;
- lvl = &mt->levels[mtLevel];
- if (lvl->width != texImage->Width ||
+ lvl = &mt->levels[level];
+ if (!lvl->valid ||
+ lvl->width != texImage->Width ||
lvl->height != texImage->Height ||
lvl->depth != texImage->Depth)
return GL_FALSE;
@@ -410,38 +410,17 @@ radeon_miptree_image_offset(radeon_mipmap_tree *mt,
}
/**
- * Convert radeon miptree texture level to GL texture level
- * @param[in] tObj texture object whom level is to be converted
- * @param[in] level radeon miptree texture level
- * @return GL texture level
- */
-unsigned radeon_miptree_level_to_gl_level(struct gl_texture_object *tObj, unsigned level)
-{
- return level + tObj->BaseLevel;
-}
-
-/**
- * Convert GL texture level to radeon miptree texture level
- * @param[in] tObj texture object whom level is to be converted
- * @param[in] level GL texture level
- * @return radeon miptree texture level
- */
-unsigned radeon_gl_level_to_miptree_level(struct gl_texture_object *tObj, unsigned level)
-{
- return level - tObj->BaseLevel;
-}
-
-/**
* Ensure that the given image is stored in the given miptree from now on.
*/
static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
radeon_texture_image *image,
- int face, int mtLevel)
+ int face, int level)
{
- radeon_mipmap_level *dstlvl = &mt->levels[mtLevel];
+ radeon_mipmap_level *dstlvl = &mt->levels[level];
unsigned char *dest;
assert(image->mt != mt);
+ assert(dstlvl->valid);
assert(dstlvl->width == image->base.Width);
assert(dstlvl->height == image->base.Height);
assert(dstlvl->depth == image->base.Depth);
@@ -458,6 +437,7 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
+ assert(image->mtlevel == level);
assert(srclvl->size == dstlvl->size);
assert(srclvl->rowstride == dstlvl->rowstride);
@@ -495,7 +475,7 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
radeon_miptree_reference(mt, &image->mt);
image->mtface = face;
- image->mtlevel = mtLevel;
+ image->mtlevel = level;
}
/**
@@ -522,7 +502,7 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
if (!img)
break;
- if (!img->mt || !radeon_miptree_matches_texture(img->mt, &texObj->base))
+ if (!img->mt)
continue;
for (int i = 0; i < mtCount; ++i) {
@@ -533,8 +513,8 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
}
}
- if (!found) {
- mtSizes[mtCount] += img->mt->levels[img->mtlevel].size;
+ if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) {
+ mtSizes[mtCount] = img->mt->levels[img->mtlevel].size;
mts[mtCount] = img->mt;
mtCount++;
}
@@ -592,6 +572,11 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t
radeon_miptree_unreference(&t->mt);
radeon_try_alloc_miptree(rmesa, t);
dst_miptree = t->mt;
+ if (RADEON_DEBUG & RADEON_TEXTURE) {
+ fprintf(stderr, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__, t->mt);
+ }
+ } else if (RADEON_DEBUG & RADEON_TEXTURE) {
+ fprintf(stderr, "%s: Using miptree %p\n", __FUNCTION__, t->mt);
}
const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1;
@@ -610,7 +595,11 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t
if (RADEON_DEBUG & RADEON_TEXTURE) {
fprintf(stderr, "MIGRATING\n");
}
- migrate_image_to_miptree(dst_miptree, img, face, radeon_gl_level_to_miptree_level(texObj, level));
+ struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo;
+ if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) {
+ radeon_firevertices(rmesa);
+ }
+ migrate_image_to_miptree(dst_miptree, img, face, level);
} else if (RADEON_DEBUG & RADEON_TEXTURE) {
fprintf(stderr, "OK\n");
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index 28b8485095..a10649b5ae 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -44,6 +44,7 @@ struct _radeon_mipmap_level {
GLuint depth;
GLuint size; /** Size of each image, in bytes */
GLuint rowstride; /** in bytes */
+ GLuint valid;
radeon_mipmap_image faces[6];
};
@@ -70,9 +71,9 @@ struct _radeon_mipmap_tree {
GLuint baseLevel; /** gl_texture_object->baseLevel it was created for */
GLuint numLevels; /** Number of mip levels stored in this mipmap tree */
- GLuint width0; /** Width of firstLevel image */
- GLuint height0; /** Height of firstLevel image */
- GLuint depth0; /** Depth of firstLevel image */
+ GLuint width0; /** Width of baseLevel image */
+ GLuint height0; /** Height of baseLevel image */
+ GLuint depth0; /** Depth of baseLevel image */
GLuint tilebits; /** RADEON_TXO_xxx_TILE */
@@ -89,8 +90,5 @@ GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
GLuint face, GLuint level);
void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets);
-unsigned radeon_miptree_level_to_gl_level(struct gl_texture_object *tObj, unsigned level);
-unsigned radeon_gl_level_to_miptree_level(struct gl_texture_object *tObj, unsigned level);
-
uint32_t get_base_teximage_offset(radeonTexObj *texObj);
#endif /* __RADEON_MIPMAP_TREE_H_ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 1ee9e2792a..0390d376ba 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -509,6 +509,27 @@ gl_format radeonChooseTextureFormat(GLcontext * ctx,
return MESA_FORMAT_NONE; /* never get here */
}
+/** Check if given image is valid within current texture object.
+ */
+static int image_matches_texture_obj(struct gl_texture_object *texObj,
+ struct gl_texture_image *texImage,
+ unsigned level)
+{
+ const struct gl_texture_image *baseImage = texObj->Image[0][level];
+
+ if (level < texObj->BaseLevel || level > texObj->MaxLevel)
+ return 0;
+
+ const unsigned levelDiff = level - texObj->BaseLevel;
+ const unsigned refWidth = baseImage->Width >> levelDiff;
+ const unsigned refHeight = baseImage->Height >> levelDiff;
+ const unsigned refDepth = baseImage->Depth >> levelDiff;
+
+ return (texImage->Width == refWidth &&
+ texImage->Height == refHeight &&
+ texImage->Depth == refDepth);
+}
+
static void teximage_assign_miptree(radeonContextPtr rmesa,
struct gl_texture_object *texObj,
struct gl_texture_image *texImage,
@@ -518,18 +539,28 @@ static void teximage_assign_miptree(radeonContextPtr rmesa,
radeonTexObj *t = radeon_tex_obj(texObj);
radeon_texture_image* image = get_radeon_texture_image(texImage);
+ /* Since miptree holds only images for levels <BaseLevel..MaxLevel>
+ * don't allocate the miptree if the teximage won't fit.
+ */
+ if (!image_matches_texture_obj(texObj, texImage, level))
+ return;
+
/* Try using current miptree, or create new if there isn't any */
- if (!t->mt || !radeon_miptree_matches_image(t->mt, texImage, face,
- radeon_gl_level_to_miptree_level(texObj, level))) {
+ if (!t->mt || !radeon_miptree_matches_image(t->mt, texImage, face, level)) {
radeon_miptree_unreference(&t->mt);
radeon_try_alloc_miptree(rmesa, t);
+ if (RADEON_DEBUG & RADEON_TEXTURE) {
+ fprintf(stderr, "%s: texObj %p, texImage %p, face %d, level %d, "
+ "texObj miptree doesn't match, allocated new miptree %p\n",
+ __FUNCTION__, texObj, texImage, face, level, t->mt);
+ }
}
/* Miptree alocation may have failed,
* when there was no image for baselevel specified */
if (t->mt) {
image->mtface = face;
- image->mtlevel = radeon_gl_level_to_miptree_level(texObj, level);
+ image->mtlevel = level;
radeon_miptree_reference(t->mt, &image->mt);
}
}
@@ -585,6 +616,8 @@ static void radeon_store_teximage(GLcontext* ctx, int dims,
dstRowStride = _mesa_format_row_stride(texImage->TexFormat, texImage->Width);
}
+ assert(dstRowStride);
+
if (dims == 3) {
unsigned alignedWidth = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat);
dstImageOffsets = allocate_image_offsets(ctx, alignedWidth, texImage->Height, texImage->Depth);
@@ -670,6 +703,11 @@ static void radeon_teximage(
}
}
+ if (RADEON_DEBUG & RADEON_TEXTURE) {
+ fprintf(stderr, "radeon_teximage%dd: texObj %p, texImage %p, face %d, level %d\n",
+ dims, texObj, texImage, face, level);
+ }
+
t->validated = GL_FALSE;
if (ctx->_ImageTransferState & IMAGE_CONVOLUTION_BIT) {
@@ -694,12 +732,17 @@ static void radeon_teximage(
if (!t->bo) {
teximage_assign_miptree(rmesa, texObj, texImage, face, level);
- if (!t->mt) {
+ if (!image->mt) {
int size = _mesa_format_image_size(texImage->TexFormat,
texImage->Width,
texImage->Height,
texImage->Depth);
texImage->Data = _mesa_alloc_texmemory(size);
+ if (RADEON_DEBUG & RADEON_TEXTURE) {
+ fprintf(stderr, "radeon_teximage%dd: texObj %p, texImage %p, "
+ " no miptree assigned, using local memory %p\n",
+ dims, texObj, texImage, texImage->Data);
+ }
}
}
@@ -801,6 +844,11 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int leve
}
}
+ if (RADEON_DEBUG & RADEON_TEXTURE) {
+ fprintf(stderr, "radeon_texsubimage%dd: texObj %p, texImage %p, face %d, level %d\n",
+ dims, texObj, texImage, radeon_face_for_target(target), level);
+ }
+
t->validated = GL_FALSE;
if (compressed) {
pixels = _mesa_validate_pbo_compressed_teximage(
diff --git a/src/mesa/drivers/dri/swrast/swrast_span.c b/src/mesa/drivers/dri/swrast/swrast_span.c
index 2d3c25dcbe..f8e503463f 100644
--- a/src/mesa/drivers/dri/swrast/swrast_span.c
+++ b/src/mesa/drivers/dri/swrast/swrast_span.c
@@ -63,56 +63,42 @@ static const GLubyte kernel[16] = {
/* 32-bit BGRA */
#define STORE_PIXEL_A8R8G8B8(DST, X, Y, VALUE) \
- DST[3] = VALUE[ACOMP]; \
- DST[2] = VALUE[RCOMP]; \
- DST[1] = VALUE[GCOMP]; \
- DST[0] = VALUE[BCOMP]
+ *DST = VALUE[ACOMP] << 24 | VALUE[RCOMP] << 16 | VALUE[GCOMP] << 8 | VALUE[BCOMP]
#define STORE_PIXEL_RGB_A8R8G8B8(DST, X, Y, VALUE) \
- DST[3] = 0xff; \
- DST[2] = VALUE[RCOMP]; \
- DST[1] = VALUE[GCOMP]; \
- DST[0] = VALUE[BCOMP]
+ *DST = 0xff << 24 | VALUE[RCOMP] << 16 | VALUE[GCOMP] << 8 | VALUE[BCOMP]
#define FETCH_PIXEL_A8R8G8B8(DST, SRC) \
- DST[ACOMP] = SRC[3]; \
- DST[RCOMP] = SRC[2]; \
- DST[GCOMP] = SRC[1]; \
- DST[BCOMP] = SRC[0]
+ DST[ACOMP] = *SRC >> 24; \
+ DST[RCOMP] = (*SRC >> 16) & 0xff; \
+ DST[GCOMP] = (*SRC >> 8) & 0xff; \
+ DST[BCOMP] = *SRC & 0xff
/* 32-bit BGRX */
#define STORE_PIXEL_X8R8G8B8(DST, X, Y, VALUE) \
- DST[3] = 0xff; \
- DST[2] = VALUE[RCOMP]; \
- DST[1] = VALUE[GCOMP]; \
- DST[0] = VALUE[BCOMP]
+ *DST = 0xff << 24 | VALUE[RCOMP] << 16 | VALUE[GCOMP] << 8 | VALUE[BCOMP]
#define STORE_PIXEL_RGB_X8R8G8B8(DST, X, Y, VALUE) \
- DST[3] = 0xff; \
- DST[2] = VALUE[RCOMP]; \
- DST[1] = VALUE[GCOMP]; \
- DST[0] = VALUE[BCOMP]
+ *DST = 0xff << 24 | VALUE[RCOMP] << 16 | VALUE[GCOMP] << 8 | VALUE[BCOMP]
#define FETCH_PIXEL_X8R8G8B8(DST, SRC) \
- DST[ACOMP] = 0xff; \
- DST[RCOMP] = SRC[2]; \
- DST[GCOMP] = SRC[1]; \
- DST[BCOMP] = SRC[0]
+ DST[ACOMP] = 0xff; \
+ DST[RCOMP] = (*SRC >> 16) & 0xff; \
+ DST[GCOMP] = (*SRC >> 8) & 0xff; \
+ DST[BCOMP] = *SRC & 0xff
/* 16-bit BGR */
#define STORE_PIXEL_R5G6B5(DST, X, Y, VALUE) \
do { \
int d = DITHER_COMP(X, Y) >> 6; \
- GLushort *p = (GLushort *)DST; \
- *p = ( ((DITHER_CLAMP((VALUE[RCOMP]) + d) & 0xf8) << 8) | \
- ((DITHER_CLAMP((VALUE[GCOMP]) + d) & 0xfc) << 3) | \
- ((DITHER_CLAMP((VALUE[BCOMP]) + d) & 0xf8) >> 3) ); \
+ *DST = ( ((DITHER_CLAMP((VALUE[RCOMP]) + d) & 0xf8) << 8) | \
+ ((DITHER_CLAMP((VALUE[GCOMP]) + d) & 0xfc) << 3) | \
+ ((DITHER_CLAMP((VALUE[BCOMP]) + d) & 0xf8) >> 3) ); \
} while(0)
#define FETCH_PIXEL_R5G6B5(DST, SRC) \
do { \
- GLushort p = *(GLushort *)SRC; \
DST[ACOMP] = 0xff; \
- DST[RCOMP] = ((p >> 8) & 0xf8) * 255 / 0xf8; \
- DST[GCOMP] = ((p >> 3) & 0xfc) * 255 / 0xfc; \
- DST[BCOMP] = ((p << 3) & 0xf8) * 255 / 0xf8; \
+ DST[RCOMP] = ((*SRC >> 8) & 0xf8) * 255 / 0xf8; \
+ DST[GCOMP] = ((*SRC >> 3) & 0xfc) * 255 / 0xfc; \
+ DST[BCOMP] = ((*SRC << 3) & 0xf8) * 255 / 0xf8; \
} while(0)
@@ -145,8 +131,8 @@ static const GLubyte kernel[16] = {
#define SPAN_VARS \
struct swrast_renderbuffer *xrb = swrast_renderbuffer(rb);
#define INIT_PIXEL_PTR(P, X, Y) \
- GLubyte *P = (GLubyte *)xrb->Base.Data + YFLIP(xrb, Y) * xrb->pitch + (X) * 4;
-#define INC_PIXEL_PTR(P) P += 4
+ GLuint *P = (GLuint *)xrb->Base.Data + YFLIP(xrb, Y) * xrb->pitch / 4 + (X)
+#define INC_PIXEL_PTR(P) P++
#define STORE_PIXEL(DST, X, Y, VALUE) \
STORE_PIXEL_A8R8G8B8(DST, X, Y, VALUE)
#define STORE_PIXEL_RGB(DST, X, Y, VALUE) \
@@ -163,8 +149,8 @@ static const GLubyte kernel[16] = {
#define SPAN_VARS \
struct swrast_renderbuffer *xrb = swrast_renderbuffer(rb);
#define INIT_PIXEL_PTR(P, X, Y) \
- GLubyte *P = (GLubyte *)xrb->Base.Data + YFLIP(xrb, Y) * xrb->pitch + (X) * 4;
-#define INC_PIXEL_PTR(P) P += 4
+ GLuint *P = (GLuint *)xrb->Base.Data + YFLIP(xrb, Y) * xrb->pitch / 4 + (X);
+#define INC_PIXEL_PTR(P) P++
#define STORE_PIXEL(DST, X, Y, VALUE) \
STORE_PIXEL_X8R8G8B8(DST, X, Y, VALUE)
#define STORE_PIXEL_RGB(DST, X, Y, VALUE) \
@@ -181,8 +167,8 @@ static const GLubyte kernel[16] = {
#define SPAN_VARS \
struct swrast_renderbuffer *xrb = swrast_renderbuffer(rb);
#define INIT_PIXEL_PTR(P, X, Y) \
- GLubyte *P = (GLubyte *)xrb->Base.Data + YFLIP(xrb, Y) * xrb->pitch + (X) * 2;
-#define INC_PIXEL_PTR(P) P += 2
+ GLushort *P = (GLushort *)xrb->Base.Data + YFLIP(xrb, Y) * xrb->pitch / 2 + (X);
+#define INC_PIXEL_PTR(P) P++
#define STORE_PIXEL(DST, X, Y, VALUE) \
STORE_PIXEL_R5G6B5(DST, X, Y, VALUE)
#define FETCH_PIXEL(DST, SRC) \
@@ -234,8 +220,8 @@ static const GLubyte kernel[16] = {
#define SPAN_VARS \
struct swrast_renderbuffer *xrb = swrast_renderbuffer(rb);
#define INIT_PIXEL_PTR(P, X, Y) \
- GLubyte *P = (GLubyte *)row;
-#define INC_PIXEL_PTR(P) P += 4
+ GLuint *P = (GLuint *)row;
+#define INC_PIXEL_PTR(P) P++
#define STORE_PIXEL(DST, X, Y, VALUE) \
STORE_PIXEL_A8R8G8B8(DST, X, Y, VALUE)
#define STORE_PIXEL_RGB(DST, X, Y, VALUE) \
@@ -252,8 +238,8 @@ static const GLubyte kernel[16] = {
#define SPAN_VARS \
struct swrast_renderbuffer *xrb = swrast_renderbuffer(rb);
#define INIT_PIXEL_PTR(P, X, Y) \
- GLubyte *P = (GLubyte *)row;
-#define INC_PIXEL_PTR(P) P += 4
+ GLuint *P = (GLuint *)row;
+#define INC_PIXEL_PTR(P) P++
#define STORE_PIXEL(DST, X, Y, VALUE) \
STORE_PIXEL_X8R8G8B8(DST, X, Y, VALUE)
#define STORE_PIXEL_RGB(DST, X, Y, VALUE) \
@@ -270,7 +256,7 @@ static const GLubyte kernel[16] = {
#define SPAN_VARS \
struct swrast_renderbuffer *xrb = swrast_renderbuffer(rb);
#define INIT_PIXEL_PTR(P, X, Y) \
- GLubyte *P = (GLubyte *)row;
+ GLushort *P = (GLushort *)row;
#define INC_PIXEL_PTR(P) P += 2
#define STORE_PIXEL(DST, X, Y, VALUE) \
STORE_PIXEL_R5G6B5(DST, X, Y, VALUE)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-01 23:03:30 +0000