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-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c119
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.h1
2 files changed, 61 insertions, 59 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 652fd65995..7b4d478596 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1051,6 +1051,67 @@ void checkop_init(r700_AssemblerBase* pAsm)
pAsm->aArgSubst[3] = -1;
}
+static GLboolean next_ins(r700_AssemblerBase *pAsm)
+{
+ struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
+
+ if (GL_TRUE == pAsm->is_tex)
+ {
+ if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX)
+ {
+ if (GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE))
+ {
+ radeon_error("Error assembling TEX instruction\n");
+ return GL_FALSE;
+ }
+ }
+ else
+ {
+ if (GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE))
+ {
+ radeon_error("Error assembling TEX instruction\n");
+ return GL_FALSE;
+ }
+ }
+ }
+ else
+ { //ALU
+ if (GL_FALSE == assemble_alu_instruction(pAsm))
+ {
+ radeon_error("Error assembling ALU instruction\n");
+ return GL_FALSE;
+ }
+ }
+
+ if (pAsm->D.dst.rtype == DST_REG_OUT)
+ {
+ assert(pAsm->D.dst.reg >= pAsm->starting_export_register_number);
+
+ if (pAsm->D.dst.op3)
+ {
+ // There is no mask for OP3 instructions, so all channels are written
+ pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF;
+ }
+ else
+ {
+ pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number]
+ |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask;
+ }
+ }
+
+ //reset for next inst.
+ pAsm->D.bits = 0;
+ pAsm->D2.bits = 0;
+ pAsm->S[0].bits = 0;
+ pAsm->S[1].bits = 0;
+ pAsm->S[2].bits = 0;
+ pAsm->is_tex = GL_FALSE;
+ pAsm->need_tex_barrier = GL_FALSE;
+ pAsm->D2.bits = 0;
+ pAsm->C[0].bits = pAsm->C[1].bits = pAsm->C[2].bits = pAsm->C[3].bits = 0;
+ return GL_TRUE;
+}
+
GLboolean mov_temp(r700_AssemblerBase* pAsm, int src)
{
GLuint tmp = gethelpr(pAsm);
@@ -2578,64 +2639,6 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
return GL_TRUE;
}
-GLboolean next_ins(r700_AssemblerBase *pAsm)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- if( GL_TRUE == pAsm->is_tex )
- {
- if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) {
- if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) )
- {
- radeon_error("Error assembling TEX instruction\n");
- return GL_FALSE;
- }
- } else {
- if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) )
- {
- radeon_error("Error assembling TEX instruction\n");
- return GL_FALSE;
- }
- }
- }
- else
- { //ALU
- if( GL_FALSE == assemble_alu_instruction(pAsm) )
- {
- radeon_error("Error assembling ALU instruction\n");
- return GL_FALSE;
- }
- }
-
- if(pAsm->D.dst.rtype == DST_REG_OUT)
- {
- assert(pAsm->D.dst.reg >= pAsm->starting_export_register_number);
-
- if(pAsm->D.dst.op3)
- {
- // There is no mask for OP3 instructions, so all channels are written
- pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF;
- }
- else
- {
- pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number]
- |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask;
- }
- }
-
- //reset for next inst.
- pAsm->D.bits = 0;
- pAsm->D2.bits = 0;
- pAsm->S[0].bits = 0;
- pAsm->S[1].bits = 0;
- pAsm->S[2].bits = 0;
- pAsm->is_tex = GL_FALSE;
- pAsm->need_tex_barrier = GL_FALSE;
- pAsm->D2.bits = 0;
- pAsm->C[0].bits = pAsm->C[1].bits = pAsm->C[2].bits = pAsm->C[3].bits = 0;
- return GL_TRUE;
-}
-
GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode)
{
BITS tmp;
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h
index 0064d0814f..2d3c32487e 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.h
+++ b/src/mesa/drivers/dri/r600/r700_assembler.h
@@ -582,7 +582,6 @@ GLboolean check_scalar(r700_AssemblerBase* pAsm,
GLboolean check_vector(r700_AssemblerBase* pAsm,
R700ALUInstruction* alu_instruction_ptr);
GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm);
-GLboolean next_ins(r700_AssemblerBase *pAsm);
GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops);
GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset);