summaryrefslogtreecommitdiff
path: root/src/mesa/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i915/Makefile1
-rw-r--r--src/mesa/drivers/dri/i915/i915_tex_layout.c21
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_glsl.c60
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_iz.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_pass2.c21
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_sampler_state.c10
-rw-r--r--src/mesa/drivers/dri/intel/intel_buffer_objects.c16
-rw-r--r--src/mesa/drivers/dri/intel/intel_buffer_objects.h1
-rw-r--r--src/mesa/drivers/dri/intel/intel_buffers.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_clear.c99
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c6
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h8
-rw-r--r--src/mesa/drivers/dri/intel/intel_extensions.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_image.c6
18 files changed, 192 insertions, 75 deletions
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 9f4bd1699f..beaf9a4b12 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -19,6 +19,7 @@ DRIVER_SOURCES = \
intel_batchbuffer.c \
intel_clear.c \
intel_extensions.c \
+ intel_generatemipmap.c \
intel_mipmap_tree.c \
intel_tex_layout.c \
intel_tex_image.c \
diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index d44a2f47b3..40bcf7a9af 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -55,6 +55,17 @@ static GLint step_offsets[6][2] = {
[FACE_NEG_Z] = {-1, 1},
};
+
+static GLint bottom_offsets[6] = {
+ [FACE_POS_X] = 16 + 0 * 8,
+ [FACE_POS_Y] = 16 + 1 * 8,
+ [FACE_POS_Z] = 16 + 2 * 8,
+ [FACE_NEG_X] = 16 + 3 * 8,
+ [FACE_NEG_Y] = 16 + 4 * 8,
+ [FACE_NEG_Z] = 16 + 5 * 8,
+};
+
+
/**
* Cube texture map layout for i830M-GM915.
*
@@ -297,7 +308,7 @@ i915_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt)
* +---+ +---+ +---+ +---+ +---+ +---+
*
* The bottom row continues with the remaining 2x2 then the 1x1 mip contents
- * in order, with each of them aligned to a 4x4 block boundary. Thus, for
+ * in order, with each of them aligned to a 8x8 block boundary. Thus, for
* 32x32 cube maps and smaller, the bottom row layout is going to dictate the
* pitch of the tree. For a tree with 4x4 images, the pitch is at least
* 14 * 8 = 112 texels, for 2x2 it is at least 12 * 8 texels, and for 1x1
@@ -375,10 +386,11 @@ i945_miptree_layout_cube(struct intel_context *intel,
x = (face - 4) * 8;
break;
}
+ break;
case 2:
y = mt->total_height - 4;
- x = 16 + face * 8;
+ x = bottom_offsets[face];
break;
case 1:
@@ -454,7 +466,10 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt)
{
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
- i945_miptree_layout_cube(intel, mt);
+ if (mt->compressed)
+ i945_miptree_layout_cube(intel, mt);
+ else
+ i915_miptree_layout_cube(intel, mt);
break;
case GL_TEXTURE_3D:
i945_miptree_layout_3d(intel, mt);
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 62c98bd8bb..bc7756ceab 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -97,7 +97,7 @@ struct brw_glsl_call;
#define BRW_EU_MAX_INSN_STACK 5
-#define BRW_EU_MAX_INSN 4000
+#define BRW_EU_MAX_INSN 10000
struct brw_compile {
struct brw_instruction store[BRW_EU_MAX_INSN];
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index cd65f57bbc..3e476fd3be 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -319,6 +319,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
key->drawable_height = brw->intel.driDrawable->h;
}
+ /* CACHE_NEW_VS_PROG */
+ key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS;
+
/* The unique fragment program ID */
key->program_string_id = fp->id;
}
@@ -357,7 +360,7 @@ const struct brw_tracked_state brw_wm_prog = {
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_WM_INPUT_DIMENSIONS |
BRW_NEW_REDUCED_PRIMITIVE),
- .cache = 0
+ .cache = CACHE_NEW_VS_PROG,
},
.prepare = brw_prepare_wm_prog
};
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 59ead757b5..fb15c03e83 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -75,6 +75,7 @@ struct brw_wm_prog_key {
GLuint program_string_id:32;
GLuint origin_x, origin_y;
GLuint drawable_height;
+ GLuint vp_outputs_written;
};
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index efe8b5126c..4936703799 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -302,7 +302,7 @@ static void prealloc_reg(struct brw_wm_compile *c)
{
int i, j;
struct brw_reg reg;
- int nr_interp_regs = 0;
+ int urb_read_length = 0;
GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
GLuint reg_index = 0;
@@ -366,18 +366,29 @@ static void prealloc_reg(struct brw_wm_compile *c)
}
/* fragment shader inputs */
- for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
- if (inputs & (1<<i)) {
- nr_interp_regs++;
- reg = brw_vec8_grf(reg_index, 0);
- for (j = 0; j < 4; j++)
- set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
- reg_index += 2;
- }
+ for (i = 0; i < VERT_RESULT_MAX; i++) {
+ int fp_input;
+
+ if (i >= VERT_RESULT_VAR0)
+ fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0;
+ else if (i <= VERT_RESULT_TEX7)
+ fp_input = i;
+ else
+ fp_input = -1;
+
+ if (fp_input >= 0 && inputs & (1 << fp_input)) {
+ urb_read_length = reg_index;
+ reg = brw_vec8_grf(reg_index, 0);
+ for (j = 0; j < 4; j++)
+ set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg);
+ }
+ if (c->key.vp_outputs_written & (1 << i)) {
+ reg_index += 2;
+ }
}
c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
- c->prog_data.urb_read_length = nr_interp_regs * 2;
+ c->prog_data.urb_read_length = urb_read_length;
c->prog_data.curb_read_length = c->nr_creg;
c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
reg_index++;
@@ -509,6 +520,14 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c,
const GLuint nr = 1;
const GLuint component = GET_SWZ(src->Swizzle, channel);
+ /* Extended swizzle terms */
+ if (component == SWIZZLE_ZERO) {
+ return brw_imm_f(0.0F);
+ }
+ else if (component == SWIZZLE_ONE) {
+ return brw_imm_f(1.0F);
+ }
+
if (c->fp->use_const_buffer &&
(src->File == PROGRAM_STATE_VAR ||
src->File == PROGRAM_CONSTANT ||
@@ -806,27 +825,26 @@ static void emit_fb_write(struct brw_wm_compile *c,
}
if (c->key.dest_depth_reg) {
- GLuint comp = c->key.dest_depth_reg / 2;
- GLuint off = c->key.dest_depth_reg % 2;
+ const GLuint comp = c->key.dest_depth_reg / 2;
+ const GLuint off = c->key.dest_depth_reg % 2;
- assert(comp == 1);
- assert(off == 0);
-#if 0
- /* XXX do we need this code? comp always 1, off always 0, it seems */
if (off != 0) {
+ /* XXX this code needs review/testing */
+ struct brw_reg arg1_0 = get_src_reg(c, inst, 1, comp);
+ struct brw_reg arg1_1 = get_src_reg(c, inst, 1, comp+1);
+
brw_push_insn_state(p);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_MOV(p, brw_message_reg(nr), offset(arg1[comp],1));
+ brw_MOV(p, brw_message_reg(nr), offset(arg1_0, 1));
/* 2nd half? */
- brw_MOV(p, brw_message_reg(nr+1), arg1[comp+1]);
+ brw_MOV(p, brw_message_reg(nr+1), arg1_1);
brw_pop_insn_state(p);
}
else
-#endif
{
- struct brw_reg src = get_src_reg(c, inst, 1, 1);
- brw_MOV(p, brw_message_reg(nr), src);
+ struct brw_reg src = get_src_reg(c, inst, 1, 1);
+ brw_MOV(p, brw_message_reg(nr), src);
}
nr += 2;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.c b/src/mesa/drivers/dri/i965/brw_wm_iz.c
index bd60ac9b31..8fd067abe7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.c
@@ -116,6 +116,10 @@ const struct {
{ C, 0, 1, 1, 1 }
};
+/**
+ * \param line_aa AA_NEVER, AA_ALWAYS or AA_SOMETIMES
+ * \param lookup bitmask of IZ_* flags
+ */
void brw_wm_lookup_iz( GLuint line_aa,
GLuint lookup,
struct brw_wm_prog_key *key )
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 780edbc42e..6faea018fb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,8 +69,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
*/
static void init_registers( struct brw_wm_compile *c )
{
- struct brw_context *brw = c->func.brw;
- GLuint inputs = (brw->vs.prog_data->outputs_written & DO_SETUP_BITS);
GLuint nr_interp_regs = 0;
GLuint i = 0;
GLuint j;
@@ -85,16 +83,19 @@ static void init_registers( struct brw_wm_compile *c )
prealloc_reg(c, &c->creg[j], i++);
for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
- if (inputs & (1<<j)) {
- /* index for vs output and ps input are not the same
- in shader varying */
- GLuint index;
- if (j > FRAG_ATTRIB_VAR0)
- index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+ if (c->key.vp_outputs_written & (1<<j)) {
+ int fp_index;
+
+ if (j >= VERT_RESULT_VAR0)
+ fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+ else if (j <= VERT_RESULT_TEX7)
+ fp_index = j;
else
- index = j;
+ fp_index = -1;
+
nr_interp_regs++;
- prealloc_reg(c, &c->payload.input_interp[index], i++);
+ if (fp_index >= 0)
+ prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index c604ef0162..3fc18ff1f3 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -178,6 +178,16 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key,
sampler->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CUBE;
sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CUBE;
}
+ else if (key->tex_target == GL_TEXTURE_1D) {
+ /* There's a bug in 1D texture sampling - it actually pays
+ * attention to the wrap_t value, though it should not.
+ * Override the wrap_t value here to GL_REPEAT to keep
+ * any nonexistent border pixels from floating in.
+ */
+ sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
+ sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
+ sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
+ }
else {
sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index f6b0d769c6..0db1f392c0 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -214,6 +214,7 @@ intel_bufferobj_map(GLcontext * ctx,
struct intel_context *intel = intel_context(ctx);
struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
GLboolean read_only = (access == GL_READ_ONLY_ARB);
+ GLboolean write_only = (access == GL_WRITE_ONLY_ARB);
assert(intel_obj);
@@ -225,7 +226,14 @@ intel_bufferobj_map(GLcontext * ctx,
return NULL;
}
- dri_bo_map(intel_obj->buffer, !read_only);
+ if (write_only && intel->intelScreen->kernel_exec_fencing) {
+ drm_intel_gem_bo_map_gtt(intel_obj->buffer);
+ intel_obj->mapped_gtt = GL_TRUE;
+ } else {
+ drm_intel_bo_map(intel_obj->buffer, !read_only);
+ intel_obj->mapped_gtt = GL_FALSE;
+ }
+
obj->Pointer = intel_obj->buffer->virtual;
return obj->Pointer;
}
@@ -243,7 +251,11 @@ intel_bufferobj_unmap(GLcontext * ctx,
assert(intel_obj);
if (intel_obj->buffer != NULL) {
assert(obj->Pointer);
- dri_bo_unmap(intel_obj->buffer);
+ if (intel_obj->mapped_gtt) {
+ drm_intel_gem_bo_unmap_gtt(intel_obj->buffer);
+ } else {
+ drm_intel_bo_unmap(intel_obj->buffer);
+ }
obj->Pointer = NULL;
}
return GL_TRUE;
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.h b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
index bf6dbd58f2..7ef723833c 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
@@ -46,6 +46,7 @@ struct intel_buffer_object
struct intel_region *region; /* Is there a zero-copy texture
associated with this (pixel)
buffer object? */
+ GLboolean mapped_gtt;
};
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index 4f4ea45b74..df5c3fc176 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -276,7 +276,7 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb)
ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
(ctx->Depth.Test && fb->Visual.depthBits > 0));
ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
- (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0));
+ (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
}
else {
/* Mesa's Stencil._Enabled field is updated when
diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index aed95c7c56..4dfaee8a4a 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -30,6 +30,7 @@
#include "main/enums.h"
#include "main/image.h"
#include "main/mtypes.h"
+#include "main/arrayobj.h"
#include "main/attrib.h"
#include "main/blend.h"
#include "main/bufferobj.h"
@@ -66,6 +67,45 @@
BUFFER_BIT_COLOR6 | \
BUFFER_BIT_COLOR7)
+
+/**
+ * Per-context one-time init of things for intl_clear_tris().
+ * Basically set up a private array object for vertex/color arrays.
+ */
+static void
+init_clear(GLcontext *ctx)
+{
+ struct intel_context *intel = intel_context(ctx);
+ struct gl_array_object *arraySave = NULL;
+ const GLuint arrayBuffer = ctx->Array.ArrayBufferObj->Name;
+ const GLuint elementBuffer = ctx->Array.ElementArrayBufferObj->Name;
+
+ /* create new array object */
+ intel->clear.arrayObj = _mesa_new_array_object(ctx, ~0);
+
+ /* save current array object, bind new one */
+ _mesa_reference_array_object(ctx, &arraySave, ctx->Array.ArrayObj);
+ _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, intel->clear.arrayObj);
+
+ /* one-time setup of vertex arrays (pos, color) */
+ _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
+ _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
+ _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), intel->clear.color);
+ _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), intel->clear.vertices);
+ _mesa_Enable(GL_COLOR_ARRAY);
+ _mesa_Enable(GL_VERTEX_ARRAY);
+
+ /* restore original array object */
+ _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, arraySave);
+ _mesa_reference_array_object(ctx, &arraySave, NULL);
+
+ /* restore original buffer objects */
+ _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, arrayBuffer);
+ _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, elementBuffer);
+}
+
+
+
/**
* Perform glClear where mask contains only color, depth, and/or stencil.
*
@@ -78,14 +118,16 @@ void
intel_clear_tris(GLcontext *ctx, GLbitfield mask)
{
struct intel_context *intel = intel_context(ctx);
- GLfloat vertices[4][3];
- GLfloat color[4][4];
GLfloat dst_z;
struct gl_framebuffer *fb = ctx->DrawBuffer;
int i;
GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE;
GLuint saved_shader_program = 0;
unsigned int saved_active_texture;
+ struct gl_array_object *arraySave = NULL;
+
+ if (!intel->clear.arrayObj)
+ init_clear(ctx);
assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH |
BUFFER_BIT_STENCIL)) == 0);
@@ -98,7 +140,6 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
GL_STENCIL_BUFFER_BIT |
GL_TRANSFORM_BIT |
GL_CURRENT_BIT);
- _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
saved_active_texture = ctx->Texture.CurrentUnit;
/* Disable existing GL state we don't want to apply to a clear. */
@@ -149,18 +190,14 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
}
}
-#if FEATURE_ARB_vertex_buffer_object
- _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
- _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
-#endif
+ /* save current array object, bind our private one */
+ _mesa_reference_array_object(ctx, &arraySave, ctx->Array.ArrayObj);
+ _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, intel->clear.arrayObj);
intel_meta_set_passthrough_transform(intel);
for (i = 0; i < 4; i++) {
- color[i][0] = ctx->Color.ClearColor[0];
- color[i][1] = ctx->Color.ClearColor[1];
- color[i][2] = ctx->Color.ClearColor[2];
- color[i][3] = ctx->Color.ClearColor[3];
+ COPY_4FV(intel->clear.color[i], ctx->Color.ClearColor);
}
/* convert clear Z from [0,1] to NDC coord in [-1,1] */
@@ -169,23 +206,18 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
/* Prepare the vertices, which are the same regardless of which buffer we're
* drawing to.
*/
- vertices[0][0] = fb->_Xmin;
- vertices[0][1] = fb->_Ymin;
- vertices[0][2] = dst_z;
- vertices[1][0] = fb->_Xmax;
- vertices[1][1] = fb->_Ymin;
- vertices[1][2] = dst_z;
- vertices[2][0] = fb->_Xmax;
- vertices[2][1] = fb->_Ymax;
- vertices[2][2] = dst_z;
- vertices[3][0] = fb->_Xmin;
- vertices[3][1] = fb->_Ymax;
- vertices[3][2] = dst_z;
-
- _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color);
- _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices);
- _mesa_Enable(GL_COLOR_ARRAY);
- _mesa_Enable(GL_VERTEX_ARRAY);
+ intel->clear.vertices[0][0] = fb->_Xmin;
+ intel->clear.vertices[0][1] = fb->_Ymin;
+ intel->clear.vertices[0][2] = dst_z;
+ intel->clear.vertices[1][0] = fb->_Xmax;
+ intel->clear.vertices[1][1] = fb->_Ymin;
+ intel->clear.vertices[1][2] = dst_z;
+ intel->clear.vertices[2][0] = fb->_Xmax;
+ intel->clear.vertices[2][1] = fb->_Ymax;
+ intel->clear.vertices[2][2] = dst_z;
+ intel->clear.vertices[3][0] = fb->_Xmin;
+ intel->clear.vertices[3][1] = fb->_Ymax;
+ intel->clear.vertices[3][2] = dst_z;
while (mask != 0) {
GLuint this_mask = 0;
@@ -223,8 +255,10 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
/* Control writing of the stencil clear value to stencil. */
if (this_mask & BUFFER_BIT_STENCIL) {
_mesa_Enable(GL_STENCIL_TEST);
- _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
- _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear,
+ _mesa_StencilOpSeparate(GL_FRONT_AND_BACK,
+ GL_REPLACE, GL_REPLACE, GL_REPLACE);
+ _mesa_StencilFuncSeparate(GL_FRONT_AND_BACK, GL_ALWAYS,
+ ctx->Stencil.Clear,
ctx->Stencil.WriteMask[0]);
} else {
_mesa_Disable(GL_STENCIL_TEST);
@@ -246,8 +280,11 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
if (saved_shader_program)
_mesa_UseProgramObjectARB(saved_shader_program);
- _mesa_PopClientAttrib();
_mesa_PopAttrib();
+
+ /* restore current array object */
+ _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, arraySave);
+ _mesa_reference_array_object(ctx, &arraySave, NULL);
}
static const char *buffer_names[] = {
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 8b3e50f9b6..49eadc7532 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -28,6 +28,7 @@
#include "main/glheader.h"
#include "main/context.h"
+#include "main/arrayobj.h"
#include "main/extensions.h"
#include "main/framebuffer.h"
#include "main/imports.h"
@@ -393,7 +394,7 @@ intel_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
if (!driContext->driScreenPriv->dri2.enabled)
return;
- if (!intel->internal_viewport_call) {
+ if (!intel->internal_viewport_call && ctx->DrawBuffer->Name == 0) {
intel_update_renderbuffers(driContext, driContext->driDrawablePriv);
if (driContext->driDrawablePriv != driContext->driReadablePriv)
intel_update_renderbuffers(driContext, driContext->driReadablePriv);
@@ -755,6 +756,9 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
INTEL_FIREVERTICES(intel);
+ if (intel->clear.arrayObj)
+ _mesa_delete_array_object(&intel->ctx, intel->clear.arrayObj);
+
intel->vtbl.destroy(intel);
release_texture_heaps = (intel->ctx.Shared->RefCount == 1);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index c16732d7b5..e931e401e9 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -225,6 +225,14 @@ struct intel_context
GLuint ClearColor565;
GLuint ClearColor8888;
+ /* info for intel_clear_tris() */
+ struct
+ {
+ struct gl_array_object *arrayObj;
+ GLfloat vertices[4][3];
+ GLfloat color[4][4];
+ } clear;
+
/* Offsets of fields within the current vertex:
*/
GLuint coloroffset;
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c
index 9ec1b4ec2f..1e8b1878ab 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -48,6 +48,7 @@
#define need_GL_EXT_point_parameters
#define need_GL_EXT_secondary_color
#define need_GL_EXT_stencil_two_side
+#define need_GL_APPLE_vertex_array_object
#define need_GL_ATI_separate_stencil
#define need_GL_ATI_envmap_bumpmap
#define need_GL_NV_point_sprite
@@ -95,6 +96,7 @@ static const struct dri_extension card_extensions[] = {
{ "GL_EXT_texture_lod_bias", NULL },
{ "GL_3DFX_texture_compression_FXT1", NULL },
{ "GL_APPLE_client_storage", NULL },
+ { "GL_APPLE_vertex_array_object", GL_APPLE_vertex_array_object_functions},
{ "GL_MESA_pack_invert", NULL },
{ "GL_MESA_ycbcr_texture", NULL },
{ "GL_NV_blend_square", NULL },
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 65e62947ef..2728823142 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -236,7 +236,7 @@ intel_get_param(__DRIscreenPrivate *psp, int param, int *value)
ret = drmCommandWriteRead(psp->fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
if (ret) {
- fprintf(stderr, "drm_i915_getparam: %d\n", ret);
+ _mesa_warning(NULL, "drm_i915_getparam: %d\n", ret);
return GL_FALSE;
}
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index b71fe2a7ae..ddbb13e74a 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -208,7 +208,7 @@ try_pbo_upload(struct intel_context *intel,
if (!pbo ||
intel->ctx._ImageTransferState ||
unpack->SkipPixels || unpack->SkipRows) {
- _mesa_printf("%s: failure 1\n", __FUNCTION__);
+ DBG("%s: failure 1\n", __FUNCTION__);
return GL_FALSE;
}
@@ -264,7 +264,7 @@ try_pbo_zcopy(struct intel_context *intel,
if (!pbo ||
intel->ctx._ImageTransferState ||
unpack->SkipPixels || unpack->SkipRows) {
- _mesa_printf("%s: failure 1\n", __FUNCTION__);
+ DBG("%s: failure 1\n", __FUNCTION__);
return GL_FALSE;
}
@@ -283,7 +283,7 @@ try_pbo_zcopy(struct intel_context *intel,
dst_stride = intelImage->mt->pitch;
if (src_stride != dst_stride || dst_offset != 0 || src_offset != 0) {
- _mesa_printf("%s: failure 2\n", __FUNCTION__);
+ DBG("%s: failure 2\n", __FUNCTION__);
return GL_FALSE;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 18:51:16 +0000