diff options
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_cmdbuf.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_pixel.c | 14 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_swtcl.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_tex.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r700_debug.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_context.c | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_dma.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_ioctl.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 29 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_span.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_swtcl.c | 2 | 
13 files changed, 31 insertions, 43 deletions
| diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index e63935378e..5f10279e56 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -105,7 +105,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa )     insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] );  } -void r200EmitScissor(r200ContextPtr rmesa) +static void r200EmitScissor(r200ContextPtr rmesa)  {      unsigned x1, y1, x2, y2;      struct radeon_renderbuffer *rrb; @@ -234,7 +234,6 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,  				    GLuint min_nr )  {     GLushort *retval; -   int ret;     if (R200_DEBUG & DEBUG_IOCTL)        fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 654f2c6ae9..7201ddad2d 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -101,7 +101,7 @@ check_color_per_fragment_ops( const GLcontext *ctx )  } - +#if 0  static GLboolean  clip_pixelrect( const GLcontext *ctx,  		const GLframebuffer *buffer, @@ -142,6 +142,7 @@ clip_pixelrect( const GLcontext *ctx,     return GL_TRUE;  } +#endif  static GLboolean  r200TryReadPixels( GLcontext *ctx, @@ -150,14 +151,14 @@ r200TryReadPixels( GLcontext *ctx,  		  const struct gl_pixelstore_attrib *pack,  		  GLvoid *pixels )  { +   return GL_FALSE; +#if 0     r200ContextPtr rmesa = R200_CONTEXT(ctx);     GLint pitch = pack->RowLength ? pack->RowLength : width;     GLint blit_format;     GLuint cpp = rmesa->radeon.radeonScreen->cpp;     GLint size = width * height * cpp; -   return GL_FALSE; -#if 0     if (R200_DEBUG & DEBUG_PIXEL)        fprintf(stderr, "%s\n", __FUNCTION__); @@ -292,6 +293,10 @@ static void do_draw_pix( GLcontext *ctx,  			 const void *pixels,  			 GLuint planemask)  { +   if (R200_DEBUG & DEBUG_PIXEL) +      fprintf(stderr, "%s\n", __FUNCTION__); + +#if 0     r200ContextPtr rmesa = R200_CONTEXT(ctx);     __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);     drm_clip_rect_t *box = dPriv->pClipRects; @@ -304,9 +309,6 @@ static void do_draw_pix( GLcontext *ctx,     int src_offset = r200GartOffsetFromVirtual( rmesa, pixels );     int src_pitch = pitch * rmesa->radeon.radeonScreen->cpp; -   if (R200_DEBUG & DEBUG_PIXEL) -      fprintf(stderr, "%s\n", __FUNCTION__); -#if 0     switch ( rmesa->radeon.radeonScreen->cpp ) {     case 2:        blit_format = R200_CP_COLOR_FORMAT_RGB565; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 56930c7863..13bd6ac4e2 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -444,7 +444,7 @@ do {							\  #define LOCAL_VARS(n)							\     r200ContextPtr rmesa = R200_CONTEXT(ctx);			\ -   GLuint color[n], spec[n];						\ +   GLuint color[n] = {0}, spec[n] = {0};						\     GLuint coloroffset = rmesa->swtcl.coloroffset;	\     GLuint specoffset = rmesa->swtcl.specoffset;			\     (void) color; (void) spec; (void) coloroffset; (void) specoffset; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c index 609e510ff2..8071899eaa 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c @@ -91,6 +91,7 @@ static struct prog_dst_register dstreg(int file, int index)  	dst.Index = index;  	dst.WriteMask = WRITEMASK_XYZW;  	dst.CondMask = COND_TR; +	dst.RelAddr = 0;  	dst.CondSwizzle = SWIZZLE_NOOP;  	dst.CondSrc = 0;  	dst.pad = 0; @@ -99,10 +100,11 @@ static struct prog_dst_register dstreg(int file, int index)  static struct prog_dst_register dstregtmpmask(int index, int mask)  { -	struct prog_dst_register dst; +	struct prog_dst_register dst = {0};  	dst.File = PROGRAM_TEMPORARY;  	dst.Index = index;  	dst.WriteMask = mask; +	dst.RelAddr = 0;  	dst.CondMask = COND_TR;  	dst.CondSwizzle = SWIZZLE_NOOP;  	dst.CondSrc = 0; diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 6d531bf0f9..a06a1fa921 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -167,9 +167,9 @@ static void r600SetTexDefaultState(radeonTexObjPtr t)  } +#if 0  static GLuint aniso_filter(GLfloat anisotropy)  { -#if 0  	if (anisotropy >= 16.0) {  		return R300_TX_MAX_ANISO_16_TO_1;  	} else if (anisotropy >= 8.0) { @@ -181,9 +181,9 @@ static GLuint aniso_filter(GLfloat anisotropy)  	} else {  		return R300_TX_MAX_ANISO_1_TO_1;  	} -#endif  	return 0;  } +#endif  /**   * Set the texture magnification and minification modes. diff --git a/src/mesa/drivers/dri/r600/r700_debug.c b/src/mesa/drivers/dri/r600/r700_debug.c index ecdb75ad48..dabd0d2c25 100644 --- a/src/mesa/drivers/dri/r600/r700_debug.c +++ b/src/mesa/drivers/dri/r600/r700_debug.c @@ -75,7 +75,7 @@ void DumpHwBinary(int type, void *addr, int size)      {          DEBUGP("0x%08x,\t", *pHw);          if (i%4 == 3) -            DEBUGP("\n", *pHw); +            DEBUGP("0x%08x\n", *pHw);          pHw++;      } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index c457fb654e..12e4ed0a95 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -202,6 +202,7 @@ static void r100_init_vtbl(radeonContextPtr radeon)     radeon->vtbl.swtcl_flush = r100_swtcl_flush;     radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;     radeon->vtbl.fallback = radeonFallback; +   radeon->vtbl.free_context = r100_vtbl_free_context;  }  /* Create the device specific context. diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 4f1065ebcf..587e2acf91 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -317,7 +317,7 @@ static int cs_emit(struct radeon_cs *cs)      if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) &&          (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */  	drm_radeon_irq_emit_t emit_cmd; -	emit_cmd.irq_seq = &csm->pending_age; +	emit_cmd.irq_seq = (int*)&csm->pending_age;  	r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));  	if (r) {  		return r; diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index f306befec4..f15013c33b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -173,6 +173,7 @@ void radeon_init_dma(radeonContextPtr rmesa)  void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size)  { +	struct radeon_dma_bo *dma_bo = NULL;  	/* we set minimum sizes to at least requested size  	   aligned to next 16 bytes. */  	if (size > rmesa->dma.minimum_size) @@ -191,7 +192,7 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size)  	if (is_empty_list(&rmesa->dma.free)  	      || last_elem(&rmesa->dma.free)->bo->size < size) { -		struct radeon_dma_bo *dma_bo = CALLOC(sizeof(struct radeon_dma_bo)); +		dma_bo = CALLOC_STRUCT(radeon_dma_bo);  		assert(dma_bo);  again_alloc: @@ -208,7 +209,7 @@ again_alloc:  		/* We push and pop buffers from end of list so we can keep  		   counter on unused buffers for later freeing them from  		   begin of list */ -		struct radeon_dma_bo *dma_bo = last_elem(&rmesa->dma.free); +		dma_bo = last_elem(&rmesa->dma.free);  		assert(dma_bo->bo->cref == 1);  		remove_from_list(dma_bo);  		insert_at_head(&rmesa->dma.reserved, dma_bo); @@ -265,7 +266,7 @@ void radeonAllocDmaRegion(radeonContextPtr rmesa,  void radeonFreeDmaRegions(radeonContextPtr rmesa)  { -	struct radeon_dma_bo *dma_bo; +	struct radeon_dma_bo *dma_bo = CALLOC_STRUCT(radeon_dma_bo);  	struct radeon_dma_bo *temp;  	if (RADEON_DEBUG & DEBUG_DMA)  		fprintf(stderr, "%s\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index a5e4df7941..afdb5e723e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -113,7 +113,7 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )     insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);  } -void radeonEmitScissor(r100ContextPtr rmesa) +static void radeonEmitScissor(r100ContextPtr rmesa)  {      BATCH_LOCALS(&rmesa->radeon);      if (!rmesa->radeon.radeonScreen->kernel_mm) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index bdcfd10c06..e8b2dc89fe 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -259,7 +259,7 @@ radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value)    struct drm_radeon_info info = { 0 };    if (sPriv->drm_version.major >= 2) { -      info.value = (uint64_t)value; +      info.value = (uint64_t)(uintptr_t)value;        switch (param) {        case RADEON_PARAM_DEVICE_ID:            info.request = RADEON_INFO_DEVICE_ID; @@ -1604,28 +1604,6 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)      _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);  } -/** - * Choose the appropriate CreateContext function based on the chipset. - * Eventually, all drivers will go through this process. - */ -static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, -				     __DRIcontextPrivate * driContextPriv, -				     void *sharedContextPriv) -{ -	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; -	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) -	if (IS_R300_CLASS(screen)) -		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); -#endif - -#if !RADEON_COMMON -	(void)screen; -	return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); -#endif -	return GL_FALSE; -} -  /**   * This is the driver specific part of the createNewScreen entry point. @@ -1824,8 +1802,11 @@ const struct __DriverAPIRec driDriverAPI = {  #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)     .CreateContext   = r600CreateContext,     .DestroyContext  = radeonDestroyContext, +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +   .CreateContext   = r300CreateContext, +   .DestroyContext  = radeonDestroyContext,  #else -   .CreateContext   = radeonCreateContext, +   .CreateContext   = r100CreateContext,     .DestroyContext  = radeonDestroyContext,  #endif     .CreateBuffer    = radeonCreateBuffer, diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 5e4bf00d7a..4e100d854e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -55,6 +55,7 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);  /* r200 depth buffer is always tiled - this is the formula     according to the docs unless I typo'ed in it  */ +#if defined(RADEON_COMMON_FOR_R200)  static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb,  				 GLint x, GLint y)  { @@ -103,6 +104,7 @@ static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb,      }      return &ptr[offset];  } +#endif  /* radeon tiling on r300-r500 has 4 states,     macro-linear/micro-linear diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 20ce6c470b..14d5b5a2af 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -552,7 +552,7 @@ do {							\  #define LOCAL_VARS(n)							\     r100ContextPtr rmesa = R100_CONTEXT(ctx);			\ -   GLuint color[n], spec[n];						\ +   GLuint color[n] = {0}, spec[n] = {0};						\     GLuint coloroffset = rmesa->swtcl.coloroffset;	\     GLuint specoffset = rmesa->swtcl.specoffset;			\     (void) color; (void) spec; (void) coloroffset; (void) specoffset; | 
