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-rw-r--r--src/mesa/pipe/i965simple/brw_context.h10
-rw-r--r--src/mesa/pipe/i965simple/brw_draw.c5
-rw-r--r--src/mesa/pipe/i965simple/brw_draw_upload.c16
-rw-r--r--src/mesa/pipe/i965simple/brw_state.c46
-rw-r--r--src/mesa/pipe/i965simple/brw_vs_emit.c31
5 files changed, 48 insertions, 60 deletions
diff --git a/src/mesa/pipe/i965simple/brw_context.h b/src/mesa/pipe/i965simple/brw_context.h
index 11146570be..fc2cb055e9 100644
--- a/src/mesa/pipe/i965simple/brw_context.h
+++ b/src/mesa/pipe/i965simple/brw_context.h
@@ -443,14 +443,6 @@ struct brw_cached_batch_item {
*/
#define ATTRIB_BIT_DWORDS ((PIPE_ATTRIB_MAX+31)/32)
-struct brw_vertex_element {
- struct brw_vertex_element_state vep;
-
- unsigned index;
- unsigned element_size;
- unsigned count;
- unsigned vbo_rebase_offset;
-};
@@ -508,7 +500,7 @@ struct brw_context
*/
struct pipe_vertex_buffer *vbo_array[PIPE_ATTRIB_MAX];
- struct brw_vertex_element inputs[PIPE_ATTRIB_MAX];
+ struct brw_vertex_element_state inputs[PIPE_ATTRIB_MAX];
#define BRW_NR_UPLOAD_BUFS 17
#define BRW_UPLOAD_INIT_SIZE (128*1024)
diff --git a/src/mesa/pipe/i965simple/brw_draw.c b/src/mesa/pipe/i965simple/brw_draw.c
index 25861a4373..acfb524a30 100644
--- a/src/mesa/pipe/i965simple/brw_draw.c
+++ b/src/mesa/pipe/i965simple/brw_draw.c
@@ -158,10 +158,13 @@ static boolean brw_try_draw_elements( struct pipe_context *pipe,
/* Upload index, vertex data:
*/
- if (index_buffer &&
+ if (index_buffer &&
!brw_upload_indices( brw, index_buffer, index_size, start, count ))
return FALSE;
+ if (!brw_upload_vertex_buffers(brw))
+ return FALSE;
+
if (!brw_upload_vertex_elements( brw ))
return FALSE;
diff --git a/src/mesa/pipe/i965simple/brw_draw_upload.c b/src/mesa/pipe/i965simple/brw_draw_upload.c
index 79144837e8..88d6c9d111 100644
--- a/src/mesa/pipe/i965simple/brw_draw_upload.c
+++ b/src/mesa/pipe/i965simple/brw_draw_upload.c
@@ -217,7 +217,7 @@ boolean brw_upload_vertex_buffers( struct brw_context *brw )
for (i = 0; i < BRW_VEP_MAX; i++)
{
- if (brw->vb.vbo_array[i]->buffer == NULL) {
+ if (brw->vb.vbo_array[i] == NULL) {
nr_enabled = i;
break;
}
@@ -260,18 +260,8 @@ boolean brw_upload_vertex_elements( struct brw_context *brw )
memset(&vep, 0, sizeof(vep));
- for (i = 0; i < nr_enabled; i++) {
- struct brw_vertex_element *input = &brw->vb.inputs[i];
-
- switch (brw->vb.vbo_array[input->vep.ve0.vertex_buffer_index]->pitch) {
- case 0: input->vep.ve1.vfcomponent0 = BRW_VFCOMPONENT_STORE_0;
- case 1: input->vep.ve1.vfcomponent1 = BRW_VFCOMPONENT_STORE_0;
- case 2: input->vep.ve1.vfcomponent2 = BRW_VFCOMPONENT_STORE_0;
- case 3: input->vep.ve1.vfcomponent3 = BRW_VFCOMPONENT_STORE_1_FLT;
- break;
- }
- vep.ve[i] = input->vep;
- }
+ for (i = 0; i < nr_enabled; i++)
+ vep.ve[i] = brw->vb.inputs[i];
vep.header.length = (1 + nr_enabled * sizeof(vep.ve[0])/4) - 2;
diff --git a/src/mesa/pipe/i965simple/brw_state.c b/src/mesa/pipe/i965simple/brw_state.c
index 2008853654..daf14ff4ff 100644
--- a/src/mesa/pipe/i965simple/brw_state.c
+++ b/src/mesa/pipe/i965simple/brw_state.c
@@ -272,31 +272,27 @@ static void brw_set_vertex_element(struct pipe_context *pipe,
struct brw_context *brw = brw_context(pipe);
assert(index < PIPE_ATTRIB_MAX);
- struct brw_vertex_element el;
- memset(&el, 0, sizeof(struct brw_vertex_element));
-
- /* do we need those anymore?*/
- el.index = index;
-#if 0
- /*FIXME*/
- el.element_size = 0;
- el.count = 0;
- el.vbo_rebase_offset = 0;
-#endif
-
- el.vep.ve0.src_offset = element->src_offset;
- el.vep.ve0.src_format = brw_translate_surface_format(element->src_format);
- el.vep.ve0.valid = 1;
- el.vep.ve0.vertex_buffer_index = element->vertex_buffer_index;
-
- el.vep.ve1.dst_offset = index * 4;
- el.vep.ve1.vfcomponent3 = BRW_VFCOMPONENT_STORE_SRC;
- el.vep.ve1.vfcomponent2 = BRW_VFCOMPONENT_STORE_SRC;
- el.vep.ve1.vfcomponent1 = BRW_VFCOMPONENT_STORE_SRC;
- el.vep.ve1.vfcomponent0 = BRW_VFCOMPONENT_STORE_SRC;
- /*can we count of brw->vb.vbo_array[element->vertex_buffer_index]
- * being initialized ok to actually compute vbcomponent's
- * correctly? */
+ struct brw_vertex_element_state el;
+ memset(&el, 0, sizeof(el));
+
+ el.ve0.src_offset = element->src_offset;
+ el.ve0.src_format = brw_translate_surface_format(element->src_format);
+ el.ve0.valid = 1;
+ el.ve0.vertex_buffer_index = element->vertex_buffer_index;
+
+ el.ve1.dst_offset = index * 4;
+
+ el.ve1.vfcomponent3 = BRW_VFCOMPONENT_STORE_SRC;
+ el.ve1.vfcomponent2 = BRW_VFCOMPONENT_STORE_SRC;
+ el.ve1.vfcomponent1 = BRW_VFCOMPONENT_STORE_SRC;
+ el.ve1.vfcomponent0 = BRW_VFCOMPONENT_STORE_SRC;
+
+ switch (element->nr_components) {
+ case 1: el.ve1.vfcomponent1 = BRW_VFCOMPONENT_STORE_0;
+ case 2: el.ve1.vfcomponent2 = BRW_VFCOMPONENT_STORE_0;
+ case 3: el.ve1.vfcomponent3 = BRW_VFCOMPONENT_STORE_1_FLT;
+ break;
+ }
brw->vb.inputs[index] = el;
}
diff --git a/src/mesa/pipe/i965simple/brw_vs_emit.c b/src/mesa/pipe/i965simple/brw_vs_emit.c
index 530e17a736..f4d61eade0 100644
--- a/src/mesa/pipe/i965simple/brw_vs_emit.c
+++ b/src/mesa/pipe/i965simple/brw_vs_emit.c
@@ -995,7 +995,7 @@ static void process_declaration(const struct tgsi_full_declaration *decl,
printf("DECLARATION MASK = %d\n",
decl->u.DeclarationMask.Mask);
assert(0);
- } else { //range
+ } else { /*range*/
idx = decl->u.DeclarationRange.First;
}
switch (decl->Semantic.SemanticName) {
@@ -1057,17 +1057,15 @@ static void process_instruction(struct brw_vs_compile *c,
unsigned insn, if_insn = 0;
*/
- /* Get argument regs. SWZ is special and does this itself. */
- if (inst->Instruction.Opcode != TGSI_OPCODE_SWZ)
- for (i = 0; i < 3; i++) {
- struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
- index = src->SrcRegister.Index;
- file = src->SrcRegister.File;
- if (file == TGSI_FILE_OUTPUT&&c->output_regs[index].used_in_src)
- args[i] = c->output_regs[index].reg;
- else
- args[i] = get_arg(c, &src->SrcRegister);
- }
+ for (i = 0; i < 3; i++) {
+ struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
+ index = src->SrcRegister.Index;
+ file = src->SrcRegister.File;
+ if (file == TGSI_FILE_OUTPUT&&c->output_regs[index].used_in_src)
+ args[i] = c->output_regs[index].reg;
+ else
+ args[i] = get_arg(c, &src->SrcRegister);
+ }
/* Get dest regs. Note that it is possible for a reg to be both
* dst and arg, given the static allocation of registers. So
@@ -1208,11 +1206,16 @@ static void process_instruction(struct brw_vs_compile *c,
break;
#endif
case TGSI_OPCODE_RET:
+#if 0
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(-4));
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
+#else
+ /*brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));*/
+#endif
+ break;
case TGSI_OPCODE_END:
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
break;
@@ -1295,7 +1298,11 @@ void brw_vs_emit(struct brw_vs_compile *c)
* now that we know what vars are being used allocate
* registers for them.*/
brw_vs_alloc_regs(c, &prog_info);
+
+ brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
+ brw_set_access_mode(p, BRW_ALIGN_16);
+
allocated_registers = 1;
}
process_instruction(c, inst, &prog_info);
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-25 23:57:44 +0000