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-rw-r--r--src/mesa/drivers/dri/common/xmlpool.h6
-rw-r--r--src/mesa/drivers/dri/r200/r200_cmdbuf.c2
-rw-r--r--src/mesa/drivers/dri/r200/r200_context.h14
-rw-r--r--src/mesa/drivers/dri/r200/r200_reg.h3
-rw-r--r--src/mesa/drivers/dri/r200/r200_sanity.c11
-rw-r--r--src/mesa/drivers/dri/r200/r200_screen.c5
-rw-r--r--src/mesa/drivers/dri/r200/r200_screen.h1
-rw-r--r--src/mesa/drivers/dri/r200/r200_state_init.c11
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_sanity.c1
9 files changed, 44 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/common/xmlpool.h b/src/mesa/drivers/dri/common/xmlpool.h
index dfa5f49524..46096d8c92 100644
--- a/src/mesa/drivers/dri/common/xmlpool.h
+++ b/src/mesa/drivers/dri/common/xmlpool.h
@@ -298,6 +298,12 @@ DRI_CONF_OPT_BEGIN(texture_level_hack,bool,def) \
DRI_CONF_DESC(en,"Enable texture level hack for radeon/r200 for playing games with compressed textures") \
DRI_CONF_OPT_END
+#define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
+DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
+ DRI_CONF_DESC(en, "texture blend quality, aka brilinear texture filtering") \
+ DRI_CONF_DESC(de, "Texturfilterqualität, auch bekannt als brilineare Texturfilterung") \
+DRI_CONF_OPT_END
+
#define DRI_CONF_TEXTURE_HEAPS_ALL 0
#define DRI_CONF_TEXTURE_HEAPS_CARD 1
#define DRI_CONF_TEXTURE_HEAPS_GART 2
diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index 67eb117554..2891054b05 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -105,6 +105,8 @@ void r200SetUpAtomList( r200ContextPtr rmesa )
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mtl[i] );
for (i = 0; i < 6; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ucp[i] );
+ /* FIXME: is this a good place to insert that atom ? */
+ insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.prf );
}
static void r200SaveHwState( r200ContextPtr rmesa )
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index 7e0a46ae51..eea3a7fe35 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -488,7 +488,10 @@ struct r200_state_atom {
#define CST_SE_TCL_INPUT_VTX_3 17
#define CST_STATE_SIZE 18
-
+#define PRF_CMD_0 0
+#define PRF_PP_TRI_PERF 1
+#define PRF_PP_PERF_CNTL 2
+#define PRF_STATE_SIZE 3
struct r200_hw_state {
@@ -518,15 +521,16 @@ struct r200_hw_state {
struct r200_state_atom tex[6];
struct r200_state_atom cube[6];
struct r200_state_atom zbs;
- struct r200_state_atom mtl[2];
- struct r200_state_atom mat[9];
+ struct r200_state_atom mtl[2];
+ struct r200_state_atom mat[9];
struct r200_state_atom lit[8]; /* includes vec, scl commands */
struct r200_state_atom ucp[6];
struct r200_state_atom pix[6]; /* pixshader stages */
struct r200_state_atom eye; /* eye pos */
struct r200_state_atom grd; /* guard band clipping */
- struct r200_state_atom fog;
- struct r200_state_atom glt;
+ struct r200_state_atom fog;
+ struct r200_state_atom glt;
+ struct r200_state_atom prf;
int max_state_size; /* Number of bytes necessary for a full state emit. */
GLboolean is_dirty, all_dirty;
diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h
index b39bcb05ef..dd5f17cc36 100644
--- a/src/mesa/drivers/dri/r200/r200_reg.h
+++ b/src/mesa/drivers/dri/r200/r200_reg.h
@@ -971,6 +971,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* gap */
#define R200_PP_CNTL_X 0x2cc4
/* gap */
+#define R200_PP_TRI_PERF 0x2cf8
+#define R200_TRI_CUTOFF_MASK (0x1f << 0)
+#define R200_PP_PERF_CNTL 0x2cfc
#define R200_PP_TXOFFSET_0 0x2d00
#define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
diff --git a/src/mesa/drivers/dri/r200/r200_sanity.c b/src/mesa/drivers/dri/r200/r200_sanity.c
index a950b36414..79d0f3c552 100644
--- a/src/mesa/drivers/dri/r200/r200_sanity.c
+++ b/src/mesa/drivers/dri/r200/r200_sanity.c
@@ -150,6 +150,7 @@ static struct {
{ RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+ { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" },
};
struct reg_names {
@@ -475,11 +476,13 @@ static struct reg_names reg_names[] = {
{ R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
{ R200_PP_CNTL_X, "R200_PP_CNTL_X" },
- { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
+ { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
+ { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
};
static struct reg_names scalar_names[] = {
diff --git a/src/mesa/drivers/dri/r200/r200_screen.c b/src/mesa/drivers/dri/r200/r200_screen.c
index 103d5d3384..a8302a44b0 100644
--- a/src/mesa/drivers/dri/r200/r200_screen.c
+++ b/src/mesa/drivers/dri/r200/r200_screen.c
@@ -74,6 +74,7 @@ DRI_CONF_BEGIN
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_TEXTURE_LEVEL_HACK(false)
+ DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
@@ -83,7 +84,7 @@ DRI_CONF_BEGIN
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 16;
+static const GLuint __driNConfigOptions = 17;
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
@@ -345,6 +346,8 @@ r200CreateScreen( __DRIscreenPrivate *sPriv )
/* Check if kernel module is new enough to support blend color and
separate blend functions/equations */
screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
+
+ screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
}
/* Check if ddx has set up a surface reg to cover depth buffer */
screen->depthHasSurface = (sPriv->ddxMajor > 4);
diff --git a/src/mesa/drivers/dri/r200/r200_screen.h b/src/mesa/drivers/dri/r200/r200_screen.h
index fdfb21a6c5..91b43cbd75 100644
--- a/src/mesa/drivers/dri/r200/r200_screen.h
+++ b/src/mesa/drivers/dri/r200/r200_screen.h
@@ -96,6 +96,7 @@ typedef struct {
GLboolean drmSupportsCubeMaps; /* need radeon kernel module >=1.7 */
GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
+ GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */
GLboolean depthHasSurface;
/* Configuration cache with default values for all contexts */
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 6115b57cb5..f004cf79ce 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -305,6 +305,12 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( pix[3], tex, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
ALLOC_STATE( pix[4], tex, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
ALLOC_STATE( pix[5], tex, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
+ if (rmesa->r200Screen->drmSupportsTriPerf) {
+ ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
+ }
+ else {
+ ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
+ }
r200SetUpAtomList( rmesa );
@@ -370,6 +376,7 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL);
rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL);
rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL);
+ rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL);
rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
@@ -504,6 +511,10 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
}
+ rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
+ driQueryOptionf (&rmesa->optionCache,"texture_blend_quality");
+ rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
+
rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
R200_BFACE_SOLID |
R200_FFACE_SOLID |
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index 40a681e861..84112464e1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -146,6 +146,7 @@ static struct {
{ RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+ { 0, 2, "R200_PP_TRI_PERF" },
};
struct reg_names {
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 20:05:39 +0000