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2009-09-12tgsi: add missing implementation of constant decl changeKeith Whitwell
2009-09-13r300g: delete unused flag due to commit: 09b566e1610Cooper Yuan
2009-09-12ureg: add a mechanism to get the built tokens rather than a full shaderKeith Whitwell
Previously ureg would always call the driver's create-shader function. This allows the caller the opportunity to hold onto the tokens if it needs to reuse them, eg. to create an internal draw shader.
2009-09-12ureg: add generic emitters for tex and branch instructionsKeith Whitwell
Couldn't previously emit these except by calling the opcode-specific helper.
2009-09-12tgsi/ureg: give ureg_DECL_constant an explicit index parameterKeith Whitwell
Avoid the need to emit all constant declarations in order. Makes referring to a specific constant in the constant buffer much easier.
2009-09-12mesa: remove unused SATURATE_PLUS_MINUS_ONE flagKeith Whitwell
Never set in mesa. Remove from tgsi translation as well.
2009-09-12tgsi/ureg: VS inputs don't have any semantic tags, just an indexKeith Whitwell
Fix ureg_DECL_vs_input to reflect this and fix up all callers.
2009-09-12tgsi: free tokens on errorKeith Whitwell
2009-09-12tgsi: sanity check ureg programsKeith Whitwell
2009-09-12tgsi: add const qualifierKeith Whitwell
2009-09-12r300g: There is no such thing as "texture stride"Nicolai Hähnle
Individual texture images have a stride, but textures as a whole do not. There are still pieces of code which are confused about this, but the core of the confusion is hopefully gone. Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-11i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt
Previously, it was trying to mess around with the varying's WM setup data to produce a result. Along with not actually working when passed a varying, this wouldn't work if you did dFd[xy]() on a temporary. Instead, just calculate the derivative using the neighbors in the subspan.
2009-09-11r600: fix texcoords from constantsAndre Maasikas
with some minor updates from Richard.
2009-09-11Revert "r600: support tex coords from constants"Alex Deucher
This reverts commit 4099bb76148007f9ccb6c86838b2bf37ea42de56. Tex coord src has to be a GPR.
2009-09-11r300g: only allocate one BO for vertex buffers, default size is 64*1024Cooper Yuan
it can fix redbook/sceneflat, scene, scenebamb, surface, nurbs and so on
2009-09-11r600: support tex coords from constantsAlex Deucher
Fixes neverball among other things.
2009-09-11r600: enable caching of vertex programsAndre Maasikas
2009-09-11llvmpipe: set dirty_render_cache in llvmpipe_clear()José Fonseca
Based on Brian's softpipe change on commit 988db641195819c948249a1bb2d59f13577a482f. We don't use the tile cache for zsbuf though, only for color buffers.
2009-09-11llvmpipe: Update status in README and TODO/FIXME comments throughout the code.José Fonseca
2009-09-10i965: Enable loops in the VS.Eric Anholt
Passes piglit glsl-vs-loop testcase. Bug #20171
2009-09-10mesa: nicer vertex setupBrian Paul
2009-09-10st/mesa: use st_context() helperBrian Paul
2009-09-10softpipe: remove no-op softpipe_init_texture_funcs() functionBrian Paul
2009-09-10softpipe: remove unused #includes, move commentBrian Paul
2009-09-10util: remove unneeded #includesBrian Paul
2009-09-10softpipe: reformatting, clean-ups, commentsBrian Paul
2009-09-10util: minor clean-ups, reformattingBrian Paul
2009-09-10softpipe: remove unneeded #includesBrian Paul
2009-09-10Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-10st/xorg: rename ctx to pipe to match every other gallium state trackerZack Rusin
plus it avoids the "ctx->ctx->" syntax
2009-09-10Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
2009-09-10intel: disable intel_stencil_drawpixels() for nowBrian Paul
It doesn't work reliably even when all the prerequisite checks are made.
2009-09-10st/xorg: temporarily disablie copiesZack Rusin
2009-09-10st/xorg: implement pipelines surface/texture copiesZack Rusin
2009-09-10st/xorg: unite finalization and stub out pipelined copiesZack Rusin
2009-09-10st/xorg: abstract flushing and syncing for the exa codeZack Rusin
2009-09-10st/xorg: disable solid fills until copies are accelerated as wellZack Rusin
2009-09-10st/xorg: implement exasolids with full pipeliningZack Rusin
plus fix some small issues with the shaders
2009-09-10st/xorg: start adding support for surface fillsZack Rusin
2009-09-10docs: document Gallium glDrawPixels(GL_STENCIL_INDEX) fixBrian Paul
2009-09-10softpipe: minor indentation fixBrian Paul
2009-09-10softpipe: set dirty_render_cache in softpipe_clear()Brian Paul
This fixes a bug seen when doing a glDrawPixels(GL_STENCIL_INDEX) right after a glClear(). The check-for-flush test was failing because we didn't set the dirty_render_cache flag in softpipe_clear(). So we saw stale data when we mapped the stencil buffer.
2009-09-10nv50: Fix tiling mode for lower mipmap levels.Marcin Kościelnicki
2009-09-10docs: initial 7.5.2 release notes pageBrian Paul
2009-09-10Fix merge failIan Romanick
One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <brianp@vmware.com> Date: Wed Sep 9 08:33:39 2009 -0600
2009-09-10tgsi: use new tgsi_call_record to handle execution mask stacksBrian Paul
This fixes some issues when "return"ing from nested loops/conditionals.
2009-09-10mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul
Plus, check for pixel transfer stencil index/offset.
2009-09-10Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/drivers/dri/intel/intel_context.c
2009-09-10i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
2009-09-10intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
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