| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-11-07 | r300g: Organize inlined state. | Corbin Simpson | |
| 2009-11-07 | r300g: DCE. | Corbin Simpson | |
| This must never have been called before; it's completely wrong. | |||
| 2009-11-07 | r300g: Minor code cleanup to avoid confusion. | Corbin Simpson | |
| 2009-11-07 | r300g: Remove do-nothing functions. | Corbin Simpson | |
| 2009-11-07 | r300g: Remove faulty assert. | Corbin Simpson | |
| 2009-11-07 | Merge branch 'r300g-vbo' | Corbin Simpson | |
| This is an experimental HW TCL fastpath for r300g. It should run alright. Thanks to osiris for making this possible. | |||
| 2009-11-07 | r300g: Be more verbose in what's killing us WRT vert formats. | Corbin Simpson | |
| 2009-11-07 | r300g: Comments. | Corbin Simpson | |
| 2009-11-07 | r300g: Don't assert on oversized VBOs, just return FALSE. | Corbin Simpson | |
| 2009-11-07 | r300g: Moar vbo cleanup. | Corbin Simpson | |
| 2009-11-07 | r300g: s/false/FALSE/ | Corbin Simpson | |
| Also s/true/TRUE/ | |||
| 2009-11-07 | r300g: Clean up indexbuf render, switch to RELOC macro. | Corbin Simpson | |
| 2009-11-07 | r300g: Clean up r300_setup_vertex_buffers. | Corbin Simpson | |
| 2009-11-07 | r300g: Don't pass hw_prim around in the context. | Corbin Simpson | |
| And some other fixes. | |||
| 2009-11-07 | r300g: Use common state funcs for translating vert formats. | Corbin Simpson | |
| 2009-11-07 | r300g: don't hang GPU on misbehaving apps | Maciej Cencora | |
| 2009-11-07 | r300g: VBOs WIP | Maciej Cencora | |
| 2009-11-07 | r300g: add missing flush | Maciej Cencora | |
| 2009-11-07 | r300g: enable CS dumping | Maciej Cencora | |
| 2009-11-07 | r300g: move vborender context function to seperate file | Maciej Cencora | |
| r300g: Un-migrate r300_draw_render. It'll make maintaining the SW TCL path easier. | |||
| 2009-11-07 | i915g: Fix comment in is buffer referenced | Jakob Bornecrantz | |
| 2009-11-07 | mesa: move code after decl | brian | |
| Fixes bug 24967. | |||
| 2009-11-07 | nv50: enable all 32 threads of a warp | Christoph Bumiller | |
| This should be the default setting. See also 7d967b9b7c08aea2a471c5bf6aced8bfafdae874. | |||
| 2009-11-06 | i965: Use Compr4 instruction compression mode on G4X and newer. | Eric Anholt | |
| No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size. | |||
| 2009-11-06 | i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
| 2009-11-06 | i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
| This should fix issues with antialiased lines in GLSL. | |||
| 2009-11-06 | i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
| The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst. | |||
| 2009-11-06 | i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c. | Eric Anholt | |
| 2009-11-06 | i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c. | Eric Anholt | |
| 2009-11-06 | i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
| 2009-11-06 | i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
| 2009-11-06 | i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code. | Eric Anholt | |
| 2009-11-06 | i965: Use a normal alu1 emit for OPCODE_TRUNC. | Eric Anholt | |
| 2009-11-06 | i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c | Eric Anholt | |
| This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain. | |||
| 2009-11-06 | i965: Collect GLSL src/dst regs up in generic code. | Eric Anholt | |
| This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced. | |||
| 2009-11-06 | st/xorg: implement batching for the composite op | Zack Rusin | |
| something is broken so disabled for now | |||
| 2009-11-06 | st/xorg: batch solid fill requests | Zack Rusin | |
| instead of lots of very small transfers, one larger is a lot better for performance | |||
| 2009-11-06 | st/xorg: start accumulating vertices in a common buffer | Zack Rusin | |
| 2009-11-06 | st/xorg: use quads instead of triangle fans | Zack Rusin | |
| easier to split, accumulate and batch those | |||
| 2009-11-06 | st/xorg: make the buffer size global | Zack Rusin | |
| 2009-11-06 | mesa: Reduce the source channels considered in optimization passes. | Eric Anholt | |
| Depending on the writemask or the opcode, we can often trim the source channels considered used for dead code elimination. This saves actual instructions on 965 in the non-GLSL path for glean glsl1, and cleans up the writemasks of programs even further. | |||
| 2009-11-06 | mesa: Fix remove_instructions to successfully remove when removeFlags[0]. | Eric Anholt | |
| This fixes the dead code elimination to work on the particular code mentioned in the previous commit. | |||
| 2009-11-06 | mesa: Add an optimization path to remove use of pointless MOVs. | Eric Anholt | |
| GLSL code such as: vec4 result = {0, 1, 0, 0}; gl_FragColor = result; emits code like: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], TEMP[0]; and this replaces it with: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], CONST[0]; Even when the dead code eliminator fails to clean up a now-useless MOV instruction (since it doesn't do live/dead ranges), this should at reduce dependencies. | |||
| 2009-11-06 | mesa: Fix up the remove_dead_code pass to operate on a channel basis. | Eric Anholt | |
| This cleans up a bunch of instructions in GLSL programs to have limited writemasks, which would translate to wins in shaders that hit the i965 brw_wm_glsl.c path by depending less on in-driver optimizations. It will also help hit other optimization passes I'm looking at. | |||
| 2009-11-06 | intel: better front color buffer test in intelClear() | Brian Paul | |
| 2009-11-06 | i965: Always pass the size argument to brw_cache_data. | Eric Anholt | |
| This keeps the individual state files from having to export their structures for brw_state_cache initialization. | |||
| 2009-11-06 | intel: Finish removing the fallback code for bug #16697. | Eric Anholt | |
| I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54. | |||
| 2009-11-06 | intel: Don't validate in a texture image used as a render target. | Eric Anholt | |
| Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation. | |||
| 2009-11-06 | mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture() | Eric Anholt | |
| This is probably not 100% complete (bind vs unbind may still not pair up exactly), but it should help out drivers which are relying on FinishRenderTexture to be called when we're done rendering to a particular texture level, not just when we're done rendering to the object at all. This is the case for the one consumer of FinishRenderTexture() so far: the gallium state tracker. Noticed when trying to make use of FRT() in the intel driver. | |||
| 2009-11-06 | intel: Clean up some extra struct indirection in finalize. | Eric Anholt | |
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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